Merge branch 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc

* 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc: (25 commits)
  [POWERPC] 85xx: Added needed MPC85xx PCI device IDs
  [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs
  [POWERPC] 85xxCDS: MPC8548 DTS cleanup.
  [POWERPC] 85xxCDS: Misc 8548 PCI Corrections.
  [POWERPC] 85xxCDS: Delay 8259 cascade hookup.
  [POWERPC] 85xxCDS: Make sure restart resets the PCI bus.
  [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line.
  [POWERPC] FSL: Add support for PCI-X controllers
  [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB
  [POWERPC] Provide ability to setup P2P bridge registers from struct resource
  [POWERPC] Add basic PCI/PCI Express support for 8544DS board
  [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime
  [POWERPC] Removed setup_indirect_pci_nomap
  [POWERPC] 85xx: Add quirk to ignore bogus FPGA on CDS
  [POWERPC] 85xx: Added 8568 PCIe support
  [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected
  [POWERPC] Add basic PCI node for mpc8568mds board
  [POWERPC] Use Freescale pci/pcie common code for 85xx boards
  [POWERPC] Update PCI nodes in the 83xx/85xx boards device tree
  [POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node
  ...

7 files changed, 380 insertions, 123 deletions

diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 484eb4e0e9d..08ce31e612c 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PPC_PMI)		+= pmi.o
 obj-$(CONFIG_U3_DART)           += dart_iommu.o
 obj-$(CONFIG_MMIO_NVRAM)        += mmio_nvram.o
 obj-$(CONFIG_FSL_SOC)           += fsl_soc.o
+obj-$(CONFIG_FSL_PCI)           += fsl_pci.o
 obj-$(CONFIG_TSI108_BRIDGE)     += tsi108_pci.o tsi108_dev.o
 obj-$(CONFIG_QUICC_ENGINE)      += qe_lib/
 mv64x60-$(CONFIG_PCI)           += mv64x60_pci.o
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
new file mode 100644
index 00000000000..51c223385fe
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -0,0 +1,257 @@
+/*
+ * MPC85xx/86xx PCI/PCIE support routing.
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc
+ *
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Rewrite the routing for Frescale PCI and PCI Express
+ *      Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+/* atmu setup for fsl pci/pcie controller */
+void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
+{
+        struct ccsr_pci __iomem *pci;
+        int i;
+
+        pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start,
+                        rsrc->end - rsrc->start + 1);
+        pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
+
+        /* Disable all windows (except powar0 since its ignored) */
+        for(i = 1; i < 5; i++)
+                out_be32(&pci->pow[i].powar, 0);
+        for(i = 0; i < 3; i++)
+                out_be32(&pci->piw[i].piwar, 0);
+
+        /* Setup outbound MEM window */
+        for(i = 0; i < 3; i++)
+                if (hose->mem_resources[i].flags & IORESOURCE_MEM){
+                        pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n",
+                                hose->mem_resources[i].start,
+                                hose->mem_resources[i].end
+                                  - hose->mem_resources[i].start + 1);
+                        out_be32(&pci->pow[i+1].potar,
+                                (hose->mem_resources[i].start >> 12)
+                                & 0x000fffff);
+                        out_be32(&pci->pow[i+1].potear, 0);
+                        out_be32(&pci->pow[i+1].powbar,
+                                (hose->mem_resources[i].start >> 12)
+                                & 0x000fffff);
+                        /* Enable, Mem R/W */
+                        out_be32(&pci->pow[i+1].powar, 0x80044000
+                                | (__ilog2(hose->mem_resources[i].end
+                                - hose->mem_resources[i].start + 1) - 1));
+                }
+
+        /* Setup outbound IO window */
+        if (hose->io_resource.flags & IORESOURCE_IO){
+                pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
+                        hose->io_resource.start,
+                        hose->io_resource.end - hose->io_resource.start + 1,
+                        hose->io_base_phys);
+                out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12)
+                                & 0x000fffff);
+                out_be32(&pci->pow[i+1].potear, 0);
+                out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12)
+                                & 0x000fffff);
+                /* Enable, IO R/W */
+                out_be32(&pci->pow[i+1].powar, 0x80088000
+                        | (__ilog2(hose->io_resource.end
+                        - hose->io_resource.start + 1) - 1));
+        }
+
+        /* Setup 2G inbound Memory Window @ 1 */
+        out_be32(&pci->piw[2].pitar, 0x00000000);
+        out_be32(&pci->piw[2].piwbar,0x00000000);
+        out_be32(&pci->piw[2].piwar, PIWAR_2G);
+}
+
+void __init setup_pci_cmd(struct pci_controller *hose)
+{
+        u16 cmd;
+        int cap_x;
+
+        early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
+        cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+                | PCI_COMMAND_IO;
+        early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
+
+        cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
+        if (cap_x) {
+                int pci_x_cmd = cap_x + PCI_X_CMD;
+                cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+                        | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+                early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
+        } else {
+                early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
+        }
+}
+
+static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
+{
+        struct resource *res;
+        int i, res_idx = PCI_BRIDGE_RESOURCES;
+        struct pci_controller *hose;
+
+        /* if we aren't a PCIe don't bother */
+        if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
+                return ;
+
+        /*
+         * Make the bridge be transparent.
+         */
+        dev->transparent = 1;
+
+        hose = pci_bus_to_host(dev->bus);
+        if (!hose) {
+                printk(KERN_ERR "Can't find hose for bus %d\n",
+                       dev->bus->number);
+                return;
+        }
+
+        /* Clear out any of the virtual P2P bridge registers */
+        pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0);
+        pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 0);
+        pci_write_config_byte(dev, PCI_IO_BASE, 0x10);
+        pci_write_config_byte(dev, PCI_IO_LIMIT, 0);
+        pci_write_config_word(dev, PCI_MEMORY_BASE, 0x10);
+        pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
+        pci_write_config_word(dev, PCI_PREF_BASE_UPPER32, 0x0);
+        pci_write_config_word(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+        pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
+        pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
+
+        if (hose->io_resource.flags) {
+                res = &dev->resource[res_idx++];
+                res->start = hose->io_resource.start;
+                res->end = hose->io_resource.end;
+                res->flags = hose->io_resource.flags;
+                update_bridge_resource(dev, res);
+        }
+
+        for (i = 0; i < 3; i++) {
+                res = &dev->resource[res_idx + i];
+                res->start = hose->mem_resources[i].start;
+                res->end = hose->mem_resources[i].end;
+                res->flags = hose->mem_resources[i].flags;
+                update_bridge_resource(dev, res);
+        }
+}
+
+int __init fsl_pcie_check_link(struct pci_controller *hose)
+{
+        u16 val;
+        early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
+        if (val < PCIE_LTSSM_L0)
+                return 1;
+        return 0;
+}
+
+void fsl_pcibios_fixup_bus(struct pci_bus *bus)
+{
+        struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
+        int i;
+
+        /* deal with bogus pci_bus when we don't have anything connected on PCIe */
+        if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
+                if (bus->parent) {
+                        for (i = 0; i < 4; ++i)
+                                bus->resource[i] = bus->parent->resource[i];
+                }
+        }
+}
+
+int __init fsl_add_bridge(struct device_node *dev, int is_primary)
+{
+        int len;
+        struct pci_controller *hose;
+        struct resource rsrc;
+        const int *bus_range;
+
+        pr_debug("Adding PCI host bridge %s\n", dev->full_name);
+
+        /* Fetch host bridge registers address */
+        if (of_address_to_resource(dev, 0, &rsrc)) {
+                printk(KERN_WARNING "Can't get pci register base!");
+                return -ENOMEM;
+        }
+
+        /* Get bus range if any */
+        bus_range = of_get_property(dev, "bus-range", &len);
+        if (bus_range == NULL || len < 2 * sizeof(int))
+                printk(KERN_WARNING "Can't get bus-range for %s, assume"
+                        " bus 0\n", dev->full_name);
+
+        pci_assign_all_buses = 1;
+        hose = pcibios_alloc_controller(dev);
+        if (!hose)
+                return -ENOMEM;
+
+        hose->first_busno = bus_range ? bus_range[0] : 0x0;
+        hose->last_busno = bus_range ? bus_range[1] : 0xff;
+
+        setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
+                PPC_INDIRECT_TYPE_BIG_ENDIAN);
+        setup_pci_cmd(hose);
+
+        /* check PCI express link status */
+        if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
+                hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
+                        PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
+                if (fsl_pcie_check_link(hose))
+                        hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+        }
+
+        printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx."
+                "Firmware bus number: %d->%d\n",
+                (unsigned long long)rsrc.start, hose->first_busno,
+                hose->last_busno);
+
+        pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
+                hose, hose->cfg_addr, hose->cfg_data);
+
+        /* Interpret the "ranges" property */
+        /* This also maps the I/O region and sets isa_io/mem_base */
+        pci_process_bridge_OF_ranges(hose, dev, is_primary);
+
+        /* Setup PEX window registers */
+        setup_pci_atmu(hose, &rsrc);
+
+        return 0;
+}
+
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent);
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
new file mode 100644
index 00000000000..37b04ad2657
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -0,0 +1,88 @@
+/*
+ * MPC85xx/86xx PCI Express structure define
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __POWERPC_FSL_PCI_H
+#define __POWERPC_FSL_PCI_H
+
+#define PCIE_LTSSM      0x0404          /* PCIE Link Training and Status */
+#define PCIE_LTSSM_L0   0x16            /* L0 state */
+#define PIWAR_2G        0xa0f5501e      /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
+
+/* PCI/PCI Express outbound window reg */
+struct pci_outbound_window_regs {
+        __be32  potar;  /* 0x.0 - Outbound translation address register */
+        __be32  potear; /* 0x.4 - Outbound translation extended address register */
+        __be32  powbar; /* 0x.8 - Outbound window base address register */
+        u8      res1[4];
+        __be32  powar;  /* 0x.10 - Outbound window attributes register */
+        u8      res2[12];
+};
+
+/* PCI/PCI Express inbound window reg */
+struct pci_inbound_window_regs {
+        __be32  pitar;  /* 0x.0 - Inbound translation address register */
+        u8      res1[4];
+        __be32  piwbar; /* 0x.8 - Inbound window base address register */
+        __be32  piwbear;        /* 0x.c - Inbound window base extended address register */
+        __be32  piwar;  /* 0x.10 - Inbound window attributes register */
+        u8      res2[12];
+};
+
+/* PCI/PCI Express IO block registers for 85xx/86xx */
+struct ccsr_pci {
+        __be32  config_addr;            /* 0x.000 - PCI/PCIE Configuration Address Register */
+        __be32  config_data;            /* 0x.004 - PCI/PCIE Configuration Data Register */
+        __be32  int_ack;                /* 0x.008 - PCI Interrupt Acknowledge Register */
+        __be32  pex_otb_cpl_tor;        /* 0x.00c - PCIE Outbound completion timeout register */
+        __be32  pex_conf_tor;           /* 0x.010 - PCIE configuration timeout register */
+        u8      res2[12];
+        __be32  pex_pme_mes_dr;         /* 0x.020 - PCIE PME and message detect register */
+        __be32  pex_pme_mes_disr;       /* 0x.024 - PCIE PME and message disable register */
+        __be32  pex_pme_mes_ier;        /* 0x.028 - PCIE PME and message interrupt enable register */
+        __be32  pex_pmcr;               /* 0x.02c - PCIE power management command register */
+        u8      res3[3024];
+
+/* PCI/PCI Express outbound window 0-4
+ * Window 0 is the default window and is the only window enabled upon reset.
+ * The default outbound register set is used when a transaction misses
+ * in all of the other outbound windows.
+ */
+        struct pci_outbound_window_regs pow[5];
+
+        u8      res14[256];
+
+/* PCI/PCI Express inbound window 3-1
+ * inbound window 1 supports only a 32-bit base address and does not
+ * define an inbound window base extended address register.
+ */
+        struct pci_inbound_window_regs piw[3];
+
+        __be32  pex_err_dr;             /* 0x.e00 - PCI/PCIE error detect register */
+        u8      res21[4];
+        __be32  pex_err_en;             /* 0x.e08 - PCI/PCIE error interrupt enable register */
+        u8      res22[4];
+        __be32  pex_err_disr;           /* 0x.e10 - PCI/PCIE error disable register */
+        u8      res23[12];
+        __be32  pex_err_cap_stat;       /* 0x.e20 - PCI/PCIE error capture status register */
+        u8      res24[4];
+        __be32  pex_err_cap_r0;         /* 0x.e28 - PCIE error capture register 0 */
+        __be32  pex_err_cap_r1;         /* 0x.e2c - PCIE error capture register 0 */
+        __be32  pex_err_cap_r2;         /* 0x.e30 - PCIE error capture register 0 */
+        __be32  pex_err_cap_r3;         /* 0x.e34 - PCIE error capture register 0 */
+};
+
+extern int fsl_add_bridge(struct device_node *dev, int is_primary);
+extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
+
+#endif /* __POWERPC_FSL_PCI_H */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/sysdev/fsl_pcie.h b/arch/powerpc/sysdev/fsl_pcie.h
deleted file mode 100644
index 8d9779c84be..00000000000
--- a/arch/powerpc/sysdev/fsl_pcie.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * MPC85xx/86xx PCI Express structure define
- *
- * Copyright 2007 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __POWERPC_FSL_PCIE_H
-#define __POWERPC_FSL_PCIE_H
-
-/* PCIE Express IO block registers in 85xx/86xx */
-
-struct ccsr_pex {
-        __be32 __iomem    pex_config_addr;      /* 0x.000 - PCI Express Configuration Address Register */
-        __be32 __iomem    pex_config_data;      /* 0x.004 - PCI Express Configuration Data Register */
-        u8 __iomem    res1[4];
-        __be32 __iomem    pex_otb_cpl_tor;      /* 0x.00c - PCI Express Outbound completion timeout register */
-        __be32 __iomem    pex_conf_tor;         /* 0x.010 - PCI Express configuration timeout register */
-        u8 __iomem    res2[12];
-        __be32 __iomem    pex_pme_mes_dr;       /* 0x.020 - PCI Express PME and message detect register */
-        __be32 __iomem    pex_pme_mes_disr;     /* 0x.024 - PCI Express PME and message disable register */
-        __be32 __iomem    pex_pme_mes_ier;      /* 0x.028 - PCI Express PME and message interrupt enable register */
-        __be32 __iomem    pex_pmcr;             /* 0x.02c - PCI Express power management command register */
-        u8 __iomem    res3[3024];
-        __be32 __iomem    pexotar0;             /* 0x.c00 - PCI Express outbound translation address register 0 */
-        __be32 __iomem    pexotear0;            /* 0x.c04 - PCI Express outbound translation extended address register 0*/
-        u8 __iomem    res4[8];
-        __be32 __iomem    pexowar0;             /* 0x.c10 - PCI Express outbound window attributes register 0*/
-        u8 __iomem    res5[12];
-        __be32 __iomem    pexotar1;             /* 0x.c20 - PCI Express outbound translation address register 1 */
-        __be32 __iomem    pexotear1;            /* 0x.c24 - PCI Express outbound translation extended address register 1*/
-        __be32 __iomem    pexowbar1;            /* 0x.c28 - PCI Express outbound window base address register 1*/
-        u8 __iomem    res6[4];
-        __be32 __iomem    pexowar1;             /* 0x.c30 - PCI Express outbound window attributes register 1*/
-        u8 __iomem    res7[12];
-        __be32 __iomem    pexotar2;             /* 0x.c40 - PCI Express outbound translation address register 2 */
-        __be32 __iomem    pexotear2;            /* 0x.c44 - PCI Express outbound translation extended address register 2*/
-        __be32 __iomem    pexowbar2;            /* 0x.c48 - PCI Express outbound window base address register 2*/
-        u8 __iomem    res8[4];
-        __be32 __iomem    pexowar2;             /* 0x.c50 - PCI Express outbound window attributes register 2*/
-        u8 __iomem    res9[12];
-        __be32 __iomem    pexotar3;             /* 0x.c60 - PCI Express outbound translation address register 3 */
-        __be32 __iomem    pexotear3;            /* 0x.c64 - PCI Express outbound translation extended address register 3*/
-        __be32 __iomem    pexowbar3;            /* 0x.c68 - PCI Express outbound window base address register 3*/
-        u8 __iomem    res10[4];
-        __be32 __iomem    pexowar3;             /* 0x.c70 - PCI Express outbound window attributes register 3*/
-        u8 __iomem    res11[12];
-        __be32 __iomem    pexotar4;             /* 0x.c80 - PCI Express outbound translation address register 4 */
-        __be32 __iomem    pexotear4;            /* 0x.c84 - PCI Express outbound translation extended address register 4*/
-        __be32 __iomem    pexowbar4;            /* 0x.c88 - PCI Express outbound window base address register 4*/
-        u8 __iomem    res12[4];
-        __be32 __iomem    pexowar4;             /* 0x.c90 - PCI Express outbound window attributes register 4*/
-        u8 __iomem    res13[12];
-        u8 __iomem    res14[256];
-        __be32 __iomem    pexitar3;             /* 0x.da0 - PCI Express inbound translation address register 3 */
-        u8 __iomem    res15[4];
-        __be32 __iomem    pexiwbar3;            /* 0x.da8 - PCI Express inbound window base address register 3 */
-        __be32 __iomem    pexiwbear3;           /* 0x.dac - PCI Express inbound window base extended address register 3 */
-        __be32 __iomem    pexiwar3;             /* 0x.db0 - PCI Express inbound window attributes register 3 */
-        u8 __iomem    res16[12];
-        __be32 __iomem    pexitar2;             /* 0x.dc0 - PCI Express inbound translation address register 2 */
-        u8 __iomem    res17[4];
-        __be32 __iomem    pexiwbar2;            /* 0x.dc8 - PCI Express inbound window base address register 2 */
-        __be32 __iomem    pexiwbear2;           /* 0x.dcc - PCI Express inbound window base extended address register 2 */
-        __be32 __iomem    pexiwar2;             /* 0x.dd0 - PCI Express inbound window attributes register 2 */
-        u8 __iomem    res18[12];
-        __be32 __iomem    pexitar1;             /* 0x.de0 - PCI Express inbound translation address register 2 */
-        u8 __iomem    res19[4];
-        __be32 __iomem    pexiwbar1;            /* 0x.de8 - PCI Express inbound window base address register 2 */
-        __be32 __iomem    pexiwbear1;           /* 0x.dec - PCI Express inbound window base extended address register 2 */
-        __be32 __iomem    pexiwar1;             /* 0x.df0 - PCI Express inbound window attributes register 2 */
-        u8 __iomem    res20[12];
-        __be32 __iomem    pex_err_dr;           /* 0x.e00 - PCI Express error detect register */
-        u8 __iomem    res21[4];
-        __be32 __iomem    pex_err_en;           /* 0x.e08 - PCI Express error interrupt enable register */
-        u8 __iomem    res22[4];
-        __be32 __iomem    pex_err_disr;         /* 0x.e10 - PCI Express error disable register */
-        u8 __iomem    res23[12];
-        __be32 __iomem    pex_err_cap_stat;     /* 0x.e20 - PCI Express error capture status register */
-        u8 __iomem    res24[4];
-        __be32 __iomem    pex_err_cap_r0;       /* 0x.e28 - PCI Express error capture register 0 */
-        __be32 __iomem    pex_err_cap_r1;       /* 0x.e2c - PCI Express error capture register 0 */
-        __be32 __iomem    pex_err_cap_r2;       /* 0x.e30 - PCI Express error capture register 0 */
-        __be32 __iomem    pex_err_cap_r3;       /* 0x.e34 - PCI Express error capture register 0 */
-};
-
-#endif /* __POWERPC_FSL_PCIE_H */
-#endif /* __KERNEL__ */
diff --git a/arch/powerpc/sysdev/grackle.c b/arch/powerpc/sysdev/grackle.c
index 42053625f49..11ad5622eb7 100644
--- a/arch/powerpc/sysdev/grackle.c
+++ b/arch/powerpc/sysdev/grackle.c
@@ -55,7 +55,7 @@ static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
 
 void __init setup_grackle(struct pci_controller *hose)
 {
-        setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
+        setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
         if (machine_is_compatible("PowerMac1,1"))
                 pci_assign_all_buses = 1;
         if (machine_is_compatible("AAPL,PowerBook1998"))
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index c7e6e859b39..a8ac2dfdd3d 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -20,12 +20,6 @@
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
 
-#ifdef CONFIG_PPC_INDIRECT_PCI_BE
-#define PCI_CFG_OUT out_be32
-#else
-#define PCI_CFG_OUT out_le32
-#endif
-
 static int
 indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
                      int len, u32 *val)
@@ -35,10 +29,17 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
         u8 cfg_type = 0;
         u32 bus_no, reg;
 
+        if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
+                if (bus->number != hose->first_busno)
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+                if (devfn != 0)
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
         if (ppc_md.pci_exclude_device)
                 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
                         return PCIBIOS_DEVICE_NOT_FOUND;
-        
+
         if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
                 if (bus->number != hose->first_busno)
                         cfg_type = 1;
@@ -51,9 +52,12 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
         else
                 reg = offset & 0xfc;
 
-        PCI_CFG_OUT(hose->cfg_addr,
-                 (0x80000000 | (bus_no << 16)
-                  | (devfn << 8) | reg | cfg_type));
+        if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
+                out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
+                         (devfn << 8) | reg | cfg_type));
+        else
+                out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
+                         (devfn << 8) | reg | cfg_type));
 
         /*
          * Note: the caller has already checked that offset is
@@ -83,6 +87,13 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
         u8 cfg_type = 0;
         u32 bus_no, reg;
 
+        if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
+                if (bus->number != hose->first_busno)
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+                if (devfn != 0)
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
         if (ppc_md.pci_exclude_device)
                 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
                         return PCIBIOS_DEVICE_NOT_FOUND;
@@ -99,9 +110,12 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
         else
                 reg = offset & 0xfc;
 
-        PCI_CFG_OUT(hose->cfg_addr,
-                 (0x80000000 | (bus_no << 16)
-                  | (devfn << 8) | reg | cfg_type));
+        if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
+                out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
+                         (devfn << 8) | reg | cfg_type));
+        else
+                out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
+                         (devfn << 8) | reg | cfg_type));
 
         /* surpress setting of PCI_PRIMARY_BUS */
         if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
@@ -135,24 +149,15 @@ static struct pci_ops indirect_pci_ops =
 };
 
 void __init
-setup_indirect_pci_nomap(struct pci_controller* hose, void __iomem * cfg_addr,
-        void __iomem * cfg_data)
-{
-        hose->cfg_addr = cfg_addr;
-        hose->cfg_data = cfg_data;
-        hose->ops = &indirect_pci_ops;
-}
-
-void __init
-setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
+setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data, u32 flags)
 {
         unsigned long base = cfg_addr & PAGE_MASK;
-        void __iomem *mbase, *addr, *data;
+        void __iomem *mbase;
 
         mbase = ioremap(base, PAGE_SIZE);
-        addr = mbase + (cfg_addr & ~PAGE_MASK);
+        hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
         if ((cfg_data & PAGE_MASK) != base)
                 mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
-        data = mbase + (cfg_data & ~PAGE_MASK);
-        setup_indirect_pci_nomap(hose, addr, data);
+        hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
+        hose->ops = &indirect_pci_ops;
 }
diff --git a/arch/powerpc/sysdev/mv64x60_pci.c b/arch/powerpc/sysdev/mv64x60_pci.c
index 45db86c2363..9b3baa7317d 100644
--- a/arch/powerpc/sysdev/mv64x60_pci.c
+++ b/arch/powerpc/sysdev/mv64x60_pci.c
@@ -144,7 +144,7 @@ static int __init mv64x60_add_bridge(struct device_node *dev)
         hose->first_busno = bus_range ? bus_range[0] : 0;
         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 
-        setup_indirect_pci(hose, rsrc.start, rsrc.start + 4);
+        setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0);
         hose->self_busno = hose->first_busno;
 
         printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. "