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authorIshizaki Kou <kou.ishizaki@toshiba.co.jp>2007-01-11 20:03:28 -0500
committerPaul Mackerras <paulus@samba.org>2007-01-24 05:35:45 -0500
commit551a3d87856c67248f9e467a7984865eee4bb0b1 (patch)
tree6d1e5ce95b83fbf0c1e888b066c33f38c475dd3f /arch/powerpc/platforms/celleb
parent983e3f6027374bc8b63f05422d281e0d1f2c37f7 (diff)
[POWERPC] Celleb: Support PCI bus and base of I/O
This patch includes support for pci buses, base of Celleb specific devices, and etc. It works on of_platform bus. Signed-off-by: Kou Ishizaki <kou.ishizaki@toshiba.co.jp> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/celleb')
-rw-r--r--arch/powerpc/platforms/celleb/pci.c481
-rw-r--r--arch/powerpc/platforms/celleb/pci.h35
-rw-r--r--arch/powerpc/platforms/celleb/scc_epci.c409
3 files changed, 925 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/celleb/pci.c b/arch/powerpc/platforms/celleb/pci.c
new file mode 100644
index 00000000000..867f83a7d0c
--- /dev/null
+++ b/arch/powerpc/platforms/celleb/pci.c
@@ -0,0 +1,481 @@
1/*
2 * Support for PCI on Celleb platform.
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This code is based on arch/powerpc/kernel/rtas_pci.c:
7 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25#undef DEBUG
26
27#include <linux/kernel.h>
28#include <linux/threads.h>
29#include <linux/pci.h>
30#include <linux/string.h>
31#include <linux/init.h>
32#include <linux/bootmem.h>
33#include <linux/pci_regs.h>
34
35#include <asm/io.h>
36#include <asm/irq.h>
37#include <asm/prom.h>
38#include <asm/machdep.h>
39#include <asm/pci-bridge.h>
40#include <asm/ppc-pci.h>
41
42#include "pci.h"
43#include "interrupt.h"
44
45#define MAX_PCI_DEVICES 32
46#define MAX_PCI_FUNCTIONS 8
47#define MAX_PCI_BASE_ADDRS 3 /* use 64 bit address */
48
49/* definition for fake pci configuration area for GbE, .... ,and etc. */
50
51struct celleb_pci_resource {
52 struct resource r[MAX_PCI_BASE_ADDRS];
53};
54
55struct celleb_pci_private {
56 unsigned char *fake_config[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
57 struct celleb_pci_resource *res[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
58};
59
60static inline u8 celleb_fake_config_readb(void *addr)
61{
62 u8 *p = addr;
63 return *p;
64}
65
66static inline u16 celleb_fake_config_readw(void *addr)
67{
68 u16 *p = addr;
69 return le16_to_cpu(*p);
70}
71
72static inline u32 celleb_fake_config_readl(void *addr)
73{
74 u32 *p = addr;
75 return le32_to_cpu(*p);
76}
77
78static inline void celleb_fake_config_writeb(u32 val, void *addr)
79{
80 u8 *p = addr;
81 *p = val;
82}
83
84static inline void celleb_fake_config_writew(u32 val, void *addr)
85{
86 u16 val16;
87 u16 *p = addr;
88 val16 = cpu_to_le16(val);
89 *p = val16;
90}
91
92static inline void celleb_fake_config_writel(u32 val, void *addr)
93{
94 u32 val32;
95 u32 *p = addr;
96 val32 = cpu_to_le32(val);
97 *p = val32;
98}
99
100static unsigned char *get_fake_config_start(struct pci_controller *hose,
101 int devno, int fn)
102{
103 struct celleb_pci_private *private = hose->private_data;
104
105 if (private == NULL)
106 return NULL;
107
108 return private->fake_config[devno][fn];
109}
110
111static struct celleb_pci_resource *get_resource_start(
112 struct pci_controller *hose,
113 int devno, int fn)
114{
115 struct celleb_pci_private *private = hose->private_data;
116
117 if (private == NULL)
118 return NULL;
119
120 return private->res[devno][fn];
121}
122
123
124static void celleb_config_read_fake(unsigned char *config, int where,
125 int size, u32 *val)
126{
127 char *p = config + where;
128
129 switch (size) {
130 case 1:
131 *val = celleb_fake_config_readb(p);
132 break;
133 case 2:
134 *val = celleb_fake_config_readw(p);
135 break;
136 case 4:
137 *val = celleb_fake_config_readl(p);
138 break;
139 }
140
141 return;
142}
143
144static void celleb_config_write_fake(unsigned char *config, int where,
145 int size, u32 val)
146{
147 char *p = config + where;
148
149 switch (size) {
150 case 1:
151 celleb_fake_config_writeb(val, p);
152 break;
153 case 2:
154 celleb_fake_config_writew(val, p);
155 break;
156 case 4:
157 celleb_fake_config_writel(val, p);
158 break;
159 }
160 return;
161}
162
163static int celleb_fake_pci_read_config(struct pci_bus *bus,
164 unsigned int devfn, int where, int size, u32 *val)
165{
166 char *config;
167 struct device_node *node;
168 struct pci_controller *hose;
169 unsigned int devno = devfn >> 3;
170 unsigned int fn = devfn & 0x7;
171
172 /* allignment check */
173 BUG_ON(where % size);
174
175 pr_debug(" fake read: bus=0x%x, ", bus->number);
176 node = (struct device_node *)bus->sysdata;
177 hose = pci_find_hose_for_OF_device(node);
178 config = get_fake_config_start(hose, devno, fn);
179
180 pr_debug("devno=0x%x, where=0x%x, size=0x%x, ", devno, where, size);
181 if (!config) {
182 pr_debug("failed\n");
183 return PCIBIOS_DEVICE_NOT_FOUND;
184 }
185
186 celleb_config_read_fake(config, where, size, val);
187 pr_debug("val=0x%x\n", *val);
188
189 return PCIBIOS_SUCCESSFUL;
190}
191
192
193static int celleb_fake_pci_write_config(struct pci_bus *bus,
194 unsigned int devfn, int where, int size, u32 val)
195{
196 char *config;
197 struct device_node *node;
198 struct pci_controller *hose;
199 struct celleb_pci_resource *res;
200 unsigned int devno = devfn >> 3;
201 unsigned int fn = devfn & 0x7;
202
203 /* allignment check */
204 BUG_ON(where % size);
205
206 node = (struct device_node *)bus->sysdata;
207 hose = pci_find_hose_for_OF_device(node);
208 config = get_fake_config_start(hose, devno, fn);
209
210 if (!config)
211 return PCIBIOS_DEVICE_NOT_FOUND;
212
213 if (val == ~0) {
214 int i = (where - PCI_BASE_ADDRESS_0) >> 3;
215
216 switch (where) {
217 case PCI_BASE_ADDRESS_0:
218 case PCI_BASE_ADDRESS_2:
219 if (size != 4)
220 return PCIBIOS_DEVICE_NOT_FOUND;
221 res = get_resource_start(hose, devno, fn);
222 if (!res)
223 return PCIBIOS_DEVICE_NOT_FOUND;
224 celleb_config_write_fake(config, where, size,
225 (res->r[i].end - res->r[i].start));
226 return PCIBIOS_SUCCESSFUL;
227 case PCI_BASE_ADDRESS_1:
228 case PCI_BASE_ADDRESS_3:
229 case PCI_BASE_ADDRESS_4:
230 case PCI_BASE_ADDRESS_5:
231 break;
232 default:
233 break;
234 }
235 }
236
237 celleb_config_write_fake(config, where, size, val);
238 pr_debug(" fake write: where=%x, size=%d, val=%x\n",
239 where, size, val);
240
241 return PCIBIOS_SUCCESSFUL;
242}
243
244static struct pci_ops celleb_fake_pci_ops = {
245 celleb_fake_pci_read_config,
246 celleb_fake_pci_write_config
247};
248
249static inline void celleb_setup_pci_base_addrs(struct pci_controller *hose,
250 unsigned int devno, unsigned int fn,
251 unsigned int num_base_addr)
252{
253 u32 val;
254 unsigned char *config;
255 struct celleb_pci_resource *res;
256
257 config = get_fake_config_start(hose, devno, fn);
258 res = get_resource_start(hose, devno, fn);
259
260 if (!config || !res)
261 return;
262
263 switch (num_base_addr) {
264 case 3:
265 val = (res->r[2].start & 0xfffffff0)
266 | PCI_BASE_ADDRESS_MEM_TYPE_64;
267 celleb_config_write_fake(config, PCI_BASE_ADDRESS_4, 4, val);
268 val = res->r[2].start >> 32;
269 celleb_config_write_fake(config, PCI_BASE_ADDRESS_5, 4, val);
270 /* FALLTHROUGH */
271 case 2:
272 val = (res->r[1].start & 0xfffffff0)
273 | PCI_BASE_ADDRESS_MEM_TYPE_64;
274 celleb_config_write_fake(config, PCI_BASE_ADDRESS_2, 4, val);
275 val = res->r[1].start >> 32;
276 celleb_config_write_fake(config, PCI_BASE_ADDRESS_3, 4, val);
277 /* FALLTHROUGH */
278 case 1:
279 val = (res->r[0].start & 0xfffffff0)
280 | PCI_BASE_ADDRESS_MEM_TYPE_64;
281 celleb_config_write_fake(config, PCI_BASE_ADDRESS_0, 4, val);
282 val = res->r[0].start >> 32;
283 celleb_config_write_fake(config, PCI_BASE_ADDRESS_1, 4, val);
284 break;
285 }
286
287 val = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
288 celleb_config_write_fake(config, PCI_COMMAND, 2, val);
289}
290
291static int __devinit celleb_setup_fake_pci_device(struct device_node *node,
292 struct pci_controller *hose)
293{
294 unsigned int rlen;
295 int num_base_addr = 0;
296 u32 val;
297 const u32 *wi0, *wi1, *wi2, *wi3, *wi4;
298 unsigned int devno, fn;
299 struct celleb_pci_private *private = hose->private_data;
300 unsigned char **config = NULL;
301 struct celleb_pci_resource **res = NULL;
302 const char *name;
303 const unsigned long *li;
304 int size, result;
305
306 if (private == NULL) {
307 printk(KERN_ERR "PCI: "
308 "memory space for pci controller is not assigned\n");
309 goto error;
310 }
311
312 name = get_property(node, "model", &rlen);
313 if (!name) {
314 printk(KERN_ERR "PCI: model property not found.\n");
315 goto error;
316 }
317
318 wi4 = get_property(node, "reg", &rlen);
319 if (wi4 == NULL)
320 goto error;
321
322 devno = ((wi4[0] >> 8) & 0xff) >> 3;
323 fn = (wi4[0] >> 8) & 0x7;
324
325 pr_debug("PCI: celleb_setup_fake_pci() %s devno=%x fn=%x\n", name,
326 devno, fn);
327
328 size = 256;
329 config = &private->fake_config[devno][fn];
330 if (mem_init_done)
331 *config = kzalloc(size, GFP_KERNEL);
332 else
333 *config = alloc_bootmem(size);
334 if (*config == NULL) {
335 printk(KERN_ERR "PCI: "
336 "not enough memory for fake configuration space\n");
337 goto error;
338 }
339 pr_debug("PCI: fake config area assigned 0x%016lx\n",
340 (unsigned long)*config);
341
342 size = sizeof(struct celleb_pci_resource);
343 res = &private->res[devno][fn];
344 if (mem_init_done)
345 *res = kzalloc(size, GFP_KERNEL);
346 else
347 *res = alloc_bootmem(size);
348 if (*res == NULL) {
349 printk(KERN_ERR
350 "PCI: not enough memory for resource data space\n");
351 goto error;
352 }
353 pr_debug("PCI: res assigned 0x%016lx\n", (unsigned long)*res);
354
355 wi0 = get_property(node, "device-id", NULL);
356 wi1 = get_property(node, "vendor-id", NULL);
357 wi2 = get_property(node, "class-code", NULL);
358 wi3 = get_property(node, "revision-id", NULL);
359
360 celleb_config_write_fake(*config, PCI_DEVICE_ID, 2, wi0[0] & 0xffff);
361 celleb_config_write_fake(*config, PCI_VENDOR_ID, 2, wi1[0] & 0xffff);
362 pr_debug("class-code = 0x%08x\n", wi2[0]);
363
364 celleb_config_write_fake(*config, PCI_CLASS_PROG, 1, wi2[0] & 0xff);
365 celleb_config_write_fake(*config, PCI_CLASS_DEVICE, 2,
366 (wi2[0] >> 8) & 0xffff);
367 celleb_config_write_fake(*config, PCI_REVISION_ID, 1, wi3[0]);
368
369 while (num_base_addr < MAX_PCI_BASE_ADDRS) {
370 result = of_address_to_resource(node,
371 num_base_addr, &(*res)->r[num_base_addr]);
372 if (result)
373 break;
374 num_base_addr++;
375 }
376
377 celleb_setup_pci_base_addrs(hose, devno, fn, num_base_addr);
378
379 li = get_property(node, "interrupts", &rlen);
380 val = li[0];
381 celleb_config_write_fake(*config, PCI_INTERRUPT_PIN, 1, 1);
382 celleb_config_write_fake(*config, PCI_INTERRUPT_LINE, 1, val);
383
384#ifdef DEBUG
385 pr_debug("PCI: %s irq=%ld\n", name, li[0]);
386 for (i = 0; i < 6; i++) {
387 celleb_config_read_fake(*config,
388 PCI_BASE_ADDRESS_0 + 0x4 * i, 4,
389 &val);
390 pr_debug("PCI: %s fn=%d base_address_%d=0x%x\n",
391 name, fn, i, val);
392 }
393#endif
394
395 celleb_config_write_fake(*config, PCI_HEADER_TYPE, 1,
396 PCI_HEADER_TYPE_NORMAL);
397
398 return 0;
399
400error:
401 if (mem_init_done) {
402 if (config && *config)
403 kfree(*config);
404 if (res && *res)
405 kfree(*res);
406
407 } else {
408 if (config && *config) {
409 size = 256;
410 free_bootmem((unsigned long)(*config), size);
411 }
412 if (res && *res) {
413 size = sizeof(struct celleb_pci_resource);
414 free_bootmem((unsigned long)(*res), size);
415 }
416 }
417
418 return 1;
419}
420
421static int __devinit phb_set_bus_ranges(struct device_node *dev,
422 struct pci_controller *phb)
423{
424 const int *bus_range;
425 unsigned int len;
426
427 bus_range = get_property(dev, "bus-range", &len);
428 if (bus_range == NULL || len < 2 * sizeof(int))
429 return 1;
430
431 phb->first_busno = bus_range[0];
432 phb->last_busno = bus_range[1];
433
434 return 0;
435}
436
437static void __devinit celleb_alloc_private_mem(struct pci_controller *hose)
438{
439 if (mem_init_done)
440 hose->private_data =
441 kzalloc(sizeof(struct celleb_pci_private), GFP_KERNEL);
442 else
443 hose->private_data =
444 alloc_bootmem(sizeof(struct celleb_pci_private));
445}
446
447int __devinit celleb_setup_phb(struct pci_controller *phb)
448{
449 const char *name;
450 struct device_node *dev = phb->arch_data;
451 struct device_node *node;
452 unsigned int rlen;
453
454 name = get_property(dev, "name", &rlen);
455 if (!name)
456 return 1;
457
458 pr_debug("PCI: celleb_setup_phb() %s\n", name);
459 phb_set_bus_ranges(dev, phb);
460
461 if (strcmp(name, "epci") == 0) {
462 phb->ops = &celleb_epci_ops;
463 return celleb_setup_epci(dev, phb);
464
465 } else if (strcmp(name, "pci-pseudo") == 0) {
466 phb->ops = &celleb_fake_pci_ops;
467 celleb_alloc_private_mem(phb);
468 for (node = of_get_next_child(dev, NULL);
469 node != NULL; node = of_get_next_child(dev, node))
470 celleb_setup_fake_pci_device(node, phb);
471
472 } else
473 return 1;
474
475 return 0;
476}
477
478int celleb_pci_probe_mode(struct pci_bus *bus)
479{
480 return PCI_PROBE_DEVTREE;
481}
diff --git a/arch/powerpc/platforms/celleb/pci.h b/arch/powerpc/platforms/celleb/pci.h
new file mode 100644
index 00000000000..5340e348e29
--- /dev/null
+++ b/arch/powerpc/platforms/celleb/pci.h
@@ -0,0 +1,35 @@
1/*
2 * pci prototypes for Celleb platform
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef _CELLEB_PCI_H
22#define _CELLEB_PCI_H
23
24#include <linux/pci.h>
25
26#include <asm/pci-bridge.h>
27#include <asm/prom.h>
28
29extern int celleb_setup_phb(struct pci_controller *);
30extern int celleb_pci_probe_mode(struct pci_bus *);
31
32extern struct pci_ops celleb_epci_ops;
33extern int celleb_setup_epci(struct device_node *, struct pci_controller *);
34
35#endif /* _CELLEB_PCI_H */
diff --git a/arch/powerpc/platforms/celleb/scc_epci.c b/arch/powerpc/platforms/celleb/scc_epci.c
new file mode 100644
index 00000000000..0edbc0c4f33
--- /dev/null
+++ b/arch/powerpc/platforms/celleb/scc_epci.c
@@ -0,0 +1,409 @@
1/*
2 * Support for SCC external PCI
3 *
4 * (C) Copyright 2004-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#undef DEBUG
22
23#include <linux/kernel.h>
24#include <linux/threads.h>
25#include <linux/pci.h>
26#include <linux/init.h>
27#include <linux/pci_regs.h>
28#include <linux/bootmem.h>
29
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/prom.h>
33#include <asm/machdep.h>
34#include <asm/pci-bridge.h>
35#include <asm/ppc-pci.h>
36
37#include "scc.h"
38#include "pci.h"
39#include "interrupt.h"
40
41#define MAX_PCI_DEVICES 32
42#define MAX_PCI_FUNCTIONS 8
43
44#define iob() __asm__ __volatile__("eieio; sync":::"memory")
45
46
47#if 0 /* test code for epci dummy read */
48static void celleb_epci_dummy_read(struct pci_dev *dev)
49{
50 void *epci_base;
51 struct device_node *node;
52 struct pci_controller *hose;
53 u32 val;
54
55 node = (struct device_node *)dev->bus->sysdata;
56 hose = pci_find_hose_for_OF_device(node);
57
58 if (!hose)
59 return;
60
61 epci_base = (void *)hose->cfg_addr;
62
63 val = in_be32(epci_base + SCC_EPCI_WATRP);
64 iosync();
65
66 return;
67}
68#endif
69
70static inline void clear_and_disable_master_abort_interrupt(
71 struct pci_controller *hose)
72{
73 void __iomem *addr;
74 addr = (void *)hose->cfg_addr + PCI_COMMAND;
75 out_be32(addr, in_be32(addr) | (PCI_STATUS_REC_MASTER_ABORT << 16));
76}
77
78static int celleb_epci_check_abort(struct pci_controller *hose,
79 unsigned long addr)
80{
81 void __iomem *reg, *epci_base;
82 u32 val;
83
84 iob();
85 epci_base = (void *)hose->cfg_addr;
86
87 reg = epci_base + PCI_COMMAND;
88 val = in_be32(reg);
89
90 if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
91 out_be32(reg,
92 (val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));
93
94 /* clear PCI Controller error, FRE, PMFE */
95 reg = epci_base + SCC_EPCI_STATUS;
96 out_be32(reg, SCC_EPCI_INT_PAI);
97
98 reg = epci_base + SCC_EPCI_VCSR;
99 val = in_be32(reg) & 0xffff;
100 val |= SCC_EPCI_VCSR_FRE;
101 out_be32(reg, val);
102
103 reg = epci_base + SCC_EPCI_VISTAT;
104 out_be32(reg, SCC_EPCI_VISTAT_PMFE);
105 return PCIBIOS_DEVICE_NOT_FOUND;
106 }
107
108 return PCIBIOS_SUCCESSFUL;
109}
110
111static unsigned long celleb_epci_make_config_addr(struct pci_controller *hose,
112 unsigned int devfn, int where)
113{
114 unsigned long addr;
115 struct pci_bus *bus = hose->bus;
116
117 if (bus->self)
118 addr = (unsigned long)hose->cfg_data +
119 (((bus->number & 0xff) << 16)
120 | ((devfn & 0xff) << 8)
121 | (where & 0xff)
122 | 0x01000000);
123 else
124 addr = (unsigned long)hose->cfg_data +
125 (((devfn & 0xff) << 8) | (where & 0xff));
126
127 pr_debug("EPCI: config_addr = 0x%016lx\n", addr);
128
129 return addr;
130}
131
132static int celleb_epci_read_config(struct pci_bus *bus,
133 unsigned int devfn, int where, int size, u32 * val)
134{
135 unsigned long addr;
136 struct device_node *node;
137 struct pci_controller *hose;
138
139 /* allignment check */
140 BUG_ON(where % size);
141
142 node = (struct device_node *)bus->sysdata;
143 hose = pci_find_hose_for_OF_device(node);
144
145 if (!hose->cfg_data)
146 return PCIBIOS_DEVICE_NOT_FOUND;
147
148 if (bus->number == hose->first_busno && devfn == 0) {
149 /* EPCI controller self */
150
151 addr = (unsigned long)hose->cfg_addr + where;
152
153 switch (size) {
154 case 1:
155 *val = in_8((u8 *)addr);
156 break;
157 case 2:
158 *val = in_be16((u16 *)addr);
159 break;
160 case 4:
161 *val = in_be32((u32 *)addr);
162 break;
163 default:
164 return PCIBIOS_DEVICE_NOT_FOUND;
165 }
166
167 } else {
168
169 clear_and_disable_master_abort_interrupt(hose);
170 addr = celleb_epci_make_config_addr(hose, devfn, where);
171
172 switch (size) {
173 case 1:
174 *val = in_8((u8 *)addr);
175 break;
176 case 2:
177 *val = in_le16((u16 *)addr);
178 break;
179 case 4:
180 *val = in_le32((u32 *)addr);
181 break;
182 default:
183 return PCIBIOS_DEVICE_NOT_FOUND;
184 }
185 }
186
187 pr_debug("EPCI: "
188 "addr=0x%lx, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
189 addr, devfn, where, size, *val);
190
191 return celleb_epci_check_abort(hose, 0);
192}
193
194static int celleb_epci_write_config(struct pci_bus *bus,
195 unsigned int devfn, int where, int size, u32 val)
196{
197 unsigned long addr;
198 struct device_node *node;
199 struct pci_controller *hose;
200
201 /* allignment check */
202 BUG_ON(where % size);
203
204 node = (struct device_node *)bus->sysdata;
205 hose = pci_find_hose_for_OF_device(node);
206
207 if (!hose->cfg_data)
208 return PCIBIOS_DEVICE_NOT_FOUND;
209
210 if (bus->number == hose->first_busno && devfn == 0) {
211 /* EPCI controller self */
212
213 addr = (unsigned long)hose->cfg_addr + where;
214
215 switch (size) {
216 case 1:
217 out_8((u8 *)addr, val);
218 break;
219 case 2:
220 out_be16((u16 *)addr, val);
221 break;
222 case 4:
223 out_be32((u32 *)addr, val);
224 break;
225 default:
226 return PCIBIOS_DEVICE_NOT_FOUND;
227 }
228
229 } else {
230
231 clear_and_disable_master_abort_interrupt(hose);
232 addr = celleb_epci_make_config_addr(hose, devfn, where);
233
234 switch (size) {
235 case 1:
236 out_8((u8 *)addr, val);
237 break;
238 case 2:
239 out_le16((u16 *)addr, val);
240 break;
241 case 4:
242 out_le32((u32 *)addr, val);
243 break;
244 default:
245 return PCIBIOS_DEVICE_NOT_FOUND;
246 }
247 }
248
249 return celleb_epci_check_abort(hose, addr);
250}
251
252struct pci_ops celleb_epci_ops = {
253 celleb_epci_read_config,
254 celleb_epci_write_config,
255};
256
257/* to be moved in FW */
258static int __devinit celleb_epci_init(struct pci_controller *hose)
259{
260 u32 val;
261 void __iomem *reg, *epci_base;
262 int hwres = 0;
263
264 epci_base = (void *)hose->cfg_addr;
265
266 /* PCI core reset(Internal bus and PCI clock) */
267 reg = epci_base + SCC_EPCI_CKCTRL;
268 val = in_be32(reg);
269 if (val == 0x00030101)
270 hwres = 1;
271 else {
272 val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
273 out_be32(reg, val);
274
275 /* set PCI core clock */
276 val = in_be32(reg);
277 val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
278 out_be32(reg, val);
279
280 /* release PCI core reset (internal bus) */
281 val = in_be32(reg);
282 val |= SCC_EPCI_CKCTRL_CRST0;
283 out_be32(reg, val);
284
285 /* set PCI clock select */
286 reg = epci_base + SCC_EPCI_CLKRST;
287 val = in_be32(reg);
288 val &= ~SCC_EPCI_CLKRST_CKS_MASK;
289 val |= SCC_EPCI_CLKRST_CKS_2;
290 out_be32(reg, val);
291
292 /* set arbiter */
293 reg = epci_base + SCC_EPCI_ABTSET;
294 out_be32(reg, 0x0f1f001f); /* temporary value */
295
296 /* buffer on */
297 reg = epci_base + SCC_EPCI_CLKRST;
298 val = in_be32(reg);
299 val |= SCC_EPCI_CLKRST_BC;
300 out_be32(reg, val);
301
302 /* PCI clock enable */
303 val = in_be32(reg);
304 val |= SCC_EPCI_CLKRST_PCKEN;
305 out_be32(reg, val);
306
307 /* release PCI core reset (all) */
308 reg = epci_base + SCC_EPCI_CKCTRL;
309 val = in_be32(reg);
310 val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
311 out_be32(reg, val);
312
313 /* set base translation registers. (already set by Beat) */
314
315 /* set base address masks. (already set by Beat) */
316 }
317
318 /* release interrupt masks and clear all interrupts */
319 reg = epci_base + SCC_EPCI_INTSET;
320 out_be32(reg, 0x013f011f); /* all interrupts enable */
321 reg = epci_base + SCC_EPCI_VIENAB;
322 val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
323 out_be32(reg, val);
324 reg = epci_base + SCC_EPCI_STATUS;
325 out_be32(reg, 0xffffffff);
326 reg = epci_base + SCC_EPCI_VISTAT;
327 out_be32(reg, 0xffffffff);
328
329 /* disable PCI->IB address translation */
330 reg = epci_base + SCC_EPCI_VCSR;
331 val = in_be32(reg);
332 val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
333 out_be32(reg, val);
334
335 /* set base addresses. (no need to set?) */
336
337 /* memory space, bus master enable */
338 reg = epci_base + PCI_COMMAND;
339 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
340 out_be32(reg, val);
341
342 /* endian mode setup */
343 reg = epci_base + SCC_EPCI_ECMODE;
344 val = 0x00550155;
345 out_be32(reg, val);
346
347 /* set control option */
348 reg = epci_base + SCC_EPCI_CNTOPT;
349 val = in_be32(reg);
350 val |= SCC_EPCI_CNTOPT_O2PMB;
351 out_be32(reg, val);
352
353 /* XXX: temporay: set registers for address conversion setup */
354 reg = epci_base + SCC_EPCI_CNF10_REG;
355 out_be32(reg, 0x80000008);
356 reg = epci_base + SCC_EPCI_CNF14_REG;
357 out_be32(reg, 0x40000008);
358
359 reg = epci_base + SCC_EPCI_BAM0;
360 out_be32(reg, 0x80000000);
361 reg = epci_base + SCC_EPCI_BAM1;
362 out_be32(reg, 0xe0000000);
363
364 reg = epci_base + SCC_EPCI_PVBAT;
365 out_be32(reg, 0x80000000);
366
367 if (!hwres) {
368 /* release external PCI reset */
369 reg = epci_base + SCC_EPCI_CLKRST;
370 val = in_be32(reg);
371 val |= SCC_EPCI_CLKRST_PCIRST;
372 out_be32(reg, val);
373 }
374
375 return 0;
376}
377
378int __devinit celleb_setup_epci(struct device_node *node,
379 struct pci_controller *hose)
380{
381 struct resource r;
382
383 pr_debug("PCI: celleb_setup_epci()\n");
384
385 if (of_address_to_resource(node, 0, &r))
386 goto error;
387 hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
388 if (!hose->cfg_addr)
389 goto error;
390 pr_debug("EPCI: cfg_addr map 0x%016lx->0x%016lx + 0x%016lx\n",
391 r.start, (unsigned long)hose->cfg_addr,
392 (r.end - r.start + 1));
393
394 if (of_address_to_resource(node, 2, &r))
395 goto error;
396 hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
397 if (!hose->cfg_data)
398 goto error;
399 pr_debug("EPCI: cfg_data map 0x%016lx->0x%016lx + 0x%016lx\n",
400 r.start, (unsigned long)hose->cfg_data,
401 (r.end - r.start + 1));
402
403 celleb_epci_init(hose);
404
405 return 0;
406
407error:
408 return 1;
409}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 20:55:19 -0400