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authorIshizaki Kou <kou.ishizaki@toshiba.co.jp>2007-12-13 05:13:14 -0500
committerPaul Mackerras <paulus@samba.org>2007-12-20 00:15:30 -0500
commit7e1961ff4954d6ab627d9b606785afdcd0dda84b (patch)
tree74b6414cf51dd9d08b5279eb9242209ec6f7f751 /arch/powerpc/platforms/celleb/setup.c
parent4751505cf7299318d19a42bdabe0eb5db6d732c4 (diff)
[POWERPC] celleb: Split machine definition
This splits the machine definition for celleb into two definitions, one for celleb_beat, and the other for celleb_native. Though this looks complex because of sorting some functions, there are no more semantic changes than that for the splitting. Signed-off-by: Kou Ishizaki <Kou.Ishizaki@toshiba.co.jp> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/celleb/setup.c')
-rw-r--r--arch/powerpc/platforms/celleb/setup.c185
1 files changed, 110 insertions, 75 deletions
diff --git a/arch/powerpc/platforms/celleb/setup.c b/arch/powerpc/platforms/celleb/setup.c
index 8b03a1bdc79..0f0c4680bf0 100644
--- a/arch/powerpc/platforms/celleb/setup.c
+++ b/arch/powerpc/platforms/celleb/setup.c
@@ -93,30 +93,43 @@ static void celleb_progress(char *s, unsigned short hex)
93 printk("*** %04x : %s\n", hex, s ? s : ""); 93 printk("*** %04x : %s\n", hex, s ? s : "");
94} 94}
95 95
96static void __init celleb_init_IRQ_native(void) 96static void __init celleb_setup_arch_common(void)
97{ 97{
98 iic_init_IRQ(); 98 /* init to some ~sane value until calibrate_delay() runs */
99 spider_init_IRQ(); 99 loops_per_jiffy = 50000000;
100
101#ifdef CONFIG_DUMMY_CONSOLE
102 conswitchp = &dummy_con;
103#endif
100} 104}
101 105
102static void __init celleb_setup_arch_beat(void) 106static struct of_device_id celleb_bus_ids[] __initdata = {
107 { .type = "scc", },
108 { .type = "ioif", }, /* old style */
109 {},
110};
111
112static int __init celleb_publish_devices(void)
103{ 113{
104 ppc_md.restart = beat_restart; 114 if (!machine_is(celleb_beat) &&
105 ppc_md.power_off = beat_power_off; 115 !machine_is(celleb_native))
106 ppc_md.halt = beat_halt; 116 return -ENODEV;
107 ppc_md.get_rtc_time = beat_get_rtc_time; 117
108 ppc_md.set_rtc_time = beat_set_rtc_time; 118 /* Publish OF platform devices for southbridge IOs */
109 ppc_md.power_save = beat_power_save; 119 of_platform_bus_probe(NULL, celleb_bus_ids, NULL);
110 ppc_md.nvram_size = beat_nvram_get_size; 120
111 ppc_md.nvram_read = beat_nvram_read; 121 celleb_pci_workaround_init();
112 ppc_md.nvram_write = beat_nvram_write;
113 ppc_md.set_dabr = beat_set_xdabr;
114 ppc_md.init_IRQ = beatic_init_IRQ;
115 ppc_md.get_irq = beatic_get_irq;
116#ifdef CONFIG_KEXEC
117 ppc_md.kexec_cpu_down = beat_kexec_cpu_down;
118#endif
119 122
123 return 0;
124}
125device_initcall(celleb_publish_devices);
126
127
128/*
129 * functions for Celleb-Beat
130 */
131static void __init celleb_setup_arch_beat(void)
132{
120#ifdef CONFIG_SPU_BASE 133#ifdef CONFIG_SPU_BASE
121 spu_priv1_ops = &spu_priv1_beat_ops; 134 spu_priv1_ops = &spu_priv1_beat_ops;
122 spu_management_ops = &spu_management_of_ops; 135 spu_management_ops = &spu_management_of_ops;
@@ -125,18 +138,36 @@ static void __init celleb_setup_arch_beat(void)
125#ifdef CONFIG_SMP 138#ifdef CONFIG_SMP
126 smp_init_celleb(); 139 smp_init_celleb();
127#endif 140#endif
141
142 celleb_setup_arch_common();
128} 143}
129 144
130static void __init celleb_setup_arch_native(void) 145static int __init celleb_probe_beat(void)
131{ 146{
132 ppc_md.restart = rtas_restart; 147 unsigned long root = of_get_flat_dt_root();
133 ppc_md.power_off = rtas_power_off;
134 ppc_md.halt = rtas_halt;
135 ppc_md.get_boot_time = rtas_get_boot_time;
136 ppc_md.get_rtc_time = rtas_get_rtc_time;
137 ppc_md.set_rtc_time = rtas_set_rtc_time;
138 ppc_md.init_IRQ = celleb_init_IRQ_native;
139 148
149 if (!of_flat_dt_is_compatible(root, "Beat"))
150 return 0;
151
152 powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS
153 | FW_FEATURE_BEAT | FW_FEATURE_LPAR;
154 hpte_init_beat_v3();
155
156 return 1;
157}
158
159
160/*
161 * functions for Celleb-native
162 */
163static void __init celleb_init_IRQ_native(void)
164{
165 iic_init_IRQ();
166 spider_init_IRQ();
167}
168
169static void __init celleb_setup_arch_native(void)
170{
140#ifdef CONFIG_SPU_BASE 171#ifdef CONFIG_SPU_BASE
141 spu_priv1_ops = &spu_priv1_mmio_ops; 172 spu_priv1_ops = &spu_priv1_mmio_ops;
142 spu_management_ops = &spu_management_of_ops; 173 spu_management_ops = &spu_management_of_ops;
@@ -153,71 +184,75 @@ static void __init celleb_setup_arch_native(void)
153#endif 184#endif
154 185
155 cbe_pervasive_init(); 186 cbe_pervasive_init();
156}
157 187
158static void __init celleb_setup_arch(void) 188 /* XXX: nvram initialization should be added */
159{
160 if (firmware_has_feature(FW_FEATURE_BEAT))
161 celleb_setup_arch_beat();
162 else
163 celleb_setup_arch_native();
164
165 /* init to some ~sane value until calibrate_delay() runs */
166 loops_per_jiffy = 50000000;
167 189
168#ifdef CONFIG_DUMMY_CONSOLE 190 celleb_setup_arch_common();
169 conswitchp = &dummy_con;
170#endif
171} 191}
172 192
173static int __init celleb_probe(void) 193static int __init celleb_probe_native(void)
174{ 194{
175 unsigned long root = of_get_flat_dt_root(); 195 unsigned long root = of_get_flat_dt_root();
176 196
177 if (of_flat_dt_is_compatible(root, "Beat")) { 197 if (of_flat_dt_is_compatible(root, "Beat") ||
178 powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS 198 !of_flat_dt_is_compatible(root, "TOSHIBA,Celleb"))
179 | FW_FEATURE_BEAT | FW_FEATURE_LPAR;
180 hpte_init_beat_v3();
181 return 1;
182 }
183 if (of_flat_dt_is_compatible(root, "TOSHIBA,Celleb")) {
184 powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS;
185 hpte_init_native();
186 return 1;
187 }
188
189 return 0;
190}
191
192static struct of_device_id celleb_bus_ids[] __initdata = {
193 { .type = "scc", },
194 { .type = "ioif", }, /* old style */
195 {},
196};
197
198static int __init celleb_publish_devices(void)
199{
200 if (!machine_is(celleb))
201 return 0; 199 return 0;
202 200
203 /* Publish OF platform devices for southbridge IOs */ 201 powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS;
204 of_platform_bus_probe(NULL, celleb_bus_ids, NULL); 202 hpte_init_native();
205
206 celleb_pci_workaround_init();
207 203
208 return 0; 204 return 1;
209} 205}
210device_initcall(celleb_publish_devices);
211 206
212define_machine(celleb) { 207
213 .name = "Cell Reference Set", 208/*
214 .probe = celleb_probe, 209 * machine definitions
215 .setup_arch = celleb_setup_arch, 210 */
211define_machine(celleb_beat) {
212 .name = "Cell Reference Set (Beat)",
213 .probe = celleb_probe_beat,
214 .setup_arch = celleb_setup_arch_beat,
215 .show_cpuinfo = celleb_show_cpuinfo,
216 .restart = beat_restart,
217 .power_off = beat_power_off,
218 .halt = beat_halt,
219 .get_rtc_time = beat_get_rtc_time,
220 .set_rtc_time = beat_set_rtc_time,
221 .calibrate_decr = generic_calibrate_decr,
222 .progress = celleb_progress,
223 .power_save = beat_power_save,
224 .nvram_size = beat_nvram_get_size,
225 .nvram_read = beat_nvram_read,
226 .nvram_write = beat_nvram_write,
227 .set_dabr = beat_set_xdabr,
228 .init_IRQ = beatic_init_IRQ,
229 .get_irq = beatic_get_irq,
230 .pci_probe_mode = celleb_pci_probe_mode,
231 .pci_setup_phb = celleb_setup_phb,
232#ifdef CONFIG_KEXEC
233 .kexec_cpu_down = beat_kexec_cpu_down,
234 .machine_kexec = default_machine_kexec,
235 .machine_kexec_prepare = default_machine_kexec_prepare,
236 .machine_crash_shutdown = default_machine_crash_shutdown,
237#endif
238};
239
240define_machine(celleb_native) {
241 .name = "Cell Reference Set (native)",
242 .probe = celleb_probe_native,
243 .setup_arch = celleb_setup_arch_native,
216 .show_cpuinfo = celleb_show_cpuinfo, 244 .show_cpuinfo = celleb_show_cpuinfo,
245 .restart = rtas_restart,
246 .power_off = rtas_power_off,
247 .halt = rtas_halt,
248 .get_boot_time = rtas_get_boot_time,
249 .get_rtc_time = rtas_get_rtc_time,
250 .set_rtc_time = rtas_set_rtc_time,
217 .calibrate_decr = generic_calibrate_decr, 251 .calibrate_decr = generic_calibrate_decr,
218 .progress = celleb_progress, 252 .progress = celleb_progress,
219 .pci_probe_mode = celleb_pci_probe_mode, 253 .pci_probe_mode = celleb_pci_probe_mode,
220 .pci_setup_phb = celleb_setup_phb, 254 .pci_setup_phb = celleb_setup_phb,
255 .init_IRQ = celleb_init_IRQ_native,
221#ifdef CONFIG_KEXEC 256#ifdef CONFIG_KEXEC
222 .machine_kexec = default_machine_kexec, 257 .machine_kexec = default_machine_kexec,
223 .machine_kexec_prepare = default_machine_kexec_prepare, 258 .machine_kexec_prepare = default_machine_kexec_prepare,