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authorIngo Molnar <mingo@elte.hu>2010-01-29 03:24:57 -0500
committerIngo Molnar <mingo@elte.hu>2010-01-29 04:36:22 -0500
commitae7f6711d6231c9ba54feb5ba9856c3775e482f8 (patch)
tree89070c82204b2503348e4fd6c51d25a169375545 /arch/powerpc/kernel
parent64abebf731df87e6f4ae7d9ffc340bdf0c033e44 (diff)
parentb23ff0e9330e4b11e18af984d50573598e10e7f9 (diff)
Merge branch 'perf/urgent' into perf/core
Merge reason: We want to queue up a dependent patch. Also update to later -rc's. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/powerpc/kernel')
-rw-r--r--arch/powerpc/kernel/head_8xx.S12
-rw-r--r--arch/powerpc/kernel/rtas-proc.c14
-rw-r--r--arch/powerpc/kernel/smp.c12
-rw-r--r--arch/powerpc/kernel/swsusp_32.S2
-rw-r--r--arch/powerpc/kernel/time.c11
5 files changed, 36 insertions, 15 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 678f98cd5e6..3ef743fa5d7 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -542,11 +542,11 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR
542FixupDAR:/* Entry point for dcbx workaround. */ 542FixupDAR:/* Entry point for dcbx workaround. */
543 /* fetch instruction from memory. */ 543 /* fetch instruction from memory. */
544 mfspr r10, SPRN_SRR0 544 mfspr r10, SPRN_SRR0
545 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
545 DO_8xx_CPU6(0x3780, r3) 546 DO_8xx_CPU6(0x3780, r3)
546 mtspr SPRN_MD_EPN, r10 547 mtspr SPRN_MD_EPN, r10
547 mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */ 548 mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */
548 cmplwi cr0, r11, 0x0800 549 beq- 3f /* Branch if user space */
549 blt- 3f /* Branch if user space */
550 lis r11, (swapper_pg_dir-PAGE_OFFSET)@h 550 lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
551 ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l 551 ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
552 rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */ 552 rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */
@@ -768,12 +768,12 @@ start_here:
768 */ 768 */
769initial_mmu: 769initial_mmu:
770 tlbia /* Invalidate all TLB entries */ 770 tlbia /* Invalidate all TLB entries */
771#ifdef CONFIG_PIN_TLB 771/* Always pin the first 8 MB ITLB to prevent ITLB
772 misses while mucking around with SRR0/SRR1 in asm
773*/
772 lis r8, MI_RSV4I@h 774 lis r8, MI_RSV4I@h
773 ori r8, r8, 0x1c00 775 ori r8, r8, 0x1c00
774#else 776
775 li r8, 0
776#endif
777 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 777 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
778 778
779#ifdef CONFIG_PIN_TLB 779#ifdef CONFIG_PIN_TLB
diff --git a/arch/powerpc/kernel/rtas-proc.c b/arch/powerpc/kernel/rtas-proc.c
index 1be9fe38bcb..8777fb02349 100644
--- a/arch/powerpc/kernel/rtas-proc.c
+++ b/arch/powerpc/kernel/rtas-proc.c
@@ -262,19 +262,19 @@ static int __init proc_rtas_init(void)
262 if (rtas_node == NULL) 262 if (rtas_node == NULL)
263 return -ENODEV; 263 return -ENODEV;
264 264
265 proc_create("ppc64/rtas/progress", S_IRUGO|S_IWUSR, NULL, 265 proc_create("powerpc/rtas/progress", S_IRUGO|S_IWUSR, NULL,
266 &ppc_rtas_progress_operations); 266 &ppc_rtas_progress_operations);
267 proc_create("ppc64/rtas/clock", S_IRUGO|S_IWUSR, NULL, 267 proc_create("powerpc/rtas/clock", S_IRUGO|S_IWUSR, NULL,
268 &ppc_rtas_clock_operations); 268 &ppc_rtas_clock_operations);
269 proc_create("ppc64/rtas/poweron", S_IWUSR|S_IRUGO, NULL, 269 proc_create("powerpc/rtas/poweron", S_IWUSR|S_IRUGO, NULL,
270 &ppc_rtas_poweron_operations); 270 &ppc_rtas_poweron_operations);
271 proc_create("ppc64/rtas/sensors", S_IRUGO, NULL, 271 proc_create("powerpc/rtas/sensors", S_IRUGO, NULL,
272 &ppc_rtas_sensors_operations); 272 &ppc_rtas_sensors_operations);
273 proc_create("ppc64/rtas/frequency", S_IWUSR|S_IRUGO, NULL, 273 proc_create("powerpc/rtas/frequency", S_IWUSR|S_IRUGO, NULL,
274 &ppc_rtas_tone_freq_operations); 274 &ppc_rtas_tone_freq_operations);
275 proc_create("ppc64/rtas/volume", S_IWUSR|S_IRUGO, NULL, 275 proc_create("powerpc/rtas/volume", S_IWUSR|S_IRUGO, NULL,
276 &ppc_rtas_tone_volume_operations); 276 &ppc_rtas_tone_volume_operations);
277 proc_create("ppc64/rtas/rmo_buffer", S_IRUSR, NULL, 277 proc_create("powerpc/rtas/rmo_buffer", S_IRUSR, NULL,
278 &ppc_rtas_rmo_buf_ops); 278 &ppc_rtas_rmo_buf_ops);
279 return 0; 279 return 0;
280} 280}
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index a521fb8a40e..c2ee1449807 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -619,4 +619,16 @@ void __cpu_die(unsigned int cpu)
619 if (smp_ops->cpu_die) 619 if (smp_ops->cpu_die)
620 smp_ops->cpu_die(cpu); 620 smp_ops->cpu_die(cpu);
621} 621}
622
623static DEFINE_MUTEX(powerpc_cpu_hotplug_driver_mutex);
624
625void cpu_hotplug_driver_lock()
626{
627 mutex_lock(&powerpc_cpu_hotplug_driver_mutex);
628}
629
630void cpu_hotplug_driver_unlock()
631{
632 mutex_unlock(&powerpc_cpu_hotplug_driver_mutex);
633}
622#endif 634#endif
diff --git a/arch/powerpc/kernel/swsusp_32.S b/arch/powerpc/kernel/swsusp_32.S
index b47d8ceffb5..b0754e23743 100644
--- a/arch/powerpc/kernel/swsusp_32.S
+++ b/arch/powerpc/kernel/swsusp_32.S
@@ -303,7 +303,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
303 lis r4,0x1000 303 lis r4,0x1000
3041: addic. r4,r4,-0x1000 3041: addic. r4,r4,-0x1000
305 tlbie r4 305 tlbie r4
306 blt 1b 306 bgt 1b
307 sync 307 sync
308 308
309 /* restore the MSR and turn on the MMU */ 309 /* restore the MSR and turn on the MMU */
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 9ba2cc88591..6c6093d67f3 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -903,12 +903,21 @@ static void decrementer_set_mode(enum clock_event_mode mode,
903 decrementer_set_next_event(DECREMENTER_MAX, dev); 903 decrementer_set_next_event(DECREMENTER_MAX, dev);
904} 904}
905 905
906static inline uint64_t div_sc64(unsigned long ticks, unsigned long nsec,
907 int shift)
908{
909 uint64_t tmp = ((uint64_t)ticks) << shift;
910
911 do_div(tmp, nsec);
912 return tmp;
913}
914
906static void __init setup_clockevent_multiplier(unsigned long hz) 915static void __init setup_clockevent_multiplier(unsigned long hz)
907{ 916{
908 u64 mult, shift = 32; 917 u64 mult, shift = 32;
909 918
910 while (1) { 919 while (1) {
911 mult = div_sc(hz, NSEC_PER_SEC, shift); 920 mult = div_sc64(hz, NSEC_PER_SEC, shift);
912 if (mult && (mult >> 32UL) == 0UL) 921 if (mult && (mult >> 32UL) == 0UL)
913 break; 922 break;
914 923