aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/include
diff options
context:
space:
mode:
authorTony Breeds <tony@bakeyournoodle.com>2012-10-02 11:52:19 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-11-14 20:59:24 -0500
commit1afc149def25ac1c44a83882f6c0e42a8e88ce9f (patch)
treed12722f1b7633438507f005b7d97fd57562ca319 /arch/powerpc/include
parent8662d0bcab61032fb453550bed6945b09fbb7d73 (diff)
powerpc/47x: Use the new ppc-opcode infrastructure
Don't use 47x only #defines for TLBIVAX or ICBT, supply and use helpers in ppc-opcode.h This fixes a compile breakage. Signed-off-by: Tony Breeds <tony@bakeyournoodle.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/ppc-opcode.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 5f73ce63fca..66bec4611ca 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -86,6 +86,7 @@
86#define PPC_INST_DCBA_MASK 0xfc0007fe 86#define PPC_INST_DCBA_MASK 0xfc0007fe
87#define PPC_INST_DCBAL 0x7c2005ec 87#define PPC_INST_DCBAL 0x7c2005ec
88#define PPC_INST_DCBZL 0x7c2007ec 88#define PPC_INST_DCBZL 0x7c2007ec
89#define PPC_INST_ICBT 0x7c00002c
89#define PPC_INST_ISEL 0x7c00001e 90#define PPC_INST_ISEL 0x7c00001e
90#define PPC_INST_ISEL_MASK 0xfc00003e 91#define PPC_INST_ISEL_MASK 0xfc00003e
91#define PPC_INST_LDARX 0x7c0000a8 92#define PPC_INST_LDARX 0x7c0000a8
@@ -198,6 +199,7 @@
198#define __PPC_MB(s) (((s) & 0x1f) << 6) 199#define __PPC_MB(s) (((s) & 0x1f) << 6)
199#define __PPC_ME(s) (((s) & 0x1f) << 1) 200#define __PPC_ME(s) (((s) & 0x1f) << 1)
200#define __PPC_BI(s) (((s) & 0x1f) << 16) 201#define __PPC_BI(s) (((s) & 0x1f) << 16)
202#define __PPC_CT(t) (((t) & 0x0f) << 21)
201 203
202/* 204/*
203 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a 205 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
@@ -260,6 +262,8 @@
260 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b)) 262 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
261#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \ 263#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
262 __PPC_RT(t) | __PPC_RB(b)) 264 __PPC_RT(t) | __PPC_RB(b))
265#define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \
266 __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
263/* PASemi instructions */ 267/* PASemi instructions */
264#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \ 268#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \
265 __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b)) 269 __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))