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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-12-07 21:20:34 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-12-07 21:20:34 -0500
commitfaa8bf8878636e40646d307e0516dbadb3b65b4f (patch)
tree2f9736f1ec827ad80a3fd61af5846e664ded2ab1 /arch/powerpc/include/asm
parent48b1bf86c308532669571e929619e98a8d88ef54 (diff)
parent1f6820b4c1d09b017625ce32ba23fa39ebfdb27a (diff)
Merge branch 'booke-hugetlb' into next
Diffstat (limited to 'arch/powerpc/include/asm')
-rw-r--r--arch/powerpc/include/asm/hugetlb.h38
-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h7
-rw-r--r--arch/powerpc/include/asm/page_64.h2
3 files changed, 38 insertions, 9 deletions
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 86004930a78..dfdb95bc59a 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -5,7 +5,6 @@
5#include <asm/page.h> 5#include <asm/page.h>
6 6
7extern struct kmem_cache *hugepte_cache; 7extern struct kmem_cache *hugepte_cache;
8extern void __init reserve_hugetlb_gpages(void);
9 8
10static inline pte_t *hugepd_page(hugepd_t hpd) 9static inline pte_t *hugepd_page(hugepd_t hpd)
11{ 10{
@@ -22,14 +21,14 @@ static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
22 unsigned pdshift) 21 unsigned pdshift)
23{ 22{
24 /* 23 /*
25 * On 32-bit, we have multiple higher-level table entries that point to 24 * On FSL BookE, we have multiple higher-level table entries that
26 * the same hugepte. Just use the first one since they're all 25 * point to the same hugepte. Just use the first one since they're all
27 * identical. So for that case, idx=0. 26 * identical. So for that case, idx=0.
28 */ 27 */
29 unsigned long idx = 0; 28 unsigned long idx = 0;
30 29
31 pte_t *dir = hugepd_page(*hpdp); 30 pte_t *dir = hugepd_page(*hpdp);
32#ifdef CONFIG_PPC64 31#ifndef CONFIG_PPC_FSL_BOOK3E
33 idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp); 32 idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
34#endif 33#endif
35 34
@@ -53,7 +52,8 @@ static inline int is_hugepage_only_range(struct mm_struct *mm,
53} 52}
54#endif 53#endif
55 54
56void book3e_hugetlb_preload(struct mm_struct *mm, unsigned long ea, pte_t pte); 55void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
56 pte_t pte);
57void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr); 57void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
58 58
59void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr, 59void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
@@ -124,7 +124,17 @@ static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
124 unsigned long addr, pte_t *ptep, 124 unsigned long addr, pte_t *ptep,
125 pte_t pte, int dirty) 125 pte_t pte, int dirty)
126{ 126{
127#ifdef HUGETLB_NEED_PRELOAD
128 /*
129 * The "return 1" forces a call of update_mmu_cache, which will write a
130 * TLB entry. Without this, platforms that don't do a write of the TLB
131 * entry in the TLB miss handler asm will fault ad infinitum.
132 */
133 ptep_set_access_flags(vma, addr, ptep, pte, dirty);
134 return 1;
135#else
127 return ptep_set_access_flags(vma, addr, ptep, pte, dirty); 136 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
137#endif
128} 138}
129 139
130static inline pte_t huge_ptep_get(pte_t *ptep) 140static inline pte_t huge_ptep_get(pte_t *ptep)
@@ -142,14 +152,24 @@ static inline void arch_release_hugepage(struct page *page)
142} 152}
143 153
144#else /* ! CONFIG_HUGETLB_PAGE */ 154#else /* ! CONFIG_HUGETLB_PAGE */
145static inline void reserve_hugetlb_gpages(void)
146{
147 pr_err("Cannot reserve gpages without hugetlb enabled\n");
148}
149static inline void flush_hugetlb_page(struct vm_area_struct *vma, 155static inline void flush_hugetlb_page(struct vm_area_struct *vma,
150 unsigned long vmaddr) 156 unsigned long vmaddr)
151{ 157{
152} 158}
159#endif /* CONFIG_HUGETLB_PAGE */
160
161
162/*
163 * FSL Book3E platforms require special gpage handling - the gpages
164 * are reserved early in the boot process by memblock instead of via
165 * the .dts as on IBM platforms.
166 */
167#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_FSL_BOOK3E)
168extern void __init reserve_hugetlb_gpages(void);
169#else
170static inline void reserve_hugetlb_gpages(void)
171{
172}
153#endif 173#endif
154 174
155#endif /* _ASM_POWERPC_HUGETLB_H */ 175#endif /* _ASM_POWERPC_HUGETLB_H */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 50210b9b014..f5f89cafebd 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -258,6 +258,13 @@ extern int mmu_vmemmap_psize;
258 258
259#ifdef CONFIG_PPC64 259#ifdef CONFIG_PPC64
260extern unsigned long linear_map_top; 260extern unsigned long linear_map_top;
261
262/*
263 * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
264 * HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to
265 * return 1, indicating that the tlb requires preloading.
266 */
267#define HUGETLB_NEED_PRELOAD
261#endif 268#endif
262 269
263#endif /* !__ASSEMBLY__ */ 270#endif /* !__ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index fb40ede6bc0..fed85e6290e 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -130,7 +130,9 @@ do { \
130 130
131#ifdef CONFIG_HUGETLB_PAGE 131#ifdef CONFIG_HUGETLB_PAGE
132 132
133#ifdef CONFIG_PPC_MM_SLICES
133#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA 134#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
135#endif
134 136
135#endif /* !CONFIG_HUGETLB_PAGE */ 137#endif /* !CONFIG_HUGETLB_PAGE */
136 138