powerpc: Use names rather than numbers for SPRGs (v2)

The kernel uses SPRG registers for various purposes, typically in
low level assembly code as scratch registers or to hold per-cpu
global infos such as the PACA or the current thread_info pointer.

We want to be able to easily shuffle the usage of those registers
as some implementations have specific constraints realted to some
of them, for example, some have userspace readable aliases, etc..
and the current choice isn't always the best.

This patch should not change any code generation, and replaces the
usage of SPRN_SPRGn everywhere in the kernel with a named replacement
and adds documentation next to the definition of the names as to
what those are used for on each processor family.

The only parts that still use the original numbers are bits of KVM
or suspend/resume code that just blindly needs to save/restore all
the SPRGs.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 files changed, 113 insertions, 0 deletions

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1170267736d..a8179cc99ac 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -646,6 +646,119 @@
 #endif
 
 /*
+ * SPRG usage:
+ *
+ * All 64-bit:
+ *      - SPRG3 stores PACA pointer
+ *
+ * 64-bit server:
+ *      - SPRG0 unused (reserved for HV on Power4)
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 scratch for exception vectors
+ *
+ * All 32-bit:
+ *      - SPRG3 current thread_info pointer
+ *        (virtual on BookE, physical on others)
+ *
+ * 32-bit classic:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 indicator that we are in RTAS
+ *      - SPRG4 (603 only) pseudo TLB LRU data
+ *
+ * 32-bit 40x:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 scratch for exception vectors
+ *      - SPRG4 scratch for exception vectors (not 403)
+ *      - SPRG5 scratch for exception vectors (not 403)
+ *      - SPRG6 scratch for exception vectors (not 403)
+ *      - SPRG7 scratch for exception vectors (not 403)
+ *
+ * 32-bit 440 and FSL BookE:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors (*)
+ *      - SPRG2 scratch for crit interrupts handler
+ *      - SPRG4 scratch for exception vectors
+ *      - SPRG5 scratch for exception vectors
+ *      - SPRG6 scratch for machine check handler
+ *      - SPRG7 scratch for exception vectors
+ *      - SPRG9 scratch for debug vectors (e500 only)
+ *
+ *      Additionally, BookE separates "read" and "write"
+ *      of those registers. That allows to use the userspace
+ *      readable variant for reads, which can avoid a fault
+ *      with KVM type virtualization.
+ *
+ *      (*) Under KVM, the host SPRG1 is used to point to
+ *      the current VCPU data structure
+ *
+ * 32-bit 8xx:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 apparently unused but initialized
+ *
+ */
+#ifdef CONFIG_PPC64
+#define SPRN_SPRG_PACA          SPRN_SPRG3
+#else
+#define SPRN_SPRG_THREAD        SPRN_SPRG3
+#endif
+
+#ifdef CONFIG_PPC_BOOK3S_64
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG1
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG2
+#endif
+
+#ifdef CONFIG_PPC_BOOK3S_32
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
+#define SPRN_SPRG_RTAS          SPRN_SPRG2
+#define SPRN_SPRG_603_LRU       SPRN_SPRG4
+#endif
+
+#ifdef CONFIG_40x
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
+#define SPRN_SPRG_SCRATCH2      SPRN_SPRG2
+#define SPRN_SPRG_SCRATCH3      SPRN_SPRG4
+#define SPRN_SPRG_SCRATCH4      SPRN_SPRG5
+#define SPRN_SPRG_SCRATCH5      SPRN_SPRG6
+#define SPRN_SPRG_SCRATCH6      SPRN_SPRG7
+#endif
+
+#ifdef CONFIG_BOOKE
+#define SPRN_SPRG_RSCRATCH0     SPRN_SPRG0
+#define SPRN_SPRG_WSCRATCH0     SPRN_SPRG0
+#define SPRN_SPRG_RSCRATCH1     SPRN_SPRG1
+#define SPRN_SPRG_WSCRATCH1     SPRN_SPRG1
+#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
+#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
+#define SPRN_SPRG_RSCRATCH2     SPRN_SPRG4R
+#define SPRN_SPRG_WSCRATCH2     SPRN_SPRG4W
+#define SPRN_SPRG_RSCRATCH3     SPRN_SPRG5R
+#define SPRN_SPRG_WSCRATCH3     SPRN_SPRG5W
+#define SPRN_SPRG_RSCRATCH_MC   SPRN_SPRG6R
+#define SPRN_SPRG_WSCRATCH_MC   SPRN_SPRG6W
+#define SPRN_SPRG_RSCRATCH4     SPRN_SPRG7R
+#define SPRN_SPRG_WSCRATCH4     SPRN_SPRG7W
+#ifdef CONFIG_E200
+#define SPRN_SPRG_RSCRATCH_DBG  SPRN_SPRG6R
+#define SPRN_SPRG_WSCRATCH_DBG  SPRN_SPRG6W
+#else
+#define SPRN_SPRG_RSCRATCH_DBG  SPRN_SPRG9
+#define SPRN_SPRG_WSCRATCH_DBG  SPRN_SPRG9
+#endif
+#define SPRN_SPRG_RVCPU         SPRN_SPRG1
+#define SPRN_SPRG_WVCPU         SPRN_SPRG1
+#endif
+
+#ifdef CONFIG_8xx
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
+#endif
+
+/*
  * An mtfsf instruction with the L bit set. On CPUs that support this a
  * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
  *