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authorLinus Torvalds <torvalds@linux-foundation.org>2010-08-05 12:03:46 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-05 12:03:46 -0400
commitcdd854bc42b5e6c79bbbc40c6600d995ffe6e747 (patch)
tree18c4dcc07bbb8aeb2b23bc812cd60cc293f36cd8 /arch/powerpc/boot
parentbbc4fd12a635492ad9d12bb418124fa2d5f0d734 (diff)
parent42a0ae2282b512d1a8f6f020327f5f7b8f31a5ea (diff)
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (79 commits) powerpc/8xx: Add support for the MPC8xx based boards from TQC powerpc/85xx: Introduce support for the Freescale P1022DS reference board powerpc/85xx: Adding DTS for the STx GP3-SSA MPC8555 board powerpc/85xx: Change deprecated binding for 85xx-based boards powerpc/tqm85xx: add a quirk for ti1520 PCMCIA bridge powerpc/tqm85xx: update PCI interrupt-map attribute powerpc/mpc8308rdb: support for MPC8308RDB board from Freescale powerpc/fsl_pci: add quirk for mpc8308 pcie bridge powerpc/85xx: Cleanup QE initialization for MPC85xxMDS boards powerpc/85xx: Fix booting for P1021MDS boards powerpc/85xx: Fix SWIOTLB initalization for MPC85xxMDS boards powerpc/85xx: kexec for SMP 85xx BookE systems powerpc/5200/i2c: improve i2c bus error recovery of/xilinxfb: update tft compatible versions powerpc/fsl-diu-fb: Support setting display mode using EDID powerpc/5121: doc/dts-bindings: update doc of FSL DIU bindings powerpc/5121: shared DIU framebuffer support powerpc/5121: move fsl-diu-fb.h to include/linux powerpc/5121: fsl-diu-fb: fix issue with re-enabling DIU area descriptor powerpc/512x: add clock structure for Video-IN (VIU) unit ...
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts4
-rw-r--r--arch/powerpc/boot/dts/glacier.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8308rdb.dts303
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts4
-rw-r--r--arch/powerpc/boot/dts/p1021mds.dts1
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts633
-rw-r--r--arch/powerpc/boot/dts/pdm360ng.dts410
-rw-r--r--arch/powerpc/boot/dts/stxssa8555.dts380
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8548-bigflash.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8548.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8xx.dts172
21 files changed, 1965 insertions, 24 deletions
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index cd56bb5b347..5806ef0b860 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -270,7 +270,7 @@
270 clock-frequency = <0>; /* Filled in by U-Boot */ 270 clock-frequency = <0>; /* Filled in by U-Boot */
271 current-speed = <0>; /* Filled in by U-Boot */ 271 current-speed = <0>; /* Filled in by U-Boot */
272 interrupt-parent = <&UIC1>; 272 interrupt-parent = <&UIC1>;
273 interrupts = <0x1d 0x4>; 273 interrupts = <28 0x4>;
274 }; 274 };
275 275
276 UART3: serial@ef600600 { 276 UART3: serial@ef600600 {
@@ -281,7 +281,7 @@
281 clock-frequency = <0>; /* Filled in by U-Boot */ 281 clock-frequency = <0>; /* Filled in by U-Boot */
282 current-speed = <0>; /* Filled in by U-Boot */ 282 current-speed = <0>; /* Filled in by U-Boot */
283 interrupt-parent = <&UIC1>; 283 interrupt-parent = <&UIC1>;
284 interrupts = <0x1e 0x4>; 284 interrupts = <29 0x4>;
285 }; 285 };
286 286
287 IIC0: i2c@ef600700 { 287 IIC0: i2c@ef600700 {
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
index d62a4fb6f93..e618fc4cbc9 100644
--- a/arch/powerpc/boot/dts/glacier.dts
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -259,7 +259,7 @@
259 clock-frequency = <0>; /* Filled in by U-Boot */ 259 clock-frequency = <0>; /* Filled in by U-Boot */
260 current-speed = <0>; /* Filled in by U-Boot */ 260 current-speed = <0>; /* Filled in by U-Boot */
261 interrupt-parent = <&UIC1>; 261 interrupt-parent = <&UIC1>;
262 interrupts = <0x1d 0x4>; 262 interrupts = <28 0x4>;
263 }; 263 };
264 264
265 UART3: serial@ef600600 { 265 UART3: serial@ef600600 {
@@ -270,7 +270,7 @@
270 clock-frequency = <0>; /* Filled in by U-Boot */ 270 clock-frequency = <0>; /* Filled in by U-Boot */
271 current-speed = <0>; /* Filled in by U-Boot */ 271 current-speed = <0>; /* Filled in by U-Boot */
272 interrupt-parent = <&UIC1>; 272 interrupt-parent = <&UIC1>;
273 interrupts = <0x1e 0x4>; 273 interrupts = <29 0x4>;
274 }; 274 };
275 275
276 IIC0: i2c@ef600700 { 276 IIC0: i2c@ef600700 {
diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts
new file mode 100644
index 00000000000..a97eb2db5a1
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8308rdb.dts
@@ -0,0 +1,303 @@
1/*
2 * MPC8308RDB Device Tree Source
3 *
4 * Copyright 2009 Freescale Semiconductor Inc.
5 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16 compatible = "fsl,mpc8308rdb";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 PowerPC,8308@0 {
33 device_type = "cpu";
34 reg = <0x0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <16384>;
38 i-cache-size = <16384>;
39 timebase-frequency = <0>; // from bootloader
40 bus-frequency = <0>; // from bootloader
41 clock-frequency = <0>; // from bootloader
42 };
43 };
44
45 memory {
46 device_type = "memory";
47 reg = <0x00000000 0x08000000>; // 128MB at 0
48 };
49
50 localbus@e0005000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
54 reg = <0xe0005000 0x1000>;
55 interrupts = <77 0x8>;
56 interrupt-parent = <&ipic>;
57
58 // CS0 and CS1 are swapped when
59 // booting from nand, but the
60 // addresses are the same.
61 ranges = <0x0 0x0 0xfe000000 0x00800000
62 0x1 0x0 0xe0600000 0x00002000
63 0x2 0x0 0xf0000000 0x00020000
64 0x3 0x0 0xfa000000 0x00008000>;
65
66 flash@0,0 {
67 #address-cells = <1>;
68 #size-cells = <1>;
69 compatible = "cfi-flash";
70 reg = <0x0 0x0 0x800000>;
71 bank-width = <2>;
72 device-width = <1>;
73
74 u-boot@0 {
75 reg = <0x0 0x60000>;
76 read-only;
77 };
78 env@60000 {
79 reg = <0x60000 0x10000>;
80 };
81 env1@70000 {
82 reg = <0x70000 0x10000>;
83 };
84 kernel@80000 {
85 reg = <0x80000 0x200000>;
86 };
87 dtb@280000 {
88 reg = <0x280000 0x10000>;
89 };
90 ramdisk@290000 {
91 reg = <0x290000 0x570000>;
92 };
93 };
94
95 nand@1,0 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 compatible = "fsl,mpc8315-fcm-nand",
99 "fsl,elbc-fcm-nand";
100 reg = <0x1 0x0 0x2000>;
101
102 jffs2@0 {
103 reg = <0x0 0x2000000>;
104 };
105 };
106 };
107
108 immr@e0000000 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 device_type = "soc";
112 compatible = "fsl,mpc8315-immr", "simple-bus";
113 ranges = <0 0xe0000000 0x00100000>;
114 reg = <0xe0000000 0x00000200>;
115 bus-frequency = <0>;
116
117 i2c@3000 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 cell-index = <0>;
121 compatible = "fsl-i2c";
122 reg = <0x3000 0x100>;
123 interrupts = <14 0x8>;
124 interrupt-parent = <&ipic>;
125 dfsrr;
126 rtc@68 {
127 compatible = "dallas,ds1339";
128 reg = <0x68>;
129 };
130 };
131
132 usb@23000 {
133 compatible = "fsl-usb2-dr";
134 reg = <0x23000 0x1000>;
135 #address-cells = <1>;
136 #size-cells = <0>;
137 interrupt-parent = <&ipic>;
138 interrupts = <38 0x8>;
139 dr_mode = "peripheral";
140 phy_type = "ulpi";
141 };
142
143 enet0: ethernet@24000 {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 ranges = <0x0 0x24000 0x1000>;
147
148 cell-index = <0>;
149 device_type = "network";
150 model = "eTSEC";
151 compatible = "gianfar";
152 reg = <0x24000 0x1000>;
153 local-mac-address = [ 00 00 00 00 00 00 ];
154 interrupts = <32 0x8 33 0x8 34 0x8>;
155 interrupt-parent = <&ipic>;
156 tbi-handle = < &tbi0 >;
157 phy-handle = < &phy2 >;
158 fsl,magic-packet;
159
160 mdio@520 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,gianfar-mdio";
164 reg = <0x520 0x20>;
165 phy2: ethernet-phy@2 {
166 interrupt-parent = <&ipic>;
167 interrupts = <17 0x8>;
168 reg = <0x2>;
169 device_type = "ethernet-phy";
170 };
171 tbi0: tbi-phy@11 {
172 reg = <0x11>;
173 device_type = "tbi-phy";
174 };
175 };
176 };
177
178 enet1: ethernet@25000 {
179 #address-cells = <1>;
180 #size-cells = <1>;
181 cell-index = <1>;
182 device_type = "network";
183 model = "eTSEC";
184 compatible = "gianfar";
185 reg = <0x25000 0x1000>;
186 ranges = <0x0 0x25000 0x1000>;
187 local-mac-address = [ 00 00 00 00 00 00 ];
188 interrupts = <35 0x8 36 0x8 37 0x8>;
189 interrupt-parent = <&ipic>;
190 tbi-handle = < &tbi1 >;
191 /* Vitesse 7385 isn't on the MDIO bus */
192 fixed-link = <1 1 1000 0 0>;
193 fsl,magic-packet;
194
195 mdio@520 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 compatible = "fsl,gianfar-tbi";
199 reg = <0x520 0x20>;
200
201 tbi1: tbi-phy@11 {
202 reg = <0x11>;
203 device_type = "tbi-phy";
204 };
205 };
206 };
207
208 serial0: serial@4500 {
209 cell-index = <0>;
210 device_type = "serial";
211 compatible = "ns16550";
212 reg = <0x4500 0x100>;
213 clock-frequency = <133333333>;
214 interrupts = <9 0x8>;
215 interrupt-parent = <&ipic>;
216 };
217
218 serial1: serial@4600 {
219 cell-index = <1>;
220 device_type = "serial";
221 compatible = "ns16550";
222 reg = <0x4600 0x100>;
223 clock-frequency = <133333333>;
224 interrupts = <10 0x8>;
225 interrupt-parent = <&ipic>;
226 };
227
228 gpio@c00 {
229 #gpio-cells = <2>;
230 device_type = "gpio";
231 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
232 reg = <0xc00 0x18>;
233 interrupts = <74 0x8>;
234 interrupt-parent = <&ipic>;
235 gpio-controller;
236 };
237
238 /* IPIC
239 * interrupts cell = <intr #, sense>
240 * sense values match linux IORESOURCE_IRQ_* defines:
241 * sense == 8: Level, low assertion
242 * sense == 2: Edge, high-to-low change
243 */
244 ipic: interrupt-controller@700 {
245 compatible = "fsl,ipic";
246 interrupt-controller;
247 #address-cells = <0>;
248 #interrupt-cells = <2>;
249 reg = <0x700 0x100>;
250 device_type = "ipic";
251 };
252
253 ipic-msi@7c0 {
254 compatible = "fsl,ipic-msi";
255 reg = <0x7c0 0x40>;
256 msi-available-ranges = <0x0 0x100>;
257 interrupts = < 0x43 0x8
258 0x4 0x8
259 0x51 0x8
260 0x52 0x8
261 0x56 0x8
262 0x57 0x8
263 0x58 0x8
264 0x59 0x8 >;
265 interrupt-parent = < &ipic >;
266 };
267
268 };
269
270 pci0: pcie@e0009000 {
271 #address-cells = <3>;
272 #size-cells = <2>;
273 #interrupt-cells = <1>;
274 device_type = "pci";
275 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
276 reg = <0xe0009000 0x00001000
277 0xb0000000 0x01000000>;
278 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
279 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
280 bus-range = <0 0>;
281 interrupt-map-mask = <0xf800 0 0 7>;
282 interrupt-map = <0 0 0 1 &ipic 1 8
283 0 0 0 2 &ipic 1 8
284 0 0 0 3 &ipic 1 8
285 0 0 0 4 &ipic 1 8>;
286 interrupts = <0x1 0x8>;
287 interrupt-parent = <&ipic>;
288 clock-frequency = <0>;
289
290 pcie@0 {
291 #address-cells = <3>;
292 #size-cells = <2>;
293 device_type = "pci";
294 reg = <0 0 0 0 0>;
295 ranges = <0x02000000 0 0xa0000000
296 0x02000000 0 0xa0000000
297 0 0x10000000
298 0x01000000 0 0x00000000
299 0x01000000 0 0x00000000
300 0 0x00800000>;
301 };
302 };
303};
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 9dc292962a9..8d1bf0fd926 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -71,14 +71,14 @@
71 }; 71 };
72 72
73 memory-controller@2000 { 73 memory-controller@2000 {
74 compatible = "fsl,8540-memory-controller"; 74 compatible = "fsl,mpc8540-memory-controller";
75 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>; 77 interrupts = <18 2>;
78 }; 78 };
79 79
80 L2: l2-cache-controller@20000 { 80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8540-l2-cache-controller"; 81 compatible = "fsl,mpc8540-l2-cache-controller";
82 reg = <0x20000 0x1000>; 82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes 83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K 84 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 9a3ad311aed..87ff96549fa 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -71,14 +71,14 @@
71 }; 71 };
72 72
73 memory-controller@2000 { 73 memory-controller@2000 {
74 compatible = "fsl,8541-memory-controller"; 74 compatible = "fsl,mpc8541-memory-controller";
75 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>; 77 interrupts = <18 2>;
78 }; 78 };
79 79
80 L2: l2-cache-controller@20000 { 80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8541-l2-cache-controller"; 81 compatible = "fsl,mpc8541-l2-cache-controller";
82 reg = <0x20000 0x1000>; 82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes 83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K 84 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 98e94b46566..d793968743c 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -73,14 +73,14 @@
73 }; 73 };
74 74
75 memory-controller@2000 { 75 memory-controller@2000 {
76 compatible = "fsl,8544-memory-controller"; 76 compatible = "fsl,mpc8544-memory-controller";
77 reg = <0x2000 0x1000>; 77 reg = <0x2000 0x1000>;
78 interrupt-parent = <&mpic>; 78 interrupt-parent = <&mpic>;
79 interrupts = <18 2>; 79 interrupts = <18 2>;
80 }; 80 };
81 81
82 L2: l2-cache-controller@20000 { 82 L2: l2-cache-controller@20000 {
83 compatible = "fsl,8544-l2-cache-controller"; 83 compatible = "fsl,mpc8544-l2-cache-controller";
84 reg = <0x20000 0x1000>; 84 reg = <0x20000 0x1000>;
85 cache-line-size = <32>; // 32 bytes 85 cache-line-size = <32>; // 32 bytes
86 cache-size = <0x40000>; // L2, 256K 86 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 0f526245268..a17a5572fb7 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -74,14 +74,14 @@
74 }; 74 };
75 75
76 memory-controller@2000 { 76 memory-controller@2000 {
77 compatible = "fsl,8548-memory-controller"; 77 compatible = "fsl,mpc8548-memory-controller";
78 reg = <0x2000 0x1000>; 78 reg = <0x2000 0x1000>;
79 interrupt-parent = <&mpic>; 79 interrupt-parent = <&mpic>;
80 interrupts = <18 2>; 80 interrupts = <18 2>;
81 }; 81 };
82 82
83 L2: l2-cache-controller@20000 { 83 L2: l2-cache-controller@20000 {
84 compatible = "fsl,8548-l2-cache-controller"; 84 compatible = "fsl,mpc8548-l2-cache-controller";
85 reg = <0x20000 0x1000>; 85 reg = <0x20000 0x1000>;
86 cache-line-size = <32>; // 32 bytes 86 cache-line-size = <32>; // 32 bytes
87 cache-size = <0x80000>; // L2, 512K 87 cache-size = <0x80000>; // L2, 512K
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 065b2f093de..5c5614f9eb1 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -71,14 +71,14 @@
71 }; 71 };
72 72
73 memory-controller@2000 { 73 memory-controller@2000 {
74 compatible = "fsl,8555-memory-controller"; 74 compatible = "fsl,mpc8555-memory-controller";
75 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>; 77 interrupts = <18 2>;
78 }; 78 };
79 79
80 L2: l2-cache-controller@20000 { 80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8555-l2-cache-controller"; 81 compatible = "fsl,mpc8555-l2-cache-controller";
82 reg = <0x20000 0x1000>; 82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes 83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K 84 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index a5bb1ec70a5..6e85e1ba085 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -71,14 +71,14 @@
71 }; 71 };
72 72
73 memory-controller@2000 { 73 memory-controller@2000 {
74 compatible = "fsl,8540-memory-controller"; 74 compatible = "fsl,mpc8540-memory-controller";
75 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>; 77 interrupts = <18 2>;
78 }; 78 };
79 79
80 L2: l2-cache-controller@20000 { 80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8540-l2-cache-controller"; 81 compatible = "fsl,mpc8540-l2-cache-controller";
82 reg = <0x20000 0x1000>; 82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes 83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K 84 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 92fb17876e7..30cf0e098bb 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -124,14 +124,14 @@
124 }; 124 };
125 125
126 memory-controller@2000 { 126 memory-controller@2000 {
127 compatible = "fsl,8568-memory-controller"; 127 compatible = "fsl,mpc8568-memory-controller";
128 reg = <0x2000 0x1000>; 128 reg = <0x2000 0x1000>;
129 interrupt-parent = <&mpic>; 129 interrupt-parent = <&mpic>;
130 interrupts = <18 2>; 130 interrupts = <18 2>;
131 }; 131 };
132 132
133 L2: l2-cache-controller@20000 { 133 L2: l2-cache-controller@20000 {
134 compatible = "fsl,8568-l2-cache-controller"; 134 compatible = "fsl,mpc8568-l2-cache-controller";
135 reg = <0x20000 0x1000>; 135 reg = <0x20000 0x1000>;
136 cache-line-size = <32>; // 32 bytes 136 cache-line-size = <32>; // 32 bytes
137 cache-size = <0x80000>; // L2, 512K 137 cache-size = <0x80000>; // L2, 512K
diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts
index 7fad2df2598..ad5b8526900 100644
--- a/arch/powerpc/boot/dts/p1021mds.dts
+++ b/arch/powerpc/boot/dts/p1021mds.dts
@@ -617,6 +617,7 @@
617 bus-frequency = <0>; 617 bus-frequency = <0>;
618 fsl,qe-num-riscs = <1>; 618 fsl,qe-num-riscs = <1>;
619 fsl,qe-num-snums = <28>; 619 fsl,qe-num-snums = <28>;
620 status = "disabled"; /* no firmware loaded */
620 621
621 qeic: interrupt-controller@80 { 622 qeic: interrupt-controller@80 {
622 interrupt-controller; 623 interrupt-controller;
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
new file mode 100644
index 00000000000..8bcb10b9267
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -0,0 +1,633 @@
1/*
2 * P1022 DS 36Bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12/ {
13 model = "fsl,P1022";
14 compatible = "fsl,P1022DS";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&mpic>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P1022@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P1022@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 };
49
50 localbus@fffe05000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>;
56
57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
58 0x1 0x0 0xf 0xe0000000 0x08000000
59 0x2 0x0 0x0 0xffa00000 0x00040000
60 0x3 0x0 0xf 0xffdf0000 0x00008000>;
61
62 nor@0,0 {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "cfi-flash";
66 reg = <0x0 0x0 0x8000000>;
67 bank-width = <2>;
68 device-width = <1>;
69
70 partition@0 {
71 reg = <0x0 0x03000000>;
72 label = "ramdisk-nor";
73 read-only;
74 };
75
76 partition@3000000 {
77 reg = <0x03000000 0x00e00000>;
78 label = "diagnostic-nor";
79 read-only;
80 };
81
82 partition@3e00000 {
83 reg = <0x03e00000 0x00200000>;
84 label = "dink-nor";
85 read-only;
86 };
87
88 partition@4000000 {
89 reg = <0x04000000 0x00400000>;
90 label = "kernel-nor";
91 read-only;
92 };
93
94 partition@4400000 {
95 reg = <0x04400000 0x03b00000>;
96 label = "jffs2-nor";
97 };
98
99 partition@7f00000 {
100 reg = <0x07f00000 0x00080000>;
101 label = "dtb-nor";
102 read-only;
103 };
104
105 partition@7f80000 {
106 reg = <0x07f80000 0x00080000>;
107 label = "u-boot-nor";
108 read-only;
109 };
110 };
111
112 nand@2,0 {
113 #address-cells = <1>;
114 #size-cells = <1>;
115 compatible = "fsl,elbc-fcm-nand";
116 reg = <0x2 0x0 0x40000>;
117
118 partition@0 {
119 reg = <0x0 0x02000000>;
120 label = "u-boot-nand";
121 read-only;
122 };
123
124 partition@2000000 {
125 reg = <0x02000000 0x10000000>;
126 label = "jffs2-nand";
127 };
128
129 partition@12000000 {
130 reg = <0x12000000 0x10000000>;
131 label = "ramdisk-nand";
132 read-only;
133 };
134
135 partition@22000000 {
136 reg = <0x22000000 0x04000000>;
137 label = "kernel-nand";
138 };
139
140 partition@26000000 {
141 reg = <0x26000000 0x01000000>;
142 label = "dtb-nand";
143 read-only;
144 };
145
146 partition@27000000 {
147 reg = <0x27000000 0x19000000>;
148 label = "reserved-nand";
149 };
150 };
151 };
152
153 soc@fffe00000 {
154 #address-cells = <1>;
155 #size-cells = <1>;
156 device_type = "soc";
157 compatible = "fsl,p1022-immr", "simple-bus";
158 ranges = <0x0 0xf 0xffe00000 0x100000>;
159 bus-frequency = <0>; // Filled out by uboot.
160
161 ecm-law@0 {
162 compatible = "fsl,ecm-law";
163 reg = <0x0 0x1000>;
164 fsl,num-laws = <12>;
165 };
166
167 ecm@1000 {
168 compatible = "fsl,p1022-ecm", "fsl,ecm";
169 reg = <0x1000 0x1000>;
170 interrupts = <16 2>;
171 };
172
173 memory-controller@2000 {
174 compatible = "fsl,p1022-memory-controller";
175 reg = <0x2000 0x1000>;
176 interrupts = <16 2>;
177 };
178
179 i2c@3000 {
180 #address-cells = <1>;
181 #size-cells = <0>;
182 cell-index = <0>;
183 compatible = "fsl-i2c";
184 reg = <0x3000 0x100>;
185 interrupts = <43 2>;
186 dfsrr;
187 };
188
189 i2c@3100 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 cell-index = <1>;
193 compatible = "fsl-i2c";
194 reg = <0x3100 0x100>;
195 interrupts = <43 2>;
196 dfsrr;
197
198 wm8776:codec@1a {
199 compatible = "wlf,wm8776";
200 reg = <0x1a>;
201 /* MCLK source is a stand-alone oscillator */
202 clock-frequency = <12288000>;
203 };
204 };
205
206 serial0: serial@4500 {
207 cell-index = <0>;
208 device_type = "serial";
209 compatible = "ns16550";
210 reg = <0x4500 0x100>;
211 clock-frequency = <0>;
212 interrupts = <42 2>;
213 };
214
215 serial1: serial@4600 {
216 cell-index = <1>;
217 device_type = "serial";
218 compatible = "ns16550";
219 reg = <0x4600 0x100>;
220 clock-frequency = <0>;
221 interrupts = <42 2>;
222 };
223
224 spi@7000 {
225 cell-index = <0>;
226 #address-cells = <1>;
227 #size-cells = <0>;
228 compatible = "fsl,espi";
229 reg = <0x7000 0x1000>;
230 interrupts = <59 0x2>;
231 espi,num-ss-bits = <4>;
232 mode = "cpu";
233
234 fsl_m25p80@0 {
235 #address-cells = <1>;
236 #size-cells = <1>;
237 compatible = "fsl,espi-flash";
238 reg = <0>;
239 linux,modalias = "fsl_m25p80";
240 spi-max-frequency = <40000000>; /* input clock */
241 partition@0 {
242 label = "u-boot-spi";
243 reg = <0x00000000 0x00100000>;
244 read-only;
245 };
246 partition@100000 {
247 label = "kernel-spi";
248 reg = <0x00100000 0x00500000>;
249 read-only;
250 };
251 partition@600000 {
252 label = "dtb-spi";
253 reg = <0x00600000 0x00100000>;
254 read-only;
255 };
256 partition@700000 {
257 label = "file system-spi";
258 reg = <0x00700000 0x00900000>;
259 };
260 };
261 };
262
263 ssi@15000 {
264 compatible = "fsl,mpc8610-ssi";
265 cell-index = <0>;
266 reg = <0x15000 0x100>;
267 interrupts = <75 2>;
268 fsl,mode = "i2s-slave";
269 codec-handle = <&wm8776>;
270 fsl,playback-dma = <&dma00>;
271 fsl,capture-dma = <&dma01>;
272 fsl,fifo-depth = <16>;
273 };
274
275 dma@c300 {
276 #address-cells = <1>;
277 #size-cells = <1>;
278 compatible = "fsl,eloplus-dma";
279 reg = <0xc300 0x4>;
280 ranges = <0x0 0xc100 0x200>;
281 cell-index = <1>;
282 dma00: dma-channel@0 {
283 compatible = "fsl,eloplus-dma-channel";
284 reg = <0x0 0x80>;
285 cell-index = <0>;
286 interrupts = <76 2>;
287 };
288 dma01: dma-channel@80 {
289 compatible = "fsl,eloplus-dma-channel";
290 reg = <0x80 0x80>;
291 cell-index = <1>;
292 interrupts = <77 2>;
293 };
294 dma-channel@100 {
295 compatible = "fsl,eloplus-dma-channel";
296 reg = <0x100 0x80>;
297 cell-index = <2>;
298 interrupts = <78 2>;
299 };
300 dma-channel@180 {
301 compatible = "fsl,eloplus-dma-channel";
302 reg = <0x180 0x80>;
303 cell-index = <3>;
304 interrupts = <79 2>;
305 };
306 };
307
308 gpio: gpio-controller@f000 {
309 #gpio-cells = <2>;
310 compatible = "fsl,mpc8572-gpio";
311 reg = <0xf000 0x100>;
312 interrupts = <47 0x2>;
313 gpio-controller;
314 };
315
316 L2: l2-cache-controller@20000 {
317 compatible = "fsl,p1022-l2-cache-controller";
318 reg = <0x20000 0x1000>;
319 cache-line-size = <32>; // 32 bytes
320 cache-size = <0x40000>; // L2, 256K
321 interrupts = <16 2>;
322 };
323
324 dma@21300 {
325 #address-cells = <1>;
326 #size-cells = <1>;
327 compatible = "fsl,eloplus-dma";
328 reg = <0x21300 0x4>;
329 ranges = <0x0 0x21100 0x200>;
330 cell-index = <0>;
331 dma-channel@0 {
332 compatible = "fsl,eloplus-dma-channel";
333 reg = <0x0 0x80>;
334 cell-index = <0>;
335 interrupts = <20 2>;
336 };
337 dma-channel@80 {
338 compatible = "fsl,eloplus-dma-channel";
339 reg = <0x80 0x80>;
340 cell-index = <1>;
341 interrupts = <21 2>;
342 };
343 dma-channel@100 {
344 compatible = "fsl,eloplus-dma-channel";
345 reg = <0x100 0x80>;
346 cell-index = <2>;
347 interrupts = <22 2>;
348 };
349 dma-channel@180 {
350 compatible = "fsl,eloplus-dma-channel";
351 reg = <0x180 0x80>;
352 cell-index = <3>;
353 interrupts = <23 2>;
354 };
355 };
356
357 usb@22000 {
358 #address-cells = <1>;
359 #size-cells = <0>;
360 compatible = "fsl-usb2-dr";
361 reg = <0x22000 0x1000>;
362 interrupts = <28 0x2>;
363 phy_type = "ulpi";
364 };
365
366 mdio@24000 {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 compatible = "fsl,etsec2-mdio";
370 reg = <0x24000 0x1000 0xb0030 0x4>;
371
372 phy0: ethernet-phy@0 {
373 interrupts = <3 1>;
374 reg = <0x1>;
375 };
376 phy1: ethernet-phy@1 {
377 interrupts = <9 1>;
378 reg = <0x2>;
379 };
380 };
381
382 mdio@25000 {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 compatible = "fsl,etsec2-mdio";
386 reg = <0x25000 0x1000 0xb1030 0x4>;
387 };
388
389 enet0: ethernet@B0000 {
390 #address-cells = <1>;
391 #size-cells = <1>;
392 cell-index = <0>;
393 device_type = "network";
394 model = "eTSEC";
395 compatible = "fsl,etsec2";
396 fsl,num_rx_queues = <0x8>;
397 fsl,num_tx_queues = <0x8>;
398 fsl,magic-packet;
399 fsl,wake-on-filer;
400 local-mac-address = [ 00 00 00 00 00 00 ];
401 fixed-link = <1 1 1000 0 0>;
402 phy-handle = <&phy0>;
403 phy-connection-type = "rgmii-id";
404 queue-group@0{
405 #address-cells = <1>;
406 #size-cells = <1>;
407 reg = <0xB0000 0x1000>;
408 interrupts = <29 2 30 2 34 2>;
409 };
410 queue-group@1{
411 #address-cells = <1>;
412 #size-cells = <1>;
413 reg = <0xB4000 0x1000>;
414 interrupts = <17 2 18 2 24 2>;
415 };
416 };
417
418 enet1: ethernet@B1000 {
419 #address-cells = <1>;
420 #size-cells = <1>;
421 cell-index = <0>;
422 device_type = "network";
423 model = "eTSEC";
424 compatible = "fsl,etsec2";
425 fsl,num_rx_queues = <0x8>;
426 fsl,num_tx_queues = <0x8>;
427 local-mac-address = [ 00 00 00 00 00 00 ];
428 fixed-link = <1 1 1000 0 0>;
429 phy-handle = <&phy1>;
430 phy-connection-type = "rgmii-id";
431 queue-group@0{
432 #address-cells = <1>;
433 #size-cells = <1>;
434 reg = <0xB1000 0x1000>;
435 interrupts = <35 2 36 2 40 2>;
436 };
437 queue-group@1{
438 #address-cells = <1>;
439 #size-cells = <1>;
440 reg = <0xB5000 0x1000>;
441 interrupts = <51 2 52 2 67 2>;
442 };
443 };
444
445 sdhci@2e000 {
446 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
447 reg = <0x2e000 0x1000>;
448 interrupts = <72 0x2>;
449 fsl,sdhci-auto-cmd12;
450 /* Filled in by U-Boot */
451 clock-frequency = <0>;
452 };
453
454 crypto@30000 {
455 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
456 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
457 "fsl,sec2.0";
458 reg = <0x30000 0x10000>;
459 interrupts = <45 2 58 2>;
460 fsl,num-channels = <4>;
461 fsl,channel-fifo-len = <24>;
462 fsl,exec-units-mask = <0x97c>;
463 fsl,descriptor-types-mask = <0x3a30abf>;
464 };
465
466 sata@18000 {
467 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
468 reg = <0x18000 0x1000>;
469 cell-index = <1>;
470 interrupts = <74 0x2>;
471 };
472
473 sata@19000 {
474 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
475 reg = <0x19000 0x1000>;
476 cell-index = <2>;
477 interrupts = <41 0x2>;
478 };
479
480 power@e0070{
481 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
482 reg = <0xe0070 0x20>;
483 };
484
485 display@10000 {
486 compatible = "fsl,diu", "fsl,p1022-diu";
487 reg = <0x10000 1000>;
488 interrupts = <64 2>;
489 };
490
491 timer@41100 {
492 compatible = "fsl,mpic-global-timer";
493 reg = <0x41100 0x204>;
494 interrupts = <0xf7 0x2>;
495 };
496
497 mpic: pic@40000 {
498 interrupt-controller;
499 #address-cells = <0>;
500 #interrupt-cells = <2>;
501 reg = <0x40000 0x40000>;
502 compatible = "chrp,open-pic";
503 device_type = "open-pic";
504 };
505
506 msi@41600 {
507 compatible = "fsl,p1022-msi", "fsl,mpic-msi";
508 reg = <0x41600 0x80>;
509 msi-available-ranges = <0 0x100>;
510 interrupts = <
511 0xe0 0
512 0xe1 0
513 0xe2 0
514 0xe3 0
515 0xe4 0
516 0xe5 0
517 0xe6 0
518 0xe7 0>;
519 };
520
521 global-utilities@e0000 { //global utilities block
522 compatible = "fsl,p1022-guts";
523 reg = <0xe0000 0x1000>;
524 fsl,has-rstcr;
525 };
526 };
527
528 pci0: pcie@fffe09000 {
529 compatible = "fsl,p1022-pcie";
530 device_type = "pci";
531 #interrupt-cells = <1>;
532 #size-cells = <2>;
533 #address-cells = <3>;
534 reg = <0xf 0xffe09000 0 0x1000>;
535 bus-range = <0 255>;
536 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
537 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
538 clock-frequency = <33333333>;
539 interrupts = <16 2>;
540 interrupt-map-mask = <0xf800 0 0 7>;
541 interrupt-map = <
542 /* IDSEL 0x0 */
543 0000 0 0 1 &mpic 4 1
544 0000 0 0 2 &mpic 5 1
545 0000 0 0 3 &mpic 6 1
546 0000 0 0 4 &mpic 7 1
547 >;
548 pcie@0 {
549 reg = <0x0 0x0 0x0 0x0 0x0>;
550 #size-cells = <2>;
551 #address-cells = <3>;
552 device_type = "pci";
553 ranges = <0x2000000 0x0 0xe0000000
554 0x2000000 0x0 0xe0000000
555 0x0 0x20000000
556
557 0x1000000 0x0 0x0
558 0x1000000 0x0 0x0
559 0x0 0x100000>;
560 };
561 };
562
563 pci1: pcie@fffe0a000 {
564 compatible = "fsl,p1022-pcie";
565 device_type = "pci";
566 #interrupt-cells = <1>;
567 #size-cells = <2>;
568 #address-cells = <3>;
569 reg = <0xf 0xffe0a000 0 0x1000>;
570 bus-range = <0 255>;
571 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
572 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
573 clock-frequency = <33333333>;
574 interrupts = <16 2>;
575 interrupt-map-mask = <0xf800 0 0 7>;
576 interrupt-map = <
577 /* IDSEL 0x0 */
578 0000 0 0 1 &mpic 0 1
579 0000 0 0 2 &mpic 1 1
580 0000 0 0 3 &mpic 2 1
581 0000 0 0 4 &mpic 3 1
582 >;
583 pcie@0 {
584 reg = <0x0 0x0 0x0 0x0 0x0>;
585 #size-cells = <2>;
586 #address-cells = <3>;
587 device_type = "pci";
588 ranges = <0x2000000 0x0 0xe0000000
589 0x2000000 0x0 0xe0000000
590 0x0 0x20000000
591
592 0x1000000 0x0 0x0
593 0x1000000 0x0 0x0
594 0x0 0x100000>;
595 };
596 };
597
598
599 pci2: pcie@fffe0b000 {
600 compatible = "fsl,p1022-pcie";
601 device_type = "pci";
602 #interrupt-cells = <1>;
603 #size-cells = <2>;
604 #address-cells = <3>;
605 reg = <0xf 0xffe0b000 0 0x1000>;
606 bus-range = <0 255>;
607 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
608 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
609 clock-frequency = <33333333>;
610 interrupts = <16 2>;
611 interrupt-map-mask = <0xf800 0 0 7>;
612 interrupt-map = <
613 /* IDSEL 0x0 */
614 0000 0 0 1 &mpic 8 1
615 0000 0 0 2 &mpic 9 1
616 0000 0 0 3 &mpic 10 1
617 0000 0 0 4 &mpic 11 1
618 >;
619 pcie@0 {
620 reg = <0x0 0x0 0x0 0x0 0x0>;
621 #size-cells = <2>;
622 #address-cells = <3>;
623 device_type = "pci";
624 ranges = <0x2000000 0x0 0xe0000000
625 0x2000000 0x0 0xe0000000
626 0x0 0x20000000
627
628 0x1000000 0x0 0x0
629 0x1000000 0x0 0x0
630 0x0 0x100000>;
631 };
632 };
633};
diff --git a/arch/powerpc/boot/dts/pdm360ng.dts b/arch/powerpc/boot/dts/pdm360ng.dts
new file mode 100644
index 00000000000..94dfa5c9a7f
--- /dev/null
+++ b/arch/powerpc/boot/dts/pdm360ng.dts
@@ -0,0 +1,410 @@
1/*
2 * Device Tree Source for IFM PDM360NG.
3 *
4 * Copyright 2009 - 2010 DENX Software Engineering.
5 * Anatolij Gustschin <agust@denx.de>
6 *
7 * Based on MPC5121E ADS dts.
8 * Copyright 2008 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16/dts-v1/;
17
18/ {
19 model = "pdm360ng";
20 compatible = "ifm,pdm360ng";
21 #address-cells = <1>;
22 #size-cells = <1>;
23 interrupt-parent = <&ipic>;
24
25 aliases {
26 ethernet0 = &eth0;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,5121@0 {
34 device_type = "cpu";
35 reg = <0>;
36 d-cache-line-size = <0x20>; // 32 bytes
37 i-cache-line-size = <0x20>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
41 bus-frequency = <198000000>; // 198 MHz csb bus
42 clock-frequency = <396000000>; // 396 MHz ppc core
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x20000000>; // 512MB at 0
49 };
50
51 nfc@40000000 {
52 compatible = "fsl,mpc5121-nfc";
53 reg = <0x40000000 0x100000>;
54 interrupts = <0x6 0x8>;
55 #address-cells = <0x1>;
56 #size-cells = <0x1>;
57 bank-width = <0x1>;
58 chips = <0x1>;
59
60 partition@0 {
61 label = "nand0";
62 reg = <0x0 0x40000000>;
63 };
64 };
65
66 sram@50000000 {
67 compatible = "fsl,mpc5121-sram";
68 reg = <0x50000000 0x20000>; // 128K at 0x50000000
69 };
70
71 localbus@80000020 {
72 compatible = "fsl,mpc5121-localbus";
73 #address-cells = <2>;
74 #size-cells = <1>;
75 reg = <0x80000020 0x40>;
76
77 ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */
78 0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */
79
80 flash@0,0 {
81 compatible = "amd,s29gl01gp", "cfi-flash";
82 reg = <0 0x00000000 0x08000000
83 0 0x08000000 0x08000000>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86 bank-width = <4>;
87 device-width = <2>;
88
89 partition@0 {
90 label = "u-boot";
91 reg = <0x00000000 0x00080000>;
92 read-only;
93 };
94 partition@80000 {
95 label = "environment";
96 reg = <0x00080000 0x00080000>;
97 read-only;
98 };
99 partition@100000 {
100 label = "splash-image";
101 reg = <0x00100000 0x00080000>;
102 read-only;
103 };
104 partition@180000 {
105 label = "device-tree";
106 reg = <0x00180000 0x00040000>;
107 };
108 partition@1c0000 {
109 label = "kernel";
110 reg = <0x001c0000 0x00500000>;
111 };
112 partition@6c0000 {
113 label = "filesystem";
114 reg = <0x006c0000 0x07940000>;
115 };
116 };
117
118 mram0@2,0 {
119 compatible = "mtd-ram";
120 reg = <2 0x00000 0x10000>;
121 bank-width = <2>;
122 };
123
124 mram1@2,10000 {
125 compatible = "mtd-ram";
126 reg = <2 0x010000 0x10000>;
127 bank-width = <2>;
128 };
129 };
130
131 soc@80000000 {
132 compatible = "fsl,mpc5121-immr";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 #interrupt-cells = <2>;
136 ranges = <0x0 0x80000000 0x400000>;
137 reg = <0x80000000 0x400000>;
138 bus-frequency = <66000000>; // 66 MHz ips bus
139
140 // IPIC
141 // interrupts cell = <intr #, sense>
142 // sense values match linux IORESOURCE_IRQ_* defines:
143 // sense == 8: Level, low assertion
144 // sense == 2: Edge, high-to-low change
145 //
146 ipic: interrupt-controller@c00 {
147 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
148 interrupt-controller;
149 #address-cells = <0>;
150 #interrupt-cells = <2>;
151 reg = <0xc00 0x100>;
152 };
153
154 rtc@a00 { // Real time clock
155 compatible = "fsl,mpc5121-rtc";
156 reg = <0xa00 0x100>;
157 interrupts = <79 0x8 80 0x8>;
158 };
159
160 reset@e00 { // Reset module
161 compatible = "fsl,mpc5121-reset";
162 reg = <0xe00 0x100>;
163 };
164
165 clock@f00 { // Clock control
166 compatible = "fsl,mpc5121-clock";
167 reg = <0xf00 0x100>;
168 };
169
170 pmc@1000{ //Power Management Controller
171 compatible = "fsl,mpc5121-pmc";
172 reg = <0x1000 0x100>;
173 interrupts = <83 0x2>;
174 };
175
176 gpio@1100 {
177 compatible = "fsl,mpc5121-gpio";
178 reg = <0x1100 0x100>;
179 interrupts = <78 0x8>;
180 };
181
182 can@1300 {
183 compatible = "fsl,mpc5121-mscan";
184 interrupts = <12 0x8>;
185 reg = <0x1300 0x80>;
186 };
187
188 can@1380 {
189 compatible = "fsl,mpc5121-mscan";
190 interrupts = <13 0x8>;
191 reg = <0x1380 0x80>;
192 };
193
194 i2c@1700 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "fsl,mpc5121-i2c";
198 reg = <0x1700 0x20>;
199 interrupts = <0x9 0x8>;
200 fsl,preserve-clocking;
201
202 eeprom@50 {
203 compatible = "at,24c01";
204 reg = <0x50>;
205 };
206
207 rtc@68 {
208 compatible = "stm,m41t00";
209 reg = <0x68>;
210 };
211 };
212
213 i2c@1740 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "fsl,mpc5121-i2c";
217 reg = <0x1740 0x20>;
218 interrupts = <0xb 0x8>;
219 fsl,preserve-clocking;
220 };
221
222 i2ccontrol@1760 {
223 compatible = "fsl,mpc5121-i2c-ctrl";
224 reg = <0x1760 0x8>;
225 };
226
227 axe@2000 {
228 compatible = "fsl,mpc5121-axe";
229 reg = <0x2000 0x100>;
230 interrupts = <42 0x8>;
231 };
232
233 display@2100 {
234 compatible = "fsl,mpc5121-diu";
235 reg = <0x2100 0x100>;
236 interrupts = <64 0x8>;
237 };
238
239 can@2300 {
240 compatible = "fsl,mpc5121-mscan";
241 interrupts = <90 0x8>;
242 reg = <0x2300 0x80>;
243 };
244
245 can@2380 {
246 compatible = "fsl,mpc5121-mscan";
247 interrupts = <91 0x8>;
248 reg = <0x2380 0x80>;
249 };
250
251 viu@2400 {
252 compatible = "fsl,mpc5121-viu";
253 reg = <0x2400 0x400>;
254 interrupts = <67 0x8>;
255 };
256
257 mdio@2800 {
258 compatible = "fsl,mpc5121-fec-mdio";
259 reg = <0x2800 0x200>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 phy: ethernet-phy@0 {
263 compatible = "smsc,lan8700";
264 reg = <0x1f>;
265 };
266 };
267
268 eth0: ethernet@2800 {
269 compatible = "fsl,mpc5121-fec";
270 reg = <0x2800 0x200>;
271 local-mac-address = [ 00 00 00 00 00 00 ];
272 interrupts = <4 0x8>;
273 phy-handle = < &phy >;
274 };
275
276 // USB1 using external ULPI PHY
277 usb@3000 {
278 compatible = "fsl,mpc5121-usb2-dr";
279 reg = <0x3000 0x600>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 interrupts = <43 0x8>;
283 dr_mode = "host";
284 phy_type = "ulpi";
285 };
286
287 // USB0 using internal UTMI PHY
288 usb@4000 {
289 compatible = "fsl,mpc5121-usb2-dr";
290 reg = <0x4000 0x600>;
291 #address-cells = <1>;
292 #size-cells = <0>;
293 interrupts = <44 0x8>;
294 dr_mode = "otg";
295 phy_type = "utmi_wide";
296 fsl,invert-pwr-fault;
297 };
298
299 // IO control
300 ioctl@a000 {
301 compatible = "fsl,mpc5121-ioctl";
302 reg = <0xA000 0x1000>;
303 };
304
305 // 512x PSCs are not 52xx PSCs compatible
306 serial@11000 {
307 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
308 cell-index = <0>;
309 reg = <0x11000 0x100>;
310 interrupts = <40 0x8>;
311 fsl,rx-fifo-size = <16>;
312 fsl,tx-fifo-size = <16>;
313 };
314
315 serial@11100 {
316 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
317 cell-index = <1>;
318 reg = <0x11100 0x100>;
319 interrupts = <40 0x8>;
320 fsl,rx-fifo-size = <16>;
321 fsl,tx-fifo-size = <16>;
322 };
323
324 serial@11200 {
325 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
326 cell-index = <2>;
327 reg = <0x11200 0x100>;
328 interrupts = <40 0x8>;
329 fsl,rx-fifo-size = <16>;
330 fsl,tx-fifo-size = <16>;
331 };
332
333 serial@11300 {
334 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
335 cell-index = <3>;
336 reg = <0x11300 0x100>;
337 interrupts = <40 0x8>;
338 fsl,rx-fifo-size = <16>;
339 fsl,tx-fifo-size = <16>;
340 };
341
342 serial@11400 {
343 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
344 cell-index = <4>;
345 reg = <0x11400 0x100>;
346 interrupts = <40 0x8>;
347 fsl,rx-fifo-size = <16>;
348 fsl,tx-fifo-size = <16>;
349 };
350
351 serial@11600 {
352 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
353 cell-index = <6>;
354 reg = <0x11600 0x100>;
355 interrupts = <40 0x8>;
356 fsl,rx-fifo-size = <16>;
357 fsl,tx-fifo-size = <16>;
358 };
359
360 serial@11800 {
361 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
362 cell-index = <8>;
363 reg = <0x11800 0x100>;
364 interrupts = <40 0x8>;
365 fsl,rx-fifo-size = <16>;
366 fsl,tx-fifo-size = <16>;
367 };
368
369 serial@11B00 {
370 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
371 cell-index = <11>;
372 reg = <0x11B00 0x100>;
373 interrupts = <40 0x8>;
374 fsl,rx-fifo-size = <16>;
375 fsl,tx-fifo-size = <16>;
376 };
377
378 pscfifo@11f00 {
379 compatible = "fsl,mpc5121-psc-fifo";
380 reg = <0x11f00 0x100>;
381 interrupts = <40 0x8>;
382 };
383
384 spi@11900 {
385 compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
386 cell-index = <9>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 reg = <0x11900 0x100>;
390 interrupts = <40 0x8>;
391 fsl,rx-fifo-size = <16>;
392 fsl,tx-fifo-size = <16>;
393
394 // 7845 touch screen controller
395 ts@0 {
396 compatible = "ti,ads7846";
397 reg = <0x0>;
398 spi-max-frequency = <3000000>;
399 // pen irq is GPIO25
400 interrupts = <78 0x8>;
401 };
402 };
403
404 dma@14000 {
405 compatible = "fsl,mpc5121-dma";
406 reg = <0x14000 0x1800>;
407 interrupts = <65 0x8>;
408 };
409 };
410};
diff --git a/arch/powerpc/boot/dts/stxssa8555.dts b/arch/powerpc/boot/dts/stxssa8555.dts
new file mode 100644
index 00000000000..49efd44057d
--- /dev/null
+++ b/arch/powerpc/boot/dts/stxssa8555.dts
@@ -0,0 +1,380 @@
1/*
2 * MPC8555-based STx GP3 Device Tree Source
3 *
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 *
6 * Copyright 2010 Silicon Turnkey Express LLC.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "stx,gp3";
18 compatible = "stx,gp3-8560", "stx,gp3";
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 aliases {
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8555@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>; // 33 MHz, from uboot
42 bus-frequency = <0>; // 166 MHz
43 clock-frequency = <0>; // 825 MHz, from uboot
44 next-level-cache = <&L2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0x00000000 0x10000000>;
51 };
52
53 soc8555@e0000000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 device_type = "soc";
57 compatible = "simple-bus";
58 ranges = <0x0 0xe0000000 0x100000>;
59 bus-frequency = <0>;
60
61 ecm-law@0 {
62 compatible = "fsl,ecm-law";
63 reg = <0x0 0x1000>;
64 fsl,num-laws = <8>;
65 };
66
67 ecm@1000 {
68 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
69 reg = <0x1000 0x1000>;
70 interrupts = <17 2>;
71 interrupt-parent = <&mpic>;
72 };
73
74 memory-controller@2000 {
75 compatible = "fsl,mpc8555-memory-controller";
76 reg = <0x2000 0x1000>;
77 interrupt-parent = <&mpic>;
78 interrupts = <18 2>;
79 };
80
81 L2: l2-cache-controller@20000 {
82 compatible = "fsl,mpc8555-l2-cache-controller";
83 reg = <0x20000 0x1000>;
84 cache-line-size = <32>; // 32 bytes
85 cache-size = <0x40000>; // L2, 256K
86 interrupt-parent = <&mpic>;
87 interrupts = <16 2>;
88 };
89
90 i2c@3000 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 cell-index = <0>;
94 compatible = "fsl-i2c";
95 reg = <0x3000 0x100>;
96 interrupts = <43 2>;
97 interrupt-parent = <&mpic>;
98 dfsrr;
99 };
100
101 dma@21300 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
105 reg = <0x21300 0x4>;
106 ranges = <0x0 0x21100 0x200>;
107 cell-index = <0>;
108 dma-channel@0 {
109 compatible = "fsl,mpc8555-dma-channel",
110 "fsl,eloplus-dma-channel";
111 reg = <0x0 0x80>;
112 cell-index = <0>;
113 interrupt-parent = <&mpic>;
114 interrupts = <20 2>;
115 };
116 dma-channel@80 {
117 compatible = "fsl,mpc8555-dma-channel",
118 "fsl,eloplus-dma-channel";
119 reg = <0x80 0x80>;
120 cell-index = <1>;
121 interrupt-parent = <&mpic>;
122 interrupts = <21 2>;
123 };
124 dma-channel@100 {
125 compatible = "fsl,mpc8555-dma-channel",
126 "fsl,eloplus-dma-channel";
127 reg = <0x100 0x80>;
128 cell-index = <2>;
129 interrupt-parent = <&mpic>;
130 interrupts = <22 2>;
131 };
132 dma-channel@180 {
133 compatible = "fsl,mpc8555-dma-channel",
134 "fsl,eloplus-dma-channel";
135 reg = <0x180 0x80>;
136 cell-index = <3>;
137 interrupt-parent = <&mpic>;
138 interrupts = <23 2>;
139 };
140 };
141
142 enet0: ethernet@24000 {
143 #address-cells = <1>;
144 #size-cells = <1>;
145 cell-index = <0>;
146 device_type = "network";
147 model = "TSEC";
148 compatible = "gianfar";
149 reg = <0x24000 0x1000>;
150 ranges = <0x0 0x24000 0x1000>;
151 local-mac-address = [ 00 00 00 00 00 00 ];
152 interrupts = <29 2 30 2 34 2>;
153 interrupt-parent = <&mpic>;
154 tbi-handle = <&tbi0>;
155 phy-handle = <&phy0>;
156
157 mdio@520 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,gianfar-mdio";
161 reg = <0x520 0x20>;
162
163 phy0: ethernet-phy@2 {
164 interrupt-parent = <&mpic>;
165 interrupts = <5 1>;
166 reg = <0x2>;
167 device_type = "ethernet-phy";
168 };
169 phy1: ethernet-phy@4 {
170 interrupt-parent = <&mpic>;
171 interrupts = <5 1>;
172 reg = <0x4>;
173 device_type = "ethernet-phy";
174 };
175 tbi0: tbi-phy@11 {
176 reg = <0x11>;
177 device_type = "tbi-phy";
178 };
179 };
180 };
181
182 enet1: ethernet@25000 {
183 #address-cells = <1>;
184 #size-cells = <1>;
185 cell-index = <1>;
186 device_type = "network";
187 model = "TSEC";
188 compatible = "gianfar";
189 reg = <0x25000 0x1000>;
190 ranges = <0x0 0x25000 0x1000>;
191 local-mac-address = [ 00 00 00 00 00 00 ];
192 interrupts = <35 2 36 2 40 2>;
193 interrupt-parent = <&mpic>;
194 tbi-handle = <&tbi1>;
195 phy-handle = <&phy1>;
196
197 mdio@520 {
198 #address-cells = <1>;
199 #size-cells = <0>;
200 compatible = "fsl,gianfar-tbi";
201 reg = <0x520 0x20>;
202
203 tbi1: tbi-phy@11 {
204 reg = <0x11>;
205 device_type = "tbi-phy";
206 };
207 };
208 };
209
210 serial0: serial@4500 {
211 cell-index = <0>;
212 device_type = "serial";
213 compatible = "ns16550";
214 reg = <0x4500 0x100>; // reg base, size
215 clock-frequency = <0>; // should we fill in in uboot?
216 interrupts = <42 2>;
217 interrupt-parent = <&mpic>;
218 };
219
220 serial1: serial@4600 {
221 cell-index = <1>;
222 device_type = "serial";
223 compatible = "ns16550";
224 reg = <0x4600 0x100>; // reg base, size
225 clock-frequency = <0>; // should we fill in in uboot?
226 interrupts = <42 2>;
227 interrupt-parent = <&mpic>;
228 };
229
230 crypto@30000 {
231 compatible = "fsl,sec2.0";
232 reg = <0x30000 0x10000>;
233 interrupts = <45 2>;
234 interrupt-parent = <&mpic>;
235 fsl,num-channels = <4>;
236 fsl,channel-fifo-len = <24>;
237 fsl,exec-units-mask = <0x7e>;
238 fsl,descriptor-types-mask = <0x01010ebf>;
239 };
240
241 mpic: pic@40000 {
242 interrupt-controller;
243 #address-cells = <0>;
244 #interrupt-cells = <2>;
245 reg = <0x40000 0x40000>;
246 compatible = "chrp,open-pic";
247 device_type = "open-pic";
248 };
249
250 cpm@919c0 {
251 #address-cells = <1>;
252 #size-cells = <1>;
253 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
254 reg = <0x919c0 0x30>;
255 ranges;
256
257 muram@80000 {
258 #address-cells = <1>;
259 #size-cells = <1>;
260 ranges = <0x0 0x80000 0x10000>;
261
262 data@0 {
263 compatible = "fsl,cpm-muram-data";
264 reg = <0x0 0x2000 0x9000 0x1000>;
265 };
266 };
267
268 brg@919f0 {
269 compatible = "fsl,mpc8555-brg",
270 "fsl,cpm2-brg",
271 "fsl,cpm-brg";
272 reg = <0x919f0 0x10 0x915f0 0x10>;
273 };
274
275 cpmpic: pic@90c00 {
276 interrupt-controller;
277 #address-cells = <0>;
278 #interrupt-cells = <2>;
279 interrupts = <46 2>;
280 interrupt-parent = <&mpic>;
281 reg = <0x90c00 0x80>;
282 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
283 };
284 };
285 };
286
287 pci0: pci@e0008000 {
288 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
289 interrupt-map = <
290
291 /* IDSEL 0x10 */
292 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
293 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
294 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
295 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
296
297 /* IDSEL 0x11 */
298 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
299 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
300 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
301 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
302
303 /* IDSEL 0x12 (Slot 1) */
304 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
305 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
306 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
307 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
308
309 /* IDSEL 0x13 (Slot 2) */
310 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
311 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
312 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
313 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
314
315 /* IDSEL 0x14 (Slot 3) */
316 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
317 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
318 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
319 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
320
321 /* IDSEL 0x15 (Slot 4) */
322 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
323 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
324 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
325 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
326
327 /* Bus 1 (Tundra Bridge) */
328 /* IDSEL 0x12 (ISA bridge) */
329 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
330 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
331 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
332 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
333 interrupt-parent = <&mpic>;
334 interrupts = <24 2>;
335 bus-range = <0 0>;
336 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
337 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
338 clock-frequency = <66666666>;
339 #interrupt-cells = <1>;
340 #size-cells = <2>;
341 #address-cells = <3>;
342 reg = <0xe0008000 0x1000>;
343 compatible = "fsl,mpc8540-pci";
344 device_type = "pci";
345
346 i8259@19000 {
347 interrupt-controller;
348 device_type = "interrupt-controller";
349 reg = <0x19000 0x0 0x0 0x0 0x1>;
350 #address-cells = <0>;
351 #interrupt-cells = <2>;
352 compatible = "chrp,iic";
353 interrupts = <1>;
354 interrupt-parent = <&pci0>;
355 };
356 };
357
358 pci1: pci@e0009000 {
359 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
360 interrupt-map = <
361
362 /* IDSEL 0x15 */
363 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
364 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
365 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
366 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
367 interrupt-parent = <&mpic>;
368 interrupts = <25 2>;
369 bus-range = <0 0>;
370 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
371 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
372 clock-frequency = <66666666>;
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 reg = <0xe0009000 0x1000>;
377 compatible = "fsl,mpc8540-pci";
378 device_type = "pci";
379 };
380};
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 71347537b83..15ca731bc24 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -289,7 +289,14 @@
289 interrupt-map = < 289 interrupt-map = <
290 /* IDSEL 28 */ 290 /* IDSEL 28 */
291 0xe000 0 0 1 &mpic 2 1 291 0xe000 0 0 1 &mpic 2 1
292 0xe000 0 0 2 &mpic 3 1>; 292 0xe000 0 0 2 &mpic 3 1
293 0xe000 0 0 3 &mpic 6 1
294 0xe000 0 0 4 &mpic 5 1
295
296 /* IDSEL 11 */
297 0x5800 0 0 1 &mpic 6 1
298 0x5800 0 0 2 &mpic 5 1
299 >;
293 300
294 interrupt-parent = <&mpic>; 301 interrupt-parent = <&mpic>;
295 interrupts = <24 2>; 302 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index b30f63753d4..f49d0918131 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -311,7 +311,14 @@
311 interrupt-map = < 311 interrupt-map = <
312 /* IDSEL 28 */ 312 /* IDSEL 28 */
313 0xe000 0 0 1 &mpic 2 1 313 0xe000 0 0 1 &mpic 2 1
314 0xe000 0 0 2 &mpic 3 1>; 314 0xe000 0 0 2 &mpic 3 1
315 0xe000 0 0 3 &mpic 6 1
316 0xe000 0 0 4 &mpic 5 1
317
318 /* IDSEL 11 */
319 0x5800 0 0 1 &mpic 6 1
320 0x5800 0 0 2 &mpic 5 1
321 >;
315 322
316 interrupt-parent = <&mpic>; 323 interrupt-parent = <&mpic>;
317 interrupts = <24 2>; 324 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 61f25e15fd6..5dbb36edb03 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -442,7 +442,14 @@
442 interrupt-map = < 442 interrupt-map = <
443 /* IDSEL 28 */ 443 /* IDSEL 28 */
444 0xe000 0 0 1 &mpic 2 1 444 0xe000 0 0 1 &mpic 2 1
445 0xe000 0 0 2 &mpic 3 1>; 445 0xe000 0 0 2 &mpic 3 1
446 0xe000 0 0 3 &mpic 6 1
447 0xe000 0 0 4 &mpic 5 1
448
449 /* IDSEL 11 */
450 0x5800 0 0 1 &mpic 6 1
451 0x5800 0 0 2 &mpic 5 1
452 >;
446 453
447 interrupt-parent = <&mpic>; 454 interrupt-parent = <&mpic>;
448 interrupts = <24 2>; 455 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 025759c7c95..a050ae42710 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -442,7 +442,14 @@
442 interrupt-map = < 442 interrupt-map = <
443 /* IDSEL 28 */ 443 /* IDSEL 28 */
444 0xe000 0 0 1 &mpic 2 1 444 0xe000 0 0 1 &mpic 2 1
445 0xe000 0 0 2 &mpic 3 1>; 445 0xe000 0 0 2 &mpic 3 1
446 0xe000 0 0 3 &mpic 6 1
447 0xe000 0 0 4 &mpic 5 1
448
449 /* IDSEL 11 */
450 0x5800 0 0 1 &mpic 6 1
451 0x5800 0 0 2 &mpic 5 1
452 >;
446 453
447 interrupt-parent = <&mpic>; 454 interrupt-parent = <&mpic>;
448 interrupts = <24 2>; 455 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 95e28738183..81bad8cd375 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -311,7 +311,14 @@
311 interrupt-map = < 311 interrupt-map = <
312 /* IDSEL 28 */ 312 /* IDSEL 28 */
313 0xe000 0 0 1 &mpic 2 1 313 0xe000 0 0 1 &mpic 2 1
314 0xe000 0 0 2 &mpic 3 1>; 314 0xe000 0 0 2 &mpic 3 1
315 0xe000 0 0 3 &mpic 6 1
316 0xe000 0 0 4 &mpic 5 1
317
318 /* IDSEL 11 */
319 0x5800 0 0 1 &mpic 6 1
320 0x5800 0 0 2 &mpic 5 1
321 >;
315 322
316 interrupt-parent = <&mpic>; 323 interrupt-parent = <&mpic>;
317 interrupts = <24 2>; 324 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index ff70580a8f4..22ec39b5bee 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -382,7 +382,14 @@
382 interrupt-map = < 382 interrupt-map = <
383 /* IDSEL 28 */ 383 /* IDSEL 28 */
384 0xe000 0 0 1 &mpic 2 1 384 0xe000 0 0 1 &mpic 2 1
385 0xe000 0 0 2 &mpic 3 1>; 385 0xe000 0 0 2 &mpic 3 1
386 0xe000 0 0 3 &mpic 6 1
387 0xe000 0 0 4 &mpic 5 1
388
389 /* IDSEL 11 */
390 0x5800 0 0 1 &mpic 6 1
391 0x5800 0 0 2 &mpic 5 1
392 >;
386 393
387 interrupt-parent = <&mpic>; 394 interrupt-parent = <&mpic>;
388 interrupts = <24 2>; 395 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8xx.dts b/arch/powerpc/boot/dts/tqm8xx.dts
new file mode 100644
index 00000000000..f6da7ec49a8
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm8xx.dts
@@ -0,0 +1,172 @@
1/*
2 * TQM8XX Device Tree Source
3 *
4 * Heiko Schocher <hs@denx.de>
5 * 2010 DENX Software Engineering GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16 model = "TQM8xx";
17 compatible = "tqc,tqm8xx";
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 aliases {
22 ethernet0 = &eth0;
23 ethernet1 = &eth1;
24 mdio1 = &phy1;
25 serial0 = &smc1;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 PowerPC,860@0 {
33 device_type = "cpu";
34 reg = <0x0>;
35 d-cache-line-size = <16>; // 16 bytes
36 i-cache-line-size = <16>; // 16 bytes
37 d-cache-size = <0x1000>; // L1, 4K
38 i-cache-size = <0x1000>; // L1, 4K
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
42 interrupts = <15 2>; // decrementer interrupt
43 interrupt-parent = <&PIC>;
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x0 0x2000000>;
50 };
51
52 localbus@fff00100 {
53 compatible = "fsl,mpc860-localbus", "fsl,pq1-localbus";
54 #address-cells = <2>;
55 #size-cells = <1>;
56 reg = <0xfff00100 0x40>;
57
58 ranges = <
59 0x0 0x0 0x40000000 0x800000
60 >;
61
62 flash@0,0 {
63 compatible = "cfi-flash";
64 reg = <0 0 0x800000>;
65 #address-cells = <1>;
66 #size-cells = <1>;
67 bank-width = <4>;
68 device-width = <2>;
69 };
70 };
71
72 soc@fff00000 {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 device_type = "soc";
76 ranges = <0x0 0xfff00000 0x00004000>;
77
78 phy1: mdio@e00 {
79 compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
80 reg = <0xe00 0x188>;
81 #address-cells = <1>;
82 #size-cells = <0>;
83 PHY: ethernet-phy@f {
84 reg = <0xf>;
85 device_type = "ethernet-phy";
86 };
87 };
88
89 eth1: ethernet@e00 {
90 device_type = "network";
91 compatible = "fsl,mpc866-fec-enet",
92 "fsl,pq1-fec-enet";
93 reg = <0xe00 0x188>;
94 interrupts = <3 1>;
95 interrupt-parent = <&PIC>;
96 phy-handle = <&PHY>;
97 linux,network-index = <1>;
98 };
99
100 PIC: pic@0 {
101 interrupt-controller;
102 #interrupt-cells = <2>;
103 reg = <0x0 0x24>;
104 compatible = "fsl,mpc860-pic", "fsl,pq1-pic";
105 };
106
107 cpm@9c0 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "fsl,mpc860-cpm", "fsl,cpm1";
111 ranges;
112 reg = <0x9c0 0x40>;
113 brg-frequency = <0>;
114 interrupts = <0 2>; // cpm error interrupt
115 interrupt-parent = <&CPM_PIC>;
116
117 muram@2000 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 ranges = <0x0 0x2000 0x2000>;
121
122 data@0 {
123 compatible = "fsl,cpm-muram-data";
124 reg = <0x0 0x2000>;
125 };
126 };
127
128 brg@9f0 {
129 compatible = "fsl,mpc860-brg",
130 "fsl,cpm1-brg",
131 "fsl,cpm-brg";
132 reg = <0x9f0 0x10>;
133 clock-frequency = <0>;
134 };
135
136 CPM_PIC: pic@930 {
137 interrupt-controller;
138 #address-cells = <0>;
139 #interrupt-cells = <1>;
140 interrupts = <5 2 0 2>;
141 interrupt-parent = <&PIC>;
142 reg = <0x930 0x20>;
143 compatible = "fsl,mpc860-cpm-pic",
144 "fsl,cpm1-pic";
145 };
146
147
148 smc1: serial@a80 {
149 device_type = "serial";
150 compatible = "fsl,mpc860-smc-uart",
151 "fsl,cpm1-smc-uart";
152 reg = <0xa80 0x10 0x3e80 0x40>;
153 interrupts = <4>;
154 interrupt-parent = <&CPM_PIC>;
155 fsl,cpm-brg = <1>;
156 fsl,cpm-command = <0x90>;
157 };
158
159 eth0: ethernet@a00 {
160 device_type = "network";
161 compatible = "fsl,mpc860-scc-enet",
162 "fsl,cpm1-scc-enet";
163 reg = <0xa00 0x18 0x3c00 0x100>;
164 interrupts = <30>;
165 interrupt-parent = <&CPM_PIC>;
166 fsl,cpm-command = <0000>;
167 linux,network-index = <0>;
168 fixed-link = <0 0 10 0 0>;
169 };
170 };
171 };
172};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 01:15:56 -0400