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authorKumar Gala <galak@kernel.crashing.org>2007-09-12 19:23:46 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-09-14 09:53:22 -0400
commit1b3c5cdab49a605f0e048e1ccbf4cc61a2626485 (patch)
treeb81e6642588b00a7dbb42611614e745517b6a6b9 /arch/powerpc/boot/dts/mpc8548cds.dts
parentf0c8ac8083cbd9347b398bfddcca20f1e2786016 (diff)
[POWERPC] Move PCI nodes to be sibilings with SOC nodes
Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8548cds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts399
1 files changed, 203 insertions, 196 deletions
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 11b823595a0..69ca5025d97 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -42,13 +42,7 @@
42 #address-cells = <1>; 42 #address-cells = <1>;
43 #size-cells = <1>; 43 #size-cells = <1>;
44 device_type = "soc"; 44 device_type = "soc";
45 ranges = <00001000 e0001000 000ff000 45 ranges = <00000000 e0000000 00100000>;
46 80000000 80000000 10000000
47 e2000000 e2000000 00800000
48 90000000 90000000 10000000
49 e2800000 e2800000 00800000
50 a0000000 a0000000 20000000
51 e3000000 e3000000 01000000>;
52 reg = <e0000000 00001000>; // CCSRBAR 46 reg = <e0000000 00001000>; // CCSRBAR
53 bus-frequency = <0>; 47 bus-frequency = <0>;
54 48
@@ -187,212 +181,225 @@
187 fsl,has-rstcr; 181 fsl,has-rstcr;
188 }; 182 };
189 183
190 pci@8000 { 184 mpic: pic@40000 {
185 clock-frequency = <0>;
186 interrupt-controller;
187 #address-cells = <0>;
188 #interrupt-cells = <2>;
189 reg = <40000 40000>;
190 compatible = "chrp,open-pic";
191 device_type = "open-pic";
192 big-endian;
193 };
194 };
195
196 pci@e0008000 {
197 interrupt-map-mask = <f800 0 0 7>;
198 interrupt-map = <
199 /* IDSEL 0x4 (PCIX Slot 2) */
200 02000 0 0 1 &mpic 0 1
201 02000 0 0 2 &mpic 1 1
202 02000 0 0 3 &mpic 2 1
203 02000 0 0 4 &mpic 3 1
204
205 /* IDSEL 0x5 (PCIX Slot 3) */
206 02800 0 0 1 &mpic 1 1
207 02800 0 0 2 &mpic 2 1
208 02800 0 0 3 &mpic 3 1
209 02800 0 0 4 &mpic 0 1
210
211 /* IDSEL 0x6 (PCIX Slot 4) */
212 03000 0 0 1 &mpic 2 1
213 03000 0 0 2 &mpic 3 1
214 03000 0 0 3 &mpic 0 1
215 03000 0 0 4 &mpic 1 1
216
217 /* IDSEL 0x8 (PCIX Slot 5) */
218 04000 0 0 1 &mpic 0 1
219 04000 0 0 2 &mpic 1 1
220 04000 0 0 3 &mpic 2 1
221 04000 0 0 4 &mpic 3 1
222
223 /* IDSEL 0xC (Tsi310 bridge) */
224 06000 0 0 1 &mpic 0 1
225 06000 0 0 2 &mpic 1 1
226 06000 0 0 3 &mpic 2 1
227 06000 0 0 4 &mpic 3 1
228
229 /* IDSEL 0x14 (Slot 2) */
230 0a000 0 0 1 &mpic 0 1
231 0a000 0 0 2 &mpic 1 1
232 0a000 0 0 3 &mpic 2 1
233 0a000 0 0 4 &mpic 3 1
234
235 /* IDSEL 0x15 (Slot 3) */
236 0a800 0 0 1 &mpic 1 1
237 0a800 0 0 2 &mpic 2 1
238 0a800 0 0 3 &mpic 3 1
239 0a800 0 0 4 &mpic 0 1
240
241 /* IDSEL 0x16 (Slot 4) */
242 0b000 0 0 1 &mpic 2 1
243 0b000 0 0 2 &mpic 3 1
244 0b000 0 0 3 &mpic 0 1
245 0b000 0 0 4 &mpic 1 1
246
247 /* IDSEL 0x18 (Slot 5) */
248 0c000 0 0 1 &mpic 0 1
249 0c000 0 0 2 &mpic 1 1
250 0c000 0 0 3 &mpic 2 1
251 0c000 0 0 4 &mpic 3 1
252
253 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
254 0E000 0 0 1 &mpic 0 1
255 0E000 0 0 2 &mpic 1 1
256 0E000 0 0 3 &mpic 2 1
257 0E000 0 0 4 &mpic 3 1>;
258
259 interrupt-parent = <&mpic>;
260 interrupts = <18 2>;
261 bus-range = <0 0>;
262 ranges = <02000000 0 80000000 80000000 0 10000000
263 01000000 0 00000000 e2000000 0 00800000>;
264 clock-frequency = <3f940aa>;
265 #interrupt-cells = <1>;
266 #size-cells = <2>;
267 #address-cells = <3>;
268 reg = <e0008000 1000>;
269 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
270 device_type = "pci";
271
272 pci_bridge@1c {
191 interrupt-map-mask = <f800 0 0 7>; 273 interrupt-map-mask = <f800 0 0 7>;
192 interrupt-map = < 274 interrupt-map = <
193 /* IDSEL 0x4 (PCIX Slot 2) */
194 02000 0 0 1 &mpic 0 1
195 02000 0 0 2 &mpic 1 1
196 02000 0 0 3 &mpic 2 1
197 02000 0 0 4 &mpic 3 1
198
199 /* IDSEL 0x5 (PCIX Slot 3) */
200 02800 0 0 1 &mpic 1 1
201 02800 0 0 2 &mpic 2 1
202 02800 0 0 3 &mpic 3 1
203 02800 0 0 4 &mpic 0 1
204
205 /* IDSEL 0x6 (PCIX Slot 4) */
206 03000 0 0 1 &mpic 2 1
207 03000 0 0 2 &mpic 3 1
208 03000 0 0 3 &mpic 0 1
209 03000 0 0 4 &mpic 1 1
210
211 /* IDSEL 0x8 (PCIX Slot 5) */
212 04000 0 0 1 &mpic 0 1
213 04000 0 0 2 &mpic 1 1
214 04000 0 0 3 &mpic 2 1
215 04000 0 0 4 &mpic 3 1
216
217 /* IDSEL 0xC (Tsi310 bridge) */
218 06000 0 0 1 &mpic 0 1
219 06000 0 0 2 &mpic 1 1
220 06000 0 0 3 &mpic 2 1
221 06000 0 0 4 &mpic 3 1
222
223 /* IDSEL 0x14 (Slot 2) */
224 0a000 0 0 1 &mpic 0 1
225 0a000 0 0 2 &mpic 1 1
226 0a000 0 0 3 &mpic 2 1
227 0a000 0 0 4 &mpic 3 1
228
229 /* IDSEL 0x15 (Slot 3) */
230 0a800 0 0 1 &mpic 1 1
231 0a800 0 0 2 &mpic 2 1
232 0a800 0 0 3 &mpic 3 1
233 0a800 0 0 4 &mpic 0 1
234
235 /* IDSEL 0x16 (Slot 4) */
236 0b000 0 0 1 &mpic 2 1
237 0b000 0 0 2 &mpic 3 1
238 0b000 0 0 3 &mpic 0 1
239 0b000 0 0 4 &mpic 1 1
240
241 /* IDSEL 0x18 (Slot 5) */
242 0c000 0 0 1 &mpic 0 1
243 0c000 0 0 2 &mpic 1 1
244 0c000 0 0 3 &mpic 2 1
245 0c000 0 0 4 &mpic 3 1
246
247 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
248 0E000 0 0 1 &mpic 0 1
249 0E000 0 0 2 &mpic 1 1
250 0E000 0 0 3 &mpic 2 1
251 0E000 0 0 4 &mpic 3 1>;
252 275
253 interrupt-parent = <&mpic>; 276 /* IDSEL 0x00 (PrPMC Site) */
254 interrupts = <18 2>; 277 0000 0 0 1 &mpic 0 1
255 bus-range = <0 0>; 278 0000 0 0 2 &mpic 1 1
256 ranges = <02000000 0 80000000 80000000 0 10000000 279 0000 0 0 3 &mpic 2 1
257 01000000 0 00000000 e2000000 0 00800000>; 280 0000 0 0 4 &mpic 3 1
258 clock-frequency = <3f940aa>; 281
282 /* IDSEL 0x04 (VIA chip) */
283 2000 0 0 1 &mpic 0 1
284 2000 0 0 2 &mpic 1 1
285 2000 0 0 3 &mpic 2 1
286 2000 0 0 4 &mpic 3 1
287
288 /* IDSEL 0x05 (8139) */
289 2800 0 0 1 &mpic 1 1
290
291 /* IDSEL 0x06 (Slot 6) */
292 3000 0 0 1 &mpic 2 1
293 3000 0 0 2 &mpic 3 1
294 3000 0 0 3 &mpic 0 1
295 3000 0 0 4 &mpic 1 1
296
297 /* IDESL 0x07 (Slot 7) */
298 3800 0 0 1 &mpic 3 1
299 3800 0 0 2 &mpic 0 1
300 3800 0 0 3 &mpic 1 1
301 3800 0 0 4 &mpic 2 1>;
302
303 reg = <e000 0 0 0 0>;
259 #interrupt-cells = <1>; 304 #interrupt-cells = <1>;
260 #size-cells = <2>; 305 #size-cells = <2>;
261 #address-cells = <3>; 306 #address-cells = <3>;
262 reg = <8000 1000>; 307 ranges = <02000000 0 80000000
263 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 308 02000000 0 80000000
264 device_type = "pci"; 309 0 20000000
310 01000000 0 00000000
311 01000000 0 00000000
312 0 00080000>;
313 clock-frequency = <1fca055>;
265 314
266 pci_bridge@1c { 315 isa@4 {
267 interrupt-map-mask = <f800 0 0 7>; 316 device_type = "isa";
268 interrupt-map = < 317 #interrupt-cells = <2>;
269 318 #size-cells = <1>;
270 /* IDSEL 0x00 (PrPMC Site) */ 319 #address-cells = <2>;
271 0000 0 0 1 &mpic 0 1 320 reg = <2000 0 0 0 0>;
272 0000 0 0 2 &mpic 1 1 321 ranges = <1 0 01000000 0 0 00001000>;
273 0000 0 0 3 &mpic 2 1 322 interrupt-parent = <&i8259>;
274 0000 0 0 4 &mpic 3 1 323
275 324 i8259: interrupt-controller@20 {
276 /* IDSEL 0x04 (VIA chip) */ 325 interrupt-controller;
277 2000 0 0 1 &mpic 0 1 326 device_type = "interrupt-controller";
278 2000 0 0 2 &mpic 1 1 327 reg = <1 20 2
279 2000 0 0 3 &mpic 2 1 328 1 a0 2
280 2000 0 0 4 &mpic 3 1 329 1 4d0 2>;
281 330 #address-cells = <0>;
282 /* IDSEL 0x05 (8139) */
283 2800 0 0 1 &mpic 1 1
284
285 /* IDSEL 0x06 (Slot 6) */
286 3000 0 0 1 &mpic 2 1
287 3000 0 0 2 &mpic 3 1
288 3000 0 0 3 &mpic 0 1
289 3000 0 0 4 &mpic 1 1
290
291 /* IDESL 0x07 (Slot 7) */
292 3800 0 0 1 &mpic 3 1
293 3800 0 0 2 &mpic 0 1
294 3800 0 0 3 &mpic 1 1
295 3800 0 0 4 &mpic 2 1>;
296
297 reg = <e000 0 0 0 0>;
298 #interrupt-cells = <1>;
299 #size-cells = <2>;
300 #address-cells = <3>;
301 ranges = <02000000 0 80000000
302 02000000 0 80000000
303 0 20000000
304 01000000 0 00000000
305 01000000 0 00000000
306 0 00080000>;
307 clock-frequency = <1fca055>;
308
309 isa@4 {
310 device_type = "isa";
311 #interrupt-cells = <2>; 331 #interrupt-cells = <2>;
312 #size-cells = <1>; 332 compatible = "chrp,iic";
313 #address-cells = <2>; 333 interrupts = <0 1>;
314 reg = <2000 0 0 0 0>; 334 interrupt-parent = <&mpic>;
315 ranges = <1 0 01000000 0 0 00001000>;
316 interrupt-parent = <&i8259>;
317
318 i8259: interrupt-controller@20 {
319 interrupt-controller;
320 device_type = "interrupt-controller";
321 reg = <1 20 2
322 1 a0 2
323 1 4d0 2>;
324 #address-cells = <0>;
325 #interrupt-cells = <2>;
326 compatible = "chrp,iic";
327 interrupts = <0 1>;
328 interrupt-parent = <&mpic>;
329 };
330
331 rtc@70 {
332 compatible = "pnpPNP,b00";
333 reg = <1 70 2>;
334 };
335 }; 335 };
336 };
337 };
338 336
339 pci@9000 { 337 rtc@70 {
340 interrupt-map-mask = <f800 0 0 7>; 338 compatible = "pnpPNP,b00";
341 interrupt-map = < 339 reg = <1 70 2>;
342 340 };
343 /* IDSEL 0x15 */ 341 };
344 a800 0 0 1 &mpic b 1
345 a800 0 0 2 &mpic 1 1
346 a800 0 0 3 &mpic 2 1
347 a800 0 0 4 &mpic 3 1>;
348
349 interrupt-parent = <&mpic>;
350 interrupts = <19 2>;
351 bus-range = <0 0>;
352 ranges = <02000000 0 90000000 90000000 0 10000000
353 01000000 0 00000000 e2800000 0 00800000>;
354 clock-frequency = <3f940aa>;
355 #interrupt-cells = <1>;
356 #size-cells = <2>;
357 #address-cells = <3>;
358 reg = <9000 1000>;
359 compatible = "fsl,mpc8540-pci";
360 device_type = "pci";
361 }; 342 };
362 /* PCI Express */ 343 };
363 pcie@a000 {
364 interrupt-map-mask = <f800 0 0 7>;
365 interrupt-map = <
366 344
367 /* IDSEL 0x0 (PEX) */ 345 pci@e0009000 {
368 00000 0 0 1 &mpic 0 1 346 interrupt-map-mask = <f800 0 0 7>;
369 00000 0 0 2 &mpic 1 1 347 interrupt-map = <
370 00000 0 0 3 &mpic 2 1 348
371 00000 0 0 4 &mpic 3 1>; 349 /* IDSEL 0x15 */
350 a800 0 0 1 &mpic b 1
351 a800 0 0 2 &mpic 1 1
352 a800 0 0 3 &mpic 2 1
353 a800 0 0 4 &mpic 3 1>;
354
355 interrupt-parent = <&mpic>;
356 interrupts = <19 2>;
357 bus-range = <0 0>;
358 ranges = <02000000 0 90000000 90000000 0 10000000
359 01000000 0 00000000 e2800000 0 00800000>;
360 clock-frequency = <3f940aa>;
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 reg = <e0009000 1000>;
365 compatible = "fsl,mpc8540-pci";
366 device_type = "pci";
367 };
372 368
373 interrupt-parent = <&mpic>; 369 pcie@e000a000 {
374 interrupts = <1a 2>; 370 interrupt-map-mask = <f800 0 0 7>;
375 bus-range = <0 ff>; 371 interrupt-map = <
376 ranges = <02000000 0 a0000000 a0000000 0 20000000 372
377 01000000 0 00000000 e3000000 0 08000000>; 373 /* IDSEL 0x0 (PEX) */
378 clock-frequency = <1fca055>; 374 00000 0 0 1 &mpic 0 1
379 #interrupt-cells = <1>; 375 00000 0 0 2 &mpic 1 1
376 00000 0 0 3 &mpic 2 1
377 00000 0 0 4 &mpic 3 1>;
378
379 interrupt-parent = <&mpic>;
380 interrupts = <1a 2>;
381 bus-range = <0 ff>;
382 ranges = <02000000 0 a0000000 a0000000 0 20000000
383 01000000 0 00000000 e3000000 0 08000000>;
384 clock-frequency = <1fca055>;
385 #interrupt-cells = <1>;
386 #size-cells = <2>;
387 #address-cells = <3>;
388 reg = <e000a000 1000>;
389 compatible = "fsl,mpc8548-pcie";
390 device_type = "pci";
391 pcie@0 {
392 reg = <0 0 0 0 0>;
380 #size-cells = <2>; 393 #size-cells = <2>;
381 #address-cells = <3>; 394 #address-cells = <3>;
382 reg = <a000 1000>;
383 compatible = "fsl,mpc8548-pcie";
384 device_type = "pci"; 395 device_type = "pci";
385 }; 396 ranges = <02000000 0 a0000000
397 02000000 0 a0000000
398 0 20000000
386 399
387 mpic: pic@40000 { 400 01000000 0 00000000
388 clock-frequency = <0>; 401 01000000 0 00000000
389 interrupt-controller; 402 0 08000000>;
390 #address-cells = <0>;
391 #interrupt-cells = <2>;
392 reg = <40000 40000>;
393 compatible = "chrp,open-pic";
394 device_type = "open-pic";
395 big-endian;
396 }; 403 };
397 }; 404 };
398}; 405};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 23:32:16 -0400