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authorManuel Lauss <manuel.lauss@googlemail.com>2011-11-01 15:03:30 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:02:05 -0500
commit809f36c6f4a0568178c909ff1096ca83eae33f7d (patch)
tree6b99b1ac701c0bd581811c39e85856f3bcbda22d /arch/mips
parentfb469f084fdf1631e31d87270f5263c20a7f5cd6 (diff)
MIPS: Alchemy: Au1300 SoC support
Add basic support for the Au1300 variant(s): - New GPIO/Interrupt controller - DBDMA ids - USB setup - MMC support - enable various PSC drivers - detection code. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/alchemy/Kconfig4
-rw-r--r--arch/mips/alchemy/common/Makefile3
-rw-r--r--arch/mips/alchemy/common/dbdma.c46
-rw-r--r--arch/mips/alchemy/common/gpioint.c411
-rw-r--r--arch/mips/alchemy/common/gpiolib.c42
-rw-r--r--arch/mips/alchemy/common/platform.c31
-rw-r--r--arch/mips/alchemy/common/power.c3
-rw-r--r--arch/mips/alchemy/common/sleeper.S73
-rw-r--r--arch/mips/alchemy/common/time.c1
-rw-r--r--arch/mips/alchemy/common/vss.c84
-rw-r--r--arch/mips/include/asm/cpu.h1
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h221
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1100_mmc.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h31
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1300.h241
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h3
-rw-r--r--arch/mips/kernel/cpu-probe.c7
17 files changed, 1189 insertions, 15 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 36df5e2c8e0..766badaef3b 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -2,6 +2,10 @@
2config ALCHEMY_GPIOINT_AU1000 2config ALCHEMY_GPIOINT_AU1000
3 bool 3 bool
4 4
5# au1300-style GPIO/INT controller
6config ALCHEMY_GPIOINT_AU1300
7 bool
8
5# select this in your board config if you don't want to use the gpio 9# select this in your board config if you don't want to use the gpio
6# namespace as documented in the manuals. In this case however you need 10# namespace as documented in the manuals. In this case however you need
7# to create the necessary gpio_* functions in your board code/headers! 11# to create the necessary gpio_* functions in your board code/headers!
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 811ece7b22e..d3f5c513780 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -6,9 +6,10 @@
6# 6#
7 7
8obj-y += prom.o time.o clocks.o platform.o power.o setup.o \ 8obj-y += prom.o time.o clocks.o platform.o power.o setup.o \
9 sleeper.o dma.o dbdma.o 9 sleeper.o dma.o dbdma.o vss.o
10 10
11obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o 11obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
12obj-$(CONFIG_ALCHEMY_GPIOINT_AU1300) += gpioint.o
12 13
13# optional gpiolib support 14# optional gpiolib support
14ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) 15ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 0e63ee487d6..c723ec1d3b2 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -148,6 +148,50 @@ static dbdev_tab_t au1200_dbdev_tab[] __initdata = {
148 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 148 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
149}; 149};
150 150
151static dbdev_tab_t au1300_dbdev_tab[] __initdata = {
152 { AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 },
153 { AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 },
154 { AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 },
155 { AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 },
156 { AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 },
157 { AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 },
158 { AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 },
159 { AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 },
160
161 { AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
162 { AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
163 { AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 },
164 { AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 },
165
166 { AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
167 { AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
168
169 { AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 },
170 { AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 },
171 { AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 },
172 { AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 },
173 { AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 },
174 { AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 },
175 { AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 },
176 { AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 },
177
178 { AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
179 { AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
180
181 { AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 },
182 { AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 },
183
184 { AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
185
186 { AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 },
187
188 { AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
189 { AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
190
191 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
192 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
193};
194
151/* 32 predefined plus 32 custom */ 195/* 32 predefined plus 32 custom */
152#define DBDEV_TAB_SIZE 64 196#define DBDEV_TAB_SIZE 64
153 197
@@ -1038,6 +1082,8 @@ static int __init alchemy_dbdma_init(void)
1038 return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab); 1082 return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
1039 case ALCHEMY_CPU_AU1200: 1083 case ALCHEMY_CPU_AU1200:
1040 return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab); 1084 return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
1085 case ALCHEMY_CPU_AU1300:
1086 return dbdma_setup(AU1300_DDMA_INT, au1300_dbdev_tab);
1041 } 1087 }
1042 return 0; 1088 return 0;
1043} 1089}
diff --git a/arch/mips/alchemy/common/gpioint.c b/arch/mips/alchemy/common/gpioint.c
new file mode 100644
index 00000000000..b8cd3364ff6
--- /dev/null
+++ b/arch/mips/alchemy/common/gpioint.c
@@ -0,0 +1,411 @@
1/*
2 * gpioint.c - Au1300 GPIO+Interrupt controller (I call it "GPIC") support.
3 *
4 * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
5 *
6 * licensed under the GPLv2.
7 */
8
9#include <linux/io.h>
10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/slab.h>
13#include <linux/syscore_ops.h>
14#include <linux/types.h>
15
16#include <asm/irq_cpu.h>
17#include <asm/mach-au1x00/au1000.h>
18#include <asm/mach-au1x00/gpio-au1300.h>
19
20static int au1300_gpic_settype(struct irq_data *d, unsigned int type);
21
22/* setup for known onchip sources */
23struct gpic_devint_data {
24 int irq; /* linux IRQ number */
25 int type; /* IRQ_TYPE_ */
26 int prio; /* irq priority, 0 highest, 3 lowest */
27 int internal; /* internal source (no ext. pin)? */
28};
29
30static const struct gpic_devint_data au1300_devints[] __initdata = {
31 /* multifunction: gpio pin or device */
32 { AU1300_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
33 { AU1300_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
34 { AU1300_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
35 { AU1300_SD1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
36 { AU1300_SD2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
37 { AU1300_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
38 { AU1300_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
39 { AU1300_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
40 { AU1300_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
41 { AU1300_NAND_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
42 /* au1300 internal */
43 { AU1300_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
44 { AU1300_MMU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
45 { AU1300_MPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
46 { AU1300_GPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
47 { AU1300_UDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
48 { AU1300_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
49 { AU1300_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
50 { AU1300_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
51 { AU1300_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
52 { AU1300_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
53 { AU1300_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
54 { AU1300_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
55 { AU1300_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 1, },
56 { AU1300_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
57 { AU1300_SD0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
58 { AU1300_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
59 { AU1300_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
60 { AU1300_BSA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
61 { AU1300_MPE_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
62 { AU1300_ITE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
63 { AU1300_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
64 { AU1300_CIM_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
65 { -1, }, /* terminator */
66};
67
68
69/*
70 * au1300_gpic_chgcfg - change PIN configuration.
71 * @gpio: pin to change (0-based GPIO number from datasheet).
72 * @clr: clear all bits set in 'clr'.
73 * @set: set these bits.
74 *
75 * modifies a pins' configuration register, bits set in @clr will
76 * be cleared in the register, bits in @set will be set.
77 */
78static inline void au1300_gpic_chgcfg(unsigned int gpio,
79 unsigned long clr,
80 unsigned long set)
81{
82 void __iomem *r = AU1300_GPIC_ADDR;
83 unsigned long l;
84
85 r += gpio * 4; /* offset into pin config array */
86 l = __raw_readl(r + AU1300_GPIC_PINCFG);
87 l &= ~clr;
88 l |= set;
89 __raw_writel(l, r + AU1300_GPIC_PINCFG);
90 wmb();
91}
92
93/*
94 * au1300_pinfunc_to_gpio - assign a pin as GPIO input (GPIO ctrl).
95 * @pin: pin (0-based GPIO number from datasheet).
96 *
97 * Assigns a GPIO pin to the GPIO controller, so its level can either
98 * be read or set through the generic GPIO functions.
99 * If you need a GPOUT, use au1300_gpio_set_value(pin, 0/1).
100 * REVISIT: is this function really necessary?
101 */
102void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio)
103{
104 au1300_gpio_direction_input(gpio + AU1300_GPIO_BASE);
105}
106EXPORT_SYMBOL_GPL(au1300_pinfunc_to_gpio);
107
108/*
109 * au1300_pinfunc_to_dev - assign a pin to the device function.
110 * @pin: pin (0-based GPIO number from datasheet).
111 *
112 * Assigns a GPIO pin to its associated device function; the pin will be
113 * driven by the device and not through GPIO functions.
114 */
115void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio)
116{
117 void __iomem *r = AU1300_GPIC_ADDR;
118 unsigned long bit;
119
120 r += GPIC_GPIO_BANKOFF(gpio);
121 bit = GPIC_GPIO_TO_BIT(gpio);
122 __raw_writel(bit, r + AU1300_GPIC_DEVSEL);
123 wmb();
124}
125EXPORT_SYMBOL_GPL(au1300_pinfunc_to_dev);
126
127/*
128 * au1300_set_irq_priority - set internal priority of IRQ.
129 * @irq: irq to set priority (linux irq number).
130 * @p: priority (0 = highest, 3 = lowest).
131 */
132void au1300_set_irq_priority(unsigned int irq, int p)
133{
134 irq -= ALCHEMY_GPIC_INT_BASE;
135 au1300_gpic_chgcfg(irq, GPIC_CFG_IL_MASK, GPIC_CFG_IL_SET(p));
136}
137EXPORT_SYMBOL_GPL(au1300_set_irq_priority);
138
139/*
140 * au1300_set_dbdma_gpio - assign a gpio to one of the DBDMA triggers.
141 * @dchan: dbdma trigger select (0, 1).
142 * @gpio: pin to assign as trigger.
143 *
144 * DBDMA controller has 2 external trigger sources; this function
145 * assigns a GPIO to the selected trigger.
146 */
147void au1300_set_dbdma_gpio(int dchan, unsigned int gpio)
148{
149 unsigned long r;
150
151 if ((dchan >= 0) && (dchan <= 1)) {
152 r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
153 r &= ~(0xff << (8 * dchan));
154 r |= (gpio & 0x7f) << (8 * dchan);
155 __raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
156 wmb();
157 }
158}
159
160/**********************************************************************/
161
162static inline void gpic_pin_set_idlewake(unsigned int gpio, int allow)
163{
164 au1300_gpic_chgcfg(gpio, GPIC_CFG_IDLEWAKE,
165 allow ? GPIC_CFG_IDLEWAKE : 0);
166}
167
168static void au1300_gpic_mask(struct irq_data *d)
169{
170 void __iomem *r = AU1300_GPIC_ADDR;
171 unsigned long bit, irq = d->irq;
172
173 irq -= ALCHEMY_GPIC_INT_BASE;
174 r += GPIC_GPIO_BANKOFF(irq);
175 bit = GPIC_GPIO_TO_BIT(irq);
176 __raw_writel(bit, r + AU1300_GPIC_IDIS);
177 wmb();
178
179 gpic_pin_set_idlewake(irq, 0);
180}
181
182static void au1300_gpic_unmask(struct irq_data *d)
183{
184 void __iomem *r = AU1300_GPIC_ADDR;
185 unsigned long bit, irq = d->irq;
186
187 irq -= ALCHEMY_GPIC_INT_BASE;
188
189 gpic_pin_set_idlewake(irq, 1);
190
191 r += GPIC_GPIO_BANKOFF(irq);
192 bit = GPIC_GPIO_TO_BIT(irq);
193 __raw_writel(bit, r + AU1300_GPIC_IEN);
194 wmb();
195}
196
197static void au1300_gpic_maskack(struct irq_data *d)
198{
199 void __iomem *r = AU1300_GPIC_ADDR;
200 unsigned long bit, irq = d->irq;
201
202 irq -= ALCHEMY_GPIC_INT_BASE;
203 r += GPIC_GPIO_BANKOFF(irq);
204 bit = GPIC_GPIO_TO_BIT(irq);
205 __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */
206 __raw_writel(bit, r + AU1300_GPIC_IDIS); /* mask */
207 wmb();
208
209 gpic_pin_set_idlewake(irq, 0);
210}
211
212static void au1300_gpic_ack(struct irq_data *d)
213{
214 void __iomem *r = AU1300_GPIC_ADDR;
215 unsigned long bit, irq = d->irq;
216
217 irq -= ALCHEMY_GPIC_INT_BASE;
218 r += GPIC_GPIO_BANKOFF(irq);
219 bit = GPIC_GPIO_TO_BIT(irq);
220 __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */
221 wmb();
222}
223
224static struct irq_chip au1300_gpic = {
225 .name = "GPIOINT",
226 .irq_ack = au1300_gpic_ack,
227 .irq_mask = au1300_gpic_mask,
228 .irq_mask_ack = au1300_gpic_maskack,
229 .irq_unmask = au1300_gpic_unmask,
230 .irq_set_type = au1300_gpic_settype,
231};
232
233static int au1300_gpic_settype(struct irq_data *d, unsigned int type)
234{
235 unsigned long s;
236 unsigned char *name = NULL;
237 irq_flow_handler_t hdl = NULL;
238
239 switch (type) {
240 case IRQ_TYPE_LEVEL_HIGH:
241 s = GPIC_CFG_IC_LEVEL_HIGH;
242 name = "high";
243 hdl = handle_level_irq;
244 break;
245 case IRQ_TYPE_LEVEL_LOW:
246 s = GPIC_CFG_IC_LEVEL_LOW;
247 name = "low";
248 hdl = handle_level_irq;
249 break;
250 case IRQ_TYPE_EDGE_RISING:
251 s = GPIC_CFG_IC_EDGE_RISE;
252 name = "posedge";
253 hdl = handle_edge_irq;
254 break;
255 case IRQ_TYPE_EDGE_FALLING:
256 s = GPIC_CFG_IC_EDGE_FALL;
257 name = "negedge";
258 hdl = handle_edge_irq;
259 break;
260 case IRQ_TYPE_EDGE_BOTH:
261 s = GPIC_CFG_IC_EDGE_BOTH;
262 name = "bothedge";
263 hdl = handle_edge_irq;
264 break;
265 case IRQ_TYPE_NONE:
266 s = GPIC_CFG_IC_OFF;
267 name = "disabled";
268 hdl = handle_level_irq;
269 break;
270 default:
271 return -EINVAL;
272 }
273
274 __irq_set_chip_handler_name_locked(d->irq, &au1300_gpic, hdl, name);
275
276 au1300_gpic_chgcfg(d->irq - ALCHEMY_GPIC_INT_BASE, GPIC_CFG_IC_MASK, s);
277
278 return 0;
279}
280
281static void __init alchemy_gpic_init_irq(const struct gpic_devint_data *dints)
282{
283 int i;
284 void __iomem *bank_base;
285
286 mips_cpu_irq_init();
287
288 /* disable & ack all possible interrupt sources */
289 for (i = 0; i < 4; i++) {
290 bank_base = AU1300_GPIC_ADDR + (i * 4);
291 __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS);
292 wmb();
293 __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND);
294 wmb();
295 }
296
297 /* register an irq_chip for them, with 2nd highest priority */
298 for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) {
299 au1300_set_irq_priority(i, 1);
300 au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);
301 }
302
303 /* setup known on-chip sources */
304 while ((i = dints->irq) != -1) {
305 au1300_gpic_settype(irq_get_irq_data(i), dints->type);
306 au1300_set_irq_priority(i, dints->prio);
307
308 if (dints->internal)
309 au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE);
310
311 dints++;
312 }
313
314 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
315}
316
317static unsigned long alchemy_gpic_pmdata[ALCHEMY_GPIC_INT_NUM + 6];
318
319static int alchemy_gpic_suspend(void)
320{
321 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
322 int i;
323
324 /* save 4 interrupt mask status registers */
325 alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0);
326 alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4);
327 alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8);
328 alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc);
329
330 /* save misc register(s) */
331 alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL);
332
333 /* molto silenzioso */
334 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
335 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
336 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
337 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
338 wmb();
339
340 /* save pin/int-type configuration */
341 base += AU1300_GPIC_PINCFG;
342 for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++)
343 alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2));
344
345 wmb();
346
347 return 0;
348}
349
350static void alchemy_gpic_resume(void)
351{
352 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
353 int i;
354
355 /* disable all first */
356 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
357 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
358 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
359 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
360 wmb();
361
362 /* restore pin/int-type configurations */
363 base += AU1300_GPIC_PINCFG;
364 for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++)
365 __raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2));
366 wmb();
367
368 /* restore misc register(s) */
369 base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
370 __raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL);
371 wmb();
372
373 /* finally restore masks */
374 __raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0);
375 __raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4);
376 __raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8);
377 __raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc);
378 wmb();
379}
380
381static struct syscore_ops alchemy_gpic_pmops = {
382 .suspend = alchemy_gpic_suspend,
383 .resume = alchemy_gpic_resume,
384};
385
386/**********************************************************************/
387
388void __init arch_init_irq(void)
389{
390 switch (alchemy_get_cputype()) {
391 case ALCHEMY_CPU_AU1300:
392 alchemy_gpic_init_irq(&au1300_devints[0]);
393 register_syscore_ops(&alchemy_gpic_pmops);
394 break;
395 }
396}
397
398#define CAUSEF_GPIC (CAUSEF_IP2 | CAUSEF_IP3 | CAUSEF_IP4 | CAUSEF_IP5)
399
400void plat_irq_dispatch(void)
401{
402 unsigned long i, c = read_c0_cause() & read_c0_status();
403
404 if (c & CAUSEF_IP7) /* c0 timer */
405 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
406 else if (likely(c & CAUSEF_GPIC)) {
407 i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC);
408 do_IRQ(i + ALCHEMY_GPIC_INT_BASE);
409 } else
410 spurious_interrupt();
411}
diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c
index 91fb4d9e30f..f1b50f0c01d 100644
--- a/arch/mips/alchemy/common/gpiolib.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -27,6 +27,7 @@
27 * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail! 27 * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
28 * au1000 SoC have only one GPIO block : GPIO1 28 * au1000 SoC have only one GPIO block : GPIO1
29 * Au1100, Au15x0, Au12x0 have a second one : GPIO2 29 * Au1100, Au15x0, Au12x0 have a second one : GPIO2
30 * Au1300 is totally different: 1 block with up to 128 GPIOs
30 */ 31 */
31 32
32#include <linux/init.h> 33#include <linux/init.h>
@@ -35,6 +36,7 @@
35#include <linux/types.h> 36#include <linux/types.h>
36#include <linux/gpio.h> 37#include <linux/gpio.h>
37#include <asm/mach-au1x00/gpio-au1000.h> 38#include <asm/mach-au1x00/gpio-au1000.h>
39#include <asm/mach-au1x00/gpio-au1300.h>
38 40
39static int gpio2_get(struct gpio_chip *chip, unsigned offset) 41static int gpio2_get(struct gpio_chip *chip, unsigned offset)
40{ 42{
@@ -115,6 +117,43 @@ struct gpio_chip alchemy_gpio_chip[] = {
115 }, 117 },
116}; 118};
117 119
120static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off)
121{
122 return au1300_gpio_get_value(off + AU1300_GPIO_BASE);
123}
124
125static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
126{
127 au1300_gpio_set_value(off + AU1300_GPIO_BASE, v);
128}
129
130static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off)
131{
132 return au1300_gpio_direction_input(off + AU1300_GPIO_BASE);
133}
134
135static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off,
136 int v)
137{
138 return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v);
139}
140
141static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off)
142{
143 return au1300_gpio_to_irq(off + AU1300_GPIO_BASE);
144}
145
146static struct gpio_chip au1300_gpiochip = {
147 .label = "alchemy-gpic",
148 .direction_input = alchemy_gpic_dir_input,
149 .direction_output = alchemy_gpic_dir_output,
150 .get = alchemy_gpic_get,
151 .set = alchemy_gpic_set,
152 .to_irq = alchemy_gpic_gpio_to_irq,
153 .base = AU1300_GPIO_BASE,
154 .ngpio = AU1300_GPIO_NUM,
155};
156
118static int __init alchemy_gpiochip_init(void) 157static int __init alchemy_gpiochip_init(void)
119{ 158{
120 int ret = 0; 159 int ret = 0;
@@ -127,6 +166,9 @@ static int __init alchemy_gpiochip_init(void)
127 ret = gpiochip_add(&alchemy_gpio_chip[0]); 166 ret = gpiochip_add(&alchemy_gpio_chip[0]);
128 ret |= gpiochip_add(&alchemy_gpio_chip[1]); 167 ret |= gpiochip_add(&alchemy_gpio_chip[1]);
129 break; 168 break;
169 case ALCHEMY_CPU_AU1300:
170 ret = gpiochip_add(&au1300_gpiochip);
171 break;
130 } 172 }
131 return ret; 173 return ret;
132} 174}
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index c8e5d72a582..95cb9113b12 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -82,6 +82,12 @@ static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {
82 PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT), 82 PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
83 PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT), 83 PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
84 }, 84 },
85 [ALCHEMY_CPU_AU1300] = {
86 PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT),
87 PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT),
88 PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT),
89 PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT),
90 },
85}; 91};
86 92
87static struct platform_device au1xx0_uart_device = { 93static struct platform_device au1xx0_uart_device = {
@@ -122,10 +128,12 @@ static unsigned long alchemy_ohci_data[][2] __initdata = {
122 [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT }, 128 [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
123 [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT }, 129 [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
124 [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT }, 130 [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
131 [ALCHEMY_CPU_AU1300] = { AU1300_USB_OHCI0_PHYS_ADDR, AU1300_USB_INT },
125}; 132};
126 133
127static unsigned long alchemy_ehci_data[][2] __initdata = { 134static unsigned long alchemy_ehci_data[][2] __initdata = {
128 [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT }, 135 [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
136 [ALCHEMY_CPU_AU1300] = { AU1300_USB_EHCI_PHYS_ADDR, AU1300_USB_INT },
129}; 137};
130 138
131static int __init _new_usbres(struct resource **r, struct platform_device **d) 139static int __init _new_usbres(struct resource **r, struct platform_device **d)
@@ -169,8 +177,8 @@ static void __init alchemy_setup_usb(int ctype)
169 printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n"); 177 printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
170 178
171 179
172 /* setup EHCI0: Au1200 */ 180 /* setup EHCI0: Au1200/Au1300 */
173 if (ctype == ALCHEMY_CPU_AU1200) { 181 if ((ctype == ALCHEMY_CPU_AU1200) || (ctype == ALCHEMY_CPU_AU1300)) {
174 if (_new_usbres(&res, &pdev)) 182 if (_new_usbres(&res, &pdev))
175 return; 183 return;
176 184
@@ -187,6 +195,25 @@ static void __init alchemy_setup_usb(int ctype)
187 if (platform_device_register(pdev)) 195 if (platform_device_register(pdev))
188 printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n"); 196 printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
189 } 197 }
198
199 /* Au1300: OHCI1 */
200 if (ctype == ALCHEMY_CPU_AU1300) {
201 if (_new_usbres(&res, &pdev))
202 return;
203
204 res[0].start = AU1300_USB_OHCI1_PHYS_ADDR;
205 res[0].end = res[0].start + 0x100 - 1;
206 res[0].flags = IORESOURCE_MEM;
207 res[1].start = AU1300_USB_INT;
208 res[1].end = res[1].start;
209 res[1].flags = IORESOURCE_IRQ;
210 pdev->name = "au1xxx-ohci";
211 pdev->id = 1;
212 pdev->dev.dma_mask = &alchemy_ohci_dmamask;
213
214 if (platform_device_register(pdev))
215 printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n");
216 }
190} 217}
191 218
192/* Macro to help defining the Ethernet MAC resources */ 219/* Macro to help defining the Ethernet MAC resources */
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index bdd6651e9a4..0c7fce2a3c1 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -126,6 +126,9 @@ void au_sleep(void)
126 case ALCHEMY_CPU_AU1200: 126 case ALCHEMY_CPU_AU1200:
127 alchemy_sleep_au1550(); 127 alchemy_sleep_au1550();
128 break; 128 break;
129 case ALCHEMY_CPU_AU1300:
130 alchemy_sleep_au1300();
131 break;
129 } 132 }
130 133
131 restore_core_regs(); 134 restore_core_regs();
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 77f3c743b71..c7bcc7e5c82 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -153,6 +153,79 @@ LEAF(alchemy_sleep_au1550)
153 153
154END(alchemy_sleep_au1550) 154END(alchemy_sleep_au1550)
155 155
156/* sleepcode for Au1300 memory controller type */
157LEAF(alchemy_sleep_au1300)
158
159 SETUP_SLEEP
160
161 /* cache following instructions, as memory gets put to sleep */
162 la t0, 2f
163 la t1, 4f
164 subu t2, t1, t0
165
166 .set mips3
167
1681: cache 0x14, 0(t0)
169 subu t2, t2, 32
170 bgez t2, 1b
171 addu t0, t0, 32
172
173 .set mips0
174
1752: lui a0, 0xb400 /* mem_xxx */
176
177 /* disable all ports in mem_sdportcfga */
178 sw zero, 0x868(a0) /* mem_sdportcfga */
179 sync
180
181 /* disable ODT */
182 li t0, 0x03010000
183 sw t0, 0x08d8(a0) /* mem_sdcmd0 */
184 sw t0, 0x08dc(a0) /* mem_sdcmd1 */
185 sync
186
187 /* precharge */
188 li t0, 0x23000400
189 sw t0, 0x08dc(a0) /* mem_sdcmd1 */
190 sw t0, 0x08d8(a0) /* mem_sdcmd0 */
191 sync
192
193 /* auto refresh */
194 sw zero, 0x08c8(a0) /* mem_sdautoref */
195 sync
196
197 /* block access to the DDR */
198 lw t0, 0x0848(a0) /* mem_sdconfigb */
199 li t1, (1 << 7 | 0x3F)
200 or t0, t0, t1
201 sw t0, 0x0848(a0) /* mem_sdconfigb */
202 sync
203
204 /* issue the Self Refresh command */
205 li t0, 0x10000000
206 sw t0, 0x08dc(a0) /* mem_sdcmd1 */
207 sw t0, 0x08d8(a0) /* mem_sdcmd0 */
208 sync
209
210 /* wait for sdram to enter self-refresh mode */
211 lui t0, 0x0300
2123: lw t1, 0x0850(a0) /* mem_sdstat */
213 and t2, t1, t0
214 bne t2, t0, 3b
215 nop
216
217 /* disable SDRAM clocks */
218 li t0, ~(3<<28)
219 lw t1, 0x0840(a0) /* mem_sdconfiga */
220 and t1, t1, t0 /* clear CE[1:0] */
221 sw t1, 0x0840(a0) /* mem_sdconfiga */
222 sync
223
224 DO_SLEEP
2254:
226
227END(alchemy_sleep_au1300)
228
156 229
157 /* This is where we return upon wakeup. 230 /* This is where we return upon wakeup.
158 * Reload all of the registers and return. 231 * Reload all of the registers and return.
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index d5da6adbf63..a594a85337d 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -178,6 +178,7 @@ static int alchemy_m2inttab[] __initdata = {
178 AU1100_RTC_MATCH2_INT, 178 AU1100_RTC_MATCH2_INT,
179 AU1550_RTC_MATCH2_INT, 179 AU1550_RTC_MATCH2_INT,
180 AU1200_RTC_MATCH2_INT, 180 AU1200_RTC_MATCH2_INT,
181 AU1300_RTC_MATCH2_INT,
181}; 182};
182 183
183void __init plat_time_init(void) 184void __init plat_time_init(void)
diff --git a/arch/mips/alchemy/common/vss.c b/arch/mips/alchemy/common/vss.c
new file mode 100644
index 00000000000..d23b1444d36
--- /dev/null
+++ b/arch/mips/alchemy/common/vss.c
@@ -0,0 +1,84 @@
1/*
2 * Au1300 media block power gating (VSS)
3 *
4 * This is a stop-gap solution until I have the clock framework integration
5 * ready. This stuff here really must be handled transparently when clocks
6 * for various media blocks are enabled/disabled.
7 */
8
9#include <linux/module.h>
10#include <linux/spinlock.h>
11#include <asm/mach-au1x00/au1000.h>
12
13#define VSS_GATE 0x00 /* gate wait timers */
14#define VSS_CLKRST 0x04 /* clock/block control */
15#define VSS_FTR 0x08 /* footers */
16
17#define VSS_ADDR(blk) (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c))
18
19static DEFINE_SPINLOCK(au1300_vss_lock);
20
21/* enable a block as outlined in the databook */
22static inline void __enable_block(int block)
23{
24 void __iomem *base = (void __iomem *)VSS_ADDR(block);
25
26 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */
27 wmb();
28
29 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */
30 wmb();
31
32 /* enable footers in sequence */
33 __raw_writel(0x01, base + VSS_FTR);
34 wmb();
35 __raw_writel(0x03, base + VSS_FTR);
36 wmb();
37 __raw_writel(0x07, base + VSS_FTR);
38 wmb();
39 __raw_writel(0x0f, base + VSS_FTR);
40 wmb();
41
42 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */
43 wmb();
44
45 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */
46 wmb();
47
48 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */
49 wmb();
50}
51
52/* disable a block as outlined in the databook */
53static inline void __disable_block(int block)
54{
55 void __iomem *base = (void __iomem *)VSS_ADDR(block);
56
57 __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */
58 wmb();
59 __raw_writel(0, base + VSS_GATE); /* disable FSM */
60 wmb();
61 __raw_writel(3, base + VSS_CLKRST); /* assert reset */
62 wmb();
63 __raw_writel(1, base + VSS_CLKRST); /* disable clock */
64 wmb();
65 __raw_writel(0, base + VSS_FTR); /* disable all footers */
66 wmb();
67}
68
69void au1300_vss_block_control(int block, int enable)
70{
71 unsigned long flags;
72
73 if (alchemy_get_cputype() != ALCHEMY_CPU_AU1300)
74 return;
75
76 /* only one block at a time */
77 spin_lock_irqsave(&au1300_vss_lock, flags);
78 if (enable)
79 __enable_block(block);
80 else
81 __disable_block(block);
82 spin_unlock_irqrestore(&au1300_vss_lock, flags);
83}
84EXPORT_SYMBOL_GPL(au1300_vss_block_control);
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 2f7f41873f2..79e4a0dad0d 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -169,6 +169,7 @@
169#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 169#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
170#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 170#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
171#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 171#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
172#define PRID_IMP_NETLOGIC_AU13XX 0x8000
172 173
173/* 174/*
174 * Definitions for 7:0 on legacy processors 175 * Definitions for 7:0 on legacy processors
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index de24ec57dd2..65f12621717 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void)
136#define ALCHEMY_CPU_AU1100 2 136#define ALCHEMY_CPU_AU1100 2
137#define ALCHEMY_CPU_AU1550 3 137#define ALCHEMY_CPU_AU1550 3
138#define ALCHEMY_CPU_AU1200 4 138#define ALCHEMY_CPU_AU1200 4
139#define ALCHEMY_CPU_AU1300 5
139 140
140static inline int alchemy_get_cputype(void) 141static inline int alchemy_get_cputype(void)
141{ 142{
@@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void)
156 case 0x05030000: 157 case 0x05030000:
157 return ALCHEMY_CPU_AU1200; 158 return ALCHEMY_CPU_AU1200;
158 break; 159 break;
160 case 0x800c0000:
161 return ALCHEMY_CPU_AU1300;
162 break;
159 } 163 }
160 164
161 return ALCHEMY_CPU_UNKNOWN; 165 return ALCHEMY_CPU_UNKNOWN;
@@ -166,6 +170,7 @@ static inline int alchemy_get_uarts(int type)
166{ 170{
167 switch (type) { 171 switch (type) {
168 case ALCHEMY_CPU_AU1000: 172 case ALCHEMY_CPU_AU1000:
173 case ALCHEMY_CPU_AU1300:
169 return 4; 174 return 4;
170 case ALCHEMY_CPU_AU1500: 175 case ALCHEMY_CPU_AU1500:
171 case ALCHEMY_CPU_AU1200: 176 case ALCHEMY_CPU_AU1200:
@@ -243,6 +248,7 @@ extern unsigned long au1xxx_calc_clock(void);
243/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ 248/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
244void alchemy_sleep_au1000(void); 249void alchemy_sleep_au1000(void);
245void alchemy_sleep_au1550(void); 250void alchemy_sleep_au1550(void);
251void alchemy_sleep_au1300(void);
246void au_sleep(void); 252void au_sleep(void);
247 253
248/* USB: drivers/usb/host/alchemy-common.c */ 254/* USB: drivers/usb/host/alchemy-common.c */
@@ -251,6 +257,7 @@ enum alchemy_usb_block {
251 ALCHEMY_USB_UDC0, 257 ALCHEMY_USB_UDC0,
252 ALCHEMY_USB_EHCI0, 258 ALCHEMY_USB_EHCI0,
253 ALCHEMY_USB_OTG0, 259 ALCHEMY_USB_OTG0,
260 ALCHEMY_USB_OHCI1,
254}; 261};
255int alchemy_usb_control(int block, int enable); 262int alchemy_usb_control(int block, int enable);
256 263
@@ -263,14 +270,92 @@ struct alchemy_pci_platdata {
263 unsigned long pci_cfg_clr; 270 unsigned long pci_cfg_clr;
264}; 271};
265 272
266/* SOC Interrupt numbers */ 273/* Multifunction pins: Each of these pins can either be assigned to the
274 * GPIO controller or a on-chip peripheral.
275 * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
276 * assign one of these to either the GPIO controller or the device.
277 */
278enum au1300_multifunc_pins {
279 /* wake-from-str pins 0-3 */
280 AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
281 AU1300_PIN_WAKE3,
282 /* external clock sources for PSCs: 4-5 */
283 AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
284 /* 8bit MMC interface on SD0: 6-9 */
285 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
286 AU1300_PIN_SD0DAT7,
287 /* aux clk input for freqgen 3: 10 */
288 AU1300_PIN_FG3AUX,
289 /* UART1 pins: 11-18 */
290 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
291 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
292 AU1300_PIN_U1RX, AU1300_PIN_U1TX,
293 /* UART0 pins: 19-24 */
294 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
295 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
296 /* UART2: 25-26 */
297 AU1300_PIN_U2RX, AU1300_PIN_U2TX,
298 /* UART3: 27-28 */
299 AU1300_PIN_U3RX, AU1300_PIN_U3TX,
300 /* LCD controller PWMs, ext pixclock: 29-31 */
301 AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
302 /* SD1 interface: 32-37 */
303 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
304 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
305 /* SD2 interface: 38-43 */
306 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
307 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
308 /* PSC0/1 clocks: 44-45 */
309 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
310 /* PSCs: 46-49/50-53/54-57/58-61 */
311 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
312 AU1300_PIN_PSC0D1,
313 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
314 AU1300_PIN_PSC1D1,
315 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
316 AU1300_PIN_PSC2D1,
317 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
318 AU1300_PIN_PSC3D1,
319 /* PCMCIA interface: 62-70 */
320 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
321 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
322 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
323 /* camera interface H/V sync inputs: 71-72 */
324 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
325 /* PSC2/3 clocks: 73-74 */
326 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
327};
328
329/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
330extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
331extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
332extern void au1300_set_irq_priority(unsigned int irq, int p);
333extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
334
335/* Au1300 allows to disconnect certain blocks from internal power supply */
336enum au1300_vss_block {
337 AU1300_VSS_MPE = 0,
338 AU1300_VSS_BSA,
339 AU1300_VSS_GPE,
340 AU1300_VSS_MGP,
341};
342
343extern void au1300_vss_block_control(int block, int enable);
344
267 345
346/* SOC Interrupt numbers */
347/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
268#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 348#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
269#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) 349#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
270#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) 350#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
271#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) 351#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
272#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST 352#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
273 353
354/* Au1300-style (GPIC): 1 controller with up to 128 sources */
355#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
356#define ALCHEMY_GPIC_INT_NUM 128
357#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
358
274enum soc_au1000_ints { 359enum soc_au1000_ints {
275 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, 360 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
276 AU1000_UART0_INT = AU1000_FIRST_INT, 361 AU1000_UART0_INT = AU1000_FIRST_INT,
@@ -591,24 +676,77 @@ enum soc_au1200_ints {
591 676
592#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 677#endif /* !defined (_LANGUAGE_ASSEMBLY) */
593 678
679/* Au1300 peripheral interrupt numbers */
680#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
681#define AU1300_UART1_INT (AU1300_FIRST_INT + 17)
682#define AU1300_UART2_INT (AU1300_FIRST_INT + 25)
683#define AU1300_UART3_INT (AU1300_FIRST_INT + 27)
684#define AU1300_SD1_INT (AU1300_FIRST_INT + 32)
685#define AU1300_SD2_INT (AU1300_FIRST_INT + 38)
686#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48)
687#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52)
688#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56)
689#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60)
690#define AU1300_NAND_INT (AU1300_FIRST_INT + 62)
691#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75)
692#define AU1300_MMU_INT (AU1300_FIRST_INT + 76)
693#define AU1300_MPU_INT (AU1300_FIRST_INT + 77)
694#define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
695#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79)
696#define AU1300_TOY_INT (AU1300_FIRST_INT + 80)
697#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81)
698#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82)
699#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83)
700#define AU1300_RTC_INT (AU1300_FIRST_INT + 84)
701#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85)
702#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86)
703#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87)
704#define AU1300_UART0_INT (AU1300_FIRST_INT + 88)
705#define AU1300_SD0_INT (AU1300_FIRST_INT + 89)
706#define AU1300_USB_INT (AU1300_FIRST_INT + 90)
707#define AU1300_LCD_INT (AU1300_FIRST_INT + 91)
708#define AU1300_BSA_INT (AU1300_FIRST_INT + 92)
709#define AU1300_MPE_INT (AU1300_FIRST_INT + 93)
710#define AU1300_ITE_INT (AU1300_FIRST_INT + 94)
711#define AU1300_AES_INT (AU1300_FIRST_INT + 95)
712#define AU1300_CIM_INT (AU1300_FIRST_INT + 96)
713
714/**********************************************************************/
715
594/* 716/*
595 * Physical base addresses for integrated peripherals 717 * Physical base addresses for integrated peripherals
596 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 718 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
597 */ 719 */
598 720
599#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ 721#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
722#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
723#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
724#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
725#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
726#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
727#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
728#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
600#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ 729#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
601#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ 730#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
731#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
602#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ 732#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
603#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */ 733#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
604#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ 734#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
735#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
605#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ 736#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
606#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ 737#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
607#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ 738#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
608#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ 739#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
740#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
741#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
609#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ 742#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
743#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
610#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ 744#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
611#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ 745#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
746#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
747#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
748#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
749#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
612#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ 750#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
613#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ 751#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
614#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ 752#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
@@ -622,38 +760,97 @@ enum soc_au1200_ints {
622#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ 760#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
623#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ 761#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
624#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ 762#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
625#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ 763#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
626#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ 764#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
627#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ 765#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
628#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ 766#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
629#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ 767#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
768#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
630#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ 769#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
631#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ 770#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
632#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ 771#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
633#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ 772#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
634#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ 773#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
635#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */ 774#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
636#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ 775#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
637#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ 776#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
638#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ 777#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
639#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ 778#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
779#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
780#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
640#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ 781#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
641#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ 782#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
642#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ 783#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
643#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ 784#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
644#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ 785#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
645#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ 786#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
787#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
788#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
789#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
790#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
791#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
792#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
646#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ 793#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
647#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */ 794#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
648#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ 795#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
649#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ 796#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
650#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ 797#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
651#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ 798#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
652#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */ 799#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
653#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */ 800#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
654#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ 801#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
802
803/**********************************************************************/
655 804
656 805
806/*
807 * Au1300 GPIO+INT controller (GPIC) register offsets and bits
808 * Registers are 128bits (0x10 bytes), divided into 4 "banks".
809 */
810#define AU1300_GPIC_PINVAL 0x0000
811#define AU1300_GPIC_PINVALCLR 0x0010
812#define AU1300_GPIC_IPEND 0x0020
813#define AU1300_GPIC_PRIENC 0x0030
814#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
815#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
816#define AU1300_GPIC_DMASEL 0x0060
817#define AU1300_GPIC_DEVSEL 0x0080
818#define AU1300_GPIC_DEVCLR 0x0090
819#define AU1300_GPIC_RSTVAL 0x00a0
820/* pin configuration space. one 32bit register for up to 128 IRQs */
821#define AU1300_GPIC_PINCFG 0x1000
822
823#define GPIC_GPIO_TO_BIT(gpio) \
824 (1 << ((gpio) & 0x1f))
825
826#define GPIC_GPIO_BANKOFF(gpio) \
827 (((gpio) >> 5) * 4)
828
829/* Pin Control bits: who owns the pin, what does it do */
830#define GPIC_CFG_PC_GPIN 0
831#define GPIC_CFG_PC_DEV 1
832#define GPIC_CFG_PC_GPOLOW 2
833#define GPIC_CFG_PC_GPOHIGH 3
834#define GPIC_CFG_PC_MASK 3
835
836/* assign pin to MIPS IRQ line */
837#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2)
838#define GPIC_CFG_IL_MASK (3 << 2)
839
840/* pin interrupt type setup */
841#define GPIC_CFG_IC_OFF (0 << 4)
842#define GPIC_CFG_IC_LEVEL_LOW (1 << 4)
843#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4)
844#define GPIC_CFG_IC_EDGE_FALL (5 << 4)
845#define GPIC_CFG_IC_EDGE_RISE (6 << 4)
846#define GPIC_CFG_IC_EDGE_BOTH (7 << 4)
847#define GPIC_CFG_IC_MASK (7 << 4)
848
849/* allow interrupt to wake cpu from 'wait' */
850#define GPIC_CFG_IDLEWAKE (1 << 7)
851
852/***********************************************************************/
853
657/* Au1000 SDRAM memory controller register offsets */ 854/* Au1000 SDRAM memory controller register offsets */
658#define AU1000_MEM_SDMODE0 0x0000 855#define AU1000_MEM_SDMODE0 0x0000
659#define AU1000_MEM_SDMODE1 0x0004 856#define AU1000_MEM_SDMODE1 0x0004
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index 94000a3b6f0..e221659f1bc 100644
--- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -130,8 +130,10 @@ struct au1xmmc_platform_data {
130#define SD_CONFIG2_DF (0x00000008) 130#define SD_CONFIG2_DF (0x00000008)
131#define SD_CONFIG2_DC (0x00000010) 131#define SD_CONFIG2_DC (0x00000010)
132#define SD_CONFIG2_xx2 (0x000000e0) 132#define SD_CONFIG2_xx2 (0x000000e0)
133#define SD_CONFIG2_BB (0x00000080)
133#define SD_CONFIG2_WB (0x00000100) 134#define SD_CONFIG2_WB (0x00000100)
134#define SD_CONFIG2_RW (0x00000200) 135#define SD_CONFIG2_RW (0x00000200)
136#define SD_CONFIG2_DP (0x00000400)
135 137
136 138
137/* 139/*
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 323ce2d145f..217810e1836 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -183,6 +183,37 @@ typedef volatile struct au1xxx_ddma_desc {
183#define AU1200_DSCR_CMD0_PSC1_SYNC 25 183#define AU1200_DSCR_CMD0_PSC1_SYNC 25
184#define AU1200_DSCR_CMD0_CIM_SYNC 26 184#define AU1200_DSCR_CMD0_CIM_SYNC 26
185 185
186#define AU1300_DSCR_CMD0_UART0_TX 0
187#define AU1300_DSCR_CMD0_UART0_RX 1
188#define AU1300_DSCR_CMD0_UART1_TX 2
189#define AU1300_DSCR_CMD0_UART1_RX 3
190#define AU1300_DSCR_CMD0_UART2_TX 4
191#define AU1300_DSCR_CMD0_UART2_RX 5
192#define AU1300_DSCR_CMD0_UART3_TX 6
193#define AU1300_DSCR_CMD0_UART3_RX 7
194#define AU1300_DSCR_CMD0_SDMS_TX0 8
195#define AU1300_DSCR_CMD0_SDMS_RX0 9
196#define AU1300_DSCR_CMD0_SDMS_TX1 10
197#define AU1300_DSCR_CMD0_SDMS_RX1 11
198#define AU1300_DSCR_CMD0_AES_TX 12
199#define AU1300_DSCR_CMD0_AES_RX 13
200#define AU1300_DSCR_CMD0_PSC0_TX 14
201#define AU1300_DSCR_CMD0_PSC0_RX 15
202#define AU1300_DSCR_CMD0_PSC1_TX 16
203#define AU1300_DSCR_CMD0_PSC1_RX 17
204#define AU1300_DSCR_CMD0_PSC2_TX 18
205#define AU1300_DSCR_CMD0_PSC2_RX 19
206#define AU1300_DSCR_CMD0_PSC3_TX 20
207#define AU1300_DSCR_CMD0_PSC3_RX 21
208#define AU1300_DSCR_CMD0_LCD 22
209#define AU1300_DSCR_CMD0_NAND_FLASH 23
210#define AU1300_DSCR_CMD0_SDMS_TX2 24
211#define AU1300_DSCR_CMD0_SDMS_RX2 25
212#define AU1300_DSCR_CMD0_CIM_SYNC 26
213#define AU1300_DSCR_CMD0_UDMA 27
214#define AU1300_DSCR_CMD0_DMA_REQ0 28
215#define AU1300_DSCR_CMD0_DMA_REQ1 29
216
186#define DSCR_CMD0_THROTTLE 30 217#define DSCR_CMD0_THROTTLE 30
187#define DSCR_CMD0_ALWAYS 31 218#define DSCR_CMD0_ALWAYS 31
188#define DSCR_NDEV_IDS 32 219#define DSCR_NDEV_IDS 32
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
new file mode 100644
index 00000000000..556e1be20bf
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
@@ -0,0 +1,241 @@
1/*
2 * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
3 *
4 * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
5 */
6
7#ifndef _GPIO_AU1300_H_
8#define _GPIO_AU1300_H_
9
10#include <asm/addrspace.h>
11#include <asm/io.h>
12#include <asm/mach-au1x00/au1000.h>
13
14/* with the current GPIC design, up to 128 GPIOs are possible.
15 * The only implementation so far is in the Au1300, which has 75 externally
16 * available GPIOs.
17 */
18#define AU1300_GPIO_BASE 0
19#define AU1300_GPIO_NUM 75
20#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
21
22#define AU1300_GPIC_ADDR \
23 (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
24
25static inline int au1300_gpio_get_value(unsigned int gpio)
26{
27 void __iomem *roff = AU1300_GPIC_ADDR;
28 int bit;
29
30 gpio -= AU1300_GPIO_BASE;
31 roff += GPIC_GPIO_BANKOFF(gpio);
32 bit = GPIC_GPIO_TO_BIT(gpio);
33 return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
34}
35
36static inline int au1300_gpio_direction_input(unsigned int gpio)
37{
38 void __iomem *roff = AU1300_GPIC_ADDR;
39 unsigned long bit;
40
41 gpio -= AU1300_GPIO_BASE;
42
43 roff += GPIC_GPIO_BANKOFF(gpio);
44 bit = GPIC_GPIO_TO_BIT(gpio);
45 __raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
46 wmb();
47
48 return 0;
49}
50
51static inline int au1300_gpio_set_value(unsigned int gpio, int v)
52{
53 void __iomem *roff = AU1300_GPIC_ADDR;
54 unsigned long bit;
55
56 gpio -= AU1300_GPIO_BASE;
57
58 roff += GPIC_GPIO_BANKOFF(gpio);
59 bit = GPIC_GPIO_TO_BIT(gpio);
60 __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
61 : AU1300_GPIC_PINVALCLR));
62 wmb();
63
64 return 0;
65}
66
67static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
68{
69 /* hw switches to output automatically */
70 return au1300_gpio_set_value(gpio, v);
71}
72
73static inline int au1300_gpio_to_irq(unsigned int gpio)
74{
75 return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
76}
77
78static inline int au1300_irq_to_gpio(unsigned int irq)
79{
80 return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
81}
82
83static inline int au1300_gpio_is_valid(unsigned int gpio)
84{
85 int ret;
86
87 switch (alchemy_get_cputype()) {
88 case ALCHEMY_CPU_AU1300:
89 ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
90 break;
91 default:
92 ret = 0;
93 }
94 return ret;
95}
96
97static inline int au1300_gpio_cansleep(unsigned int gpio)
98{
99 return 0;
100}
101
102/* hardware remembers gpio 0-63 levels on powerup */
103static inline int au1300_gpio_getinitlvl(unsigned int gpio)
104{
105 void __iomem *roff = AU1300_GPIC_ADDR;
106 unsigned long v;
107
108 if (unlikely(gpio > 63))
109 return 0;
110 else if (gpio > 31) {
111 gpio -= 32;
112 roff += 4;
113 }
114
115 v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
116 return (v >> gpio) & 1;
117}
118
119/**********************************************************************/
120
121/* Linux gpio framework integration.
122*
123* 4 use cases of Alchemy GPIOS:
124*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
125* Board must register gpiochips.
126*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
127* A gpiochip for the 75 GPIOs is registered.
128*
129*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
130* the boards' gpio.h must provide the linux gpio wrapper functions,
131*
132*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
133* inlinable gpio functions are provided which enable access to the
134* Au1300 gpios only by using the numbers straight out of the data-
135* sheets.
136
137* Cases 1 and 3 are intended for boards which want to provide their own
138* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
139* which are in part provided by spare Au1300 GPIO pins and in part by
140* an external FPGA but you still want them to be accssible in linux
141* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
142* as required).
143*/
144
145#ifndef CONFIG_GPIOLIB
146
147#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300
148
149#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
150
151static inline int gpio_direction_input(unsigned int gpio)
152{
153 return au1300_gpio_direction_input(gpio);
154}
155
156static inline int gpio_direction_output(unsigned int gpio, int v)
157{
158 return au1300_gpio_direction_output(gpio, v);
159}
160
161static inline int gpio_get_value(unsigned int gpio)
162{
163 return au1300_gpio_get_value(gpio);
164}
165
166static inline void gpio_set_value(unsigned int gpio, int v)
167{
168 au1300_gpio_set_value(gpio, v);
169}
170
171static inline int gpio_get_value_cansleep(unsigned gpio)
172{
173 return gpio_get_value(gpio);
174}
175
176static inline void gpio_set_value_cansleep(unsigned gpio, int value)
177{
178 gpio_set_value(gpio, value);
179}
180
181static inline int gpio_is_valid(unsigned int gpio)
182{
183 return au1300_gpio_is_valid(gpio);
184}
185
186static inline int gpio_cansleep(unsigned int gpio)
187{
188 return au1300_gpio_cansleep(gpio);
189}
190
191static inline int gpio_to_irq(unsigned int gpio)
192{
193 return au1300_gpio_to_irq(gpio);
194}
195
196static inline int irq_to_gpio(unsigned int irq)
197{
198 return au1300_irq_to_gpio(irq);
199}
200
201static inline int gpio_request(unsigned int gpio, const char *label)
202{
203 return 0;
204}
205
206static inline void gpio_free(unsigned int gpio)
207{
208}
209
210static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
211{
212 return -ENOSYS;
213}
214
215static inline void gpio_unexport(unsigned gpio)
216{
217}
218
219static inline int gpio_export(unsigned gpio, bool direction_may_change)
220{
221 return -ENOSYS;
222}
223
224static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
225{
226 return -ENOSYS;
227}
228
229static inline int gpio_export_link(struct device *dev, const char *name,
230 unsigned gpio)
231{
232 return -ENOSYS;
233}
234
235#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
236
237#endif /* CONFIG_ALCHEMY_GPIOINT_AU1300 */
238
239#endif /* CONFIG GPIOLIB */
240
241#endif /* _GPIO_AU1300_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index fcdc8c4809d..22e7ff17fc4 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -12,6 +12,7 @@
12 12
13#include <asm/mach-au1x00/au1000.h> 13#include <asm/mach-au1x00/au1000.h>
14#include <asm/mach-au1x00/gpio-au1000.h> 14#include <asm/mach-au1x00/gpio-au1000.h>
15#include <asm/mach-au1x00/gpio-au1300.h>
15 16
16/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before 17/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
17 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this 18 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
@@ -58,6 +59,8 @@ static inline int __au_irq_to_gpio(unsigned int irq)
58 switch (alchemy_get_cputype()) { 59 switch (alchemy_get_cputype()) {
59 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200: 60 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
60 return alchemy_irq_to_gpio(irq); 61 return alchemy_irq_to_gpio(irq);
62 case ALCHEMY_CPU_AU1300:
63 return au1300_irq_to_gpio(irq);
61 } 64 }
62 return -EINVAL; 65 return -EINVAL;
63} 66}
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c7d3cf1ce46..98383995e6a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1014,6 +1014,13 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1014{ 1014{
1015 decode_configs(c); 1015 decode_configs(c);
1016 1016
1017 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1018 c->cputype = CPU_ALCHEMY;
1019 __cpu_name[cpu] = "Au1300";
1020 /* following stuff is not for Alchemy */
1021 return;
1022 }
1023
1017 c->options = (MIPS_CPU_TLB | 1024 c->options = (MIPS_CPU_TLB |
1018 MIPS_CPU_4KEX | 1025 MIPS_CPU_4KEX |
1019 MIPS_CPU_COUNTER | 1026 MIPS_CPU_COUNTER |
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 04:28:07 -0400