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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-07-25 10:01:35 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-30 16:54:38 -0400
commit455cc256eb23915100e203fb33ee143afd127954 (patch)
tree1ad0c410fef0f7d82587347c3d3e4d4c9646dcee /arch/mips/txx9/jmr3927/irq.c
parent07517529225ae4ce770271f83d8cd1004733a01d (diff)
[MIPS] TXx9: PCI error handling
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Date: Thu, 24 Jul 2008 00:25:16 +0900 Subject: [PATCH] txx9: PCI error handling Add more control and detailed report on PCI error interrupt. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/txx9/jmr3927/irq.c')
-rw-r--r--arch/mips/txx9/jmr3927/irq.c20
1 files changed, 0 insertions, 20 deletions
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c
index 070c9a115e5..f3b60233e99 100644
--- a/arch/mips/txx9/jmr3927/irq.c
+++ b/arch/mips/txx9/jmr3927/irq.c
@@ -103,22 +103,6 @@ static int jmr3927_irq_dispatch(int pending)
103 return irq; 103 return irq;
104} 104}
105 105
106#ifdef CONFIG_PCI
107static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
108{
109 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
110 printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
111 tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
112
113 return IRQ_HANDLED;
114}
115static struct irqaction pcierr_action = {
116 .handler = jmr3927_pcierr_interrupt,
117 .mask = CPU_MASK_NONE,
118 .name = "PCI error",
119};
120#endif
121
122static void __init jmr3927_irq_init(void); 106static void __init jmr3927_irq_init(void);
123 107
124void __init jmr3927_irq_setup(void) 108void __init jmr3927_irq_setup(void)
@@ -143,10 +127,6 @@ void __init jmr3927_irq_setup(void)
143 /* setup IOC interrupt 1 (PCI, MODEM) */ 127 /* setup IOC interrupt 1 (PCI, MODEM) */
144 set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); 128 set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
145 129
146#ifdef CONFIG_PCI
147 setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
148#endif
149
150 /* enable all CPU interrupt bits. */ 130 /* enable all CPU interrupt bits. */
151 set_c0_status(ST0_IM); /* IE bit is still 0. */ 131 set_c0_status(ST0_IM); /* IE bit is still 0. */
152} 132}