Merge branch 'consolidate-clksrc-i8253' of master.kernel.org:~rmk/linux-2.6-arm into timers/clocksource

Conflicts:
	arch/ia64/kernel/cyclone.c
	arch/mips/kernel/i8253.c
	arch/x86/kernel/i8253.c

Reason: Resolve conflicts so further cleanups do not conflict further

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

5 files changed, 28 insertions, 33 deletions

diff --git a/arch/mips/sgi-ip27/Kconfig b/arch/mips/sgi-ip27/Kconfig
index 5e960ae9735..bc5e9769bb7 100644
--- a/arch/mips/sgi-ip27/Kconfig
+++ b/arch/mips/sgi-ip27/Kconfig
@@ -1,7 +1,7 @@
 #config SGI_SN0_XXL
 #       bool "IP27 XXL"
 #       depends on SGI_IP27
-#         This options adds support for userspace processes upto 16TB size.
+#         This options adds support for userspace processes up to 16TB size.
 #         Normally the limit is just .5TB.
 
 choice
diff --git a/arch/mips/sgi-ip27/TODO b/arch/mips/sgi-ip27/TODO
index 19f1512c8f2..160857ff148 100644
--- a/arch/mips/sgi-ip27/TODO
+++ b/arch/mips/sgi-ip27/TODO
@@ -13,7 +13,7 @@ being invoked on all nodes in ip27-memory.c.
 9. start_thread must turn off UX64 ... and define tlb_refill_debug.
 10. Need a bad pmd table, bad pte table. __bad_pmd_table/__bad_pagetable
 does not agree with pgd_bad/pmd_bad.
-11. All intrs (ip27_do_irq handlers) are targetted at cpu A on the node.
+11. All intrs (ip27_do_irq handlers) are targeted at cpu A on the node.
 This might need to change later. Only the timer intr is set up to be
 received on both Cpu A and B. (ip27_do_irq()/bridge_startup())
 13. Cache flushing (specially the SMP version) has to be investigated.
diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index 51d3a4f2d7e..923c080f77b 100644
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -93,7 +93,7 @@ static void __cpuinit per_hub_init(cnodeid_t cnode)
 
         /*
          * Some interrupts are reserved by hardware or by software convention.
-         * Mark these as reserved right away so they won't be used accidently
+         * Mark these as reserved right away so they won't be used accidentally
          * later.
          */
         for (i = 0; i <= BASE_PCI_IRQ; i++) {
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 6a123ea72de..0a04603d577 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -41,7 +41,7 @@
  * Linux has a controller-independent x86 interrupt architecture.
  * every controller has a 'controller-template', that is used
  * by the main code to do the right thing. Each driver-visible
- * interrupt source is transparently wired to the apropriate
+ * interrupt source is transparently wired to the appropriate
  * controller. Thus drivers need not be aware of the
  * interrupt-controller.
  *
@@ -240,7 +240,7 @@ static int intr_disconnect_level(int cpu, int bit)
 }
 
 /* Startup one of the (PCI ...) IRQs routes over a bridge.  */
-static unsigned int startup_bridge_irq(unsigned int irq)
+static unsigned int startup_bridge_irq(struct irq_data *d)
 {
         struct bridge_controller *bc;
         bridgereg_t device;
@@ -248,16 +248,16 @@ static unsigned int startup_bridge_irq(unsigned int irq)
         int pin, swlevel;
         cpuid_t cpu;
 
-        pin = SLOT_FROM_PCI_IRQ(irq);
-        bc = IRQ_TO_BRIDGE(irq);
+        pin = SLOT_FROM_PCI_IRQ(d->irq);
+        bc = IRQ_TO_BRIDGE(d->irq);
         bridge = bc->base;
 
-        pr_debug("bridge_startup(): irq= 0x%x  pin=%d\n", irq, pin);
+        pr_debug("bridge_startup(): irq= 0x%x  pin=%d\n", d->irq, pin);
         /*
          * "map" irq to a swlevel greater than 6 since the first 6 bits
          * of INT_PEND0 are taken
          */
-        swlevel = find_level(&cpu, irq);
+        swlevel = find_level(&cpu, d->irq);
         bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
         bridge->b_int_enable |= (1 << pin);
         bridge->b_int_enable |= 0x7ffffe00;     /* more stuff in int_enable */
@@ -288,58 +288,56 @@ static unsigned int startup_bridge_irq(unsigned int irq)
 }
 
 /* Shutdown one of the (PCI ...) IRQs routes over a bridge.  */
-static void shutdown_bridge_irq(unsigned int irq)
+static void shutdown_bridge_irq(struct irq_data *d)
 {
-        struct bridge_controller *bc = IRQ_TO_BRIDGE(irq);
+        struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq);
         bridge_t *bridge = bc->base;
         int pin, swlevel;
         cpuid_t cpu;
 
-        pr_debug("bridge_shutdown: irq 0x%x\n", irq);
-        pin = SLOT_FROM_PCI_IRQ(irq);
+        pr_debug("bridge_shutdown: irq 0x%x\n", d->irq);
+        pin = SLOT_FROM_PCI_IRQ(d->irq);
 
         /*
          * map irq to a swlevel greater than 6 since the first 6 bits
          * of INT_PEND0 are taken
          */
-        swlevel = find_level(&cpu, irq);
+        swlevel = find_level(&cpu, d->irq);
         intr_disconnect_level(cpu, swlevel);
 
         bridge->b_int_enable &= ~(1 << pin);
         bridge->b_wid_tflush;
 }
 
-static inline void enable_bridge_irq(unsigned int irq)
+static inline void enable_bridge_irq(struct irq_data *d)
 {
         cpuid_t cpu;
         int swlevel;
 
-        swlevel = find_level(&cpu, irq);        /* Criminal offence */
+        swlevel = find_level(&cpu, d->irq);     /* Criminal offence */
         intr_connect_level(cpu, swlevel);
 }
 
-static inline void disable_bridge_irq(unsigned int irq)
+static inline void disable_bridge_irq(struct irq_data *d)
 {
         cpuid_t cpu;
         int swlevel;
 
-        swlevel = find_level(&cpu, irq);        /* Criminal offence */
+        swlevel = find_level(&cpu, d->irq);     /* Criminal offence */
         intr_disconnect_level(cpu, swlevel);
 }
 
 static struct irq_chip bridge_irq_type = {
         .name           = "bridge",
-        .startup        = startup_bridge_irq,
-        .shutdown       = shutdown_bridge_irq,
-        .ack            = disable_bridge_irq,
-        .mask           = disable_bridge_irq,
-        .mask_ack       = disable_bridge_irq,
-        .unmask         = enable_bridge_irq,
+        .irq_startup    = startup_bridge_irq,
+        .irq_shutdown   = shutdown_bridge_irq,
+        .irq_mask       = disable_bridge_irq,
+        .irq_unmask     = enable_bridge_irq,
 };
 
 void __devinit register_bridge_irq(unsigned int irq)
 {
-        set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
+        irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
 }
 
 int __devinit request_bridge_irq(struct bridge_controller *bc)
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 3cac88382d4..8d0d2690e96 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -36,21 +36,18 @@
 #include <asm/sn/sn0/hubio.h>
 #include <asm/pci/bridge.h>
 
-static void enable_rt_irq(unsigned int irq)
+static void enable_rt_irq(struct irq_data *d)
 {
 }
 
-static void disable_rt_irq(unsigned int irq)
+static void disable_rt_irq(struct irq_data *d)
 {
 }
 
 static struct irq_chip rt_irq_type = {
         .name           = "SN HUB RT timer",
-        .ack            = disable_rt_irq,
-        .mask           = disable_rt_irq,
-        .mask_ack       = disable_rt_irq,
-        .unmask         = enable_rt_irq,
-        .eoi            = enable_rt_irq,
+        .irq_mask       = disable_rt_irq,
+        .irq_unmask     = enable_rt_irq,
 };
 
 static int rt_next_event(unsigned long delta, struct clock_event_device *evt)
@@ -156,7 +153,7 @@ static void __init hub_rt_clock_event_global_init(void)
                         panic("Allocation of irq number for timer failed");
         } while (xchg(&rt_timer_irq, irq));
 
-        set_irq_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq);
+        irq_set_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq);
         setup_irq(irq, &hub_rt_irqaction);
 }