[MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irq

Further incorporation of generic irq framework.  Replacing __do_IRQ()
by proper flow handler would make the irq handling path a bit simpler
and faster.

* use generic_handle_irq() instead of __do_IRQ().
* use handle_level_irq for obvious level-type irq chips.
* use handle_percpu_irq for irqs marked as IRQ_PER_CPU.
* setup .eoi routine for irq chips possibly used with handle_percpu_irq.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 7 insertions, 5 deletions

diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index e4bf494dd43..0dc23930edb 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -192,7 +192,7 @@ void __init arch_init_irq(void)
         int configPR;
 
         for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
-                set_irq_chip(i, &level_irq_type);
+                set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
                 mask_irq(i);    /* mask the irq just in case  */
         }
 
@@ -229,7 +229,7 @@ void __init arch_init_irq(void)
                 /* mask/priority is still 0 so we will not get any
                  * interrupts until it is unmasked */
 
-                set_irq_chip(i, &level_irq_type);
+                set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
         }
 
         /* Priority level 0 */
@@ -238,19 +238,21 @@ void __init arch_init_irq(void)
         /* Set int vector table address */
         PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
 
-        set_irq_chip(MIPS_CPU_GIC_IRQ, &level_irq_type);
+        set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
+                                 handle_level_irq);
         setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
 
         /* init of Timer interrupts */
         for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
-                set_irq_chip(i, &level_irq_type);
+                set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
 
         /* Stop Timer 1-3 */
         configPR = read_c0_config7();
         configPR |= 0x00000038;
         write_c0_config7(configPR);
 
-        set_irq_chip(MIPS_CPU_TIMER_IRQ, &level_irq_type);
+        set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
+                                 handle_level_irq);
         setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
 }