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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /arch/mips/netlogic/xlr
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'arch/mips/netlogic/xlr')
-rw-r--r--arch/mips/netlogic/xlr/Makefile7
-rw-r--r--arch/mips/netlogic/xlr/fmn-config.c290
-rw-r--r--arch/mips/netlogic/xlr/fmn.c204
-rw-r--r--arch/mips/netlogic/xlr/platform-flash.c220
-rw-r--r--arch/mips/netlogic/xlr/platform.c182
-rw-r--r--arch/mips/netlogic/xlr/setup.c60
-rw-r--r--arch/mips/netlogic/xlr/wakeup.c85
7 files changed, 34 insertions, 1014 deletions
diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
index 05902bc6f08..2dca585dd2f 100644
--- a/arch/mips/netlogic/xlr/Makefile
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -1,2 +1,5 @@
1obj-y += fmn.o fmn-config.o setup.o platform.o platform-flash.o 1obj-y += setup.o platform.o irq.o setup.o time.o
2obj-$(CONFIG_SMP) += wakeup.o 2obj-$(CONFIG_SMP) += smp.o smpboot.o
3obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o
4
5ccflags-y += -Werror
diff --git a/arch/mips/netlogic/xlr/fmn-config.c b/arch/mips/netlogic/xlr/fmn-config.c
deleted file mode 100644
index bed2cffa100..00000000000
--- a/arch/mips/netlogic/xlr/fmn-config.c
+++ /dev/null
@@ -1,290 +0,0 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <asm/cpu-info.h>
36#include <linux/irq.h>
37#include <linux/interrupt.h>
38
39#include <asm/mipsregs.h>
40#include <asm/netlogic/xlr/fmn.h>
41#include <asm/netlogic/xlr/xlr.h>
42#include <asm/netlogic/common.h>
43#include <asm/netlogic/haldefs.h>
44
45struct xlr_board_fmn_config xlr_board_fmn_config;
46
47static void __maybe_unused print_credit_config(struct xlr_fmn_info *fmn_info)
48{
49 int bkt;
50
51 pr_info("Bucket size :\n");
52 pr_info("Station\t: Size\n");
53 for (bkt = 0; bkt < 16; bkt++)
54 pr_info(" %d %d %d %d %d %d %d %d\n",
55 xlr_board_fmn_config.bucket_size[(bkt * 8) + 0],
56 xlr_board_fmn_config.bucket_size[(bkt * 8) + 1],
57 xlr_board_fmn_config.bucket_size[(bkt * 8) + 2],
58 xlr_board_fmn_config.bucket_size[(bkt * 8) + 3],
59 xlr_board_fmn_config.bucket_size[(bkt * 8) + 4],
60 xlr_board_fmn_config.bucket_size[(bkt * 8) + 5],
61 xlr_board_fmn_config.bucket_size[(bkt * 8) + 6],
62 xlr_board_fmn_config.bucket_size[(bkt * 8) + 7]);
63 pr_info("\n");
64
65 pr_info("Credits distribution :\n");
66 pr_info("Station\t: Size\n");
67 for (bkt = 0; bkt < 16; bkt++)
68 pr_info(" %d %d %d %d %d %d %d %d\n",
69 fmn_info->credit_config[(bkt * 8) + 0],
70 fmn_info->credit_config[(bkt * 8) + 1],
71 fmn_info->credit_config[(bkt * 8) + 2],
72 fmn_info->credit_config[(bkt * 8) + 3],
73 fmn_info->credit_config[(bkt * 8) + 4],
74 fmn_info->credit_config[(bkt * 8) + 5],
75 fmn_info->credit_config[(bkt * 8) + 6],
76 fmn_info->credit_config[(bkt * 8) + 7]);
77 pr_info("\n");
78}
79
80static void check_credit_distribution(void)
81{
82 struct xlr_board_fmn_config *cfg = &xlr_board_fmn_config;
83 int bkt, n, total_credits, ncores;
84
85 ncores = hweight32(nlm_current_node()->coremask);
86 for (bkt = 0; bkt < 128; bkt++) {
87 total_credits = 0;
88 for (n = 0; n < ncores; n++)
89 total_credits += cfg->cpu[n].credit_config[bkt];
90 total_credits += cfg->gmac[0].credit_config[bkt];
91 total_credits += cfg->gmac[1].credit_config[bkt];
92 total_credits += cfg->dma.credit_config[bkt];
93 total_credits += cfg->cmp.credit_config[bkt];
94 total_credits += cfg->sae.credit_config[bkt];
95 total_credits += cfg->xgmac[0].credit_config[bkt];
96 total_credits += cfg->xgmac[1].credit_config[bkt];
97 if (total_credits > cfg->bucket_size[bkt])
98 pr_err("ERROR: Bucket %d: credits (%d) > size (%d)\n",
99 bkt, total_credits, cfg->bucket_size[bkt]);
100 }
101 pr_info("Credit distribution complete.\n");
102}
103
104/**
105 * Configure bucket size and credits for a device. 'size' is the size of
106 * the buckets for the device. This size is distributed among all the CPUs
107 * so that all of them can send messages to the device.
108 *
109 * The device is also given 'cpu_credits' to send messages to the CPUs
110 *
111 * @dev_info: FMN information structure for each devices
112 * @start_stn_id: Starting station id of dev_info
113 * @end_stn_id: End station id of dev_info
114 * @num_buckets: Total number of buckets for den_info
115 * @cpu_credits: Allowed credits to cpu for each devices pointing by dev_info
116 * @size: Size of the each buckets in the device station
117 */
118static void setup_fmn_cc(struct xlr_fmn_info *dev_info, int start_stn_id,
119 int end_stn_id, int num_buckets, int cpu_credits, int size)
120{
121 int i, j, num_core, n, credits_per_cpu;
122 struct xlr_fmn_info *cpu = xlr_board_fmn_config.cpu;
123
124 num_core = hweight32(nlm_current_node()->coremask);
125 dev_info->num_buckets = num_buckets;
126 dev_info->start_stn_id = start_stn_id;
127 dev_info->end_stn_id = end_stn_id;
128
129 n = num_core;
130 if (num_core == 3)
131 n = 4;
132
133 for (i = start_stn_id; i <= end_stn_id; i++) {
134 xlr_board_fmn_config.bucket_size[i] = size;
135
136 /* Dividing device credits equally to cpus */
137 credits_per_cpu = size / n;
138 for (j = 0; j < num_core; j++)
139 cpu[j].credit_config[i] = credits_per_cpu;
140
141 /* credits left to distribute */
142 credits_per_cpu = size - (credits_per_cpu * num_core);
143
144 /* distribute the remaining credits (if any), among cores */
145 for (j = 0; (j < num_core) && (credits_per_cpu >= 4); j++) {
146 cpu[j].credit_config[i] += 4;
147 credits_per_cpu -= 4;
148 }
149 }
150
151 /* Distributing cpu per bucket credits to devices */
152 for (i = 0; i < num_core; i++) {
153 for (j = 0; j < FMN_CORE_NBUCKETS; j++)
154 dev_info->credit_config[(i * 8) + j] = cpu_credits;
155 }
156}
157
158/*
159 * Each core has 256 slots and 8 buckets,
160 * Configure the 8 buckets each with 32 slots
161 */
162static void setup_cpu_fmninfo(struct xlr_fmn_info *cpu, int num_core)
163{
164 int i, j;
165
166 for (i = 0; i < num_core; i++) {
167 cpu[i].start_stn_id = (8 * i);
168 cpu[i].end_stn_id = (8 * i + 8);
169
170 for (j = cpu[i].start_stn_id; j < cpu[i].end_stn_id; j++)
171 xlr_board_fmn_config.bucket_size[j] = 32;
172 }
173}
174
175/**
176 * Setup the FMN details for each devices according to the device available
177 * in each variant of XLR/XLS processor
178 */
179void xlr_board_info_setup(void)
180{
181 struct xlr_fmn_info *cpu = xlr_board_fmn_config.cpu;
182 struct xlr_fmn_info *gmac = xlr_board_fmn_config.gmac;
183 struct xlr_fmn_info *xgmac = xlr_board_fmn_config.xgmac;
184 struct xlr_fmn_info *dma = &xlr_board_fmn_config.dma;
185 struct xlr_fmn_info *cmp = &xlr_board_fmn_config.cmp;
186 struct xlr_fmn_info *sae = &xlr_board_fmn_config.sae;
187 int processor_id, num_core;
188
189 num_core = hweight32(nlm_current_node()->coremask);
190 processor_id = read_c0_prid() & 0xff00;
191
192 setup_cpu_fmninfo(cpu, num_core);
193 switch (processor_id) {
194 case PRID_IMP_NETLOGIC_XLS104:
195 case PRID_IMP_NETLOGIC_XLS108:
196 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
197 FMN_STNID_GMAC0_TX3, 8, 16, 32);
198 setup_fmn_cc(dma, FMN_STNID_DMA_0,
199 FMN_STNID_DMA_3, 4, 8, 64);
200 setup_fmn_cc(sae, FMN_STNID_SEC0,
201 FMN_STNID_SEC1, 2, 8, 128);
202 break;
203
204 case PRID_IMP_NETLOGIC_XLS204:
205 case PRID_IMP_NETLOGIC_XLS208:
206 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
207 FMN_STNID_GMAC0_TX3, 8, 16, 32);
208 setup_fmn_cc(dma, FMN_STNID_DMA_0,
209 FMN_STNID_DMA_3, 4, 8, 64);
210 setup_fmn_cc(sae, FMN_STNID_SEC0,
211 FMN_STNID_SEC1, 2, 8, 128);
212 break;
213
214 case PRID_IMP_NETLOGIC_XLS404:
215 case PRID_IMP_NETLOGIC_XLS408:
216 case PRID_IMP_NETLOGIC_XLS404B:
217 case PRID_IMP_NETLOGIC_XLS408B:
218 case PRID_IMP_NETLOGIC_XLS416B:
219 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
220 FMN_STNID_GMAC0_TX3, 8, 8, 32);
221 setup_fmn_cc(&gmac[1], FMN_STNID_GMAC1_FR_0,
222 FMN_STNID_GMAC1_TX3, 8, 8, 32);
223 setup_fmn_cc(dma, FMN_STNID_DMA_0,
224 FMN_STNID_DMA_3, 4, 4, 64);
225 setup_fmn_cc(cmp, FMN_STNID_CMP_0,
226 FMN_STNID_CMP_3, 4, 4, 64);
227 setup_fmn_cc(sae, FMN_STNID_SEC0,
228 FMN_STNID_SEC1, 2, 8, 128);
229 break;
230
231 case PRID_IMP_NETLOGIC_XLS412B:
232 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
233 FMN_STNID_GMAC0_TX3, 8, 8, 32);
234 setup_fmn_cc(&gmac[1], FMN_STNID_GMAC1_FR_0,
235 FMN_STNID_GMAC1_TX3, 8, 8, 32);
236 setup_fmn_cc(dma, FMN_STNID_DMA_0,
237 FMN_STNID_DMA_3, 4, 4, 64);
238 setup_fmn_cc(cmp, FMN_STNID_CMP_0,
239 FMN_STNID_CMP_3, 4, 4, 64);
240 setup_fmn_cc(sae, FMN_STNID_SEC0,
241 FMN_STNID_SEC1, 2, 8, 128);
242 break;
243
244 case PRID_IMP_NETLOGIC_XLR308:
245 case PRID_IMP_NETLOGIC_XLR308C:
246 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
247 FMN_STNID_GMAC0_TX3, 8, 16, 32);
248 setup_fmn_cc(dma, FMN_STNID_DMA_0,
249 FMN_STNID_DMA_3, 4, 8, 64);
250 setup_fmn_cc(sae, FMN_STNID_SEC0,
251 FMN_STNID_SEC1, 2, 4, 128);
252 break;
253
254 case PRID_IMP_NETLOGIC_XLR532:
255 case PRID_IMP_NETLOGIC_XLR532C:
256 case PRID_IMP_NETLOGIC_XLR516C:
257 case PRID_IMP_NETLOGIC_XLR508C:
258 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
259 FMN_STNID_GMAC0_TX3, 8, 16, 32);
260 setup_fmn_cc(dma, FMN_STNID_DMA_0,
261 FMN_STNID_DMA_3, 4, 8, 64);
262 setup_fmn_cc(sae, FMN_STNID_SEC0,
263 FMN_STNID_SEC1, 2, 4, 128);
264 break;
265
266 case PRID_IMP_NETLOGIC_XLR732:
267 case PRID_IMP_NETLOGIC_XLR716:
268 setup_fmn_cc(&xgmac[0], FMN_STNID_XMAC0_00_TX,
269 FMN_STNID_XMAC0_15_TX, 8, 0, 32);
270 setup_fmn_cc(&xgmac[1], FMN_STNID_XMAC1_00_TX,
271 FMN_STNID_XMAC1_15_TX, 8, 0, 32);
272 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
273 FMN_STNID_GMAC0_TX3, 8, 24, 32);
274 setup_fmn_cc(dma, FMN_STNID_DMA_0,
275 FMN_STNID_DMA_3, 4, 4, 64);
276 setup_fmn_cc(sae, FMN_STNID_SEC0,
277 FMN_STNID_SEC1, 2, 4, 128);
278 break;
279 default:
280 pr_err("Unknown CPU with processor ID [%d]\n", processor_id);
281 pr_err("Error: Cannot initialize FMN credits.\n");
282 }
283
284 check_credit_distribution();
285
286#if 0 /* debug */
287 print_credit_config(&cpu[0]);
288 print_credit_config(&gmac[0]);
289#endif
290}
diff --git a/arch/mips/netlogic/xlr/fmn.c b/arch/mips/netlogic/xlr/fmn.c
deleted file mode 100644
index 4d74f03de50..00000000000
--- a/arch/mips/netlogic/xlr/fmn.c
+++ /dev/null
@@ -1,204 +0,0 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/irqreturn.h>
37#include <linux/irq.h>
38#include <linux/interrupt.h>
39
40#include <asm/mipsregs.h>
41#include <asm/netlogic/interrupt.h>
42#include <asm/netlogic/xlr/fmn.h>
43#include <asm/netlogic/common.h>
44
45#define COP2_CC_INIT_CPU_DEST(dest, conf) \
46do { \
47 nlm_write_c2_cc##dest(0, conf[(dest * 8) + 0]); \
48 nlm_write_c2_cc##dest(1, conf[(dest * 8) + 1]); \
49 nlm_write_c2_cc##dest(2, conf[(dest * 8) + 2]); \
50 nlm_write_c2_cc##dest(3, conf[(dest * 8) + 3]); \
51 nlm_write_c2_cc##dest(4, conf[(dest * 8) + 4]); \
52 nlm_write_c2_cc##dest(5, conf[(dest * 8) + 5]); \
53 nlm_write_c2_cc##dest(6, conf[(dest * 8) + 6]); \
54 nlm_write_c2_cc##dest(7, conf[(dest * 8) + 7]); \
55} while (0)
56
57struct fmn_message_handler {
58 void (*action)(int, int, int, int, struct nlm_fmn_msg *, void *);
59 void *arg;
60} msg_handlers[128];
61
62/*
63 * FMN interrupt handler. We configure the FMN so that any messages in
64 * any of the CPU buckets will trigger an interrupt on the CPU.
65 * The message can be from any device on the FMN (like NAE/SAE/DMA).
66 * The source station id is used to figure out which of the registered
67 * handlers have to be called.
68 */
69static irqreturn_t fmn_message_handler(int irq, void *data)
70{
71 struct fmn_message_handler *hndlr;
72 int bucket, rv;
73 int size = 0, code = 0, src_stnid = 0;
74 struct nlm_fmn_msg msg;
75 uint32_t mflags, bkt_status;
76
77 mflags = nlm_cop2_enable();
78 /* Disable message ring interrupt */
79 nlm_fmn_setup_intr(irq, 0);
80 while (1) {
81 /* 8 bkts per core, [24:31] each bit represents one bucket
82 * Bit is Zero if bucket is not empty */
83 bkt_status = (nlm_read_c2_status() >> 24) & 0xff;
84 if (bkt_status == 0xff)
85 break;
86 for (bucket = 0; bucket < 8; bucket++) {
87 /* Continue on empty bucket */
88 if (bkt_status & (1 << bucket))
89 continue;
90 rv = nlm_fmn_receive(bucket, &size, &code, &src_stnid,
91 &msg);
92 if (rv != 0)
93 continue;
94
95 hndlr = &msg_handlers[src_stnid];
96 if (hndlr->action == NULL)
97 pr_warn("No msgring handler for stnid %d\n",
98 src_stnid);
99 else {
100 nlm_cop2_restore(mflags);
101 hndlr->action(bucket, src_stnid, size, code,
102 &msg, hndlr->arg);
103 mflags = nlm_cop2_enable();
104 }
105 }
106 };
107 /* Enable message ring intr, to any thread in core */
108 nlm_fmn_setup_intr(irq, (1 << nlm_threads_per_core) - 1);
109 nlm_cop2_restore(mflags);
110 return IRQ_HANDLED;
111}
112
113struct irqaction fmn_irqaction = {
114 .handler = fmn_message_handler,
115 .flags = IRQF_PERCPU,
116 .name = "fmn",
117};
118
119void xlr_percpu_fmn_init(void)
120{
121 struct xlr_fmn_info *cpu_fmn_info;
122 int *bucket_sizes;
123 uint32_t flags;
124 int id;
125
126 BUG_ON(nlm_thread_id() != 0);
127 id = nlm_core_id();
128
129 bucket_sizes = xlr_board_fmn_config.bucket_size;
130 cpu_fmn_info = &xlr_board_fmn_config.cpu[id];
131 flags = nlm_cop2_enable();
132
133 /* Setup bucket sizes for the core. */
134 nlm_write_c2_bucksize(0, bucket_sizes[id * 8 + 0]);
135 nlm_write_c2_bucksize(1, bucket_sizes[id * 8 + 1]);
136 nlm_write_c2_bucksize(2, bucket_sizes[id * 8 + 2]);
137 nlm_write_c2_bucksize(3, bucket_sizes[id * 8 + 3]);
138 nlm_write_c2_bucksize(4, bucket_sizes[id * 8 + 4]);
139 nlm_write_c2_bucksize(5, bucket_sizes[id * 8 + 5]);
140 nlm_write_c2_bucksize(6, bucket_sizes[id * 8 + 6]);
141 nlm_write_c2_bucksize(7, bucket_sizes[id * 8 + 7]);
142
143 /*
144 * For sending FMN messages, we need credits on the destination
145 * bucket. Program the credits this core has on the 128 possible
146 * destination buckets.
147 * We cannot use a loop here, because the the first argument has
148 * to be a constant integer value.
149 */
150 COP2_CC_INIT_CPU_DEST(0, cpu_fmn_info->credit_config);
151 COP2_CC_INIT_CPU_DEST(1, cpu_fmn_info->credit_config);
152 COP2_CC_INIT_CPU_DEST(2, cpu_fmn_info->credit_config);
153 COP2_CC_INIT_CPU_DEST(3, cpu_fmn_info->credit_config);
154 COP2_CC_INIT_CPU_DEST(4, cpu_fmn_info->credit_config);
155 COP2_CC_INIT_CPU_DEST(5, cpu_fmn_info->credit_config);
156 COP2_CC_INIT_CPU_DEST(6, cpu_fmn_info->credit_config);
157 COP2_CC_INIT_CPU_DEST(7, cpu_fmn_info->credit_config);
158 COP2_CC_INIT_CPU_DEST(8, cpu_fmn_info->credit_config);
159 COP2_CC_INIT_CPU_DEST(9, cpu_fmn_info->credit_config);
160 COP2_CC_INIT_CPU_DEST(10, cpu_fmn_info->credit_config);
161 COP2_CC_INIT_CPU_DEST(11, cpu_fmn_info->credit_config);
162 COP2_CC_INIT_CPU_DEST(12, cpu_fmn_info->credit_config);
163 COP2_CC_INIT_CPU_DEST(13, cpu_fmn_info->credit_config);
164 COP2_CC_INIT_CPU_DEST(14, cpu_fmn_info->credit_config);
165 COP2_CC_INIT_CPU_DEST(15, cpu_fmn_info->credit_config);
166
167 /* enable FMN interrupts on this CPU */
168 nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1);
169 nlm_cop2_restore(flags);
170}
171
172
173/*
174 * Register a FMN message handler with respect to the source station id
175 * @stnid: source station id
176 * @action: Handler function pointer
177 */
178int nlm_register_fmn_handler(int start_stnid, int end_stnid,
179 void (*action)(int, int, int, int, struct nlm_fmn_msg *, void *),
180 void *arg)
181{
182 int sstnid;
183
184 for (sstnid = start_stnid; sstnid <= end_stnid; sstnid++) {
185 msg_handlers[sstnid].arg = arg;
186 smp_wmb();
187 msg_handlers[sstnid].action = action;
188 }
189 pr_debug("Registered FMN msg handler for stnid %d-%d\n",
190 start_stnid, end_stnid);
191 return 0;
192}
193
194void nlm_setup_fmn_irq(void)
195{
196 uint32_t flags;
197
198 /* setup irq only once */
199 setup_irq(IRQ_FMN, &fmn_irqaction);
200
201 flags = nlm_cop2_enable();
202 nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1);
203 nlm_cop2_restore(flags);
204}
diff --git a/arch/mips/netlogic/xlr/platform-flash.c b/arch/mips/netlogic/xlr/platform-flash.c
deleted file mode 100644
index 340ab1601c4..00000000000
--- a/arch/mips/netlogic/xlr/platform-flash.c
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * Copyright 2011, Netlogic Microsystems.
3 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/ioport.h>
17#include <linux/resource.h>
18#include <linux/spi/flash.h>
19
20#include <linux/mtd/mtd.h>
21#include <linux/mtd/physmap.h>
22#include <linux/mtd/nand.h>
23#include <linux/mtd/partitions.h>
24
25#include <asm/netlogic/haldefs.h>
26#include <asm/netlogic/xlr/iomap.h>
27#include <asm/netlogic/xlr/flash.h>
28#include <asm/netlogic/xlr/bridge.h>
29#include <asm/netlogic/xlr/gpio.h>
30#include <asm/netlogic/xlr/xlr.h>
31
32/*
33 * Default NOR partition layout
34 */
35static struct mtd_partition xlr_nor_parts[] = {
36 {
37 .name = "User FS",
38 .offset = 0x800000,
39 .size = MTDPART_SIZ_FULL,
40 }
41};
42
43/*
44 * Default NAND partition layout
45 */
46static struct mtd_partition xlr_nand_parts[] = {
47 {
48 .name = "Root Filesystem",
49 .offset = 64 * 64 * 2048,
50 .size = 432 * 64 * 2048,
51 },
52 {
53 .name = "Home Filesystem",
54 .offset = MTDPART_OFS_APPEND,
55 .size = MTDPART_SIZ_FULL,
56 },
57};
58
59/* Use PHYSMAP flash for NOR */
60struct physmap_flash_data xlr_nor_data = {
61 .width = 2,
62 .parts = xlr_nor_parts,
63 .nr_parts = ARRAY_SIZE(xlr_nor_parts),
64};
65
66static struct resource xlr_nor_res[] = {
67 {
68 .flags = IORESOURCE_MEM,
69 },
70};
71
72static struct platform_device xlr_nor_dev = {
73 .name = "physmap-flash",
74 .dev = {
75 .platform_data = &xlr_nor_data,
76 },
77 .num_resources = ARRAY_SIZE(xlr_nor_res),
78 .resource = xlr_nor_res,
79};
80
81const char *xlr_part_probes[] = { "cmdlinepart", NULL };
82
83/*
84 * Use "gen_nand" driver for NAND flash
85 *
86 * There seems to be no way to store a private pointer containing
87 * platform specific info in gen_nand drivier. We will use a global
88 * struct for now, since we currently have only one NAND chip per board.
89 */
90struct xlr_nand_flash_priv {
91 int cs;
92 uint64_t flash_mmio;
93};
94
95static struct xlr_nand_flash_priv nand_priv;
96
97static void xlr_nand_ctrl(struct mtd_info *mtd, int cmd,
98 unsigned int ctrl)
99{
100 if (ctrl & NAND_CLE)
101 nlm_write_reg(nand_priv.flash_mmio,
102 FLASH_NAND_CLE(nand_priv.cs), cmd);
103 else if (ctrl & NAND_ALE)
104 nlm_write_reg(nand_priv.flash_mmio,
105 FLASH_NAND_ALE(nand_priv.cs), cmd);
106}
107
108struct platform_nand_data xlr_nand_data = {
109 .chip = {
110 .nr_chips = 1,
111 .nr_partitions = ARRAY_SIZE(xlr_nand_parts),
112 .chip_delay = 50,
113 .partitions = xlr_nand_parts,
114 .part_probe_types = xlr_part_probes,
115 },
116 .ctrl = {
117 .cmd_ctrl = xlr_nand_ctrl,
118 },
119};
120
121static struct resource xlr_nand_res[] = {
122 {
123 .flags = IORESOURCE_MEM,
124 },
125};
126
127static struct platform_device xlr_nand_dev = {
128 .name = "gen_nand",
129 .id = -1,
130 .num_resources = ARRAY_SIZE(xlr_nand_res),
131 .resource = xlr_nand_res,
132 .dev = {
133 .platform_data = &xlr_nand_data,
134 }
135};
136
137/*
138 * XLR/XLS supports upto 8 devices on its FLASH interface. The value in
139 * FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the
140 * flash devices.
141 * Under this, each flash device has an offset and size given by the
142 * CSBASE_ADDR and CSBASE_MASK registers for the device.
143 *
144 * The CSBASE_ registers are expected to be setup by the bootloader.
145 */
146static void setup_flash_resource(uint64_t flash_mmio,
147 uint64_t flash_map_base, int cs, struct resource *res)
148{
149 u32 base, mask;
150
151 base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs));
152 mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs));
153
154 res->start = flash_map_base + ((unsigned long)base << 16);
155 res->end = res->start + (mask + 1) * 64 * 1024;
156}
157
158static int __init xlr_flash_init(void)
159{
160 uint64_t gpio_mmio, flash_mmio, flash_map_base;
161 u32 gpio_resetcfg, flash_bar;
162 int cs, boot_nand, boot_nor;
163
164 /* Flash address bits 39:24 is in bridge flash BAR */
165 flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR);
166 flash_map_base = (flash_bar & 0xffff0000) << 8;
167
168 gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
169 flash_mmio = nlm_mmio_base(NETLOGIC_IO_FLASH_OFFSET);
170
171 /* Get the chip reset config */
172 gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG);
173
174 /* Check for boot flash type */
175 boot_nor = boot_nand = 0;
176 if (nlm_chip_is_xls()) {
177 /* On XLS, check boot from NAND bit (GPIO reset reg bit 16) */
178 if (gpio_resetcfg & (1 << 16))
179 boot_nand = 1;
180
181 /* check boot from PCMCIA, (GPIO reset reg bit 15 */
182 if ((gpio_resetcfg & (1 << 15)) == 0)
183 boot_nor = 1; /* not set, booted from NOR */
184 } else { /* XLR */
185 /* check boot from PCMCIA (bit 16 in GPIO reset on XLR) */
186 if ((gpio_resetcfg & (1 << 16)) == 0)
187 boot_nor = 1; /* not set, booted from NOR */
188 }
189
190 /* boot flash at chip select 0 */
191 cs = 0;
192
193 if (boot_nand) {
194 nand_priv.cs = cs;
195 nand_priv.flash_mmio = flash_mmio;
196 setup_flash_resource(flash_mmio, flash_map_base, cs,
197 xlr_nand_res);
198
199 /* Initialize NAND flash at CS 0 */
200 nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs),
201 FLASH_NAND_CSDEV_PARAM);
202 nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs),
203 FLASH_NAND_CSTIME_PARAMA);
204 nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs),
205 FLASH_NAND_CSTIME_PARAMB);
206
207 pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res);
208 return platform_device_register(&xlr_nand_dev);
209 }
210
211 if (boot_nor) {
212 setup_flash_resource(flash_mmio, flash_map_base, cs,
213 xlr_nor_res);
214 pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res);
215 return platform_device_register(&xlr_nor_dev);
216 }
217 return 0;
218}
219
220arch_initcall(xlr_flash_init);
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index 507230eeb76..609ec253464 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -14,23 +14,19 @@
14#include <linux/resource.h> 14#include <linux/resource.h>
15#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16#include <linux/serial_reg.h> 16#include <linux/serial_reg.h>
17#include <linux/i2c.h>
18#include <linux/usb/ehci_pdriver.h>
19#include <linux/usb/ohci_pdriver.h>
20 17
21#include <asm/netlogic/haldefs.h>
22#include <asm/netlogic/xlr/iomap.h> 18#include <asm/netlogic/xlr/iomap.h>
23#include <asm/netlogic/xlr/pic.h> 19#include <asm/netlogic/xlr/pic.h>
24#include <asm/netlogic/xlr/xlr.h> 20#include <asm/netlogic/xlr/xlr.h>
25 21
26unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) 22unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
27{ 23{
28 uint64_t uartbase; 24 nlm_reg_t *mmio;
29 unsigned int value; 25 unsigned int value;
30 26
31 /* sign extend to 64 bits, if needed */ 27 /* XLR uart does not need any mapping of regs */
32 uartbase = (uint64_t)(long)p->membase; 28 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift));
33 value = nlm_read_reg(uartbase, offset); 29 value = netlogic_read_reg(mmio, 0);
34 30
35 /* See XLR/XLS errata */ 31 /* See XLR/XLS errata */
36 if (offset == UART_MSR) 32 if (offset == UART_MSR)
@@ -43,10 +39,10 @@ unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
43 39
44void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) 40void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
45{ 41{
46 uint64_t uartbase; 42 nlm_reg_t *mmio;
47 43
48 /* sign extend to 64 bits, if needed */ 44 /* XLR uart does not need any mapping of regs */
49 uartbase = (uint64_t)(long)p->membase; 45 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift));
50 46
51 /* See XLR/XLS errata */ 47 /* See XLR/XLS errata */
52 if (offset == UART_MSR) 48 if (offset == UART_MSR)
@@ -54,7 +50,7 @@ void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
54 else if (offset == UART_MCR) 50 else if (offset == UART_MCR)
55 value ^= 0x3; 51 value ^= 0x3;
56 52
57 nlm_write_reg(uartbase, offset, value); 53 netlogic_write_reg(mmio, 0, value);
58} 54}
59 55
60#define PORT(_irq) \ 56#define PORT(_irq) \
@@ -86,165 +82,17 @@ static struct platform_device uart_device = {
86 82
87static int __init nlm_uart_init(void) 83static int __init nlm_uart_init(void)
88{ 84{
89 unsigned long uartbase; 85 nlm_reg_t *mmio;
90 86
91 uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET); 87 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
92 xlr_uart_data[0].membase = (void __iomem *)uartbase; 88 xlr_uart_data[0].membase = (void __iomem *)mmio;
93 xlr_uart_data[0].mapbase = CPHYSADDR(uartbase); 89 xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio);
94 90
95 uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_1_OFFSET); 91 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET);
96 xlr_uart_data[1].membase = (void __iomem *)uartbase; 92 xlr_uart_data[1].membase = (void __iomem *)mmio;
97 xlr_uart_data[1].mapbase = CPHYSADDR(uartbase); 93 xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio);
98 94
99 return platform_device_register(&uart_device); 95 return platform_device_register(&uart_device);
100} 96}
101 97
102arch_initcall(nlm_uart_init); 98arch_initcall(nlm_uart_init);
103
104#ifdef CONFIG_USB
105/* Platform USB devices, only on XLS chips */
106static u64 xls_usb_dmamask = ~(u32)0;
107#define USB_PLATFORM_DEV(n, i, irq) \
108 { \
109 .name = n, \
110 .id = i, \
111 .num_resources = 2, \
112 .dev = { \
113 .dma_mask = &xls_usb_dmamask, \
114 .coherent_dma_mask = 0xffffffff, \
115 }, \
116 .resource = (struct resource[]) { \
117 { \
118 .flags = IORESOURCE_MEM, \
119 }, \
120 { \
121 .start = irq, \
122 .end = irq, \
123 .flags = IORESOURCE_IRQ, \
124 }, \
125 }, \
126 }
127
128static struct usb_ehci_pdata xls_usb_ehci_pdata = {
129 .caps_offset = 0,
130};
131
132static struct usb_ohci_pdata xls_usb_ohci_pdata;
133
134static struct platform_device xls_usb_ehci_device =
135 USB_PLATFORM_DEV("ehci-platform", 0, PIC_USB_IRQ);
136static struct platform_device xls_usb_ohci_device_0 =
137 USB_PLATFORM_DEV("ohci-platform", 1, PIC_USB_IRQ);
138static struct platform_device xls_usb_ohci_device_1 =
139 USB_PLATFORM_DEV("ohci-platform", 2, PIC_USB_IRQ);
140
141static struct platform_device *xls_platform_devices[] = {
142 &xls_usb_ehci_device,
143 &xls_usb_ohci_device_0,
144 &xls_usb_ohci_device_1,
145};
146
147int xls_platform_usb_init(void)
148{
149 uint64_t usb_mmio, gpio_mmio;
150 unsigned long memres;
151 uint32_t val;
152
153 if (!nlm_chip_is_xls())
154 return 0;
155
156 gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
157 usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_1_OFFSET);
158
159 /* Clear Rogue Phy INTs */
160 nlm_write_reg(usb_mmio, 49, 0x10000000);
161 /* Enable all interrupts */
162 nlm_write_reg(usb_mmio, 50, 0x1f000000);
163
164 /* Enable ports */
165 nlm_write_reg(usb_mmio, 1, 0x07000500);
166
167 val = nlm_read_reg(gpio_mmio, 21);
168 if (((val >> 22) & 0x01) == 0) {
169 pr_info("Detected USB Device mode - Not supported!\n");
170 nlm_write_reg(usb_mmio, 0, 0x01000000);
171 return 0;
172 }
173
174 pr_info("Detected USB Host mode - Adding XLS USB devices.\n");
175 /* Clear reset, host mode */
176 nlm_write_reg(usb_mmio, 0, 0x02000000);
177
178 /* Memory resource for various XLS usb ports */
179 usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_0_OFFSET);
180 memres = CPHYSADDR((unsigned long)usb_mmio);
181 xls_usb_ehci_device.resource[0].start = memres;
182 xls_usb_ehci_device.resource[0].end = memres + 0x400 - 1;
183 xls_usb_ehci_device.dev.platform_data = &xls_usb_ehci_pdata;
184
185 memres += 0x400;
186 xls_usb_ohci_device_0.resource[0].start = memres;
187 xls_usb_ohci_device_0.resource[0].end = memres + 0x400 - 1;
188 xls_usb_ohci_device_0.dev.platform_data = &xls_usb_ohci_pdata;
189
190 memres += 0x400;
191 xls_usb_ohci_device_1.resource[0].start = memres;
192 xls_usb_ohci_device_1.resource[0].end = memres + 0x400 - 1;
193 xls_usb_ohci_device_1.dev.platform_data = &xls_usb_ohci_pdata;
194
195 return platform_add_devices(xls_platform_devices,
196 ARRAY_SIZE(xls_platform_devices));
197}
198
199arch_initcall(xls_platform_usb_init);
200#endif
201
202#ifdef CONFIG_I2C
203static struct i2c_board_info nlm_i2c_board_info1[] __initdata = {
204 /* All XLR boards have this RTC and Max6657 Temp Chip */
205 [0] = {
206 .type = "ds1374",
207 .addr = 0x68
208 },
209 [1] = {
210 .type = "lm90",
211 .addr = 0x4c
212 },
213};
214
215static struct resource i2c_resources[] = {
216 [0] = {
217 .start = 0, /* filled at init */
218 .end = 0,
219 .flags = IORESOURCE_MEM,
220 },
221};
222
223static struct platform_device nlm_xlr_i2c_1 = {
224 .name = "xlr-i2cbus",
225 .id = 1,
226 .num_resources = 1,
227 .resource = i2c_resources,
228};
229
230static int __init nlm_i2c_init(void)
231{
232 int err = 0;
233 unsigned int offset;
234
235 /* I2C bus 0 does not have any useful devices, configure only bus 1 */
236 offset = NETLOGIC_IO_I2C_1_OFFSET;
237 nlm_xlr_i2c_1.resource[0].start = CPHYSADDR(nlm_mmio_base(offset));
238 nlm_xlr_i2c_1.resource[0].end = nlm_xlr_i2c_1.resource[0].start + 0xfff;
239
240 platform_device_register(&nlm_xlr_i2c_1);
241
242 err = i2c_register_board_info(1, nlm_i2c_board_info1,
243 ARRAY_SIZE(nlm_i2c_board_info1));
244 if (err < 0)
245 pr_err("nlm-i2c: cannot register board I2C devices\n");
246 return err;
247}
248
249arch_initcall(nlm_i2c_init);
250#endif
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index 4e7f49d3d5a..482802569e7 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -39,32 +39,26 @@
39#include <asm/reboot.h> 39#include <asm/reboot.h>
40#include <asm/time.h> 40#include <asm/time.h>
41#include <asm/bootinfo.h> 41#include <asm/bootinfo.h>
42#include <asm/smp-ops.h>
42 43
43#include <asm/netlogic/interrupt.h> 44#include <asm/netlogic/interrupt.h>
44#include <asm/netlogic/psb-bootinfo.h> 45#include <asm/netlogic/psb-bootinfo.h>
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47 46
48#include <asm/netlogic/xlr/xlr.h> 47#include <asm/netlogic/xlr/xlr.h>
49#include <asm/netlogic/xlr/iomap.h> 48#include <asm/netlogic/xlr/iomap.h>
50#include <asm/netlogic/xlr/pic.h> 49#include <asm/netlogic/xlr/pic.h>
51#include <asm/netlogic/xlr/gpio.h> 50#include <asm/netlogic/xlr/gpio.h>
52#include <asm/netlogic/xlr/fmn.h>
53 51
54uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE; 52unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE);
53unsigned long nlm_common_ebase = 0x0;
55struct psb_info nlm_prom_info; 54struct psb_info nlm_prom_info;
56 55
57/* default to uniprocessor */ 56static void nlm_early_serial_setup(void)
58unsigned int nlm_threads_per_core = 1;
59struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
60cpumask_t nlm_cpumask = CPU_MASK_CPU0;
61
62static void __init nlm_early_serial_setup(void)
63{ 57{
64 struct uart_port s; 58 struct uart_port s;
65 unsigned long uart_base; 59 nlm_reg_t *uart_base;
66 60
67 uart_base = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET); 61 uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
68 memset(&s, 0, sizeof(s)); 62 memset(&s, 0, sizeof(s));
69 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; 63 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
70 s.iotype = UPIO_MEM32; 64 s.iotype = UPIO_MEM32;
@@ -73,18 +67,18 @@ static void __init nlm_early_serial_setup(void)
73 s.uartclk = PIC_CLKS_PER_SEC; 67 s.uartclk = PIC_CLKS_PER_SEC;
74 s.serial_in = nlm_xlr_uart_in; 68 s.serial_in = nlm_xlr_uart_in;
75 s.serial_out = nlm_xlr_uart_out; 69 s.serial_out = nlm_xlr_uart_out;
76 s.mapbase = uart_base; 70 s.mapbase = (unsigned long)uart_base;
77 s.membase = (unsigned char __iomem *)uart_base; 71 s.membase = (unsigned char __iomem *)uart_base;
78 early_serial_setup(&s); 72 early_serial_setup(&s);
79} 73}
80 74
81static void nlm_linux_exit(void) 75static void nlm_linux_exit(void)
82{ 76{
83 uint64_t gpiobase; 77 nlm_reg_t *mmio;
84 78
85 gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); 79 mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET);
86 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ 80 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
87 nlm_write_reg(gpiobase, GPIO_SWRESET_REG, 1); 81 netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1);
88 for ( ; ; ) 82 for ( ; ; )
89 cpu_wait(); 83 cpu_wait();
90} 84}
@@ -102,23 +96,12 @@ const char *get_system_type(void)
102 return "Netlogic XLR/XLS Series"; 96 return "Netlogic XLR/XLS Series";
103} 97}
104 98
105unsigned int nlm_get_cpu_frequency(void)
106{
107 return (unsigned int)nlm_prom_info.cpu_frequency;
108}
109
110void __init prom_free_prom_memory(void) 99void __init prom_free_prom_memory(void)
111{ 100{
112 /* Nothing yet */ 101 /* Nothing yet */
113} 102}
114 103
115void nlm_percpu_init(int hwcpuid) 104static void build_arcs_cmdline(int *argv)
116{
117 if (hwcpuid % 4 == 0)
118 xlr_percpu_fmn_init();
119}
120
121static void __init build_arcs_cmdline(int *argv)
122{ 105{
123 int i, remain, len; 106 int i, remain, len;
124 char *arg; 107 char *arg;
@@ -181,19 +164,9 @@ static void prom_add_memory(void)
181 } 164 }
182} 165}
183 166
184static void nlm_init_node(void)
185{
186 struct nlm_soc_info *nodep;
187
188 nodep = nlm_current_node();
189 nodep->picbase = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
190 nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
191 spin_lock_init(&nodep->piclock);
192}
193
194void __init prom_init(void) 167void __init prom_init(void)
195{ 168{
196 int i, *argv, *envp; /* passed as 32 bit ptrs */ 169 int *argv, *envp; /* passed as 32 bit ptrs */
197 struct psb_info *prom_infop; 170 struct psb_info *prom_infop;
198 171
199 /* truncate to 32 bit and sign extend all args */ 172 /* truncate to 32 bit and sign extend all args */
@@ -202,19 +175,14 @@ void __init prom_init(void)
202 prom_infop = (struct psb_info *)(long)(int)fw_arg3; 175 prom_infop = (struct psb_info *)(long)(int)fw_arg3;
203 176
204 nlm_prom_info = *prom_infop; 177 nlm_prom_info = *prom_infop;
205 nlm_init_node();
206 178
207 nlm_early_serial_setup(); 179 nlm_early_serial_setup();
208 build_arcs_cmdline(argv); 180 build_arcs_cmdline(argv);
181 nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
209 prom_add_memory(); 182 prom_add_memory();
210 183
211#ifdef CONFIG_SMP 184#ifdef CONFIG_SMP
212 for (i = 0; i < 32; i++) 185 nlm_wakeup_secondary_cpus(nlm_prom_info.online_cpu_map);
213 if (nlm_prom_info.online_cpu_map & (1 << i))
214 cpumask_set_cpu(i, &nlm_cpumask);
215 nlm_wakeup_secondary_cpus();
216 register_smp_ops(&nlm_smp_ops); 186 register_smp_ops(&nlm_smp_ops);
217#endif 187#endif
218 xlr_board_info_setup();
219 xlr_percpu_fmn_init();
220} 188}
diff --git a/arch/mips/netlogic/xlr/wakeup.c b/arch/mips/netlogic/xlr/wakeup.c
deleted file mode 100644
index 3ebf7411d67..00000000000
--- a/arch/mips/netlogic/xlr/wakeup.c
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36#include <linux/delay.h>
37#include <linux/threads.h>
38
39#include <asm/asm.h>
40#include <asm/asm-offsets.h>
41#include <asm/mipsregs.h>
42#include <asm/addrspace.h>
43#include <asm/string.h>
44
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47#include <asm/netlogic/mips-extns.h>
48
49#include <asm/netlogic/xlr/iomap.h>
50#include <asm/netlogic/xlr/pic.h>
51
52int __cpuinit xlr_wakeup_secondary_cpus(void)
53{
54 struct nlm_soc_info *nodep;
55 unsigned int i, j, boot_cpu;
56
57 /*
58 * In case of RMI boot, hit with NMI to get the cores
59 * from bootloader to linux code.
60 */
61 nodep = nlm_get_node(0);
62 boot_cpu = hard_smp_processor_id();
63 nlm_set_nmi_handler(nlm_rmiboot_preboot);
64 for (i = 0; i < NR_CPUS; i++) {
65 if (i == boot_cpu || !cpumask_test_cpu(i, &nlm_cpumask))
66 continue;
67 nlm_pic_send_ipi(nodep->picbase, i, 1, 1); /* send NMI */
68 }
69
70 /* Fill up the coremask early */
71 nodep->coremask = 1;
72 for (i = 1; i < NLM_CORES_PER_NODE; i++) {
73 for (j = 1000000; j > 0; j--) {
74 if (nlm_cpu_ready[i * NLM_THREADS_PER_CORE])
75 break;
76 udelay(10);
77 }
78 if (j != 0)
79 nodep->coremask |= (1u << i);
80 else
81 pr_err("Failed to wakeup core %d\n", i);
82 }
83
84 return 0;
85}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 06:08:08 -0400