[MIPS] checkfiles: Fix "need space after that ','" errors.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

6 files changed, 74 insertions, 66 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 8b7b7c57bac..971f6c047b8 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -164,12 +164,12 @@ static inline void tx49_blast_icache32(void)
         /* I'm in even chunk.  blast odd chunks */
         for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
-                        cache32_unroll32(addr|ws,Index_Invalidate_I);
+                        cache32_unroll32(addr|ws, Index_Invalidate_I);
         CACHE32_UNROLL32_ALIGN;
         /* I'm in odd chunk.  blast even chunks */
         for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start; addr < end; addr += 0x400 * 2)
-                        cache32_unroll32(addr|ws,Index_Invalidate_I);
+                        cache32_unroll32(addr|ws, Index_Invalidate_I);
 }
 
 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
@@ -195,12 +195,12 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page)
         /* I'm in even chunk.  blast odd chunks */
         for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
-                        cache32_unroll32(addr|ws,Index_Invalidate_I);
+                        cache32_unroll32(addr|ws, Index_Invalidate_I);
         CACHE32_UNROLL32_ALIGN;
         /* I'm in odd chunk.  blast even chunks */
         for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start; addr < end; addr += 0x400 * 2)
-                        cache32_unroll32(addr|ws,Index_Invalidate_I);
+                        cache32_unroll32(addr|ws, Index_Invalidate_I);
 }
 
 static void (* r4k_blast_icache_page)(unsigned long addr);
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 4c72e650f9b..e7f539e3284 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -271,14 +271,22 @@ asmlinkage void sb1_cache_error(void)
 
 /* Parity lookup table. */
 static const uint8_t parity[256] = {
-        0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
-        1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
-        1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
-        0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
-        1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
-        0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
-        0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
-        1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0
+        0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+        1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+        1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+        0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+        1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+        0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+        0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+        1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+        1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+        0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+        0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+        1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+        0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+        1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+        1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+        0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0
 };
 
 /* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c
index 82f42ace73c..a3e98c243a8 100644
--- a/arch/mips/mm/pg-sb1.c
+++ b/arch/mips/mm/pg-sb1.c
@@ -188,9 +188,9 @@ static inline void copy_page_cpu(void *to, void *from)
         : "+r" (src), "+r" (dst)
         : "r" (end)
 #ifdef CONFIG_64BIT
-        : "$8","$9","$10","$11","memory");
+        : "$8", "$9", "$10", "$11", "memory");
 #else
-        : "$2","$3","$6","$7","$8","$9","$10","$11","memory");
+        : "$2", "$3", "$6", "$7", "$8", "$9", "$10", "$11", "memory");
 #endif
 }
 
diff --git a/arch/mips/mm/pgtable.c b/arch/mips/mm/pgtable.c
index c93aa6cbcac..57df1c38e30 100644
--- a/arch/mips/mm/pgtable.c
+++ b/arch/mips/mm/pgtable.c
@@ -29,9 +29,9 @@ void show_mem(void)
                         shared += page_count(page) - 1;
         }
         printk("%d pages of RAM\n", total);
-        printk("%d pages of HIGHMEM\n",highmem);
-        printk("%d reserved pages\n",reserved);
-        printk("%d pages shared\n",shared);
-        printk("%d pages swap cached\n",cached);
+        printk("%d pages of HIGHMEM\n", highmem);
+        printk("%d reserved pages\n", reserved);
+        printk("%d pages shared\n", shared);
+        printk("%d pages swap cached\n", cached);
 #endif
 }
diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c
index 266a47d65ee..bd8409d8ff6 100644
--- a/arch/mips/mm/tlb-r8k.c
+++ b/arch/mips/mm/tlb-r8k.c
@@ -56,7 +56,7 @@ void local_flush_tlb_mm(struct mm_struct *mm)
         int cpu = smp_processor_id();
 
         if (cpu_context(cpu, mm) != 0)
-                drop_mmu_context(mm,cpu);
+                drop_mmu_context(mm, cpu);
 }
 
 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index c3da4fefbcb..a61246d3533 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -141,53 +141,53 @@ struct insn {
          | (f) << FUNC_SH)
 
 static __initdata struct insn insn_table[] = {
-        { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM },
-        { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD },
-        { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD },
-        { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM },
-        { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM },
-        { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM },
-        { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM },
-        { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM },
-        { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM },
-        { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM },
-        { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM },
-        { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM },
-        { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD },
-        { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD | SET},
-        { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD | SET},
-        { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE },
-        { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE },
-        { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE },
-        { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE },
-        { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE },
-        { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD },
-        { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 },
-        { insn_j, M(j_op,0,0,0,0,0), JIMM },
-        { insn_jal, M(jal_op,0,0,0,0,0), JIMM },
-        { insn_jr, M(spec_op,0,0,0,0,jr_op), RS },
-        { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM },
-        { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM },
-        { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM },
-        { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM },
-        { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM },
-        { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD | SET},
-        { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD | SET},
-        { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM },
-        { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 },
-        { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM },
-        { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM },
-        { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM },
-        { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE },
-        { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE },
-        { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE },
-        { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD },
-        { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM },
-        { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 },
-        { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 },
-        { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 },
-        { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD },
-        { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM },
+        { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
+        { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
+        { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
+        { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
+        { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
+        { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
+        { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
+        { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
+        { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
+        { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
+        { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
+        { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
+        { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
+        { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
+        { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
+        { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
+        { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
+        { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
+        { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
+        { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
+        { insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
+        { insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
+        { insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },
+        { insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
+        { insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
+        { insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
+        { insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
+        { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
+        { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
+        { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
+        { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
+        { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
+        { insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
+        { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
+        { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
+        { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
         { insn_invalid, 0, 0 }
 };