aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/mips-boards/malta/malta_int.c
diff options
context:
space:
mode:
authorDmitri Vorobiev <dmitri.vorobiev@gmail.com>2008-01-24 11:52:51 -0500
committerRalf Baechle <ralf@linux-mips.org>2008-01-29 05:15:04 -0500
commit52b3fc04ba3289ffa42fac84bfa35ef2613fc917 (patch)
treeba3245b20d3ec924670d1b8a79ba4819876ebfdd /arch/mips/mips-boards/malta/malta_int.c
parenta6352cddc743300b0b64b5fd8dfb688524e884e9 (diff)
[MIPS] Malta: else should follow close brace in malta_int.c
This patch fixes two errors reported by checkpatch.pl. No functional changes introduced. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards/malta/malta_int.c')
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index a2689129798..2473a77cea6 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -329,8 +329,7 @@ void __init arch_init_irq(void)
329 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); 329 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
330 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); 330 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
331 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); 331 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
332 } 332 } else if (cpu_has_vint) {
333 else if (cpu_has_vint) {
334 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); 333 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
335 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); 334 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
336#ifdef CONFIG_MIPS_MT_SMTC 335#ifdef CONFIG_MIPS_MT_SMTC
@@ -355,8 +354,7 @@ void __init arch_init_irq(void)
355 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 354 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
356 &corehi_irqaction); 355 &corehi_irqaction);
357#endif /* CONFIG_MIPS_MT_SMTC */ 356#endif /* CONFIG_MIPS_MT_SMTC */
358 } 357 } else {
359 else {
360 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 358 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
361 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 359 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
362 &corehi_irqaction); 360 &corehi_irqaction);