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authorRalf Baechle <ralf@linux-mips.org>2012-12-13 13:40:13 -0500
committerRalf Baechle <ralf@linux-mips.org>2012-12-13 13:40:13 -0500
commit241738bd51cb0efe58e6c570223153e970afe3ae (patch)
tree05263e1ec3fbd58cc4ba5ee69163612fbb769a4a /arch/mips/include/asm
parentbdf20507da11a9a5b32ef04fa09f352828189aef (diff)
parentce8f0d0607bcad3ec0e8599be80353204427093e (diff)
Merge branch 'mips-next' of http://dev.phrozen.org/githttp/mips-next into mips-for-linux-next
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx.h4
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/gpio.h154
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h35
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h29
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h21
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h17
-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h3
-rw-r--r--arch/mips/include/asm/mach-loongson1/platform.h3
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-clk.h7
-rw-r--r--arch/mips/include/asm/mach-netlogic/irq.h4
-rw-r--r--arch/mips/include/asm/mach-netlogic/multi-node.h54
-rw-r--r--arch/mips/include/asm/netlogic/common.h51
-rw-r--r--arch/mips/include/asm/netlogic/interrupt.h2
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h142
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h44
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h1
-rw-r--r--arch/mips/include/asm/netlogic/xlr/fmn.h363
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h2
-rw-r--r--arch/mips/include/asm/netlogic/xlr/xlr.h6
19 files changed, 714 insertions, 228 deletions
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
index 26fdaf40b93..cc7563ba1cb 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
@@ -44,8 +44,8 @@ union bcm47xx_bus {
44extern union bcm47xx_bus bcm47xx_bus; 44extern union bcm47xx_bus bcm47xx_bus;
45extern enum bcm47xx_bus_type bcm47xx_bus_type; 45extern enum bcm47xx_bus_type bcm47xx_bus_type;
46 46
47void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix); 47void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
48void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, const char *prefix); 48 bool fallback);
49 49
50#ifdef CONFIG_BCM47XX_SSB 50#ifdef CONFIG_BCM47XX_SSB
51void bcm47xx_fill_ssb_boardinfo(struct ssb_boardinfo *boardinfo, 51void bcm47xx_fill_ssb_boardinfo(struct ssb_boardinfo *boardinfo,
diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h
index 2ef17e8df40..90daefa24a4 100644
--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
@@ -1,155 +1,17 @@
1/* 1#ifndef __ASM_MIPS_MACH_BCM47XX_GPIO_H
2 * This file is subject to the terms and conditions of the GNU General Public 2#define __ASM_MIPS_MACH_BCM47XX_GPIO_H
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
7 */
8 3
9#ifndef __BCM47XX_GPIO_H 4#include <asm-generic/gpio.h>
10#define __BCM47XX_GPIO_H
11 5
12#include <linux/ssb/ssb_embedded.h> 6#define gpio_get_value __gpio_get_value
13#include <linux/bcma/bcma.h> 7#define gpio_set_value __gpio_set_value
14#include <asm/mach-bcm47xx/bcm47xx.h>
15 8
16#define BCM47XX_EXTIF_GPIO_LINES 5 9#define gpio_cansleep __gpio_cansleep
17#define BCM47XX_CHIPCO_GPIO_LINES 16 10#define gpio_to_irq __gpio_to_irq
18 11
19extern int gpio_request(unsigned gpio, const char *label); 12static inline int irq_to_gpio(unsigned int irq)
20extern void gpio_free(unsigned gpio);
21extern int gpio_to_irq(unsigned gpio);
22
23static inline int gpio_get_value(unsigned gpio)
24{ 13{
25 switch (bcm47xx_bus_type) {
26#ifdef CONFIG_BCM47XX_SSB
27 case BCM47XX_BUS_TYPE_SSB:
28 return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio);
29#endif
30#ifdef CONFIG_BCM47XX_BCMA
31 case BCM47XX_BUS_TYPE_BCMA:
32 return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc,
33 1 << gpio);
34#endif
35 }
36 return -EINVAL; 14 return -EINVAL;
37} 15}
38 16
39#define gpio_get_value_cansleep gpio_get_value
40
41static inline void gpio_set_value(unsigned gpio, int value)
42{
43 switch (bcm47xx_bus_type) {
44#ifdef CONFIG_BCM47XX_SSB
45 case BCM47XX_BUS_TYPE_SSB:
46 ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
47 value ? 1 << gpio : 0);
48 return;
49#endif
50#ifdef CONFIG_BCM47XX_BCMA
51 case BCM47XX_BUS_TYPE_BCMA:
52 bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
53 value ? 1 << gpio : 0);
54 return;
55#endif 17#endif
56 }
57}
58
59#define gpio_set_value_cansleep gpio_set_value
60
61static inline int gpio_cansleep(unsigned gpio)
62{
63 return 0;
64}
65
66static inline int gpio_is_valid(unsigned gpio)
67{
68 return gpio < (BCM47XX_EXTIF_GPIO_LINES + BCM47XX_CHIPCO_GPIO_LINES);
69}
70
71
72static inline int gpio_direction_input(unsigned gpio)
73{
74 switch (bcm47xx_bus_type) {
75#ifdef CONFIG_BCM47XX_SSB
76 case BCM47XX_BUS_TYPE_SSB:
77 ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0);
78 return 0;
79#endif
80#ifdef CONFIG_BCM47XX_BCMA
81 case BCM47XX_BUS_TYPE_BCMA:
82 bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
83 0);
84 return 0;
85#endif
86 }
87 return -EINVAL;
88}
89
90static inline int gpio_direction_output(unsigned gpio, int value)
91{
92 switch (bcm47xx_bus_type) {
93#ifdef CONFIG_BCM47XX_SSB
94 case BCM47XX_BUS_TYPE_SSB:
95 /* first set the gpio out value */
96 ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
97 value ? 1 << gpio : 0);
98 /* then set the gpio mode */
99 ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio);
100 return 0;
101#endif
102#ifdef CONFIG_BCM47XX_BCMA
103 case BCM47XX_BUS_TYPE_BCMA:
104 /* first set the gpio out value */
105 bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
106 value ? 1 << gpio : 0);
107 /* then set the gpio mode */
108 bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
109 1 << gpio);
110 return 0;
111#endif
112 }
113 return -EINVAL;
114}
115
116static inline int gpio_intmask(unsigned gpio, int value)
117{
118 switch (bcm47xx_bus_type) {
119#ifdef CONFIG_BCM47XX_SSB
120 case BCM47XX_BUS_TYPE_SSB:
121 ssb_gpio_intmask(&bcm47xx_bus.ssb, 1 << gpio,
122 value ? 1 << gpio : 0);
123 return 0;
124#endif
125#ifdef CONFIG_BCM47XX_BCMA
126 case BCM47XX_BUS_TYPE_BCMA:
127 bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc,
128 1 << gpio, value ? 1 << gpio : 0);
129 return 0;
130#endif
131 }
132 return -EINVAL;
133}
134
135static inline int gpio_polarity(unsigned gpio, int value)
136{
137 switch (bcm47xx_bus_type) {
138#ifdef CONFIG_BCM47XX_SSB
139 case BCM47XX_BUS_TYPE_SSB:
140 ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << gpio,
141 value ? 1 << gpio : 0);
142 return 0;
143#endif
144#ifdef CONFIG_BCM47XX_BCMA
145 case BCM47XX_BUS_TYPE_BCMA:
146 bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc,
147 1 << gpio, value ? 1 << gpio : 0);
148 return 0;
149#endif
150 }
151 return -EINVAL;
152}
153
154
155#endif /* __BCM47XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
new file mode 100644
index 00000000000..62d6a3b4d3b
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
@@ -0,0 +1,35 @@
1#ifndef BCM63XX_NVRAM_H
2#define BCM63XX_NVRAM_H
3
4#include <linux/types.h>
5
6/**
7 * bcm63xx_nvram_init() - initializes nvram
8 * @nvram: address of the nvram data
9 *
10 * Initialized the local nvram copy from the target address and checks
11 * its checksum.
12 *
13 * Returns 0 on success.
14 */
15int __init bcm63xx_nvram_init(void *nvram);
16
17/**
18 * bcm63xx_nvram_get_name() - returns the board name according to nvram
19 *
20 * Returns the board name field from nvram. Note that it might not be
21 * null terminated if it is exactly 16 bytes long.
22 */
23u8 *bcm63xx_nvram_get_name(void);
24
25/**
26 * bcm63xx_nvram_get_mac_address() - register & return a new mac address
27 * @mac: pointer to array for allocated mac
28 *
29 * Registers and returns a mac address from the allocated macs from nvram.
30 *
31 * Returns 0 on success.
32 */
33int bcm63xx_nvram_get_mac_address(u8 *mac);
34
35#endif /* BCM63XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 12963d05da8..c3eeb90b480 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -53,13 +53,18 @@
53 CKCTL_6338_SAR_EN | \ 53 CKCTL_6338_SAR_EN | \
54 CKCTL_6338_SPI_EN) 54 CKCTL_6338_SPI_EN)
55 55
56#define CKCTL_6345_CPU_EN (1 << 0) 56/* BCM6345 clock bits are shifted by 16 on the left, because of the test
57#define CKCTL_6345_BUS_EN (1 << 1) 57 * control register which is 16-bits wide. That way we do not have any
58#define CKCTL_6345_EBI_EN (1 << 2) 58 * specific BCM6345 code for handling clocks, and writing 0 to the test
59#define CKCTL_6345_UART_EN (1 << 3) 59 * control register is fine.
60#define CKCTL_6345_ADSLPHY_EN (1 << 4) 60 */
61#define CKCTL_6345_ENET_EN (1 << 7) 61#define CKCTL_6345_CPU_EN (1 << 16)
62#define CKCTL_6345_USBH_EN (1 << 8) 62#define CKCTL_6345_BUS_EN (1 << 17)
63#define CKCTL_6345_EBI_EN (1 << 18)
64#define CKCTL_6345_UART_EN (1 << 19)
65#define CKCTL_6345_ADSLPHY_EN (1 << 20)
66#define CKCTL_6345_ENET_EN (1 << 23)
67#define CKCTL_6345_USBH_EN (1 << 24)
63 68
64#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ 69#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
65 CKCTL_6345_USBH_EN | \ 70 CKCTL_6345_USBH_EN | \
@@ -191,6 +196,7 @@
191/* Soft Reset register */ 196/* Soft Reset register */
192#define PERF_SOFTRESET_REG 0x28 197#define PERF_SOFTRESET_REG 0x28
193#define PERF_SOFTRESET_6328_REG 0x10 198#define PERF_SOFTRESET_6328_REG 0x10
199#define PERF_SOFTRESET_6358_REG 0x34
194#define PERF_SOFTRESET_6368_REG 0x10 200#define PERF_SOFTRESET_6368_REG 0x10
195 201
196#define SOFTRESET_6328_SPI_MASK (1 << 0) 202#define SOFTRESET_6328_SPI_MASK (1 << 0)
@@ -244,6 +250,15 @@
244 SOFTRESET_6348_ACLC_MASK | \ 250 SOFTRESET_6348_ACLC_MASK | \
245 SOFTRESET_6348_ADSLMIPSPLL_MASK) 251 SOFTRESET_6348_ADSLMIPSPLL_MASK)
246 252
253#define SOFTRESET_6358_SPI_MASK (1 << 0)
254#define SOFTRESET_6358_ENET_MASK (1 << 2)
255#define SOFTRESET_6358_MPI_MASK (1 << 3)
256#define SOFTRESET_6358_EPHY_MASK (1 << 6)
257#define SOFTRESET_6358_SAR_MASK (1 << 7)
258#define SOFTRESET_6358_USBH_MASK (1 << 12)
259#define SOFTRESET_6358_PCM_MASK (1 << 13)
260#define SOFTRESET_6358_ADSL_MASK (1 << 14)
261
247#define SOFTRESET_6368_SPI_MASK (1 << 0) 262#define SOFTRESET_6368_SPI_MASK (1 << 0)
248#define SOFTRESET_6368_MPI_MASK (1 << 3) 263#define SOFTRESET_6368_MPI_MASK (1 << 3)
249#define SOFTRESET_6368_EPHY_MASK (1 << 6) 264#define SOFTRESET_6368_EPHY_MASK (1 << 6)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
new file mode 100644
index 00000000000..3a6eb9c1adc
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
@@ -0,0 +1,21 @@
1#ifndef __BCM63XX_RESET_H
2#define __BCM63XX_RESET_H
3
4enum bcm63xx_core_reset {
5 BCM63XX_RESET_SPI,
6 BCM63XX_RESET_ENET,
7 BCM63XX_RESET_USBH,
8 BCM63XX_RESET_USBD,
9 BCM63XX_RESET_SAR,
10 BCM63XX_RESET_DSL,
11 BCM63XX_RESET_EPHY,
12 BCM63XX_RESET_ENETSW,
13 BCM63XX_RESET_PCM,
14 BCM63XX_RESET_MPI,
15 BCM63XX_RESET_PCIE,
16 BCM63XX_RESET_PCIE_EXT,
17};
18
19void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
20
21#endif
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
index b0dd4bb53f7..682bcf3b492 100644
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -15,23 +15,6 @@
15#define BCM963XX_NVRAM_OFFSET 0x580 15#define BCM963XX_NVRAM_OFFSET 0x580
16 16
17/* 17/*
18 * nvram structure
19 */
20struct bcm963xx_nvram {
21 u32 version;
22 u8 reserved1[256];
23 u8 name[16];
24 u32 main_tp_number;
25 u32 psi_size;
26 u32 mac_addr_count;
27 u8 mac_addr_base[6];
28 u8 reserved2[2];
29 u32 checksum_old;
30 u8 reserved3[720];
31 u32 checksum_high;
32};
33
34/*
35 * board definition 18 * board definition
36 */ 19 */
37struct board_info { 20struct board_info {
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 6a2df709c57..133336b493b 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -82,6 +82,9 @@ extern __iomem void *ltq_cgu_membase;
82#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) 82#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
83#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) 83#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
84 84
85/* allow booting xrx200 phys */
86int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
87
85/* request a non-gpio and set the PIO config */ 88/* request a non-gpio and set the PIO config */
86#define PMU_PPE BIT(13) 89#define PMU_PPE BIT(13)
87extern void ltq_pmu_enable(unsigned int module); 90extern void ltq_pmu_enable(unsigned int module);
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h
index 2f171617bad..718a1228a4f 100644
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -18,6 +18,7 @@ extern struct platform_device ls1x_eth0_device;
18extern struct platform_device ls1x_ehci_device; 18extern struct platform_device ls1x_ehci_device;
19extern struct platform_device ls1x_rtc_device; 19extern struct platform_device ls1x_rtc_device;
20 20
21void ls1x_serial_setup(void); 21extern void __init ls1x_clk_init(void);
22extern void __init ls1x_serial_setup(struct platform_device *pdev);
22 23
23#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */ 24#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
index 8efa7fb9f73..a81fa3d0dc9 100644
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -20,14 +20,15 @@
20 20
21/* Clock PLL Divisor Register Bits */ 21/* Clock PLL Divisor Register Bits */
22#define DIV_DC_EN (0x1 << 31) 22#define DIV_DC_EN (0x1 << 31)
23#define DIV_DC (0x1f << 26)
24#define DIV_CPU_EN (0x1 << 25) 23#define DIV_CPU_EN (0x1 << 25)
25#define DIV_CPU (0x1f << 20)
26#define DIV_DDR_EN (0x1 << 19) 24#define DIV_DDR_EN (0x1 << 19)
27#define DIV_DDR (0x1f << 14)
28 25
29#define DIV_DC_SHIFT 26 26#define DIV_DC_SHIFT 26
30#define DIV_CPU_SHIFT 20 27#define DIV_CPU_SHIFT 20
31#define DIV_DDR_SHIFT 14 28#define DIV_DDR_SHIFT 14
32 29
30#define DIV_DC_WIDTH 5
31#define DIV_CPU_WIDTH 5
32#define DIV_DDR_WIDTH 5
33
33#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */ 34#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h
index b5902458e7c..868ed8a2ed5 100644
--- a/arch/mips/include/asm/mach-netlogic/irq.h
+++ b/arch/mips/include/asm/mach-netlogic/irq.h
@@ -8,7 +8,9 @@
8#ifndef __ASM_NETLOGIC_IRQ_H 8#ifndef __ASM_NETLOGIC_IRQ_H
9#define __ASM_NETLOGIC_IRQ_H 9#define __ASM_NETLOGIC_IRQ_H
10 10
11#define NR_IRQS 64 11#include <asm/mach-netlogic/multi-node.h>
12#define NR_IRQS (64 * NLM_NR_NODES)
13
12#define MIPS_CPU_IRQ_BASE 0 14#define MIPS_CPU_IRQ_BASE 0
13 15
14#endif /* __ASM_NETLOGIC_IRQ_H */ 16#endif /* __ASM_NETLOGIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h
new file mode 100644
index 00000000000..d62fc773f4d
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/multi-node.h
@@ -0,0 +1,54 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NETLOGIC_MULTI_NODE_H_
36#define _NETLOGIC_MULTI_NODE_H_
37
38#ifndef CONFIG_NLM_MULTINODE
39#define NLM_NR_NODES 1
40#else
41#if defined(CONFIG_NLM_MULTINODE_2)
42#define NLM_NR_NODES 2
43#elif defined(CONFIG_NLM_MULTINODE_4)
44#define NLM_NR_NODES 4
45#else
46#define NLM_NR_NODES 1
47#endif
48#endif
49
50#define NLM_CORES_PER_NODE 8
51#define NLM_THREADS_PER_CORE 4
52#define NLM_CPUS_PER_NODE (NLM_CORES_PER_NODE * NLM_THREADS_PER_CORE)
53
54#endif
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index fdd2f44c7b5..42bfd5f1eee 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -45,15 +45,19 @@
45#define BOOT_NMI_HANDLER 8 45#define BOOT_NMI_HANDLER 8
46 46
47#ifndef __ASSEMBLY__ 47#ifndef __ASSEMBLY__
48#include <linux/cpumask.h>
49#include <linux/spinlock.h>
50#include <asm/irq.h>
51#include <asm/mach-netlogic/multi-node.h>
52
48struct irq_desc; 53struct irq_desc;
49extern struct plat_smp_ops nlm_smp_ops;
50extern char nlm_reset_entry[], nlm_reset_entry_end[];
51void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); 54void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
52void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); 55void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
53void nlm_smp_irq_init(void); 56void nlm_smp_irq_init(int hwcpuid);
54void nlm_boot_secondary_cpus(void); 57void nlm_boot_secondary_cpus(void);
55int nlm_wakeup_secondary_cpus(u32 wakeup_mask); 58int nlm_wakeup_secondary_cpus(void);
56void nlm_rmiboot_preboot(void); 59void nlm_rmiboot_preboot(void);
60void nlm_percpu_init(int hwcpuid);
57 61
58static inline void 62static inline void
59nlm_set_nmi_handler(void *handler) 63nlm_set_nmi_handler(void *handler)
@@ -68,9 +72,42 @@ nlm_set_nmi_handler(void *handler)
68 * Misc. 72 * Misc.
69 */ 73 */
70unsigned int nlm_get_cpu_frequency(void); 74unsigned int nlm_get_cpu_frequency(void);
75void nlm_node_init(int node);
76extern struct plat_smp_ops nlm_smp_ops;
77extern char nlm_reset_entry[], nlm_reset_entry_end[];
78
79extern unsigned int nlm_threads_per_core;
80extern cpumask_t nlm_cpumask;
81
82struct nlm_soc_info {
83 unsigned long coremask; /* cores enabled on the soc */
84 unsigned long ebase;
85 uint64_t irqmask;
86 uint64_t sysbase; /* only for XLP */
87 uint64_t picbase;
88 spinlock_t piclock;
89};
90
91#define nlm_get_node(i) (&nlm_nodes[i])
92#ifdef CONFIG_CPU_XLR
93#define nlm_current_node() (&nlm_nodes[0])
94#else
95#define nlm_current_node() (&nlm_nodes[nlm_nodeid()])
96#endif
97
98struct irq_data;
99uint64_t nlm_pci_irqmask(int node);
100void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *));
101
102/*
103 * The NR_IRQs is divided between nodes, each of them has a separate irq space
104 */
105static inline int nlm_irq_to_xirq(int node, int irq)
106{
107 return node * NR_IRQS / NLM_NR_NODES + irq;
108}
71 109
72extern unsigned long nlm_common_ebase; 110extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
73extern int nlm_threads_per_core; 111extern int nlm_cpu_ready[];
74extern uint32_t nlm_cpumask, nlm_coremask;
75#endif 112#endif
76#endif /* _NETLOGIC_COMMON_H_ */ 113#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h
index a85aadb6cfd..ed5993d9b7b 100644
--- a/arch/mips/include/asm/netlogic/interrupt.h
+++ b/arch/mips/include/asm/netlogic/interrupt.h
@@ -39,7 +39,7 @@
39 39
40#define IRQ_IPI_SMP_FUNCTION 3 40#define IRQ_IPI_SMP_FUNCTION 3
41#define IRQ_IPI_SMP_RESCHEDULE 4 41#define IRQ_IPI_SMP_RESCHEDULE 4
42#define IRQ_MSGRING 6 42#define IRQ_FMN 5
43#define IRQ_TIMER 7 43#define IRQ_TIMER 7
44 44
45#endif 45#endif
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 8c53d0ba4bf..32ba6d95d47 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -73,4 +73,146 @@ static inline int hard_smp_processor_id(void)
73 return __read_32bit_c0_register($15, 1) & 0x3ff; 73 return __read_32bit_c0_register($15, 1) & 0x3ff;
74} 74}
75 75
76static inline int nlm_nodeid(void)
77{
78 return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
79}
80
81static inline unsigned int nlm_core_id(void)
82{
83 return (read_c0_ebase() & 0x1c) >> 2;
84}
85
86static inline unsigned int nlm_thread_id(void)
87{
88 return read_c0_ebase() & 0x3;
89}
90
91#define __read_64bit_c2_split(source, sel) \
92({ \
93 unsigned long long __val; \
94 unsigned long __flags; \
95 \
96 local_irq_save(__flags); \
97 if (sel == 0) \
98 __asm__ __volatile__( \
99 ".set\tmips64\n\t" \
100 "dmfc2\t%M0, " #source "\n\t" \
101 "dsll\t%L0, %M0, 32\n\t" \
102 "dsra\t%M0, %M0, 32\n\t" \
103 "dsra\t%L0, %L0, 32\n\t" \
104 ".set\tmips0\n\t" \
105 : "=r" (__val)); \
106 else \
107 __asm__ __volatile__( \
108 ".set\tmips64\n\t" \
109 "dmfc2\t%M0, " #source ", " #sel "\n\t" \
110 "dsll\t%L0, %M0, 32\n\t" \
111 "dsra\t%M0, %M0, 32\n\t" \
112 "dsra\t%L0, %L0, 32\n\t" \
113 ".set\tmips0\n\t" \
114 : "=r" (__val)); \
115 local_irq_restore(__flags); \
116 \
117 __val; \
118})
119
120#define __write_64bit_c2_split(source, sel, val) \
121do { \
122 unsigned long __flags; \
123 \
124 local_irq_save(__flags); \
125 if (sel == 0) \
126 __asm__ __volatile__( \
127 ".set\tmips64\n\t" \
128 "dsll\t%L0, %L0, 32\n\t" \
129 "dsrl\t%L0, %L0, 32\n\t" \
130 "dsll\t%M0, %M0, 32\n\t" \
131 "or\t%L0, %L0, %M0\n\t" \
132 "dmtc2\t%L0, " #source "\n\t" \
133 ".set\tmips0\n\t" \
134 : : "r" (val)); \
135 else \
136 __asm__ __volatile__( \
137 ".set\tmips64\n\t" \
138 "dsll\t%L0, %L0, 32\n\t" \
139 "dsrl\t%L0, %L0, 32\n\t" \
140 "dsll\t%M0, %M0, 32\n\t" \
141 "or\t%L0, %L0, %M0\n\t" \
142 "dmtc2\t%L0, " #source ", " #sel "\n\t" \
143 ".set\tmips0\n\t" \
144 : : "r" (val)); \
145 local_irq_restore(__flags); \
146} while (0)
147
148#define __read_32bit_c2_register(source, sel) \
149({ uint32_t __res; \
150 if (sel == 0) \
151 __asm__ __volatile__( \
152 ".set\tmips32\n\t" \
153 "mfc2\t%0, " #source "\n\t" \
154 ".set\tmips0\n\t" \
155 : "=r" (__res)); \
156 else \
157 __asm__ __volatile__( \
158 ".set\tmips32\n\t" \
159 "mfc2\t%0, " #source ", " #sel "\n\t" \
160 ".set\tmips0\n\t" \
161 : "=r" (__res)); \
162 __res; \
163})
164
165#define __read_64bit_c2_register(source, sel) \
166({ unsigned long long __res; \
167 if (sizeof(unsigned long) == 4) \
168 __res = __read_64bit_c2_split(source, sel); \
169 else if (sel == 0) \
170 __asm__ __volatile__( \
171 ".set\tmips64\n\t" \
172 "dmfc2\t%0, " #source "\n\t" \
173 ".set\tmips0\n\t" \
174 : "=r" (__res)); \
175 else \
176 __asm__ __volatile__( \
177 ".set\tmips64\n\t" \
178 "dmfc2\t%0, " #source ", " #sel "\n\t" \
179 ".set\tmips0\n\t" \
180 : "=r" (__res)); \
181 __res; \
182})
183
184#define __write_64bit_c2_register(register, sel, value) \
185do { \
186 if (sizeof(unsigned long) == 4) \
187 __write_64bit_c2_split(register, sel, value); \
188 else if (sel == 0) \
189 __asm__ __volatile__( \
190 ".set\tmips64\n\t" \
191 "dmtc2\t%z0, " #register "\n\t" \
192 ".set\tmips0\n\t" \
193 : : "Jr" (value)); \
194 else \
195 __asm__ __volatile__( \
196 ".set\tmips64\n\t" \
197 "dmtc2\t%z0, " #register ", " #sel "\n\t" \
198 ".set\tmips0\n\t" \
199 : : "Jr" (value)); \
200} while (0)
201
202#define __write_32bit_c2_register(reg, sel, value) \
203({ \
204 if (sel == 0) \
205 __asm__ __volatile__( \
206 ".set\tmips32\n\t" \
207 "mtc2\t%z0, " #reg "\n\t" \
208 ".set\tmips0\n\t" \
209 : : "Jr" (value)); \
210 else \
211 __asm__ __volatile__( \
212 ".set\tmips32\n\t" \
213 "mtc2\t%z0, " #reg ", " #sel "\n\t" \
214 ".set\tmips0\n\t" \
215 : : "Jr" (value)); \
216})
217
76#endif /*_ASM_NLM_MIPS_EXTS_H */ 218#endif /*_ASM_NLM_MIPS_EXTS_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index ad8b80233a6..b2e53a5383a 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -273,36 +273,16 @@ nlm_pic_read_irt(uint64_t base, int irt_index)
273 return nlm_read_pic_reg(base, PIC_IRT(irt_index)); 273 return nlm_read_pic_reg(base, PIC_IRT(irt_index));
274} 274}
275 275
276static inline uint64_t
277nlm_pic_read_control(uint64_t base)
278{
279 return nlm_read_pic_reg(base, PIC_CTRL);
280}
281
282static inline void
283nlm_pic_write_control(uint64_t base, uint64_t control)
284{
285 nlm_write_pic_reg(base, PIC_CTRL, control);
286}
287
288static inline void
289nlm_pic_update_control(uint64_t base, uint64_t control)
290{
291 uint64_t val;
292
293 val = nlm_read_pic_reg(base, PIC_CTRL);
294 nlm_write_pic_reg(base, PIC_CTRL, control | val);
295}
296
297static inline void 276static inline void
298nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu) 277nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
299{ 278{
300 uint64_t val; 279 uint64_t val;
301 280
302 val = nlm_read_pic_reg(base, PIC_IRT(irt)); 281 val = nlm_read_pic_reg(base, PIC_IRT(irt));
303 val |= cpu & 0xf; 282 /* clear cpuset and mask */
304 if (cpu > 15) 283 val &= ~((0x7ull << 16) | 0xffff);
305 val |= 1 << 16; 284 /* set DB, cpuset and cpumask */
285 val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf));
306 nlm_write_pic_reg(base, PIC_IRT(irt), val); 286 nlm_write_pic_reg(base, PIC_IRT(irt), val);
307} 287}
308 288
@@ -369,7 +349,7 @@ nlm_pic_enable_irt(uint64_t base, int irt)
369static inline void 349static inline void
370nlm_pic_disable_irt(uint64_t base, int irt) 350nlm_pic_disable_irt(uint64_t base, int irt)
371{ 351{
372 uint32_t reg; 352 uint64_t reg;
373 353
374 reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 354 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
375 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31)); 355 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
@@ -379,15 +359,9 @@ static inline void
379nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) 359nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
380{ 360{
381 uint64_t ipi; 361 uint64_t ipi;
382 int node, ncpu;
383
384 node = hwt / 32;
385 ncpu = hwt & 0x1f;
386 ipi = ((uint64_t)nmi << 31) | (irq << 20) | (node << 17) |
387 (1 << (ncpu & 0xf));
388 if (ncpu > 15)
389 ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
390 362
363 ipi = (nmi << 31) | (irq << 20);
364 ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */
391 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 365 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
392} 366}
393 367
@@ -404,12 +378,10 @@ nlm_pic_ack(uint64_t base, int irt_num)
404static inline void 378static inline void
405nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) 379nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
406{ 380{
407 nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, 0); 381 nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, hwt);
408} 382}
409 383
410extern uint64_t nlm_pic_base;
411int nlm_irq_to_irt(int irq); 384int nlm_irq_to_irt(int irq);
412int nlm_irt_to_irq(int irt);
413 385
414#endif /* __ASSEMBLY__ */ 386#endif /* __ASSEMBLY__ */
415#endif /* _NLM_HAL_PIC_H */ 387#endif /* _NLM_HAL_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index 21432f7d89b..258e8cc00e9 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -124,6 +124,5 @@
124#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) 124#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
125#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) 125#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
126 126
127extern uint64_t nlm_sys_base;
128#endif 127#endif
129#endif 128#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h
new file mode 100644
index 00000000000..68d5167c86b
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/fmn.h
@@ -0,0 +1,363 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NLM_FMN_H_
36#define _NLM_FMN_H_
37
38#include <asm/netlogic/mips-extns.h> /* for COP2 access */
39
40/* Station IDs */
41#define FMN_STNID_CPU0 0x00
42#define FMN_STNID_CPU1 0x08
43#define FMN_STNID_CPU2 0x10
44#define FMN_STNID_CPU3 0x18
45#define FMN_STNID_CPU4 0x20
46#define FMN_STNID_CPU5 0x28
47#define FMN_STNID_CPU6 0x30
48#define FMN_STNID_CPU7 0x38
49
50#define FMN_STNID_XGS0_TX 64
51#define FMN_STNID_XMAC0_00_TX 64
52#define FMN_STNID_XMAC0_01_TX 65
53#define FMN_STNID_XMAC0_02_TX 66
54#define FMN_STNID_XMAC0_03_TX 67
55#define FMN_STNID_XMAC0_04_TX 68
56#define FMN_STNID_XMAC0_05_TX 69
57#define FMN_STNID_XMAC0_06_TX 70
58#define FMN_STNID_XMAC0_07_TX 71
59#define FMN_STNID_XMAC0_08_TX 72
60#define FMN_STNID_XMAC0_09_TX 73
61#define FMN_STNID_XMAC0_10_TX 74
62#define FMN_STNID_XMAC0_11_TX 75
63#define FMN_STNID_XMAC0_12_TX 76
64#define FMN_STNID_XMAC0_13_TX 77
65#define FMN_STNID_XMAC0_14_TX 78
66#define FMN_STNID_XMAC0_15_TX 79
67
68#define FMN_STNID_XGS1_TX 80
69#define FMN_STNID_XMAC1_00_TX 80
70#define FMN_STNID_XMAC1_01_TX 81
71#define FMN_STNID_XMAC1_02_TX 82
72#define FMN_STNID_XMAC1_03_TX 83
73#define FMN_STNID_XMAC1_04_TX 84
74#define FMN_STNID_XMAC1_05_TX 85
75#define FMN_STNID_XMAC1_06_TX 86
76#define FMN_STNID_XMAC1_07_TX 87
77#define FMN_STNID_XMAC1_08_TX 88
78#define FMN_STNID_XMAC1_09_TX 89
79#define FMN_STNID_XMAC1_10_TX 90
80#define FMN_STNID_XMAC1_11_TX 91
81#define FMN_STNID_XMAC1_12_TX 92
82#define FMN_STNID_XMAC1_13_TX 93
83#define FMN_STNID_XMAC1_14_TX 94
84#define FMN_STNID_XMAC1_15_TX 95
85
86#define FMN_STNID_GMAC 96
87#define FMN_STNID_GMACJFR_0 96
88#define FMN_STNID_GMACRFR_0 97
89#define FMN_STNID_GMACTX0 98
90#define FMN_STNID_GMACTX1 99
91#define FMN_STNID_GMACTX2 100
92#define FMN_STNID_GMACTX3 101
93#define FMN_STNID_GMACJFR_1 102
94#define FMN_STNID_GMACRFR_1 103
95
96#define FMN_STNID_DMA 104
97#define FMN_STNID_DMA_0 104
98#define FMN_STNID_DMA_1 105
99#define FMN_STNID_DMA_2 106
100#define FMN_STNID_DMA_3 107
101
102#define FMN_STNID_XGS0FR 112
103#define FMN_STNID_XMAC0JFR 112
104#define FMN_STNID_XMAC0RFR 113
105
106#define FMN_STNID_XGS1FR 114
107#define FMN_STNID_XMAC1JFR 114
108#define FMN_STNID_XMAC1RFR 115
109#define FMN_STNID_SEC 120
110#define FMN_STNID_SEC0 120
111#define FMN_STNID_SEC1 121
112#define FMN_STNID_SEC2 122
113#define FMN_STNID_SEC3 123
114#define FMN_STNID_PK0 124
115#define FMN_STNID_SEC_RSA 124
116#define FMN_STNID_SEC_RSVD0 125
117#define FMN_STNID_SEC_RSVD1 126
118#define FMN_STNID_SEC_RSVD2 127
119
120#define FMN_STNID_GMAC1 80
121#define FMN_STNID_GMAC1_FR_0 81
122#define FMN_STNID_GMAC1_TX0 82
123#define FMN_STNID_GMAC1_TX1 83
124#define FMN_STNID_GMAC1_TX2 84
125#define FMN_STNID_GMAC1_TX3 85
126#define FMN_STNID_GMAC1_FR_1 87
127#define FMN_STNID_GMAC0 96
128#define FMN_STNID_GMAC0_FR_0 97
129#define FMN_STNID_GMAC0_TX0 98
130#define FMN_STNID_GMAC0_TX1 99
131#define FMN_STNID_GMAC0_TX2 100
132#define FMN_STNID_GMAC0_TX3 101
133#define FMN_STNID_GMAC0_FR_1 103
134#define FMN_STNID_CMP_0 108
135#define FMN_STNID_CMP_1 109
136#define FMN_STNID_CMP_2 110
137#define FMN_STNID_CMP_3 111
138#define FMN_STNID_PCIE_0 116
139#define FMN_STNID_PCIE_1 117
140#define FMN_STNID_PCIE_2 118
141#define FMN_STNID_PCIE_3 119
142#define FMN_STNID_XLS_PK0 121
143
144#define nlm_read_c2_cc0(s) __read_32bit_c2_register($16, s)
145#define nlm_read_c2_cc1(s) __read_32bit_c2_register($17, s)
146#define nlm_read_c2_cc2(s) __read_32bit_c2_register($18, s)
147#define nlm_read_c2_cc3(s) __read_32bit_c2_register($19, s)
148#define nlm_read_c2_cc4(s) __read_32bit_c2_register($20, s)
149#define nlm_read_c2_cc5(s) __read_32bit_c2_register($21, s)
150#define nlm_read_c2_cc6(s) __read_32bit_c2_register($22, s)
151#define nlm_read_c2_cc7(s) __read_32bit_c2_register($23, s)
152#define nlm_read_c2_cc8(s) __read_32bit_c2_register($24, s)
153#define nlm_read_c2_cc9(s) __read_32bit_c2_register($25, s)
154#define nlm_read_c2_cc10(s) __read_32bit_c2_register($26, s)
155#define nlm_read_c2_cc11(s) __read_32bit_c2_register($27, s)
156#define nlm_read_c2_cc12(s) __read_32bit_c2_register($28, s)
157#define nlm_read_c2_cc13(s) __read_32bit_c2_register($29, s)
158#define nlm_read_c2_cc14(s) __read_32bit_c2_register($30, s)
159#define nlm_read_c2_cc15(s) __read_32bit_c2_register($31, s)
160
161#define nlm_write_c2_cc0(s, v) __write_32bit_c2_register($16, s, v)
162#define nlm_write_c2_cc1(s, v) __write_32bit_c2_register($17, s, v)
163#define nlm_write_c2_cc2(s, v) __write_32bit_c2_register($18, s, v)
164#define nlm_write_c2_cc3(s, v) __write_32bit_c2_register($19, s, v)
165#define nlm_write_c2_cc4(s, v) __write_32bit_c2_register($20, s, v)
166#define nlm_write_c2_cc5(s, v) __write_32bit_c2_register($21, s, v)
167#define nlm_write_c2_cc6(s, v) __write_32bit_c2_register($22, s, v)
168#define nlm_write_c2_cc7(s, v) __write_32bit_c2_register($23, s, v)
169#define nlm_write_c2_cc8(s, v) __write_32bit_c2_register($24, s, v)
170#define nlm_write_c2_cc9(s, v) __write_32bit_c2_register($25, s, v)
171#define nlm_write_c2_cc10(s, v) __write_32bit_c2_register($26, s, v)
172#define nlm_write_c2_cc11(s, v) __write_32bit_c2_register($27, s, v)
173#define nlm_write_c2_cc12(s, v) __write_32bit_c2_register($28, s, v)
174#define nlm_write_c2_cc13(s, v) __write_32bit_c2_register($29, s, v)
175#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v)
176#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v)
177
178#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0)
179#define nlm_read_c2_config() __read_32bit_c2_register($3, 0)
180#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v)
181#define nlm_read_c2_bucksize(b) __read_32bit_c2_register($4, b)
182#define nlm_write_c2_bucksize(b, v) __write_32bit_c2_register($4, b, v)
183
184#define nlm_read_c2_rx_msg0() __read_64bit_c2_register($1, 0)
185#define nlm_read_c2_rx_msg1() __read_64bit_c2_register($1, 1)
186#define nlm_read_c2_rx_msg2() __read_64bit_c2_register($1, 2)
187#define nlm_read_c2_rx_msg3() __read_64bit_c2_register($1, 3)
188
189#define nlm_write_c2_tx_msg0(v) __write_64bit_c2_register($0, 0, v)
190#define nlm_write_c2_tx_msg1(v) __write_64bit_c2_register($0, 1, v)
191#define nlm_write_c2_tx_msg2(v) __write_64bit_c2_register($0, 2, v)
192#define nlm_write_c2_tx_msg3(v) __write_64bit_c2_register($0, 3, v)
193
194#define FMN_STN_RX_QSIZE 256
195#define FMN_NSTATIONS 128
196#define FMN_CORE_NBUCKETS 8
197
198static inline void nlm_msgsnd(unsigned int stid)
199{
200 __asm__ volatile (
201 ".set push\n"
202 ".set noreorder\n"
203 ".set noat\n"
204 "move $1, %0\n"
205 "c2 0x10001\n" /* msgsnd $1 */
206 ".set pop\n"
207 : : "r" (stid) : "$1"
208 );
209}
210
211static inline void nlm_msgld(unsigned int pri)
212{
213 __asm__ volatile (
214 ".set push\n"
215 ".set noreorder\n"
216 ".set noat\n"
217 "move $1, %0\n"
218 "c2 0x10002\n" /* msgld $1 */
219 ".set pop\n"
220 : : "r" (pri) : "$1"
221 );
222}
223
224static inline void nlm_msgwait(unsigned int mask)
225{
226 __asm__ volatile (
227 ".set push\n"
228 ".set noreorder\n"
229 ".set noat\n"
230 "move $8, %0\n"
231 "c2 0x10003\n" /* msgwait $1 */
232 ".set pop\n"
233 : : "r" (mask) : "$1"
234 );
235}
236
237/*
238 * Disable interrupts and enable COP2 access
239 */
240static inline uint32_t nlm_cop2_enable(void)
241{
242 uint32_t sr = read_c0_status();
243
244 write_c0_status((sr & ~ST0_IE) | ST0_CU2);
245 return sr;
246}
247
248static inline void nlm_cop2_restore(uint32_t sr)
249{
250 write_c0_status(sr);
251}
252
253static inline void nlm_fmn_setup_intr(int irq, unsigned int tmask)
254{
255 uint32_t config;
256
257 config = (1 << 24) /* interrupt water mark - 1 msg */
258 | (irq << 16) /* irq */
259 | (tmask << 8) /* thread mask */
260 | 0x2; /* enable watermark intr, disable empty intr */
261 nlm_write_c2_config(config);
262}
263
264struct nlm_fmn_msg {
265 uint64_t msg0;
266 uint64_t msg1;
267 uint64_t msg2;
268 uint64_t msg3;
269};
270
271static inline int nlm_fmn_send(unsigned int size, unsigned int code,
272 unsigned int stid, struct nlm_fmn_msg *msg)
273{
274 unsigned int dest;
275 uint32_t status;
276 int i;
277
278 /*
279 * Make sure that all the writes pending at the cpu are flushed.
280 * Any writes pending on CPU will not be see by devices. L1/L2
281 * caches are coherent with IO, so no cache flush needed.
282 */
283 __asm __volatile("sync");
284
285 /* Load TX message buffers */
286 nlm_write_c2_tx_msg0(msg->msg0);
287 nlm_write_c2_tx_msg1(msg->msg1);
288 nlm_write_c2_tx_msg2(msg->msg2);
289 nlm_write_c2_tx_msg3(msg->msg3);
290 dest = ((size - 1) << 16) | (code << 8) | stid;
291
292 /*
293 * Retry a few times on credit fail, this should be a
294 * transient condition, unless there is a configuration
295 * failure, or the receiver is stuck.
296 */
297 for (i = 0; i < 8; i++) {
298 nlm_msgsnd(dest);
299 status = nlm_read_c2_status(0);
300 if ((status & 0x2) == 1)
301 pr_info("Send pending fail!\n");
302 if ((status & 0x4) == 0)
303 return 0;
304 }
305
306 /* If there is a credit failure, return error */
307 return status & 0x06;
308}
309
310static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid,
311 struct nlm_fmn_msg *msg)
312{
313 uint32_t status, tmp;
314
315 nlm_msgld(bucket);
316
317 /* wait for load pending to clear */
318 do {
319 status = nlm_read_c2_status(1);
320 } while ((status & 0x08) != 0);
321
322 /* receive error bits */
323 tmp = status & 0x30;
324 if (tmp != 0)
325 return tmp;
326
327 *size = ((status & 0xc0) >> 6) + 1;
328 *code = (status & 0xff00) >> 8;
329 *stid = (status & 0x7f0000) >> 16;
330 msg->msg0 = nlm_read_c2_rx_msg0();
331 msg->msg1 = nlm_read_c2_rx_msg1();
332 msg->msg2 = nlm_read_c2_rx_msg2();
333 msg->msg3 = nlm_read_c2_rx_msg3();
334
335 return 0;
336}
337
338struct xlr_fmn_info {
339 int num_buckets;
340 int start_stn_id;
341 int end_stn_id;
342 int credit_config[128];
343};
344
345struct xlr_board_fmn_config {
346 int bucket_size[128]; /* size of buckets for all stations */
347 struct xlr_fmn_info cpu[8];
348 struct xlr_fmn_info gmac[2];
349 struct xlr_fmn_info dma;
350 struct xlr_fmn_info cmp;
351 struct xlr_fmn_info sae;
352 struct xlr_fmn_info xgmac[2];
353};
354
355extern int nlm_register_fmn_handler(int start, int end,
356 void (*fn)(int, int, int, int, struct nlm_fmn_msg *, void *),
357 void *arg);
358extern void xlr_percpu_fmn_init(void);
359extern void nlm_setup_fmn_irq(void);
360extern void xlr_board_info_setup(void);
361
362extern struct xlr_board_fmn_config xlr_board_fmn_config;
363#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 868013e62f3..9a691b1f91b 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -258,7 +258,5 @@ nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
258 nlm_write_reg(base, PIC_IRT_1(irt), 258 nlm_write_reg(base, PIC_IRT_1(irt),
259 (1 << 30) | (1 << 6) | irq); 259 (1 << 30) | (1 << 6) | irq);
260} 260}
261
262extern uint64_t nlm_pic_base;
263#endif 261#endif
264#endif /* _ASM_NLM_XLR_PIC_H */ 262#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index ff4a17b0bf7..c1667e0c272 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -51,10 +51,8 @@ static inline unsigned int nlm_chip_is_xls_b(void)
51 return ((prid & 0xf000) == 0x4000); 51 return ((prid & 0xf000) == 0x4000);
52} 52}
53 53
54/* 54/* XLR chip types */
55 * XLR chip types 55/* The XLS product line has chip versions 0x[48c]? */
56 */
57 /* The XLS product line has chip versions 0x[48c]? */
58static inline unsigned int nlm_chip_is_xls(void) 56static inline unsigned int nlm_chip_is_xls(void)
59{ 57{
60 uint32_t prid = read_c0_prid(); 58 uint32_t prid = read_c0_prid();
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 09:16:07 -0500