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authorManuel Lauss <manuel.lauss@googlemail.com>2011-11-10 07:06:16 -0500
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:02:06 -0500
commitf869d42e580f6260b5c29b5ab5c5cfcfd32a0756 (patch)
tree279125640d5ae76e9bb8c278d34bea2a4591c254 /arch/mips/include/asm/mach-db1x00
parent64cd04d0cffa3b3af0e81aa3112b71f135739e1a (diff)
MIPS: Alchemy: Improved DB1550 support, with audio and serial busses.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2868/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-db1x00')
-rw-r--r--arch/mips/include/asm/mach-db1x00/bcsr.h2
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1x00.h16
2 files changed, 1 insertions, 17 deletions
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
index 0ef63007130..bb9fc23d853 100644
--- a/arch/mips/include/asm/mach-db1x00/bcsr.h
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -163,7 +163,7 @@ enum bcsr_whoami_boards {
163#define BCSR_BOARD_GPIO200RST 0x0400 163#define BCSR_BOARD_GPIO200RST 0x0400
164#define BCSR_BOARD_PCICLKOUT 0x0800 164#define BCSR_BOARD_PCICLKOUT 0x0800
165#define BCSR_BOARD_PCICFG 0x1000 165#define BCSR_BOARD_PCICFG 0x1000
166#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */ 166#define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */
167#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ 167#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */
168#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ 168#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */
169 169
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
index a5affb0568e..51f1ebf0df9 100644
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
@@ -29,22 +29,6 @@
29 29
30#include <asm/mach-au1x00/au1xxx_psc.h> 30#include <asm/mach-au1x00/au1xxx_psc.h>
31 31
32#ifdef CONFIG_MIPS_DB1550
33
34#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
35#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
36#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
37#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
38
39#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
40#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
41#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
42#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
43
44#define NAND_PHYS_ADDR 0x20000000
45
46#endif
47
48/* 32/*
49 * NAND defines 33 * NAND defines
50 * 34 *