MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCs

This patch adds initial support for various Atheros SoCs based on the
MIPS 24Kc core. The following models are supported at the moment:

  - AR7130
  - AR7141
  - AR7161
  - AR9130
  - AR9132
  - AR7240
  - AR7241
  - AR7242

The current patch contains minimal support only, but the resulting
kernel can boot into user-space with using of an initramfs image on
various boards which are using these SoCs. Support for more built-in
devices and individual boards will be implemented in further patches.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: Luis R. Rodriguez <lrodriguez@atheros.com>
Cc: Cliff Holden <Cliff.Holden@Atheros.com>
Cc: Kathy Giori <Kathy.Giori@Atheros.com>
Patchwork: https://patchwork.linux-mips.org/patch/1947/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 36 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
new file mode 100644
index 00000000000..189bc6eb9c1
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -0,0 +1,36 @@
+/*
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+#ifndef __ASM_MACH_ATH79_IRQ_H
+#define __ASM_MACH_ATH79_IRQ_H
+
+#define MIPS_CPU_IRQ_BASE       0
+#define NR_IRQS                 16
+
+#define ATH79_MISC_IRQ_BASE     8
+#define ATH79_MISC_IRQ_COUNT    8
+
+#define ATH79_CPU_IRQ_IP2       (MIPS_CPU_IRQ_BASE + 2)
+#define ATH79_CPU_IRQ_USB       (MIPS_CPU_IRQ_BASE + 3)
+#define ATH79_CPU_IRQ_GE0       (MIPS_CPU_IRQ_BASE + 4)
+#define ATH79_CPU_IRQ_GE1       (MIPS_CPU_IRQ_BASE + 5)
+#define ATH79_CPU_IRQ_MISC      (MIPS_CPU_IRQ_BASE + 6)
+#define ATH79_CPU_IRQ_TIMER     (MIPS_CPU_IRQ_BASE + 7)
+
+#define ATH79_MISC_IRQ_TIMER    (ATH79_MISC_IRQ_BASE + 0)
+#define ATH79_MISC_IRQ_ERROR    (ATH79_MISC_IRQ_BASE + 1)
+#define ATH79_MISC_IRQ_GPIO     (ATH79_MISC_IRQ_BASE + 2)
+#define ATH79_MISC_IRQ_UART     (ATH79_MISC_IRQ_BASE + 3)
+#define ATH79_MISC_IRQ_WDOG     (ATH79_MISC_IRQ_BASE + 4)
+#define ATH79_MISC_IRQ_PERFC    (ATH79_MISC_IRQ_BASE + 5)
+#define ATH79_MISC_IRQ_OHCI     (ATH79_MISC_IRQ_BASE + 6)
+#define ATH79_MISC_IRQ_DMA      (ATH79_MISC_IRQ_BASE + 7)
+
+#include_next <irq.h>
+
+#endif /* __ASM_MACH_ATH79_IRQ_H */