MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs

Besides the CPU and DDR PLLs, the CPU and DDR frequencies
can be derived from other PLLs in the SRIF block on the
AR934x SoCs. The current code does not checks if the SRIF
PLLs are used and this can lead to incorrectly calculated
CPU/DDR frequencies.

Fix it by calculating the frequencies from SRIF PLLs if
those are used on a given board.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: <stable@vger.kernel.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4324/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 23 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 3ccae12cc7b..a5e0f17ea77 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -65,6 +65,8 @@
 #define AR934X_WMAC_SIZE        0x20000
 #define AR934X_EHCI_BASE        0x1b000000
 #define AR934X_EHCI_SIZE        0x200
+#define AR934X_SRIF_BASE        (AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE        0x1000
 
 /*
  * DDR_CTRL block
@@ -406,4 +408,25 @@
 #define AR933X_GPIO_COUNT               30
 #define AR934X_GPIO_COUNT               23
 
+/*
+ * SRIF block
+ */
+#define AR934X_SRIF_CPU_DPLL1_REG       0x1c0
+#define AR934X_SRIF_CPU_DPLL2_REG       0x1c4
+#define AR934X_SRIF_CPU_DPLL3_REG       0x1c8
+
+#define AR934X_SRIF_DDR_DPLL1_REG       0x240
+#define AR934X_SRIF_DDR_DPLL2_REG       0x244
+#define AR934X_SRIF_DDR_DPLL3_REG       0x248
+
+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT  27
+#define AR934X_SRIF_DPLL1_REFDIV_MASK   0x1f
+#define AR934X_SRIF_DPLL1_NINT_SHIFT    18
+#define AR934X_SRIF_DPLL1_NINT_MASK     0x1ff
+#define AR934X_SRIF_DPLL1_NFRAC_MASK    0x0003ffff
+
+#define AR934X_SRIF_DPLL2_LOCAL_PLL     BIT(30)
+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT  13
+#define AR934X_SRIF_DPLL2_OUTDIV_MASK   0x7
+
 #endif /* __ASM_MACH_AR71XX_REGS_H */