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authorManuel Lauss <mlau@msc-ge.com>2009-11-23 14:40:00 -0500
committerRalf Baechle <ralf@linux-mips.org>2010-02-27 06:53:02 -0500
commit70f82f2c59be86fad915a2ee62673fe1aad6c2bd (patch)
tree089b089e5962fbc96dd30651889b8a42a04abc6c /arch/mips/alchemy/common
parentbd2302c220566cffd0756e1ac5f65705f9e3d8e7 (diff)
MIPS: Alchemy: use runtime cpu detection in GPIO code.
Remove the cpu subtype cpp macros in favor of runtime detection, to improve compile coverage of the alchemy common code. (Increases kernel size by 700 bytes). Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/699/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy/common')
-rw-r--r--arch/mips/alchemy/common/gpiolib-au1000.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib-au1000.c
index 1bfa91f939f..c8e1a94d4a9 100644
--- a/arch/mips/alchemy/common/gpiolib-au1000.c
+++ b/arch/mips/alchemy/common/gpiolib-au1000.c
@@ -36,7 +36,6 @@
36#include <asm/mach-au1x00/au1000.h> 36#include <asm/mach-au1x00/au1000.h>
37#include <asm/mach-au1x00/gpio.h> 37#include <asm/mach-au1x00/gpio.h>
38 38
39#if !defined(CONFIG_SOC_AU1000)
40static int gpio2_get(struct gpio_chip *chip, unsigned offset) 39static int gpio2_get(struct gpio_chip *chip, unsigned offset)
41{ 40{
42 return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE); 41 return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
@@ -63,7 +62,7 @@ static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
63{ 62{
64 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE); 63 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
65} 64}
66#endif /* !defined(CONFIG_SOC_AU1000) */ 65
67 66
68static int gpio1_get(struct gpio_chip *chip, unsigned offset) 67static int gpio1_get(struct gpio_chip *chip, unsigned offset)
69{ 68{
@@ -104,7 +103,6 @@ struct gpio_chip alchemy_gpio_chip[] = {
104 .base = ALCHEMY_GPIO1_BASE, 103 .base = ALCHEMY_GPIO1_BASE,
105 .ngpio = ALCHEMY_GPIO1_NUM, 104 .ngpio = ALCHEMY_GPIO1_NUM,
106 }, 105 },
107#if !defined(CONFIG_SOC_AU1000)
108 [1] = { 106 [1] = {
109 .label = "alchemy-gpio2", 107 .label = "alchemy-gpio2",
110 .direction_input = gpio2_direction_input, 108 .direction_input = gpio2_direction_input,
@@ -115,15 +113,13 @@ struct gpio_chip alchemy_gpio_chip[] = {
115 .base = ALCHEMY_GPIO2_BASE, 113 .base = ALCHEMY_GPIO2_BASE,
116 .ngpio = ALCHEMY_GPIO2_NUM, 114 .ngpio = ALCHEMY_GPIO2_NUM,
117 }, 115 },
118#endif
119}; 116};
120 117
121static int __init alchemy_gpiolib_init(void) 118static int __init alchemy_gpiolib_init(void)
122{ 119{
123 gpiochip_add(&alchemy_gpio_chip[0]); 120 gpiochip_add(&alchemy_gpio_chip[0]);
124#if !defined(CONFIG_SOC_AU1000) 121 if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000)
125 gpiochip_add(&alchemy_gpio_chip[1]); 122 gpiochip_add(&alchemy_gpio_chip[1]);
126#endif
127 123
128 return 0; 124 return 0;
129} 125}