diff options
author | Greg Ungerer <gerg@uclinux.org> | 2009-05-21 23:33:35 -0400 |
---|---|---|
committer | Greg Ungerer <gerg@uclinux.org> | 2009-09-15 19:43:52 -0400 |
commit | 39f0fb6a3448cfc316e0d5295ed1b121db50037e (patch) | |
tree | 657db8073835e8d499708a898a36f1d3a1e39a32 /arch/m68knommu/platform/5206/config.c | |
parent | f6a66276f5fdc018d2a9378c71de3bae13c588d7 (diff) |
m68knommu: map ColdFire interrupts to correct masking bits
The older simple ColdFire interrupt controller has no one-to-one mapping
of interrupt numbers to bits in the interrupt mask register. Create a
mapping array that each ColdFire CPU type can populate with its available
interrupts and the bits that each use in the interrupt mask register.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu/platform/5206/config.c')
-rw-r--r-- | arch/m68knommu/platform/5206/config.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/m68knommu/platform/5206/config.c b/arch/m68knommu/platform/5206/config.c index c1d24796ef2..9c335465e66 100644 --- a/arch/m68knommu/platform/5206/config.c +++ b/arch/m68knommu/platform/5206/config.c | |||
@@ -49,11 +49,11 @@ static void __init m5206_uart_init_line(int line, int irq) | |||
49 | if (line == 0) { | 49 | if (line == 0) { |
50 | writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); | 50 | writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); |
51 | writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); | 51 | writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); |
52 | mcf_clrimr(MCFINTC_UART0); | 52 | mcf_mapirq2imr(irq, MCFINTC_UART0); |
53 | } else if (line == 1) { | 53 | } else if (line == 1) { |
54 | writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); | 54 | writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); |
55 | writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); | 55 | writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); |
56 | mcf_clrimr(MCFINTC_UART1); | 56 | mcf_mapirq2imr(irq, MCFINTC_UART1); |
57 | } | 57 | } |
58 | } | 58 | } |
59 | 59 | ||
@@ -73,11 +73,13 @@ static void __init m5206_timers_init(void) | |||
73 | /* Timer1 is always used as system timer */ | 73 | /* Timer1 is always used as system timer */ |
74 | writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, | 74 | writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, |
75 | MCF_MBAR + MCFSIM_TIMER1ICR); | 75 | MCF_MBAR + MCFSIM_TIMER1ICR); |
76 | mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); | ||
76 | 77 | ||
77 | #ifdef CONFIG_HIGHPROFILE | 78 | #ifdef CONFIG_HIGHPROFILE |
78 | /* Timer2 is to be used as a high speed profile timer */ | 79 | /* Timer2 is to be used as a high speed profile timer */ |
79 | writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, | 80 | writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, |
80 | MCF_MBAR + MCFSIM_TIMER2ICR); | 81 | MCF_MBAR + MCFSIM_TIMER2ICR); |
82 | mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); | ||
81 | #endif | 83 | #endif |
82 | } | 84 | } |
83 | 85 | ||
@@ -98,13 +100,18 @@ void __init config_BSP(char *commandp, int size) | |||
98 | { | 100 | { |
99 | mach_reset = m5206_cpu_reset; | 101 | mach_reset = m5206_cpu_reset; |
100 | m5206_timers_init(); | 102 | m5206_timers_init(); |
103 | m5206_uarts_init(); | ||
104 | |||
105 | /* Only support the external interrupts on their primary level */ | ||
106 | mcf_mapirq2imr(25, MCFINTC_EINT1); | ||
107 | mcf_mapirq2imr(28, MCFINTC_EINT4); | ||
108 | mcf_mapirq2imr(31, MCFINTC_EINT7); | ||
101 | } | 109 | } |
102 | 110 | ||
103 | /***************************************************************************/ | 111 | /***************************************************************************/ |
104 | 112 | ||
105 | static int __init init_BSP(void) | 113 | static int __init init_BSP(void) |
106 | { | 114 | { |
107 | m5206_uarts_init(); | ||
108 | platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices)); | 115 | platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices)); |
109 | return 0; | 116 | return 0; |
110 | } | 117 | } |