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authorPhilippe De Muyter <phdm@macqel.be>2010-09-20 07:11:11 -0400
committerGreg Ungerer <gerg@uclinux.org>2010-10-20 20:17:30 -0400
commitea49f8ffae6262e8de9a0d3e9fcdd384156c7e05 (patch)
tree546e2ec64f98b5c39a14b61c9861edcbc70e6e35 /arch/m68k
parenta7c681f620e75cb0efbe7da092723a6ecd17bc01 (diff)
m68knommu: add basic mmu-less m548x support
Add a very basic mmu-less support for coldfire m548x family. This is perhaps also valid for m547x family. The port comprises the serial, tick timer and reboot support. The gpio part compiles but is empty. This gives a functional albeit limited linux for the m548x coldfire family. This has been tested on a Freescale M548xEVB Lite board with a M5484 processor and the default dbug monitor. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/include/asm/cacheflush_no.h2
-rw-r--r--arch/m68k/include/asm/coldfire.h4
-rw-r--r--arch/m68k/include/asm/gpio.h7
-rw-r--r--arch/m68k/include/asm/m548xgpt.h88
-rw-r--r--arch/m68k/include/asm/m548xsim.h55
-rw-r--r--arch/m68k/include/asm/mcfcache.h2
-rw-r--r--arch/m68k/include/asm/mcfsim.h2
-rw-r--r--arch/m68k/include/asm/mcfslt.h44
-rw-r--r--arch/m68k/include/asm/mcfuart.h5
9 files changed, 205 insertions, 4 deletions
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 89f195656be..7085bd51668 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -29,7 +29,7 @@
29 29
30static inline void __flush_cache_all(void) 30static inline void __flush_cache_all(void)
31{ 31{
32#ifdef CONFIG_M5407 32#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
33 /* 33 /*
34 * Use cpushl to push and invalidate all cache lines. 34 * Use cpushl to push and invalidate all cache lines.
35 * Gas doesn't seem to know how to generate the ColdFire 35 * Gas doesn't seem to know how to generate the ColdFire
diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 83a9fa4e618..3b0a34d0fe3 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -32,7 +32,9 @@
32 */ 32 */
33#define MCF_MBAR 0x10000000 33#define MCF_MBAR 0x10000000
34#define MCF_MBAR2 0x80000000 34#define MCF_MBAR2 0x80000000
35#if defined(CONFIG_M520x) 35#if defined(CONFIG_M548x)
36#define MCF_IPSBAR MCF_MBAR
37#elif defined(CONFIG_M520x)
36#define MCF_IPSBAR 0xFC000000 38#define MCF_IPSBAR 0xFC000000
37#else 39#else
38#define MCF_IPSBAR 0x40000000 40#define MCF_IPSBAR 0x40000000
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index 283214dc65a..1b57adbafad 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -36,7 +36,8 @@
36 */ 36 */
37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) 39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
40 defined(CONFIG_M532x) || defined(CONFIG_M548x)
40 41
41/* These parts have GPIO organized by 8 bit ports */ 42/* These parts have GPIO organized by 8 bit ports */
42 43
@@ -136,6 +137,8 @@ static inline u32 __mcf_gpio_ppdr(unsigned gpio)
136#endif 137#endif
137 else 138 else
138 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); 139 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
140#else
141 return 0;
139#endif 142#endif
140} 143}
141 144
@@ -173,6 +176,8 @@ static inline u32 __mcf_gpio_podr(unsigned gpio)
173#endif 176#endif
174 else 177 else
175 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START); 178 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
179#else
180 return 0;
176#endif 181#endif
177} 182}
178 183
diff --git a/arch/m68k/include/asm/m548xgpt.h b/arch/m68k/include/asm/m548xgpt.h
new file mode 100644
index 00000000000..c8ef158a1c4
--- /dev/null
+++ b/arch/m68k/include/asm/m548xgpt.h
@@ -0,0 +1,88 @@
1/*
2 * File: m548xgpt.h
3 * Purpose: Register and bit definitions for the MCF548X
4 *
5 * Notes:
6 *
7 */
8
9#ifndef m548xgpt_h
10#define m548xgpt_h
11
12/*********************************************************************
13*
14* General Purpose Timers (GPT)
15*
16*********************************************************************/
17
18/* Register read/write macros */
19#define MCF_GPT_GMS0 0x000800
20#define MCF_GPT_GCIR0 0x000804
21#define MCF_GPT_GPWM0 0x000808
22#define MCF_GPT_GSR0 0x00080C
23#define MCF_GPT_GMS1 0x000810
24#define MCF_GPT_GCIR1 0x000814
25#define MCF_GPT_GPWM1 0x000818
26#define MCF_GPT_GSR1 0x00081C
27#define MCF_GPT_GMS2 0x000820
28#define MCF_GPT_GCIR2 0x000824
29#define MCF_GPT_GPWM2 0x000828
30#define MCF_GPT_GSR2 0x00082C
31#define MCF_GPT_GMS3 0x000830
32#define MCF_GPT_GCIR3 0x000834
33#define MCF_GPT_GPWM3 0x000838
34#define MCF_GPT_GSR3 0x00083C
35#define MCF_GPT_GMS(x) (0x000800+((x)*0x010))
36#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010))
37#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010))
38#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010))
39
40/* Bit definitions and macros for MCF_GPT_GMS */
41#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
42#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
43#define MCF_GPT_GMS_IEN (0x00000100)
44#define MCF_GPT_GMS_OD (0x00000200)
45#define MCF_GPT_GMS_SC (0x00000400)
46#define MCF_GPT_GMS_CE (0x00001000)
47#define MCF_GPT_GMS_WDEN (0x00008000)
48#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
49#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
50#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
51#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
52#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
53#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
54#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
55#define MCF_GPT_GMS_ICT_ANY (0x00000000)
56#define MCF_GPT_GMS_ICT_RISE (0x00010000)
57#define MCF_GPT_GMS_ICT_FALL (0x00020000)
58#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
59#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
60#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
61#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
62#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
63#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
64#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
65#define MCF_GPT_GMS_TMS_PWM (0x00000003)
66#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
67
68/* Bit definitions and macros for MCF_GPT_GCIR */
69#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
70#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
71
72/* Bit definitions and macros for MCF_GPT_GPWM */
73#define MCF_GPT_GPWM_LOAD (0x00000001)
74#define MCF_GPT_GPWM_PWMOP (0x00000100)
75#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
76
77/* Bit definitions and macros for MCF_GPT_GSR */
78#define MCF_GPT_GSR_CAPT (0x00000001)
79#define MCF_GPT_GSR_COMP (0x00000002)
80#define MCF_GPT_GSR_PWMP (0x00000004)
81#define MCF_GPT_GSR_TEXP (0x00000008)
82#define MCF_GPT_GSR_PIN (0x00000100)
83#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
84#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
85
86/********************************************************************/
87
88#endif /* m548xgpt_h */
diff --git a/arch/m68k/include/asm/m548xsim.h b/arch/m68k/include/asm/m548xsim.h
new file mode 100644
index 00000000000..149135ef30d
--- /dev/null
+++ b/arch/m68k/include/asm/m548xsim.h
@@ -0,0 +1,55 @@
1/*
2 * m548xsim.h -- ColdFire 547x/548x System Integration Unit support.
3 */
4
5#ifndef m548xsim_h
6#define m548xsim_h
7
8#define MCFINT_VECBASE 64
9
10/*
11 * Interrupt Controller Registers
12 */
13#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */
14#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
15#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
16#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
17#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
18#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
19#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
20#define MCFINTC_IRLR 0x18 /* */
21#define MCFINTC_IACKL 0x19 /* */
22#define MCFINTC_ICR0 0x40 /* Base ICR register */
23
24/*
25 * Define system peripheral IRQ usage.
26 */
27#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
28#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */
29
30/*
31 * Generic GPIO support
32 */
33#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */
34#define MCFGPIO_IRQ_MAX -1
35#define MCFGPIO_IRQ_VECBASE -1
36
37/*
38 * Some PSC related definitions
39 */
40#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
41#define MCF_PAR_SDA (0x0008)
42#define MCF_PAR_SCL (0x0004)
43#define MCF_PAR_PSC_TXD (0x04)
44#define MCF_PAR_PSC_RXD (0x08)
45#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
46#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
47#define MCF_PAR_PSC_CTS_GPIO (0x00)
48#define MCF_PAR_PSC_CTS_BCLK (0x80)
49#define MCF_PAR_PSC_CTS_CTS (0xC0)
50#define MCF_PAR_PSC_RTS_GPIO (0x00)
51#define MCF_PAR_PSC_RTS_FSYNC (0x20)
52#define MCF_PAR_PSC_RTS_RTS (0x30)
53#define MCF_PAR_PSC_CANRX (0x40)
54
55#endif /* m548xsim_h */
diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h
index c042634fada..f49dfc09f70 100644
--- a/arch/m68k/include/asm/mcfcache.h
+++ b/arch/m68k/include/asm/mcfcache.h
@@ -107,7 +107,7 @@
107.endm 107.endm
108#endif /* CONFIG_M532x */ 108#endif /* CONFIG_M532x */
109 109
110#if defined(CONFIG_M5407) 110#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
111/* 111/*
112 * Version 4 cores have a true harvard style separate instruction 112 * Version 4 cores have a true harvard style separate instruction
113 * and data cache. Invalidate and enable cache, also enable write 113 * and data cache. Invalidate and enable cache, also enable write
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index 9c70a67bf85..6901fd68165 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -41,6 +41,8 @@
41#elif defined(CONFIG_M5407) 41#elif defined(CONFIG_M5407)
42#include <asm/m5407sim.h> 42#include <asm/m5407sim.h>
43#include <asm/mcfintc.h> 43#include <asm/mcfintc.h>
44#elif defined(CONFIG_M548x)
45#include <asm/m548xsim.h>
44#endif 46#endif
45 47
46/****************************************************************************/ 48/****************************************************************************/
diff --git a/arch/m68k/include/asm/mcfslt.h b/arch/m68k/include/asm/mcfslt.h
new file mode 100644
index 00000000000..d0d0ecba533
--- /dev/null
+++ b/arch/m68k/include/asm/mcfslt.h
@@ -0,0 +1,44 @@
1/****************************************************************************/
2
3/*
4 * mcfslt.h -- ColdFire internal Slice (SLT) timer support defines.
5 *
6 * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be)
8 */
9
10/****************************************************************************/
11#ifndef mcfslt_h
12#define mcfslt_h
13/****************************************************************************/
14
15/*
16 * Get address specific defines for the 547x.
17 */
18#define MCFSLT_TIMER0 0x900 /* Base address of TIMER0 */
19#define MCFSLT_TIMER1 0x910 /* Base address of TIMER1 */
20
21
22/*
23 * Define the SLT timer register set addresses.
24 */
25#define MCFSLT_STCNT 0x00 /* Terminal count */
26#define MCFSLT_SCR 0x04 /* Control */
27#define MCFSLT_SCNT 0x08 /* Current count */
28#define MCFSLT_SSR 0x0C /* Status */
29
30/*
31 * Bit definitions for the SCR control register.
32 */
33#define MCFSLT_SCR_RUN 0x04000000 /* Run mode (continuous) */
34#define MCFSLT_SCR_IEN 0x02000000 /* Interrupt enable */
35#define MCFSLT_SCR_TEN 0x01000000 /* Timer enable */
36
37/*
38 * Bit definitions for the SSR status register.
39 */
40#define MCFSLT_SSR_BE 0x02000000 /* Bus error condition */
41#define MCFSLT_SSR_TE 0x01000000 /* Timeout condition */
42
43/****************************************************************************/
44#endif /* mcfslt_h */
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index 01a8716c5fc..af16f3be4e1 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -47,6 +47,11 @@
47#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ 47#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
48#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ 48#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
49#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ 49#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
50#elif defined(CONFIG_M548x)
51#define MCFUART_BASE1 0x8600 /* on M548x */
52#define MCFUART_BASE2 0x8700 /* on M548x */
53#define MCFUART_BASE3 0x8800 /* on M548x */
54#define MCFUART_BASE4 0x8900 /* on M548x */
50#endif 55#endif
51 56
52 57