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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-21 22:15:03 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-21 22:15:03 -0400
commit06930b94d19a8641f8a2dc9d6ec27e2a5a39d17c (patch)
tree0672b1c9181fa7e1484c511d87d1ed29acfa0650 /arch/m68k
parent2e321806b681b1920b6dfa7d81bbe3d312fe1d19 (diff)
parent7094ac08cb9568a3efa1e3da177350e168c5fd96 (diff)
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
Pull m68knommu tree from Greg Ungerer: "More merge and clean up of MMU and non-MMU common files, namely signal.c and dma.c. There is also a simplification of the ColdFire GPIO setup tables. Using a couple of simple macros we make the init tables really small and easy to read, and save a couple of thousand lines of code. Also a move of all the ColdFire subarch support files into the existing coldfire directory. The sub-directories just ended up duplicating Makefiles and now only contain really simple pieces of code. This saves quite a few lines of code too. As always a couple of bugs fixes thrown in too. Oh and a new defconfig for the ColdFire platforms that support having the MMU enabled." * 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (39 commits) m68k: add a defconfig for the M5475EVB ColdFire with MMU board m68knommu: unaligned.h fix for M68000 core m68k: merge the MMU and non-MMU versions of the arch dma code m68knommu: reorganize the no-MMU cache flushing to match m68k m68knommu: move the 54xx platform code into the common ColdFire code directory m68knommu: move the 532x platform code into the common ColdFire code directory m68knommu: move the 5407 platform code into the common ColdFire code directory m68knommu: move the 5307 platform code into the common ColdFire code directory m68knommu: move the 528x platform code into the common ColdFire code directory m68knommu: move the 527x platform code into the common ColdFire code directory m68knommu: move the 5272 platform code into the common ColdFire code directory m68knommu: move the 5249 platform code into the common ColdFire code directory m68knommu: move the 523x platform code into the common ColdFire code directory m68knommu: move the 520x platform code into the common ColdFire code directory m68knommu: move the 5206 platform code into the common ColdFire code directory m68knommu: simplify the ColdFire 5407 GPIO struct setup m68knommu: simplify the ColdFire 532x GPIO struct setup m68knommu: simplify the ColdFire 5307 GPIO struct setup m68knommu: simplify the ColdFire 528x GPIO struct setup m68knommu: simplify the ColdFire 527x GPIO struct setup ...
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/Makefile12
-rw-r--r--arch/m68k/configs/m5475evb_defconfig62
-rw-r--r--arch/m68k/include/asm/cacheflush_no.h32
-rw-r--r--arch/m68k/include/asm/flat.h7
-rw-r--r--arch/m68k/include/asm/m528xsim.h179
-rw-r--r--arch/m68k/include/asm/mcfgpio.h57
-rw-r--r--arch/m68k/include/asm/unaligned.h2
-rw-r--r--arch/m68k/kernel/dma.c165
-rw-r--r--arch/m68k/kernel/dma_mm.c131
-rw-r--r--arch/m68k/kernel/dma_no.c75
-rw-r--r--arch/m68k/kernel/signal.c1201
-rw-r--r--arch/m68k/kernel/signal_mm.c1115
-rw-r--r--arch/m68k/kernel/signal_no.c765
-rw-r--r--arch/m68k/platform/5206/Makefile18
-rw-r--r--arch/m68k/platform/5206/gpio.c49
-rw-r--r--arch/m68k/platform/520x/Makefile17
-rw-r--r--arch/m68k/platform/520x/gpio.c175
-rw-r--r--arch/m68k/platform/523x/Makefile17
-rw-r--r--arch/m68k/platform/523x/gpio.c284
-rw-r--r--arch/m68k/platform/5249/Makefile18
-rw-r--r--arch/m68k/platform/5249/gpio.c65
-rw-r--r--arch/m68k/platform/5272/Makefile18
-rw-r--r--arch/m68k/platform/5272/gpio.c81
-rw-r--r--arch/m68k/platform/527x/Makefile18
-rw-r--r--arch/m68k/platform/527x/gpio.c609
-rw-r--r--arch/m68k/platform/528x/Makefile18
-rw-r--r--arch/m68k/platform/528x/gpio.c438
-rw-r--r--arch/m68k/platform/5307/Makefile20
-rw-r--r--arch/m68k/platform/5307/gpio.c49
-rw-r--r--arch/m68k/platform/532x/Makefile18
-rw-r--r--arch/m68k/platform/532x/gpio.c337
-rw-r--r--arch/m68k/platform/5407/Makefile18
-rw-r--r--arch/m68k/platform/5407/gpio.c49
-rw-r--r--arch/m68k/platform/54xx/Makefile19
-rw-r--r--arch/m68k/platform/coldfire/Makefile28
-rw-r--r--arch/m68k/platform/coldfire/firebee.c (renamed from arch/m68k/platform/54xx/firebee.c)0
-rw-r--r--arch/m68k/platform/coldfire/gpio.c4
-rw-r--r--arch/m68k/platform/coldfire/intc-5249.c (renamed from arch/m68k/platform/5249/intc2.c)0
-rw-r--r--arch/m68k/platform/coldfire/intc-5272.c (renamed from arch/m68k/platform/5272/intc.c)0
-rw-r--r--arch/m68k/platform/coldfire/m5206.c (renamed from arch/m68k/platform/5206/config.c)9
-rw-r--r--arch/m68k/platform/coldfire/m520x.c (renamed from arch/m68k/platform/520x/config.c)16
-rw-r--r--arch/m68k/platform/coldfire/m523x.c (renamed from arch/m68k/platform/523x/config.c)22
-rw-r--r--arch/m68k/platform/coldfire/m5249.c (renamed from arch/m68k/platform/5249/config.c)10
-rw-r--r--arch/m68k/platform/coldfire/m5272.c (renamed from arch/m68k/platform/5272/config.c)11
-rw-r--r--arch/m68k/platform/coldfire/m527x.c (renamed from arch/m68k/platform/527x/config.c)43
-rw-r--r--arch/m68k/platform/coldfire/m528x.c (renamed from arch/m68k/platform/528x/config.c)31
-rw-r--r--arch/m68k/platform/coldfire/m5307.c (renamed from arch/m68k/platform/5307/config.c)9
-rw-r--r--arch/m68k/platform/coldfire/m532x.c (renamed from arch/m68k/platform/532x/config.c)25
-rw-r--r--arch/m68k/platform/coldfire/m5407.c (renamed from arch/m68k/platform/5407/config.c)9
-rw-r--r--arch/m68k/platform/coldfire/m54xx.c (renamed from arch/m68k/platform/54xx/config.c)7
-rw-r--r--arch/m68k/platform/coldfire/nettel.c (renamed from arch/m68k/platform/5307/nettel.c)0
51 files changed, 1807 insertions, 4555 deletions
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index 41b3bc926bb..b7f2e2d5cd2 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -116,18 +116,6 @@ core-$(CONFIG_M68000) += arch/m68k/platform/68328/
116core-$(CONFIG_M68EZ328) += arch/m68k/platform/68EZ328/ 116core-$(CONFIG_M68EZ328) += arch/m68k/platform/68EZ328/
117core-$(CONFIG_M68VZ328) += arch/m68k/platform/68VZ328/ 117core-$(CONFIG_M68VZ328) += arch/m68k/platform/68VZ328/
118core-$(CONFIG_COLDFIRE) += arch/m68k/platform/coldfire/ 118core-$(CONFIG_COLDFIRE) += arch/m68k/platform/coldfire/
119core-$(CONFIG_M5206) += arch/m68k/platform/5206/
120core-$(CONFIG_M5206e) += arch/m68k/platform/5206/
121core-$(CONFIG_M520x) += arch/m68k/platform/520x/
122core-$(CONFIG_M523x) += arch/m68k/platform/523x/
123core-$(CONFIG_M5249) += arch/m68k/platform/5249/
124core-$(CONFIG_M527x) += arch/m68k/platform/527x/
125core-$(CONFIG_M5272) += arch/m68k/platform/5272/
126core-$(CONFIG_M528x) += arch/m68k/platform/528x/
127core-$(CONFIG_M5307) += arch/m68k/platform/5307/
128core-$(CONFIG_M532x) += arch/m68k/platform/532x/
129core-$(CONFIG_M5407) += arch/m68k/platform/5407/
130core-$(CONFIG_M54xx) += arch/m68k/platform/54xx/
131 119
132 120
133all: zImage 121all: zImage
diff --git a/arch/m68k/configs/m5475evb_defconfig b/arch/m68k/configs/m5475evb_defconfig
new file mode 100644
index 00000000000..c5018a68819
--- /dev/null
+++ b/arch/m68k/configs/m5475evb_defconfig
@@ -0,0 +1,62 @@
1CONFIG_EXPERIMENTAL=y
2# CONFIG_SWAP is not set
3CONFIG_LOG_BUF_SHIFT=14
4CONFIG_SYSFS_DEPRECATED=y
5CONFIG_SYSFS_DEPRECATED_V2=y
6CONFIG_SYSCTL_SYSCALL=y
7# CONFIG_KALLSYMS is not set
8# CONFIG_HOTPLUG is not set
9# CONFIG_FUTEX is not set
10# CONFIG_EPOLL is not set
11# CONFIG_SIGNALFD is not set
12# CONFIG_TIMERFD is not set
13# CONFIG_EVENTFD is not set
14# CONFIG_SHMEM is not set
15# CONFIG_AIO is not set
16CONFIG_EMBEDDED=y
17CONFIG_MODULES=y
18# CONFIG_LBDAF is not set
19# CONFIG_BLK_DEV_BSG is not set
20# CONFIG_IOSCHED_DEADLINE is not set
21# CONFIG_IOSCHED_CFQ is not set
22CONFIG_COLDFIRE=y
23CONFIG_M547x=y
24CONFIG_CLOCK_SET=y
25CONFIG_CLOCK_FREQ=266000000
26# CONFIG_4KSTACKS is not set
27CONFIG_RAMBASE=0x0
28CONFIG_RAMSIZE=0x2000000
29CONFIG_VECTORBASE=0x0
30CONFIG_MBAR=0xff000000
31CONFIG_KERNELBASE=0x20000
32# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
33# CONFIG_FW_LOADER is not set
34CONFIG_MTD=y
35CONFIG_MTD_CHAR=y
36CONFIG_MTD_BLOCK=y
37CONFIG_MTD_CFI=y
38CONFIG_MTD_JEDECPROBE=y
39CONFIG_MTD_CFI_AMDSTD=y
40CONFIG_MTD_RAM=y
41CONFIG_MTD_PHYSMAP=y
42CONFIG_MTD_UCLINUX=y
43CONFIG_BLK_DEV_RAM=y
44# CONFIG_INPUT is not set
45# CONFIG_VT is not set
46# CONFIG_UNIX98_PTYS is not set
47CONFIG_SERIAL_MCF=y
48CONFIG_SERIAL_MCF_CONSOLE=y
49# CONFIG_HW_RANDOM is not set
50# CONFIG_HWMON is not set
51# CONFIG_USB_SUPPORT is not set
52# CONFIG_IOMMU_SUPPORT is not set
53CONFIG_EXT2_FS=y
54# CONFIG_FILE_LOCKING is not set
55# CONFIG_DNOTIFY is not set
56# CONFIG_INOTIFY_USER is not set
57# CONFIG_PROC_PAGE_MONITOR is not set
58CONFIG_ROMFS_FS=y
59CONFIG_ROMFS_BACKED_BY_MTD=y
60# CONFIG_SCHED_DEBUG is not set
61CONFIG_BOOTPARAM=y
62CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0"
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index cb88aa96c4f..7cafb537d03 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -30,11 +30,8 @@
30 30
31void mcf_cache_push(void); 31void mcf_cache_push(void);
32 32
33static inline void __flush_cache_all(void) 33static inline void __clear_cache_all(void)
34{ 34{
35#ifdef CACHE_PUSH
36 mcf_cache_push();
37#endif
38#ifdef CACHE_INVALIDATE 35#ifdef CACHE_INVALIDATE
39 __asm__ __volatile__ ( 36 __asm__ __volatile__ (
40 "movel %0, %%d0\n\t" 37 "movel %0, %%d0\n\t"
@@ -44,6 +41,14 @@ static inline void __flush_cache_all(void)
44#endif 41#endif
45} 42}
46 43
44static inline void __flush_cache_all(void)
45{
46#ifdef CACHE_PUSH
47 mcf_cache_push();
48#endif
49 __clear_cache_all();
50}
51
47/* 52/*
48 * Some ColdFire parts implement separate instruction and data caches, 53 * Some ColdFire parts implement separate instruction and data caches,
49 * on those we should just flush the appropriate cache. If we don't need 54 * on those we should just flush the appropriate cache. If we don't need
@@ -76,4 +81,23 @@ static inline void __flush_dcache_all(void)
76 __asm__ __volatile__ ( "nop" ); 81 __asm__ __volatile__ ( "nop" );
77#endif 82#endif
78} 83}
84
85/*
86 * Push cache entries at supplied address. We want to write back any dirty
87 * data and the invalidate the cache lines associated with this address.
88 */
89static inline void cache_push(unsigned long paddr, int len)
90{
91 __flush_cache_all();
92}
93
94/*
95 * Clear cache entries at supplied address (that is don't write back any
96 * dirty data).
97 */
98static inline void cache_clear(unsigned long paddr, int len)
99{
100 __clear_cache_all();
101}
102
79#endif /* _M68KNOMMU_CACHEFLUSH_H */ 103#endif /* _M68KNOMMU_CACHEFLUSH_H */
diff --git a/arch/m68k/include/asm/flat.h b/arch/m68k/include/asm/flat.h
index a0e29079397..f9454b89a51 100644
--- a/arch/m68k/include/asm/flat.h
+++ b/arch/m68k/include/asm/flat.h
@@ -11,6 +11,11 @@
11#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp) 11#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp)
12#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) 12#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp)
13#define flat_get_relocate_addr(rel) (rel) 13#define flat_get_relocate_addr(rel) (rel)
14#define flat_set_persistent(relval, p) 0 14
15static inline int flat_set_persistent(unsigned long relval,
16 unsigned long *persistent)
17{
18 return 0;
19}
15 20
16#endif /* __M68KNOMMU_FLAT_H__ */ 21#endif /* __M68KNOMMU_FLAT_H__ */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 569476fba18..d63b99ff7ff 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -97,100 +97,81 @@
97/* 97/*
98 * GPIO registers 98 * GPIO registers
99 */ 99 */
100#define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000) 100#define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000)
101#define MCFGPIO_PORTB (MCF_IPSBAR + 0x00100001) 101#define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001)
102#define MCFGPIO_PORTC (MCF_IPSBAR + 0x00100002) 102#define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002)
103#define MCFGPIO_PORTD (MCF_IPSBAR + 0x00100003) 103#define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003)
104#define MCFGPIO_PORTE (MCF_IPSBAR + 0x00100004) 104#define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004)
105#define MCFGPIO_PORTF (MCF_IPSBAR + 0x00100005) 105#define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005)
106#define MCFGPIO_PORTG (MCF_IPSBAR + 0x00100006) 106#define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006)
107#define MCFGPIO_PORTH (MCF_IPSBAR + 0x00100007) 107#define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007)
108#define MCFGPIO_PORTJ (MCF_IPSBAR + 0x00100008) 108#define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008)
109#define MCFGPIO_PORTDD (MCF_IPSBAR + 0x00100009) 109#define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009)
110#define MCFGPIO_PORTEH (MCF_IPSBAR + 0x0010000A) 110#define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A)
111#define MCFGPIO_PORTEL (MCF_IPSBAR + 0x0010000B) 111#define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B)
112#define MCFGPIO_PORTAS (MCF_IPSBAR + 0x0010000C) 112#define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C)
113#define MCFGPIO_PORTQS (MCF_IPSBAR + 0x0010000D) 113#define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D)
114#define MCFGPIO_PORTSD (MCF_IPSBAR + 0x0010000E) 114#define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E)
115#define MCFGPIO_PORTTC (MCF_IPSBAR + 0x0010000F) 115#define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F)
116#define MCFGPIO_PORTTD (MCF_IPSBAR + 0x00100010) 116#define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010)
117#define MCFGPIO_PORTUA (MCF_IPSBAR + 0x00100011) 117#define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011)
118 118
119#define MCFGPIO_DDRA (MCF_IPSBAR + 0x00100014) 119#define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014)
120#define MCFGPIO_DDRB (MCF_IPSBAR + 0x00100015) 120#define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015)
121#define MCFGPIO_DDRC (MCF_IPSBAR + 0x00100016) 121#define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016)
122#define MCFGPIO_DDRD (MCF_IPSBAR + 0x00100017) 122#define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017)
123#define MCFGPIO_DDRE (MCF_IPSBAR + 0x00100018) 123#define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018)
124#define MCFGPIO_DDRF (MCF_IPSBAR + 0x00100019) 124#define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019)
125#define MCFGPIO_DDRG (MCF_IPSBAR + 0x0010001A) 125#define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A)
126#define MCFGPIO_DDRH (MCF_IPSBAR + 0x0010001B) 126#define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B)
127#define MCFGPIO_DDRJ (MCF_IPSBAR + 0x0010001C) 127#define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C)
128#define MCFGPIO_DDRDD (MCF_IPSBAR + 0x0010001D) 128#define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D)
129#define MCFGPIO_DDREH (MCF_IPSBAR + 0x0010001E) 129#define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E)
130#define MCFGPIO_DDREL (MCF_IPSBAR + 0x0010001F) 130#define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F)
131#define MCFGPIO_DDRAS (MCF_IPSBAR + 0x00100020) 131#define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020)
132#define MCFGPIO_DDRQS (MCF_IPSBAR + 0x00100021) 132#define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021)
133#define MCFGPIO_DDRSD (MCF_IPSBAR + 0x00100022) 133#define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022)
134#define MCFGPIO_DDRTC (MCF_IPSBAR + 0x00100023) 134#define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023)
135#define MCFGPIO_DDRTD (MCF_IPSBAR + 0x00100024) 135#define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024)
136#define MCFGPIO_DDRUA (MCF_IPSBAR + 0x00100025) 136#define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025)
137 137
138#define MCFGPIO_PORTAP (MCF_IPSBAR + 0x00100028) 138#define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028)
139#define MCFGPIO_PORTBP (MCF_IPSBAR + 0x00100029) 139#define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029)
140#define MCFGPIO_PORTCP (MCF_IPSBAR + 0x0010002A) 140#define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A)
141#define MCFGPIO_PORTDP (MCF_IPSBAR + 0x0010002B) 141#define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B)
142#define MCFGPIO_PORTEP (MCF_IPSBAR + 0x0010002C) 142#define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C)
143#define MCFGPIO_PORTFP (MCF_IPSBAR + 0x0010002D) 143#define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D)
144#define MCFGPIO_PORTGP (MCF_IPSBAR + 0x0010002E) 144#define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E)
145#define MCFGPIO_PORTHP (MCF_IPSBAR + 0x0010002F) 145#define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F)
146#define MCFGPIO_PORTJP (MCF_IPSBAR + 0x00100030) 146#define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030)
147#define MCFGPIO_PORTDDP (MCF_IPSBAR + 0x00100031) 147#define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031)
148#define MCFGPIO_PORTEHP (MCF_IPSBAR + 0x00100032) 148#define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032)
149#define MCFGPIO_PORTELP (MCF_IPSBAR + 0x00100033) 149#define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033)
150#define MCFGPIO_PORTASP (MCF_IPSBAR + 0x00100034) 150#define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034)
151#define MCFGPIO_PORTQSP (MCF_IPSBAR + 0x00100035) 151#define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035)
152#define MCFGPIO_PORTSDP (MCF_IPSBAR + 0x00100036) 152#define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036)
153#define MCFGPIO_PORTTCP (MCF_IPSBAR + 0x00100037) 153#define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037)
154#define MCFGPIO_PORTTDP (MCF_IPSBAR + 0x00100038) 154#define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038)
155#define MCFGPIO_PORTUAP (MCF_IPSBAR + 0x00100039) 155#define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039)
156 156
157#define MCFGPIO_SETA (MCF_IPSBAR + 0x00100028) 157#define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C)
158#define MCFGPIO_SETB (MCF_IPSBAR + 0x00100029) 158#define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D)
159#define MCFGPIO_SETC (MCF_IPSBAR + 0x0010002A) 159#define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E)
160#define MCFGPIO_SETD (MCF_IPSBAR + 0x0010002B) 160#define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F)
161#define MCFGPIO_SETE (MCF_IPSBAR + 0x0010002C) 161#define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040)
162#define MCFGPIO_SETF (MCF_IPSBAR + 0x0010002D) 162#define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041)
163#define MCFGPIO_SETG (MCF_IPSBAR + 0x0010002E) 163#define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042)
164#define MCFGPIO_SETH (MCF_IPSBAR + 0x0010002F) 164#define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043)
165#define MCFGPIO_SETJ (MCF_IPSBAR + 0x00100030) 165#define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044)
166#define MCFGPIO_SETDD (MCF_IPSBAR + 0x00100031) 166#define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045)
167#define MCFGPIO_SETEH (MCF_IPSBAR + 0x00100032) 167#define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046)
168#define MCFGPIO_SETEL (MCF_IPSBAR + 0x00100033) 168#define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047)
169#define MCFGPIO_SETAS (MCF_IPSBAR + 0x00100034) 169#define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048)
170#define MCFGPIO_SETQS (MCF_IPSBAR + 0x00100035) 170#define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049)
171#define MCFGPIO_SETSD (MCF_IPSBAR + 0x00100036) 171#define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A)
172#define MCFGPIO_SETTC (MCF_IPSBAR + 0x00100037) 172#define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B)
173#define MCFGPIO_SETTD (MCF_IPSBAR + 0x00100038) 173#define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C)
174#define MCFGPIO_SETUA (MCF_IPSBAR + 0x00100039) 174#define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D)
175
176#define MCFGPIO_CLRA (MCF_IPSBAR + 0x0010003C)
177#define MCFGPIO_CLRB (MCF_IPSBAR + 0x0010003D)
178#define MCFGPIO_CLRC (MCF_IPSBAR + 0x0010003E)
179#define MCFGPIO_CLRD (MCF_IPSBAR + 0x0010003F)
180#define MCFGPIO_CLRE (MCF_IPSBAR + 0x00100040)
181#define MCFGPIO_CLRF (MCF_IPSBAR + 0x00100041)
182#define MCFGPIO_CLRG (MCF_IPSBAR + 0x00100042)
183#define MCFGPIO_CLRH (MCF_IPSBAR + 0x00100043)
184#define MCFGPIO_CLRJ (MCF_IPSBAR + 0x00100044)
185#define MCFGPIO_CLRDD (MCF_IPSBAR + 0x00100045)
186#define MCFGPIO_CLREH (MCF_IPSBAR + 0x00100046)
187#define MCFGPIO_CLREL (MCF_IPSBAR + 0x00100047)
188#define MCFGPIO_CLRAS (MCF_IPSBAR + 0x00100048)
189#define MCFGPIO_CLRQS (MCF_IPSBAR + 0x00100049)
190#define MCFGPIO_CLRSD (MCF_IPSBAR + 0x0010004A)
191#define MCFGPIO_CLRTC (MCF_IPSBAR + 0x0010004B)
192#define MCFGPIO_CLRTD (MCF_IPSBAR + 0x0010004C)
193#define MCFGPIO_CLRUA (MCF_IPSBAR + 0x0010004D)
194 175
195#define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050) 176#define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050)
196#define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051) 177#define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051)
@@ -242,11 +223,11 @@
242 * definitions for generic gpio support 223 * definitions for generic gpio support
243 * 224 *
244 */ 225 */
245#define MCFGPIO_PODR MCFGPIO_PORTA /* port output data */ 226#define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */
246#define MCFGPIO_PDDR MCFGPIO_DDRA /* port data direction */ 227#define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */
247#define MCFGPIO_PPDR MCFGPIO_PORTAP /* port pin data */ 228#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */
248#define MCFGPIO_SETR MCFGPIO_SETA /* set output */ 229#define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */
249#define MCFGPIO_CLRR MCFGPIO_CLRA /* clr output */ 230#define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */
250 231
251#define MCFGPIO_IRQ_MAX 8 232#define MCFGPIO_IRQ_MAX 8
252#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 233#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
index ee5e4ccce89..fe468eaa51e 100644
--- a/arch/m68k/include/asm/mcfgpio.h
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -29,6 +29,9 @@ struct mcf_gpio_chip {
29 const u8 *gpio_to_pinmux; 29 const u8 *gpio_to_pinmux;
30}; 30};
31 31
32extern struct mcf_gpio_chip mcf_gpio_chips[];
33extern unsigned int mcf_gpio_chips_size;
34
32int mcf_gpio_direction_input(struct gpio_chip *, unsigned); 35int mcf_gpio_direction_input(struct gpio_chip *, unsigned);
33int mcf_gpio_get_value(struct gpio_chip *, unsigned); 36int mcf_gpio_get_value(struct gpio_chip *, unsigned);
34int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int); 37int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);
@@ -37,4 +40,58 @@ void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);
37int mcf_gpio_request(struct gpio_chip *, unsigned); 40int mcf_gpio_request(struct gpio_chip *, unsigned);
38void mcf_gpio_free(struct gpio_chip *, unsigned); 41void mcf_gpio_free(struct gpio_chip *, unsigned);
39 42
43/*
44 * Define macros to ease the pain of setting up the GPIO tables. There
45 * are two cases we need to deal with here, they cover all currently
46 * available ColdFire GPIO hardware. There are of course minor differences
47 * in the layout and number of bits in each ColdFire part, but the macros
48 * take all that in.
49 *
50 * Firstly is the conventional GPIO registers where we toggle individual
51 * bits in a register, preserving the other bits in the register. For
52 * lack of a better term I have called this the slow method.
53 */
54#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \
55 { \
56 .gpio_chip = { \
57 .label = #mlabel, \
58 .request = mcf_gpio_request, \
59 .free = mcf_gpio_free, \
60 .direction_input = mcf_gpio_direction_input, \
61 .direction_output = mcf_gpio_direction_output,\
62 .get = mcf_gpio_get_value, \
63 .set = mcf_gpio_set_value, \
64 .base = mbase, \
65 .ngpio = mngpio, \
66 }, \
67 .pddr = (void __iomem *) mpddr, \
68 .podr = (void __iomem *) mpodr, \
69 .ppdr = (void __iomem *) mppdr, \
70 }
71
72/*
73 * Secondly is the faster case, where we have set and clear registers
74 * that allow us to set or clear a bit with a single write, not having
75 * to worry about preserving other bits.
76 */
77#define MCFGPF(mlabel, mbase, mngpio) \
78 { \
79 .gpio_chip = { \
80 .label = #mlabel, \
81 .request = mcf_gpio_request, \
82 .free = mcf_gpio_free, \
83 .direction_input = mcf_gpio_direction_input, \
84 .direction_output = mcf_gpio_direction_output,\
85 .get = mcf_gpio_get_value, \
86 .set = mcf_gpio_set_value_fast, \
87 .base = mbase, \
88 .ngpio = mngpio, \
89 }, \
90 .pddr = (void __iomem *) MCFGPIO_PDDR_##mlabel, \
91 .podr = (void __iomem *) MCFGPIO_PODR_##mlabel, \
92 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
93 .setr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
94 .clrr = (void __iomem *) MCFGPIO_PCLRR_##mlabel, \
95 }
96
40#endif 97#endif
diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h
index 019caa740c2..f4043ae63db 100644
--- a/arch/m68k/include/asm/unaligned.h
+++ b/arch/m68k/include/asm/unaligned.h
@@ -2,7 +2,7 @@
2#define _ASM_M68K_UNALIGNED_H 2#define _ASM_M68K_UNALIGNED_H
3 3
4 4
5#ifdef CONFIG_COLDFIRE 5#if defined(CONFIG_COLDFIRE) || defined(CONFIG_M68000)
6#include <linux/unaligned/be_struct.h> 6#include <linux/unaligned/be_struct.h>
7#include <linux/unaligned/le_byteshift.h> 7#include <linux/unaligned/le_byteshift.h>
8#include <linux/unaligned/generic.h> 8#include <linux/unaligned/generic.h>
diff --git a/arch/m68k/kernel/dma.c b/arch/m68k/kernel/dma.c
index 90e8cb726c8..f6daf6e15d2 100644
--- a/arch/m68k/kernel/dma.c
+++ b/arch/m68k/kernel/dma.c
@@ -1,5 +1,164 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file COPYING in the main directory of this archive
4 * for more details.
5 */
6
7#undef DEBUG
8
9#include <linux/dma-mapping.h>
10#include <linux/device.h>
11#include <linux/kernel.h>
12#include <linux/scatterlist.h>
13#include <linux/slab.h>
14#include <linux/vmalloc.h>
15#include <linux/export.h>
16
17#include <asm/pgalloc.h>
18
1#ifdef CONFIG_MMU 19#ifdef CONFIG_MMU
2#include "dma_mm.c" 20
21void *dma_alloc_coherent(struct device *dev, size_t size,
22 dma_addr_t *handle, gfp_t flag)
23{
24 struct page *page, **map;
25 pgprot_t pgprot;
26 void *addr;
27 int i, order;
28
29 pr_debug("dma_alloc_coherent: %d,%x\n", size, flag);
30
31 size = PAGE_ALIGN(size);
32 order = get_order(size);
33
34 page = alloc_pages(flag, order);
35 if (!page)
36 return NULL;
37
38 *handle = page_to_phys(page);
39 map = kmalloc(sizeof(struct page *) << order, flag & ~__GFP_DMA);
40 if (!map) {
41 __free_pages(page, order);
42 return NULL;
43 }
44 split_page(page, order);
45
46 order = 1 << order;
47 size >>= PAGE_SHIFT;
48 map[0] = page;
49 for (i = 1; i < size; i++)
50 map[i] = page + i;
51 for (; i < order; i++)
52 __free_page(page + i);
53 pgprot = __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
54 if (CPU_IS_040_OR_060)
55 pgprot_val(pgprot) |= _PAGE_GLOBAL040 | _PAGE_NOCACHE_S;
56 else
57 pgprot_val(pgprot) |= _PAGE_NOCACHE030;
58 addr = vmap(map, size, VM_MAP, pgprot);
59 kfree(map);
60
61 return addr;
62}
63
64void dma_free_coherent(struct device *dev, size_t size,
65 void *addr, dma_addr_t handle)
66{
67 pr_debug("dma_free_coherent: %p, %x\n", addr, handle);
68 vfree(addr);
69}
70
3#else 71#else
4#include "dma_no.c" 72
5#endif 73#include <asm/cacheflush.h>
74
75void *dma_alloc_coherent(struct device *dev, size_t size,
76 dma_addr_t *dma_handle, gfp_t gfp)
77{
78 void *ret;
79 /* ignore region specifiers */
80 gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
81
82 if (dev == NULL || (*dev->dma_mask < 0xffffffff))
83 gfp |= GFP_DMA;
84 ret = (void *)__get_free_pages(gfp, get_order(size));
85
86 if (ret != NULL) {
87 memset(ret, 0, size);
88 *dma_handle = virt_to_phys(ret);
89 }
90 return ret;
91}
92
93void dma_free_coherent(struct device *dev, size_t size,
94 void *vaddr, dma_addr_t dma_handle)
95{
96 free_pages((unsigned long)vaddr, get_order(size));
97}
98
99#endif /* CONFIG_MMU */
100
101EXPORT_SYMBOL(dma_alloc_coherent);
102EXPORT_SYMBOL(dma_free_coherent);
103
104void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
105 size_t size, enum dma_data_direction dir)
106{
107 switch (dir) {
108 case DMA_TO_DEVICE:
109 cache_push(handle, size);
110 break;
111 case DMA_FROM_DEVICE:
112 cache_clear(handle, size);
113 break;
114 default:
115 if (printk_ratelimit())
116 printk("dma_sync_single_for_device: unsupported dir %u\n", dir);
117 break;
118 }
119}
120EXPORT_SYMBOL(dma_sync_single_for_device);
121
122void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
123 enum dma_data_direction dir)
124{
125 int i;
126
127 for (i = 0; i < nents; sg++, i++)
128 dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir);
129}
130EXPORT_SYMBOL(dma_sync_sg_for_device);
131
132dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size,
133 enum dma_data_direction dir)
134{
135 dma_addr_t handle = virt_to_bus(addr);
136
137 dma_sync_single_for_device(dev, handle, size, dir);
138 return handle;
139}
140EXPORT_SYMBOL(dma_map_single);
141
142dma_addr_t dma_map_page(struct device *dev, struct page *page,
143 unsigned long offset, size_t size,
144 enum dma_data_direction dir)
145{
146 dma_addr_t handle = page_to_phys(page) + offset;
147
148 dma_sync_single_for_device(dev, handle, size, dir);
149 return handle;
150}
151EXPORT_SYMBOL(dma_map_page);
152
153int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
154 enum dma_data_direction dir)
155{
156 int i;
157
158 for (i = 0; i < nents; sg++, i++) {
159 sg->dma_address = sg_phys(sg);
160 dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir);
161 }
162 return nents;
163}
164EXPORT_SYMBOL(dma_map_sg);
diff --git a/arch/m68k/kernel/dma_mm.c b/arch/m68k/kernel/dma_mm.c
deleted file mode 100644
index a3c471b523f..00000000000
--- a/arch/m68k/kernel/dma_mm.c
+++ /dev/null
@@ -1,131 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file COPYING in the main directory of this archive
4 * for more details.
5 */
6
7#undef DEBUG
8
9#include <linux/dma-mapping.h>
10#include <linux/device.h>
11#include <linux/kernel.h>
12#include <linux/scatterlist.h>
13#include <linux/slab.h>
14#include <linux/vmalloc.h>
15#include <linux/export.h>
16
17#include <asm/pgalloc.h>
18
19void *dma_alloc_coherent(struct device *dev, size_t size,
20 dma_addr_t *handle, gfp_t flag)
21{
22 struct page *page, **map;
23 pgprot_t pgprot;
24 void *addr;
25 int i, order;
26
27 pr_debug("dma_alloc_coherent: %d,%x\n", size, flag);
28
29 size = PAGE_ALIGN(size);
30 order = get_order(size);
31
32 page = alloc_pages(flag, order);
33 if (!page)
34 return NULL;
35
36 *handle = page_to_phys(page);
37 map = kmalloc(sizeof(struct page *) << order, flag & ~__GFP_DMA);
38 if (!map) {
39 __free_pages(page, order);
40 return NULL;
41 }
42 split_page(page, order);
43
44 order = 1 << order;
45 size >>= PAGE_SHIFT;
46 map[0] = page;
47 for (i = 1; i < size; i++)
48 map[i] = page + i;
49 for (; i < order; i++)
50 __free_page(page + i);
51 pgprot = __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
52 if (CPU_IS_040_OR_060)
53 pgprot_val(pgprot) |= _PAGE_GLOBAL040 | _PAGE_NOCACHE_S;
54 else
55 pgprot_val(pgprot) |= _PAGE_NOCACHE030;
56 addr = vmap(map, size, VM_MAP, pgprot);
57 kfree(map);
58
59 return addr;
60}
61EXPORT_SYMBOL(dma_alloc_coherent);
62
63void dma_free_coherent(struct device *dev, size_t size,
64 void *addr, dma_addr_t handle)
65{
66 pr_debug("dma_free_coherent: %p, %x\n", addr, handle);
67 vfree(addr);
68}
69EXPORT_SYMBOL(dma_free_coherent);
70
71void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
72 size_t size, enum dma_data_direction dir)
73{
74 switch (dir) {
75 case DMA_TO_DEVICE:
76 cache_push(handle, size);
77 break;
78 case DMA_FROM_DEVICE:
79 cache_clear(handle, size);
80 break;
81 default:
82 if (printk_ratelimit())
83 printk("dma_sync_single_for_device: unsupported dir %u\n", dir);
84 break;
85 }
86}
87EXPORT_SYMBOL(dma_sync_single_for_device);
88
89void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
90 enum dma_data_direction dir)
91{
92 int i;
93
94 for (i = 0; i < nents; sg++, i++)
95 dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir);
96}
97EXPORT_SYMBOL(dma_sync_sg_for_device);
98
99dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size,
100 enum dma_data_direction dir)
101{
102 dma_addr_t handle = virt_to_bus(addr);
103
104 dma_sync_single_for_device(dev, handle, size, dir);
105 return handle;
106}
107EXPORT_SYMBOL(dma_map_single);
108
109dma_addr_t dma_map_page(struct device *dev, struct page *page,
110 unsigned long offset, size_t size,
111 enum dma_data_direction dir)
112{
113 dma_addr_t handle = page_to_phys(page) + offset;
114
115 dma_sync_single_for_device(dev, handle, size, dir);
116 return handle;
117}
118EXPORT_SYMBOL(dma_map_page);
119
120int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
121 enum dma_data_direction dir)
122{
123 int i;
124
125 for (i = 0; i < nents; sg++, i++) {
126 sg->dma_address = sg_phys(sg);
127 dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir);
128 }
129 return nents;
130}
131EXPORT_SYMBOL(dma_map_sg);
diff --git a/arch/m68k/kernel/dma_no.c b/arch/m68k/kernel/dma_no.c
deleted file mode 100644
index f1dc3fc71bc..00000000000
--- a/arch/m68k/kernel/dma_no.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * Dynamic DMA mapping support.
3 *
4 * We never have any address translations to worry about, so this
5 * is just alloc/free.
6 */
7
8#include <linux/types.h>
9#include <linux/gfp.h>
10#include <linux/mm.h>
11#include <linux/device.h>
12#include <linux/dma-mapping.h>
13#include <linux/export.h>
14#include <asm/cacheflush.h>
15
16void *dma_alloc_coherent(struct device *dev, size_t size,
17 dma_addr_t *dma_handle, gfp_t gfp)
18{
19 void *ret;
20 /* ignore region specifiers */
21 gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
22
23 if (dev == NULL || (*dev->dma_mask < 0xffffffff))
24 gfp |= GFP_DMA;
25 ret = (void *)__get_free_pages(gfp, get_order(size));
26
27 if (ret != NULL) {
28 memset(ret, 0, size);
29 *dma_handle = virt_to_phys(ret);
30 }
31 return ret;
32}
33
34void dma_free_coherent(struct device *dev, size_t size,
35 void *vaddr, dma_addr_t dma_handle)
36{
37 free_pages((unsigned long)vaddr, get_order(size));
38}
39
40void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
41 size_t size, enum dma_data_direction dir)
42{
43 switch (dir) {
44 case DMA_TO_DEVICE:
45 flush_dcache_range(handle, size);
46 break;
47 case DMA_FROM_DEVICE:
48 /* Should be clear already */
49 break;
50 default:
51 if (printk_ratelimit())
52 printk("dma_sync_single_for_device: unsupported dir %u\n", dir);
53 break;
54 }
55}
56
57EXPORT_SYMBOL(dma_sync_single_for_device);
58dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size,
59 enum dma_data_direction dir)
60{
61 dma_addr_t handle = virt_to_phys(addr);
62 flush_dcache_range(handle, size);
63 return handle;
64}
65EXPORT_SYMBOL(dma_map_single);
66
67dma_addr_t dma_map_page(struct device *dev, struct page *page,
68 unsigned long offset, size_t size,
69 enum dma_data_direction dir)
70{
71 dma_addr_t handle = page_to_phys(page) + offset;
72 dma_sync_single_for_device(dev, handle, size, dir);
73 return handle;
74}
75EXPORT_SYMBOL(dma_map_page);
diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c
index 2e25713e2ea..1747c7030a3 100644
--- a/arch/m68k/kernel/signal.c
+++ b/arch/m68k/kernel/signal.c
@@ -1,5 +1,1202 @@
1/*
2 * linux/arch/m68k/kernel/signal.c
3 *
4 * Copyright (C) 1991, 1992 Linus Torvalds
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11/*
12 * Linux/m68k support by Hamish Macdonald
13 *
14 * 68060 fixes by Jesper Skov
15 *
16 * 1997-12-01 Modified for POSIX.1b signals by Andreas Schwab
17 *
18 * mathemu support by Roman Zippel
19 * (Note: fpstate in the signal context is completely ignored for the emulator
20 * and the internal floating point format is put on stack)
21 */
22
23/*
24 * ++roman (07/09/96): implemented signal stacks (specially for tosemu on
25 * Atari :-) Current limitation: Only one sigstack can be active at one time.
26 * If a second signal with SA_ONSTACK set arrives while working on a sigstack,
27 * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested
28 * signal handlers!
29 */
30
31#include <linux/sched.h>
32#include <linux/mm.h>
33#include <linux/kernel.h>
34#include <linux/signal.h>
35#include <linux/syscalls.h>
36#include <linux/errno.h>
37#include <linux/wait.h>
38#include <linux/ptrace.h>
39#include <linux/unistd.h>
40#include <linux/stddef.h>
41#include <linux/highuid.h>
42#include <linux/personality.h>
43#include <linux/tty.h>
44#include <linux/binfmts.h>
45#include <linux/module.h>
46
47#include <asm/setup.h>
48#include <asm/uaccess.h>
49#include <asm/pgtable.h>
50#include <asm/traps.h>
51#include <asm/ucontext.h>
52
53#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
54
1#ifdef CONFIG_MMU 55#ifdef CONFIG_MMU
2#include "signal_mm.c" 56
57/*
58 * Handle the slight differences in classic 68k and ColdFire trap frames.
59 */
60#ifdef CONFIG_COLDFIRE
61#define FORMAT 4
62#define FMT4SIZE 0
3#else 63#else
4#include "signal_no.c" 64#define FORMAT 0
65#define FMT4SIZE sizeof(((struct frame *)0)->un.fmt4)
5#endif 66#endif
67
68static const int frame_size_change[16] = {
69 [1] = -1, /* sizeof(((struct frame *)0)->un.fmt1), */
70 [2] = sizeof(((struct frame *)0)->un.fmt2),
71 [3] = sizeof(((struct frame *)0)->un.fmt3),
72 [4] = FMT4SIZE,
73 [5] = -1, /* sizeof(((struct frame *)0)->un.fmt5), */
74 [6] = -1, /* sizeof(((struct frame *)0)->un.fmt6), */
75 [7] = sizeof(((struct frame *)0)->un.fmt7),
76 [8] = -1, /* sizeof(((struct frame *)0)->un.fmt8), */
77 [9] = sizeof(((struct frame *)0)->un.fmt9),
78 [10] = sizeof(((struct frame *)0)->un.fmta),
79 [11] = sizeof(((struct frame *)0)->un.fmtb),
80 [12] = -1, /* sizeof(((struct frame *)0)->un.fmtc), */
81 [13] = -1, /* sizeof(((struct frame *)0)->un.fmtd), */
82 [14] = -1, /* sizeof(((struct frame *)0)->un.fmte), */
83 [15] = -1, /* sizeof(((struct frame *)0)->un.fmtf), */
84};
85
86static inline int frame_extra_sizes(int f)
87{
88 return frame_size_change[f];
89}
90
91int handle_kernel_fault(struct pt_regs *regs)
92{
93 const struct exception_table_entry *fixup;
94 struct pt_regs *tregs;
95
96 /* Are we prepared to handle this kernel fault? */
97 fixup = search_exception_tables(regs->pc);
98 if (!fixup)
99 return 0;
100
101 /* Create a new four word stack frame, discarding the old one. */
102 regs->stkadj = frame_extra_sizes(regs->format);
103 tregs = (struct pt_regs *)((long)regs + regs->stkadj);
104 tregs->vector = regs->vector;
105 tregs->format = FORMAT;
106 tregs->pc = fixup->fixup;
107 tregs->sr = regs->sr;
108
109 return 1;
110}
111
112void ptrace_signal_deliver(struct pt_regs *regs, void *cookie)
113{
114 if (regs->orig_d0 < 0)
115 return;
116 switch (regs->d0) {
117 case -ERESTARTNOHAND:
118 case -ERESTARTSYS:
119 case -ERESTARTNOINTR:
120 regs->d0 = regs->orig_d0;
121 regs->orig_d0 = -1;
122 regs->pc -= 2;
123 break;
124 }
125}
126
127static inline void push_cache (unsigned long vaddr)
128{
129 /*
130 * Using the old cache_push_v() was really a big waste.
131 *
132 * What we are trying to do is to flush 8 bytes to ram.
133 * Flushing 2 cache lines of 16 bytes is much cheaper than
134 * flushing 1 or 2 pages, as previously done in
135 * cache_push_v().
136 * Jes
137 */
138 if (CPU_IS_040) {
139 unsigned long temp;
140
141 __asm__ __volatile__ (".chip 68040\n\t"
142 "nop\n\t"
143 "ptestr (%1)\n\t"
144 "movec %%mmusr,%0\n\t"
145 ".chip 68k"
146 : "=r" (temp)
147 : "a" (vaddr));
148
149 temp &= PAGE_MASK;
150 temp |= vaddr & ~PAGE_MASK;
151
152 __asm__ __volatile__ (".chip 68040\n\t"
153 "nop\n\t"
154 "cpushl %%bc,(%0)\n\t"
155 ".chip 68k"
156 : : "a" (temp));
157 }
158 else if (CPU_IS_060) {
159 unsigned long temp;
160 __asm__ __volatile__ (".chip 68060\n\t"
161 "plpar (%0)\n\t"
162 ".chip 68k"
163 : "=a" (temp)
164 : "0" (vaddr));
165 __asm__ __volatile__ (".chip 68060\n\t"
166 "cpushl %%bc,(%0)\n\t"
167 ".chip 68k"
168 : : "a" (temp));
169 } else if (!CPU_IS_COLDFIRE) {
170 /*
171 * 68030/68020 have no writeback cache;
172 * still need to clear icache.
173 * Note that vaddr is guaranteed to be long word aligned.
174 */
175 unsigned long temp;
176 asm volatile ("movec %%cacr,%0" : "=r" (temp));
177 temp += 4;
178 asm volatile ("movec %0,%%caar\n\t"
179 "movec %1,%%cacr"
180 : : "r" (vaddr), "r" (temp));
181 asm volatile ("movec %0,%%caar\n\t"
182 "movec %1,%%cacr"
183 : : "r" (vaddr + 4), "r" (temp));
184 }
185}
186
187static inline void adjustformat(struct pt_regs *regs)
188{
189}
190
191static inline void save_a5_state(struct sigcontext *sc, struct pt_regs *regs)
192{
193}
194
195#else /* CONFIG_MMU */
196
197void ret_from_user_signal(void);
198void ret_from_user_rt_signal(void);
199
200static inline int frame_extra_sizes(int f)
201{
202 /* No frame size adjustments required on non-MMU CPUs */
203 return 0;
204}
205
206static inline void adjustformat(struct pt_regs *regs)
207{
208 ((struct switch_stack *)regs - 1)->a5 = current->mm->start_data;
209 /*
210 * set format byte to make stack appear modulo 4, which it will
211 * be when doing the rte
212 */
213 regs->format = 0x4;
214}
215
216static inline void save_a5_state(struct sigcontext *sc, struct pt_regs *regs)
217{
218 sc->sc_a5 = ((struct switch_stack *)regs - 1)->a5;
219}
220
221static inline void push_cache(unsigned long vaddr)
222{
223}
224
225#endif /* CONFIG_MMU */
226
227/*
228 * Atomically swap in the new signal mask, and wait for a signal.
229 */
230asmlinkage int
231sys_sigsuspend(int unused0, int unused1, old_sigset_t mask)
232{
233 mask &= _BLOCKABLE;
234 spin_lock_irq(&current->sighand->siglock);
235 current->saved_sigmask = current->blocked;
236 siginitset(&current->blocked, mask);
237 recalc_sigpending();
238 spin_unlock_irq(&current->sighand->siglock);
239
240 current->state = TASK_INTERRUPTIBLE;
241 schedule();
242 set_restore_sigmask();
243
244 return -ERESTARTNOHAND;
245}
246
247asmlinkage int
248sys_sigaction(int sig, const struct old_sigaction __user *act,
249 struct old_sigaction __user *oact)
250{
251 struct k_sigaction new_ka, old_ka;
252 int ret;
253
254 if (act) {
255 old_sigset_t mask;
256 if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
257 __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
258 __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
259 __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
260 __get_user(mask, &act->sa_mask))
261 return -EFAULT;
262 siginitset(&new_ka.sa.sa_mask, mask);
263 }
264
265 ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
266
267 if (!ret && oact) {
268 if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
269 __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
270 __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
271 __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
272 __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
273 return -EFAULT;
274 }
275
276 return ret;
277}
278
279asmlinkage int
280sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss)
281{
282 return do_sigaltstack(uss, uoss, rdusp());
283}
284
285
286/*
287 * Do a signal return; undo the signal stack.
288 *
289 * Keep the return code on the stack quadword aligned!
290 * That makes the cache flush below easier.
291 */
292
293struct sigframe
294{
295 char __user *pretcode;
296 int sig;
297 int code;
298 struct sigcontext __user *psc;
299 char retcode[8];
300 unsigned long extramask[_NSIG_WORDS-1];
301 struct sigcontext sc;
302};
303
304struct rt_sigframe
305{
306 char __user *pretcode;
307 int sig;
308 struct siginfo __user *pinfo;
309 void __user *puc;
310 char retcode[8];
311 struct siginfo info;
312 struct ucontext uc;
313};
314
315#define FPCONTEXT_SIZE 216
316#define uc_fpstate uc_filler[0]
317#define uc_formatvec uc_filler[FPCONTEXT_SIZE/4]
318#define uc_extra uc_filler[FPCONTEXT_SIZE/4+1]
319
320#ifdef CONFIG_FPU
321
322static unsigned char fpu_version; /* version number of fpu, set by setup_frame */
323
324static inline int restore_fpu_state(struct sigcontext *sc)
325{
326 int err = 1;
327
328 if (FPU_IS_EMU) {
329 /* restore registers */
330 memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12);
331 memcpy(current->thread.fp, sc->sc_fpregs, 24);
332 return 0;
333 }
334
335 if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
336 /* Verify the frame format. */
337 if (!(CPU_IS_060 || CPU_IS_COLDFIRE) &&
338 (sc->sc_fpstate[0] != fpu_version))
339 goto out;
340 if (CPU_IS_020_OR_030) {
341 if (m68k_fputype & FPU_68881 &&
342 !(sc->sc_fpstate[1] == 0x18 || sc->sc_fpstate[1] == 0xb4))
343 goto out;
344 if (m68k_fputype & FPU_68882 &&
345 !(sc->sc_fpstate[1] == 0x38 || sc->sc_fpstate[1] == 0xd4))
346 goto out;
347 } else if (CPU_IS_040) {
348 if (!(sc->sc_fpstate[1] == 0x00 ||
349 sc->sc_fpstate[1] == 0x28 ||
350 sc->sc_fpstate[1] == 0x60))
351 goto out;
352 } else if (CPU_IS_060) {
353 if (!(sc->sc_fpstate[3] == 0x00 ||
354 sc->sc_fpstate[3] == 0x60 ||
355 sc->sc_fpstate[3] == 0xe0))
356 goto out;
357 } else if (CPU_IS_COLDFIRE) {
358 if (!(sc->sc_fpstate[0] == 0x00 ||
359 sc->sc_fpstate[0] == 0x05 ||
360 sc->sc_fpstate[0] == 0xe5))
361 goto out;
362 } else
363 goto out;
364
365 if (CPU_IS_COLDFIRE) {
366 __asm__ volatile ("fmovemd %0,%%fp0-%%fp1\n\t"
367 "fmovel %1,%%fpcr\n\t"
368 "fmovel %2,%%fpsr\n\t"
369 "fmovel %3,%%fpiar"
370 : /* no outputs */
371 : "m" (sc->sc_fpregs[0]),
372 "m" (sc->sc_fpcntl[0]),
373 "m" (sc->sc_fpcntl[1]),
374 "m" (sc->sc_fpcntl[2]));
375 } else {
376 __asm__ volatile (".chip 68k/68881\n\t"
377 "fmovemx %0,%%fp0-%%fp1\n\t"
378 "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
379 ".chip 68k"
380 : /* no outputs */
381 : "m" (*sc->sc_fpregs),
382 "m" (*sc->sc_fpcntl));
383 }
384 }
385
386 if (CPU_IS_COLDFIRE) {
387 __asm__ volatile ("frestore %0" : : "m" (*sc->sc_fpstate));
388 } else {
389 __asm__ volatile (".chip 68k/68881\n\t"
390 "frestore %0\n\t"
391 ".chip 68k"
392 : : "m" (*sc->sc_fpstate));
393 }
394 err = 0;
395
396out:
397 return err;
398}
399
400static inline int rt_restore_fpu_state(struct ucontext __user *uc)
401{
402 unsigned char fpstate[FPCONTEXT_SIZE];
403 int context_size = CPU_IS_060 ? 8 : (CPU_IS_COLDFIRE ? 12 : 0);
404 fpregset_t fpregs;
405 int err = 1;
406
407 if (FPU_IS_EMU) {
408 /* restore fpu control register */
409 if (__copy_from_user(current->thread.fpcntl,
410 uc->uc_mcontext.fpregs.f_fpcntl, 12))
411 goto out;
412 /* restore all other fpu register */
413 if (__copy_from_user(current->thread.fp,
414 uc->uc_mcontext.fpregs.f_fpregs, 96))
415 goto out;
416 return 0;
417 }
418
419 if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate))
420 goto out;
421 if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
422 if (!(CPU_IS_060 || CPU_IS_COLDFIRE))
423 context_size = fpstate[1];
424 /* Verify the frame format. */
425 if (!(CPU_IS_060 || CPU_IS_COLDFIRE) &&
426 (fpstate[0] != fpu_version))
427 goto out;
428 if (CPU_IS_020_OR_030) {
429 if (m68k_fputype & FPU_68881 &&
430 !(context_size == 0x18 || context_size == 0xb4))
431 goto out;
432 if (m68k_fputype & FPU_68882 &&
433 !(context_size == 0x38 || context_size == 0xd4))
434 goto out;
435 } else if (CPU_IS_040) {
436 if (!(context_size == 0x00 ||
437 context_size == 0x28 ||
438 context_size == 0x60))
439 goto out;
440 } else if (CPU_IS_060) {
441 if (!(fpstate[3] == 0x00 ||
442 fpstate[3] == 0x60 ||
443 fpstate[3] == 0xe0))
444 goto out;
445 } else if (CPU_IS_COLDFIRE) {
446 if (!(fpstate[3] == 0x00 ||
447 fpstate[3] == 0x05 ||
448 fpstate[3] == 0xe5))
449 goto out;
450 } else
451 goto out;
452 if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs,
453 sizeof(fpregs)))
454 goto out;
455
456 if (CPU_IS_COLDFIRE) {
457 __asm__ volatile ("fmovemd %0,%%fp0-%%fp7\n\t"
458 "fmovel %1,%%fpcr\n\t"
459 "fmovel %2,%%fpsr\n\t"
460 "fmovel %3,%%fpiar"
461 : /* no outputs */
462 : "m" (fpregs.f_fpregs[0]),
463 "m" (fpregs.f_fpcntl[0]),
464 "m" (fpregs.f_fpcntl[1]),
465 "m" (fpregs.f_fpcntl[2]));
466 } else {
467 __asm__ volatile (".chip 68k/68881\n\t"
468 "fmovemx %0,%%fp0-%%fp7\n\t"
469 "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
470 ".chip 68k"
471 : /* no outputs */
472 : "m" (*fpregs.f_fpregs),
473 "m" (*fpregs.f_fpcntl));
474 }
475 }
476 if (context_size &&
477 __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1,
478 context_size))
479 goto out;
480
481 if (CPU_IS_COLDFIRE) {
482 __asm__ volatile ("frestore %0" : : "m" (*fpstate));
483 } else {
484 __asm__ volatile (".chip 68k/68881\n\t"
485 "frestore %0\n\t"
486 ".chip 68k"
487 : : "m" (*fpstate));
488 }
489 err = 0;
490
491out:
492 return err;
493}
494
495/*
496 * Set up a signal frame.
497 */
498static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
499{
500 if (FPU_IS_EMU) {
501 /* save registers */
502 memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12);
503 memcpy(sc->sc_fpregs, current->thread.fp, 24);
504 return;
505 }
506
507 if (CPU_IS_COLDFIRE) {
508 __asm__ volatile ("fsave %0"
509 : : "m" (*sc->sc_fpstate) : "memory");
510 } else {
511 __asm__ volatile (".chip 68k/68881\n\t"
512 "fsave %0\n\t"
513 ".chip 68k"
514 : : "m" (*sc->sc_fpstate) : "memory");
515 }
516
517 if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
518 fpu_version = sc->sc_fpstate[0];
519 if (CPU_IS_020_OR_030 &&
520 regs->vector >= (VEC_FPBRUC * 4) &&
521 regs->vector <= (VEC_FPNAN * 4)) {
522 /* Clear pending exception in 68882 idle frame */
523 if (*(unsigned short *) sc->sc_fpstate == 0x1f38)
524 sc->sc_fpstate[0x38] |= 1 << 3;
525 }
526
527 if (CPU_IS_COLDFIRE) {
528 __asm__ volatile ("fmovemd %%fp0-%%fp1,%0\n\t"
529 "fmovel %%fpcr,%1\n\t"
530 "fmovel %%fpsr,%2\n\t"
531 "fmovel %%fpiar,%3"
532 : "=m" (sc->sc_fpregs[0]),
533 "=m" (sc->sc_fpcntl[0]),
534 "=m" (sc->sc_fpcntl[1]),
535 "=m" (sc->sc_fpcntl[2])
536 : /* no inputs */
537 : "memory");
538 } else {
539 __asm__ volatile (".chip 68k/68881\n\t"
540 "fmovemx %%fp0-%%fp1,%0\n\t"
541 "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
542 ".chip 68k"
543 : "=m" (*sc->sc_fpregs),
544 "=m" (*sc->sc_fpcntl)
545 : /* no inputs */
546 : "memory");
547 }
548 }
549}
550
551static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs)
552{
553 unsigned char fpstate[FPCONTEXT_SIZE];
554 int context_size = CPU_IS_060 ? 8 : (CPU_IS_COLDFIRE ? 12 : 0);
555 int err = 0;
556
557 if (FPU_IS_EMU) {
558 /* save fpu control register */
559 err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpcntl,
560 current->thread.fpcntl, 12);
561 /* save all other fpu register */
562 err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs,
563 current->thread.fp, 96);
564 return err;
565 }
566
567 if (CPU_IS_COLDFIRE) {
568 __asm__ volatile ("fsave %0" : : "m" (*fpstate) : "memory");
569 } else {
570 __asm__ volatile (".chip 68k/68881\n\t"
571 "fsave %0\n\t"
572 ".chip 68k"
573 : : "m" (*fpstate) : "memory");
574 }
575
576 err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate);
577 if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
578 fpregset_t fpregs;
579 if (!(CPU_IS_060 || CPU_IS_COLDFIRE))
580 context_size = fpstate[1];
581 fpu_version = fpstate[0];
582 if (CPU_IS_020_OR_030 &&
583 regs->vector >= (VEC_FPBRUC * 4) &&
584 regs->vector <= (VEC_FPNAN * 4)) {
585 /* Clear pending exception in 68882 idle frame */
586 if (*(unsigned short *) fpstate == 0x1f38)
587 fpstate[0x38] |= 1 << 3;
588 }
589 if (CPU_IS_COLDFIRE) {
590 __asm__ volatile ("fmovemd %%fp0-%%fp7,%0\n\t"
591 "fmovel %%fpcr,%1\n\t"
592 "fmovel %%fpsr,%2\n\t"
593 "fmovel %%fpiar,%3"
594 : "=m" (fpregs.f_fpregs[0]),
595 "=m" (fpregs.f_fpcntl[0]),
596 "=m" (fpregs.f_fpcntl[1]),
597 "=m" (fpregs.f_fpcntl[2])
598 : /* no inputs */
599 : "memory");
600 } else {
601 __asm__ volatile (".chip 68k/68881\n\t"
602 "fmovemx %%fp0-%%fp7,%0\n\t"
603 "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
604 ".chip 68k"
605 : "=m" (*fpregs.f_fpregs),
606 "=m" (*fpregs.f_fpcntl)
607 : /* no inputs */
608 : "memory");
609 }
610 err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs,
611 sizeof(fpregs));
612 }
613 if (context_size)
614 err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4,
615 context_size);
616 return err;
617}
618
619#else /* CONFIG_FPU */
620
621/*
622 * For the case with no FPU configured these all do nothing.
623 */
624static inline int restore_fpu_state(struct sigcontext *sc)
625{
626 return 0;
627}
628
629static inline int rt_restore_fpu_state(struct ucontext __user *uc)
630{
631 return 0;
632}
633
634static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
635{
636}
637
638static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs)
639{
640 return 0;
641}
642
643#endif /* CONFIG_FPU */
644
645static int mangle_kernel_stack(struct pt_regs *regs, int formatvec,
646 void __user *fp)
647{
648 int fsize = frame_extra_sizes(formatvec >> 12);
649 if (fsize < 0) {
650 /*
651 * user process trying to return with weird frame format
652 */
653#ifdef DEBUG
654 printk("user process returning with weird frame format\n");
655#endif
656 return 1;
657 }
658 if (!fsize) {
659 regs->format = formatvec >> 12;
660 regs->vector = formatvec & 0xfff;
661 } else {
662 struct switch_stack *sw = (struct switch_stack *)regs - 1;
663 unsigned long buf[fsize / 2]; /* yes, twice as much */
664
665 /* that'll make sure that expansion won't crap over data */
666 if (copy_from_user(buf + fsize / 4, fp, fsize))
667 return 1;
668
669 /* point of no return */
670 regs->format = formatvec >> 12;
671 regs->vector = formatvec & 0xfff;
672#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack))
673 __asm__ __volatile__ (
674#ifdef CONFIG_COLDFIRE
675 " movel %0,%/sp\n\t"
676 " bra ret_from_signal\n"
677#else
678 " movel %0,%/a0\n\t"
679 " subl %1,%/a0\n\t" /* make room on stack */
680 " movel %/a0,%/sp\n\t" /* set stack pointer */
681 /* move switch_stack and pt_regs */
682 "1: movel %0@+,%/a0@+\n\t"
683 " dbra %2,1b\n\t"
684 " lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */
685 " lsrl #2,%1\n\t"
686 " subql #1,%1\n\t"
687 /* copy to the gap we'd made */
688 "2: movel %4@+,%/a0@+\n\t"
689 " dbra %1,2b\n\t"
690 " bral ret_from_signal\n"
691#endif
692 : /* no outputs, it doesn't ever return */
693 : "a" (sw), "d" (fsize), "d" (frame_offset/4-1),
694 "n" (frame_offset), "a" (buf + fsize/4)
695 : "a0");
696#undef frame_offset
697 }
698 return 0;
699}
700
701static inline int
702restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp)
703{
704 int formatvec;
705 struct sigcontext context;
706 int err = 0;
707
708 /* Always make any pending restarted system calls return -EINTR */
709 current_thread_info()->restart_block.fn = do_no_restart_syscall;
710
711 /* get previous context */
712 if (copy_from_user(&context, usc, sizeof(context)))
713 goto badframe;
714
715 /* restore passed registers */
716 regs->d0 = context.sc_d0;
717 regs->d1 = context.sc_d1;
718 regs->a0 = context.sc_a0;
719 regs->a1 = context.sc_a1;
720 regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff);
721 regs->pc = context.sc_pc;
722 regs->orig_d0 = -1; /* disable syscall checks */
723 wrusp(context.sc_usp);
724 formatvec = context.sc_formatvec;
725
726 err = restore_fpu_state(&context);
727
728 if (err || mangle_kernel_stack(regs, formatvec, fp))
729 goto badframe;
730
731 return 0;
732
733badframe:
734 return 1;
735}
736
737static inline int
738rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
739 struct ucontext __user *uc)
740{
741 int temp;
742 greg_t __user *gregs = uc->uc_mcontext.gregs;
743 unsigned long usp;
744 int err;
745
746 /* Always make any pending restarted system calls return -EINTR */
747 current_thread_info()->restart_block.fn = do_no_restart_syscall;
748
749 err = __get_user(temp, &uc->uc_mcontext.version);
750 if (temp != MCONTEXT_VERSION)
751 goto badframe;
752 /* restore passed registers */
753 err |= __get_user(regs->d0, &gregs[0]);
754 err |= __get_user(regs->d1, &gregs[1]);
755 err |= __get_user(regs->d2, &gregs[2]);
756 err |= __get_user(regs->d3, &gregs[3]);
757 err |= __get_user(regs->d4, &gregs[4]);
758 err |= __get_user(regs->d5, &gregs[5]);
759 err |= __get_user(sw->d6, &gregs[6]);
760 err |= __get_user(sw->d7, &gregs[7]);
761 err |= __get_user(regs->a0, &gregs[8]);
762 err |= __get_user(regs->a1, &gregs[9]);
763 err |= __get_user(regs->a2, &gregs[10]);
764 err |= __get_user(sw->a3, &gregs[11]);
765 err |= __get_user(sw->a4, &gregs[12]);
766 err |= __get_user(sw->a5, &gregs[13]);
767 err |= __get_user(sw->a6, &gregs[14]);
768 err |= __get_user(usp, &gregs[15]);
769 wrusp(usp);
770 err |= __get_user(regs->pc, &gregs[16]);
771 err |= __get_user(temp, &gregs[17]);
772 regs->sr = (regs->sr & 0xff00) | (temp & 0xff);
773 regs->orig_d0 = -1; /* disable syscall checks */
774 err |= __get_user(temp, &uc->uc_formatvec);
775
776 err |= rt_restore_fpu_state(uc);
777
778 if (err || do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT)
779 goto badframe;
780
781 if (mangle_kernel_stack(regs, temp, &uc->uc_extra))
782 goto badframe;
783
784 return 0;
785
786badframe:
787 return 1;
788}
789
790asmlinkage int do_sigreturn(unsigned long __unused)
791{
792 struct switch_stack *sw = (struct switch_stack *) &__unused;
793 struct pt_regs *regs = (struct pt_regs *) (sw + 1);
794 unsigned long usp = rdusp();
795 struct sigframe __user *frame = (struct sigframe __user *)(usp - 4);
796 sigset_t set;
797
798 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
799 goto badframe;
800 if (__get_user(set.sig[0], &frame->sc.sc_mask) ||
801 (_NSIG_WORDS > 1 &&
802 __copy_from_user(&set.sig[1], &frame->extramask,
803 sizeof(frame->extramask))))
804 goto badframe;
805
806 sigdelsetmask(&set, ~_BLOCKABLE);
807 current->blocked = set;
808 recalc_sigpending();
809
810 if (restore_sigcontext(regs, &frame->sc, frame + 1))
811 goto badframe;
812 return regs->d0;
813
814badframe:
815 force_sig(SIGSEGV, current);
816 return 0;
817}
818
819asmlinkage int do_rt_sigreturn(unsigned long __unused)
820{
821 struct switch_stack *sw = (struct switch_stack *) &__unused;
822 struct pt_regs *regs = (struct pt_regs *) (sw + 1);
823 unsigned long usp = rdusp();
824 struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4);
825 sigset_t set;
826
827 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
828 goto badframe;
829 if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
830 goto badframe;
831
832 sigdelsetmask(&set, ~_BLOCKABLE);
833 current->blocked = set;
834 recalc_sigpending();
835
836 if (rt_restore_ucontext(regs, sw, &frame->uc))
837 goto badframe;
838 return regs->d0;
839
840badframe:
841 force_sig(SIGSEGV, current);
842 return 0;
843}
844
845static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
846 unsigned long mask)
847{
848 sc->sc_mask = mask;
849 sc->sc_usp = rdusp();
850 sc->sc_d0 = regs->d0;
851 sc->sc_d1 = regs->d1;
852 sc->sc_a0 = regs->a0;
853 sc->sc_a1 = regs->a1;
854 sc->sc_sr = regs->sr;
855 sc->sc_pc = regs->pc;
856 sc->sc_formatvec = regs->format << 12 | regs->vector;
857 save_a5_state(sc, regs);
858 save_fpu_state(sc, regs);
859}
860
861static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs)
862{
863 struct switch_stack *sw = (struct switch_stack *)regs - 1;
864 greg_t __user *gregs = uc->uc_mcontext.gregs;
865 int err = 0;
866
867 err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
868 err |= __put_user(regs->d0, &gregs[0]);
869 err |= __put_user(regs->d1, &gregs[1]);
870 err |= __put_user(regs->d2, &gregs[2]);
871 err |= __put_user(regs->d3, &gregs[3]);
872 err |= __put_user(regs->d4, &gregs[4]);
873 err |= __put_user(regs->d5, &gregs[5]);
874 err |= __put_user(sw->d6, &gregs[6]);
875 err |= __put_user(sw->d7, &gregs[7]);
876 err |= __put_user(regs->a0, &gregs[8]);
877 err |= __put_user(regs->a1, &gregs[9]);
878 err |= __put_user(regs->a2, &gregs[10]);
879 err |= __put_user(sw->a3, &gregs[11]);
880 err |= __put_user(sw->a4, &gregs[12]);
881 err |= __put_user(sw->a5, &gregs[13]);
882 err |= __put_user(sw->a6, &gregs[14]);
883 err |= __put_user(rdusp(), &gregs[15]);
884 err |= __put_user(regs->pc, &gregs[16]);
885 err |= __put_user(regs->sr, &gregs[17]);
886 err |= __put_user((regs->format << 12) | regs->vector, &uc->uc_formatvec);
887 err |= rt_save_fpu_state(uc, regs);
888 return err;
889}
890
891static inline void __user *
892get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
893{
894 unsigned long usp;
895
896 /* Default to using normal stack. */
897 usp = rdusp();
898
899 /* This is the X/Open sanctioned signal stack switching. */
900 if (ka->sa.sa_flags & SA_ONSTACK) {
901 if (!sas_ss_flags(usp))
902 usp = current->sas_ss_sp + current->sas_ss_size;
903 }
904 return (void __user *)((usp - frame_size) & -8UL);
905}
906
907static int setup_frame (int sig, struct k_sigaction *ka,
908 sigset_t *set, struct pt_regs *regs)
909{
910 struct sigframe __user *frame;
911 int fsize = frame_extra_sizes(regs->format);
912 struct sigcontext context;
913 int err = 0;
914
915 if (fsize < 0) {
916#ifdef DEBUG
917 printk ("setup_frame: Unknown frame format %#x\n",
918 regs->format);
919#endif
920 goto give_sigsegv;
921 }
922
923 frame = get_sigframe(ka, regs, sizeof(*frame) + fsize);
924
925 if (fsize)
926 err |= copy_to_user (frame + 1, regs + 1, fsize);
927
928 err |= __put_user((current_thread_info()->exec_domain
929 && current_thread_info()->exec_domain->signal_invmap
930 && sig < 32
931 ? current_thread_info()->exec_domain->signal_invmap[sig]
932 : sig),
933 &frame->sig);
934
935 err |= __put_user(regs->vector, &frame->code);
936 err |= __put_user(&frame->sc, &frame->psc);
937
938 if (_NSIG_WORDS > 1)
939 err |= copy_to_user(frame->extramask, &set->sig[1],
940 sizeof(frame->extramask));
941
942 setup_sigcontext(&context, regs, set->sig[0]);
943 err |= copy_to_user (&frame->sc, &context, sizeof(context));
944
945 /* Set up to return from userspace. */
946#ifdef CONFIG_MMU
947 err |= __put_user(frame->retcode, &frame->pretcode);
948 /* moveq #,d0; trap #0 */
949 err |= __put_user(0x70004e40 + (__NR_sigreturn << 16),
950 (long __user *)(frame->retcode));
951#else
952 err |= __put_user((void *) ret_from_user_signal, &frame->pretcode);
953#endif
954
955 if (err)
956 goto give_sigsegv;
957
958 push_cache ((unsigned long) &frame->retcode);
959
960 /*
961 * Set up registers for signal handler. All the state we are about
962 * to destroy is successfully copied to sigframe.
963 */
964 wrusp ((unsigned long) frame);
965 regs->pc = (unsigned long) ka->sa.sa_handler;
966 adjustformat(regs);
967
968 /*
969 * This is subtle; if we build more than one sigframe, all but the
970 * first one will see frame format 0 and have fsize == 0, so we won't
971 * screw stkadj.
972 */
973 if (fsize)
974 regs->stkadj = fsize;
975
976 /* Prepare to skip over the extra stuff in the exception frame. */
977 if (regs->stkadj) {
978 struct pt_regs *tregs =
979 (struct pt_regs *)((ulong)regs + regs->stkadj);
980#ifdef DEBUG
981 printk("Performing stackadjust=%04x\n", regs->stkadj);
982#endif
983 /* This must be copied with decreasing addresses to
984 handle overlaps. */
985 tregs->vector = 0;
986 tregs->format = 0;
987 tregs->pc = regs->pc;
988 tregs->sr = regs->sr;
989 }
990 return 0;
991
992give_sigsegv:
993 force_sigsegv(sig, current);
994 return err;
995}
996
997static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
998 sigset_t *set, struct pt_regs *regs)
999{
1000 struct rt_sigframe __user *frame;
1001 int fsize = frame_extra_sizes(regs->format);
1002 int err = 0;
1003
1004 if (fsize < 0) {
1005#ifdef DEBUG
1006 printk ("setup_frame: Unknown frame format %#x\n",
1007 regs->format);
1008#endif
1009 goto give_sigsegv;
1010 }
1011
1012 frame = get_sigframe(ka, regs, sizeof(*frame));
1013
1014 if (fsize)
1015 err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize);
1016
1017 err |= __put_user((current_thread_info()->exec_domain
1018 && current_thread_info()->exec_domain->signal_invmap
1019 && sig < 32
1020 ? current_thread_info()->exec_domain->signal_invmap[sig]
1021 : sig),
1022 &frame->sig);
1023 err |= __put_user(&frame->info, &frame->pinfo);
1024 err |= __put_user(&frame->uc, &frame->puc);
1025 err |= copy_siginfo_to_user(&frame->info, info);
1026
1027 /* Create the ucontext. */
1028 err |= __put_user(0, &frame->uc.uc_flags);
1029 err |= __put_user(NULL, &frame->uc.uc_link);
1030 err |= __put_user((void __user *)current->sas_ss_sp,
1031 &frame->uc.uc_stack.ss_sp);
1032 err |= __put_user(sas_ss_flags(rdusp()),
1033 &frame->uc.uc_stack.ss_flags);
1034 err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
1035 err |= rt_setup_ucontext(&frame->uc, regs);
1036 err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set));
1037
1038 /* Set up to return from userspace. */
1039#ifdef CONFIG_MMU
1040 err |= __put_user(frame->retcode, &frame->pretcode);
1041#ifdef __mcoldfire__
1042 /* movel #__NR_rt_sigreturn,d0; trap #0 */
1043 err |= __put_user(0x203c0000, (long __user *)(frame->retcode + 0));
1044 err |= __put_user(0x00004e40 + (__NR_rt_sigreturn << 16),
1045 (long __user *)(frame->retcode + 4));
1046#else
1047 /* moveq #,d0; notb d0; trap #0 */
1048 err |= __put_user(0x70004600 + ((__NR_rt_sigreturn ^ 0xff) << 16),
1049 (long __user *)(frame->retcode + 0));
1050 err |= __put_user(0x4e40, (short __user *)(frame->retcode + 4));
1051#endif
1052#else
1053 err |= __put_user((void *) ret_from_user_rt_signal, &frame->pretcode);
1054#endif /* CONFIG_MMU */
1055
1056 if (err)
1057 goto give_sigsegv;
1058
1059 push_cache ((unsigned long) &frame->retcode);
1060
1061 /*
1062 * Set up registers for signal handler. All the state we are about
1063 * to destroy is successfully copied to sigframe.
1064 */
1065 wrusp ((unsigned long) frame);
1066 regs->pc = (unsigned long) ka->sa.sa_handler;
1067 adjustformat(regs);
1068
1069 /*
1070 * This is subtle; if we build more than one sigframe, all but the
1071 * first one will see frame format 0 and have fsize == 0, so we won't
1072 * screw stkadj.
1073 */
1074 if (fsize)
1075 regs->stkadj = fsize;
1076
1077 /* Prepare to skip over the extra stuff in the exception frame. */
1078 if (regs->stkadj) {
1079 struct pt_regs *tregs =
1080 (struct pt_regs *)((ulong)regs + regs->stkadj);
1081#ifdef DEBUG
1082 printk("Performing stackadjust=%04x\n", regs->stkadj);
1083#endif
1084 /* This must be copied with decreasing addresses to
1085 handle overlaps. */
1086 tregs->vector = 0;
1087 tregs->format = 0;
1088 tregs->pc = regs->pc;
1089 tregs->sr = regs->sr;
1090 }
1091 return 0;
1092
1093give_sigsegv:
1094 force_sigsegv(sig, current);
1095 return err;
1096}
1097
1098static inline void
1099handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
1100{
1101 switch (regs->d0) {
1102 case -ERESTARTNOHAND:
1103 if (!has_handler)
1104 goto do_restart;
1105 regs->d0 = -EINTR;
1106 break;
1107
1108 case -ERESTART_RESTARTBLOCK:
1109 if (!has_handler) {
1110 regs->d0 = __NR_restart_syscall;
1111 regs->pc -= 2;
1112 break;
1113 }
1114 regs->d0 = -EINTR;
1115 break;
1116
1117 case -ERESTARTSYS:
1118 if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
1119 regs->d0 = -EINTR;
1120 break;
1121 }
1122 /* fallthrough */
1123 case -ERESTARTNOINTR:
1124 do_restart:
1125 regs->d0 = regs->orig_d0;
1126 regs->pc -= 2;
1127 break;
1128 }
1129}
1130
1131/*
1132 * OK, we're invoking a handler
1133 */
1134static void
1135handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
1136 sigset_t *oldset, struct pt_regs *regs)
1137{
1138 int err;
1139 /* are we from a system call? */
1140 if (regs->orig_d0 >= 0)
1141 /* If so, check system call restarting.. */
1142 handle_restart(regs, ka, 1);
1143
1144 /* set up the stack frame */
1145 if (ka->sa.sa_flags & SA_SIGINFO)
1146 err = setup_rt_frame(sig, ka, info, oldset, regs);
1147 else
1148 err = setup_frame(sig, ka, oldset, regs);
1149
1150 if (err)
1151 return;
1152
1153 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
1154 if (!(ka->sa.sa_flags & SA_NODEFER))
1155 sigaddset(&current->blocked,sig);
1156 recalc_sigpending();
1157
1158 if (test_thread_flag(TIF_DELAYED_TRACE)) {
1159 regs->sr &= ~0x8000;
1160 send_sig(SIGTRAP, current, 1);
1161 }
1162
1163 clear_thread_flag(TIF_RESTORE_SIGMASK);
1164}
1165
1166/*
1167 * Note that 'init' is a special process: it doesn't get signals it doesn't
1168 * want to handle. Thus you cannot kill init even with a SIGKILL even by
1169 * mistake.
1170 */
1171asmlinkage void do_signal(struct pt_regs *regs)
1172{
1173 siginfo_t info;
1174 struct k_sigaction ka;
1175 int signr;
1176 sigset_t *oldset;
1177
1178 current->thread.esp0 = (unsigned long) regs;
1179
1180 if (test_thread_flag(TIF_RESTORE_SIGMASK))
1181 oldset = &current->saved_sigmask;
1182 else
1183 oldset = &current->blocked;
1184
1185 signr = get_signal_to_deliver(&info, &ka, regs, NULL);
1186 if (signr > 0) {
1187 /* Whee! Actually deliver the signal. */
1188 handle_signal(signr, &ka, &info, oldset, regs);
1189 return;
1190 }
1191
1192 /* Did we come from a system call? */
1193 if (regs->orig_d0 >= 0)
1194 /* Restart the system call - no handlers present */
1195 handle_restart(regs, NULL, 0);
1196
1197 /* If there's no signal to deliver, we just restore the saved mask. */
1198 if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
1199 clear_thread_flag(TIF_RESTORE_SIGMASK);
1200 sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
1201 }
1202}
diff --git a/arch/m68k/kernel/signal_mm.c b/arch/m68k/kernel/signal_mm.c
deleted file mode 100644
index cb856f9da65..00000000000
--- a/arch/m68k/kernel/signal_mm.c
+++ /dev/null
@@ -1,1115 +0,0 @@
1/*
2 * linux/arch/m68k/kernel/signal.c
3 *
4 * Copyright (C) 1991, 1992 Linus Torvalds
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11/*
12 * Linux/m68k support by Hamish Macdonald
13 *
14 * 68060 fixes by Jesper Skov
15 *
16 * 1997-12-01 Modified for POSIX.1b signals by Andreas Schwab
17 *
18 * mathemu support by Roman Zippel
19 * (Note: fpstate in the signal context is completely ignored for the emulator
20 * and the internal floating point format is put on stack)
21 */
22
23/*
24 * ++roman (07/09/96): implemented signal stacks (specially for tosemu on
25 * Atari :-) Current limitation: Only one sigstack can be active at one time.
26 * If a second signal with SA_ONSTACK set arrives while working on a sigstack,
27 * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested
28 * signal handlers!
29 */
30
31#include <linux/sched.h>
32#include <linux/mm.h>
33#include <linux/kernel.h>
34#include <linux/signal.h>
35#include <linux/syscalls.h>
36#include <linux/errno.h>
37#include <linux/wait.h>
38#include <linux/ptrace.h>
39#include <linux/unistd.h>
40#include <linux/stddef.h>
41#include <linux/highuid.h>
42#include <linux/personality.h>
43#include <linux/tty.h>
44#include <linux/binfmts.h>
45#include <linux/module.h>
46
47#include <asm/setup.h>
48#include <asm/uaccess.h>
49#include <asm/pgtable.h>
50#include <asm/traps.h>
51#include <asm/ucontext.h>
52
53#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
54
55static const int frame_extra_sizes[16] = {
56 [1] = -1, /* sizeof(((struct frame *)0)->un.fmt1), */
57 [2] = sizeof(((struct frame *)0)->un.fmt2),
58 [3] = sizeof(((struct frame *)0)->un.fmt3),
59#ifdef CONFIG_COLDFIRE
60 [4] = 0,
61#else
62 [4] = sizeof(((struct frame *)0)->un.fmt4),
63#endif
64 [5] = -1, /* sizeof(((struct frame *)0)->un.fmt5), */
65 [6] = -1, /* sizeof(((struct frame *)0)->un.fmt6), */
66 [7] = sizeof(((struct frame *)0)->un.fmt7),
67 [8] = -1, /* sizeof(((struct frame *)0)->un.fmt8), */
68 [9] = sizeof(((struct frame *)0)->un.fmt9),
69 [10] = sizeof(((struct frame *)0)->un.fmta),
70 [11] = sizeof(((struct frame *)0)->un.fmtb),
71 [12] = -1, /* sizeof(((struct frame *)0)->un.fmtc), */
72 [13] = -1, /* sizeof(((struct frame *)0)->un.fmtd), */
73 [14] = -1, /* sizeof(((struct frame *)0)->un.fmte), */
74 [15] = -1, /* sizeof(((struct frame *)0)->un.fmtf), */
75};
76
77int handle_kernel_fault(struct pt_regs *regs)
78{
79 const struct exception_table_entry *fixup;
80 struct pt_regs *tregs;
81
82 /* Are we prepared to handle this kernel fault? */
83 fixup = search_exception_tables(regs->pc);
84 if (!fixup)
85 return 0;
86
87 /* Create a new four word stack frame, discarding the old one. */
88 regs->stkadj = frame_extra_sizes[regs->format];
89 tregs = (struct pt_regs *)((long)regs + regs->stkadj);
90 tregs->vector = regs->vector;
91#ifdef CONFIG_COLDFIRE
92 tregs->format = 4;
93#else
94 tregs->format = 0;
95#endif
96 tregs->pc = fixup->fixup;
97 tregs->sr = regs->sr;
98
99 return 1;
100}
101
102/*
103 * Atomically swap in the new signal mask, and wait for a signal.
104 */
105asmlinkage int
106sys_sigsuspend(int unused0, int unused1, old_sigset_t mask)
107{
108 mask &= _BLOCKABLE;
109 spin_lock_irq(&current->sighand->siglock);
110 current->saved_sigmask = current->blocked;
111 siginitset(&current->blocked, mask);
112 recalc_sigpending();
113 spin_unlock_irq(&current->sighand->siglock);
114
115 current->state = TASK_INTERRUPTIBLE;
116 schedule();
117 set_restore_sigmask();
118
119 return -ERESTARTNOHAND;
120}
121
122asmlinkage int
123sys_sigaction(int sig, const struct old_sigaction __user *act,
124 struct old_sigaction __user *oact)
125{
126 struct k_sigaction new_ka, old_ka;
127 int ret;
128
129 if (act) {
130 old_sigset_t mask;
131 if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
132 __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
133 __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
134 __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
135 __get_user(mask, &act->sa_mask))
136 return -EFAULT;
137 siginitset(&new_ka.sa.sa_mask, mask);
138 }
139
140 ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
141
142 if (!ret && oact) {
143 if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
144 __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
145 __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
146 __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
147 __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
148 return -EFAULT;
149 }
150
151 return ret;
152}
153
154asmlinkage int
155sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss)
156{
157 return do_sigaltstack(uss, uoss, rdusp());
158}
159
160
161/*
162 * Do a signal return; undo the signal stack.
163 *
164 * Keep the return code on the stack quadword aligned!
165 * That makes the cache flush below easier.
166 */
167
168struct sigframe
169{
170 char __user *pretcode;
171 int sig;
172 int code;
173 struct sigcontext __user *psc;
174 char retcode[8];
175 unsigned long extramask[_NSIG_WORDS-1];
176 struct sigcontext sc;
177};
178
179struct rt_sigframe
180{
181 char __user *pretcode;
182 int sig;
183 struct siginfo __user *pinfo;
184 void __user *puc;
185 char retcode[8];
186 struct siginfo info;
187 struct ucontext uc;
188};
189
190
191static unsigned char fpu_version; /* version number of fpu, set by setup_frame */
192
193static inline int restore_fpu_state(struct sigcontext *sc)
194{
195 int err = 1;
196
197 if (FPU_IS_EMU) {
198 /* restore registers */
199 memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12);
200 memcpy(current->thread.fp, sc->sc_fpregs, 24);
201 return 0;
202 }
203
204 if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
205 /* Verify the frame format. */
206 if (!(CPU_IS_060 || CPU_IS_COLDFIRE) &&
207 (sc->sc_fpstate[0] != fpu_version))
208 goto out;
209 if (CPU_IS_020_OR_030) {
210 if (m68k_fputype & FPU_68881 &&
211 !(sc->sc_fpstate[1] == 0x18 || sc->sc_fpstate[1] == 0xb4))
212 goto out;
213 if (m68k_fputype & FPU_68882 &&
214 !(sc->sc_fpstate[1] == 0x38 || sc->sc_fpstate[1] == 0xd4))
215 goto out;
216 } else if (CPU_IS_040) {
217 if (!(sc->sc_fpstate[1] == 0x00 ||
218 sc->sc_fpstate[1] == 0x28 ||
219 sc->sc_fpstate[1] == 0x60))
220 goto out;
221 } else if (CPU_IS_060) {
222 if (!(sc->sc_fpstate[3] == 0x00 ||
223 sc->sc_fpstate[3] == 0x60 ||
224 sc->sc_fpstate[3] == 0xe0))
225 goto out;
226 } else if (CPU_IS_COLDFIRE) {
227 if (!(sc->sc_fpstate[0] == 0x00 ||
228 sc->sc_fpstate[0] == 0x05 ||
229 sc->sc_fpstate[0] == 0xe5))
230 goto out;
231 } else
232 goto out;
233
234 if (CPU_IS_COLDFIRE) {
235 __asm__ volatile ("fmovemd %0,%%fp0-%%fp1\n\t"
236 "fmovel %1,%%fpcr\n\t"
237 "fmovel %2,%%fpsr\n\t"
238 "fmovel %3,%%fpiar"
239 : /* no outputs */
240 : "m" (sc->sc_fpregs[0]),
241 "m" (sc->sc_fpcntl[0]),
242 "m" (sc->sc_fpcntl[1]),
243 "m" (sc->sc_fpcntl[2]));
244 } else {
245 __asm__ volatile (".chip 68k/68881\n\t"
246 "fmovemx %0,%%fp0-%%fp1\n\t"
247 "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
248 ".chip 68k"
249 : /* no outputs */
250 : "m" (*sc->sc_fpregs),
251 "m" (*sc->sc_fpcntl));
252 }
253 }
254
255 if (CPU_IS_COLDFIRE) {
256 __asm__ volatile ("frestore %0" : : "m" (*sc->sc_fpstate));
257 } else {
258 __asm__ volatile (".chip 68k/68881\n\t"
259 "frestore %0\n\t"
260 ".chip 68k"
261 : : "m" (*sc->sc_fpstate));
262 }
263 err = 0;
264
265out:
266 return err;
267}
268
269#define FPCONTEXT_SIZE 216
270#define uc_fpstate uc_filler[0]
271#define uc_formatvec uc_filler[FPCONTEXT_SIZE/4]
272#define uc_extra uc_filler[FPCONTEXT_SIZE/4+1]
273
274static inline int rt_restore_fpu_state(struct ucontext __user *uc)
275{
276 unsigned char fpstate[FPCONTEXT_SIZE];
277 int context_size = CPU_IS_060 ? 8 : (CPU_IS_COLDFIRE ? 12 : 0);
278 fpregset_t fpregs;
279 int err = 1;
280
281 if (FPU_IS_EMU) {
282 /* restore fpu control register */
283 if (__copy_from_user(current->thread.fpcntl,
284 uc->uc_mcontext.fpregs.f_fpcntl, 12))
285 goto out;
286 /* restore all other fpu register */
287 if (__copy_from_user(current->thread.fp,
288 uc->uc_mcontext.fpregs.f_fpregs, 96))
289 goto out;
290 return 0;
291 }
292
293 if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate))
294 goto out;
295 if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
296 if (!(CPU_IS_060 || CPU_IS_COLDFIRE))
297 context_size = fpstate[1];
298 /* Verify the frame format. */
299 if (!(CPU_IS_060 || CPU_IS_COLDFIRE) &&
300 (fpstate[0] != fpu_version))
301 goto out;
302 if (CPU_IS_020_OR_030) {
303 if (m68k_fputype & FPU_68881 &&
304 !(context_size == 0x18 || context_size == 0xb4))
305 goto out;
306 if (m68k_fputype & FPU_68882 &&
307 !(context_size == 0x38 || context_size == 0xd4))
308 goto out;
309 } else if (CPU_IS_040) {
310 if (!(context_size == 0x00 ||
311 context_size == 0x28 ||
312 context_size == 0x60))
313 goto out;
314 } else if (CPU_IS_060) {
315 if (!(fpstate[3] == 0x00 ||
316 fpstate[3] == 0x60 ||
317 fpstate[3] == 0xe0))
318 goto out;
319 } else if (CPU_IS_COLDFIRE) {
320 if (!(fpstate[3] == 0x00 ||
321 fpstate[3] == 0x05 ||
322 fpstate[3] == 0xe5))
323 goto out;
324 } else
325 goto out;
326 if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs,
327 sizeof(fpregs)))
328 goto out;
329
330 if (CPU_IS_COLDFIRE) {
331 __asm__ volatile ("fmovemd %0,%%fp0-%%fp7\n\t"
332 "fmovel %1,%%fpcr\n\t"
333 "fmovel %2,%%fpsr\n\t"
334 "fmovel %3,%%fpiar"
335 : /* no outputs */
336 : "m" (fpregs.f_fpregs[0]),
337 "m" (fpregs.f_fpcntl[0]),
338 "m" (fpregs.f_fpcntl[1]),
339 "m" (fpregs.f_fpcntl[2]));
340 } else {
341 __asm__ volatile (".chip 68k/68881\n\t"
342 "fmovemx %0,%%fp0-%%fp7\n\t"
343 "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
344 ".chip 68k"
345 : /* no outputs */
346 : "m" (*fpregs.f_fpregs),
347 "m" (*fpregs.f_fpcntl));
348 }
349 }
350 if (context_size &&
351 __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1,
352 context_size))
353 goto out;
354
355 if (CPU_IS_COLDFIRE) {
356 __asm__ volatile ("frestore %0" : : "m" (*fpstate));
357 } else {
358 __asm__ volatile (".chip 68k/68881\n\t"
359 "frestore %0\n\t"
360 ".chip 68k"
361 : : "m" (*fpstate));
362 }
363 err = 0;
364
365out:
366 return err;
367}
368
369static int mangle_kernel_stack(struct pt_regs *regs, int formatvec,
370 void __user *fp)
371{
372 int fsize = frame_extra_sizes[formatvec >> 12];
373 if (fsize < 0) {
374 /*
375 * user process trying to return with weird frame format
376 */
377#ifdef DEBUG
378 printk("user process returning with weird frame format\n");
379#endif
380 return 1;
381 }
382 if (!fsize) {
383 regs->format = formatvec >> 12;
384 regs->vector = formatvec & 0xfff;
385 } else {
386 struct switch_stack *sw = (struct switch_stack *)regs - 1;
387 unsigned long buf[fsize / 2]; /* yes, twice as much */
388
389 /* that'll make sure that expansion won't crap over data */
390 if (copy_from_user(buf + fsize / 4, fp, fsize))
391 return 1;
392
393 /* point of no return */
394 regs->format = formatvec >> 12;
395 regs->vector = formatvec & 0xfff;
396#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack))
397 __asm__ __volatile__ (
398#ifdef CONFIG_COLDFIRE
399 " movel %0,%/sp\n\t"
400 " bra ret_from_signal\n"
401#else
402 " movel %0,%/a0\n\t"
403 " subl %1,%/a0\n\t" /* make room on stack */
404 " movel %/a0,%/sp\n\t" /* set stack pointer */
405 /* move switch_stack and pt_regs */
406 "1: movel %0@+,%/a0@+\n\t"
407 " dbra %2,1b\n\t"
408 " lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */
409 " lsrl #2,%1\n\t"
410 " subql #1,%1\n\t"
411 /* copy to the gap we'd made */
412 "2: movel %4@+,%/a0@+\n\t"
413 " dbra %1,2b\n\t"
414 " bral ret_from_signal\n"
415#endif
416 : /* no outputs, it doesn't ever return */
417 : "a" (sw), "d" (fsize), "d" (frame_offset/4-1),
418 "n" (frame_offset), "a" (buf + fsize/4)
419 : "a0");
420#undef frame_offset
421 }
422 return 0;
423}
424
425static inline int
426restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp)
427{
428 int formatvec;
429 struct sigcontext context;
430 int err;
431
432 /* Always make any pending restarted system calls return -EINTR */
433 current_thread_info()->restart_block.fn = do_no_restart_syscall;
434
435 /* get previous context */
436 if (copy_from_user(&context, usc, sizeof(context)))
437 goto badframe;
438
439 /* restore passed registers */
440 regs->d0 = context.sc_d0;
441 regs->d1 = context.sc_d1;
442 regs->a0 = context.sc_a0;
443 regs->a1 = context.sc_a1;
444 regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff);
445 regs->pc = context.sc_pc;
446 regs->orig_d0 = -1; /* disable syscall checks */
447 wrusp(context.sc_usp);
448 formatvec = context.sc_formatvec;
449
450 err = restore_fpu_state(&context);
451
452 if (err || mangle_kernel_stack(regs, formatvec, fp))
453 goto badframe;
454
455 return 0;
456
457badframe:
458 return 1;
459}
460
461static inline int
462rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
463 struct ucontext __user *uc)
464{
465 int temp;
466 greg_t __user *gregs = uc->uc_mcontext.gregs;
467 unsigned long usp;
468 int err;
469
470 /* Always make any pending restarted system calls return -EINTR */
471 current_thread_info()->restart_block.fn = do_no_restart_syscall;
472
473 err = __get_user(temp, &uc->uc_mcontext.version);
474 if (temp != MCONTEXT_VERSION)
475 goto badframe;
476 /* restore passed registers */
477 err |= __get_user(regs->d0, &gregs[0]);
478 err |= __get_user(regs->d1, &gregs[1]);
479 err |= __get_user(regs->d2, &gregs[2]);
480 err |= __get_user(regs->d3, &gregs[3]);
481 err |= __get_user(regs->d4, &gregs[4]);
482 err |= __get_user(regs->d5, &gregs[5]);
483 err |= __get_user(sw->d6, &gregs[6]);
484 err |= __get_user(sw->d7, &gregs[7]);
485 err |= __get_user(regs->a0, &gregs[8]);
486 err |= __get_user(regs->a1, &gregs[9]);
487 err |= __get_user(regs->a2, &gregs[10]);
488 err |= __get_user(sw->a3, &gregs[11]);
489 err |= __get_user(sw->a4, &gregs[12]);
490 err |= __get_user(sw->a5, &gregs[13]);
491 err |= __get_user(sw->a6, &gregs[14]);
492 err |= __get_user(usp, &gregs[15]);
493 wrusp(usp);
494 err |= __get_user(regs->pc, &gregs[16]);
495 err |= __get_user(temp, &gregs[17]);
496 regs->sr = (regs->sr & 0xff00) | (temp & 0xff);
497 regs->orig_d0 = -1; /* disable syscall checks */
498 err |= __get_user(temp, &uc->uc_formatvec);
499
500 err |= rt_restore_fpu_state(uc);
501
502 if (err || do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT)
503 goto badframe;
504
505 if (mangle_kernel_stack(regs, temp, &uc->uc_extra))
506 goto badframe;
507
508 return 0;
509
510badframe:
511 return 1;
512}
513
514asmlinkage int do_sigreturn(unsigned long __unused)
515{
516 struct switch_stack *sw = (struct switch_stack *) &__unused;
517 struct pt_regs *regs = (struct pt_regs *) (sw + 1);
518 unsigned long usp = rdusp();
519 struct sigframe __user *frame = (struct sigframe __user *)(usp - 4);
520 sigset_t set;
521
522 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
523 goto badframe;
524 if (__get_user(set.sig[0], &frame->sc.sc_mask) ||
525 (_NSIG_WORDS > 1 &&
526 __copy_from_user(&set.sig[1], &frame->extramask,
527 sizeof(frame->extramask))))
528 goto badframe;
529
530 sigdelsetmask(&set, ~_BLOCKABLE);
531 current->blocked = set;
532 recalc_sigpending();
533
534 if (restore_sigcontext(regs, &frame->sc, frame + 1))
535 goto badframe;
536 return regs->d0;
537
538badframe:
539 force_sig(SIGSEGV, current);
540 return 0;
541}
542
543asmlinkage int do_rt_sigreturn(unsigned long __unused)
544{
545 struct switch_stack *sw = (struct switch_stack *) &__unused;
546 struct pt_regs *regs = (struct pt_regs *) (sw + 1);
547 unsigned long usp = rdusp();
548 struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4);
549 sigset_t set;
550
551 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
552 goto badframe;
553 if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
554 goto badframe;
555
556 sigdelsetmask(&set, ~_BLOCKABLE);
557 current->blocked = set;
558 recalc_sigpending();
559
560 if (rt_restore_ucontext(regs, sw, &frame->uc))
561 goto badframe;
562 return regs->d0;
563
564badframe:
565 force_sig(SIGSEGV, current);
566 return 0;
567}
568
569/*
570 * Set up a signal frame.
571 */
572
573static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
574{
575 if (FPU_IS_EMU) {
576 /* save registers */
577 memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12);
578 memcpy(sc->sc_fpregs, current->thread.fp, 24);
579 return;
580 }
581
582 if (CPU_IS_COLDFIRE) {
583 __asm__ volatile ("fsave %0"
584 : : "m" (*sc->sc_fpstate) : "memory");
585 } else {
586 __asm__ volatile (".chip 68k/68881\n\t"
587 "fsave %0\n\t"
588 ".chip 68k"
589 : : "m" (*sc->sc_fpstate) : "memory");
590 }
591
592 if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
593 fpu_version = sc->sc_fpstate[0];
594 if (CPU_IS_020_OR_030 &&
595 regs->vector >= (VEC_FPBRUC * 4) &&
596 regs->vector <= (VEC_FPNAN * 4)) {
597 /* Clear pending exception in 68882 idle frame */
598 if (*(unsigned short *) sc->sc_fpstate == 0x1f38)
599 sc->sc_fpstate[0x38] |= 1 << 3;
600 }
601
602 if (CPU_IS_COLDFIRE) {
603 __asm__ volatile ("fmovemd %%fp0-%%fp1,%0\n\t"
604 "fmovel %%fpcr,%1\n\t"
605 "fmovel %%fpsr,%2\n\t"
606 "fmovel %%fpiar,%3"
607 : "=m" (sc->sc_fpregs[0]),
608 "=m" (sc->sc_fpcntl[0]),
609 "=m" (sc->sc_fpcntl[1]),
610 "=m" (sc->sc_fpcntl[2])
611 : /* no inputs */
612 : "memory");
613 } else {
614 __asm__ volatile (".chip 68k/68881\n\t"
615 "fmovemx %%fp0-%%fp1,%0\n\t"
616 "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
617 ".chip 68k"
618 : "=m" (*sc->sc_fpregs),
619 "=m" (*sc->sc_fpcntl)
620 : /* no inputs */
621 : "memory");
622 }
623 }
624}
625
626static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs)
627{
628 unsigned char fpstate[FPCONTEXT_SIZE];
629 int context_size = CPU_IS_060 ? 8 : (CPU_IS_COLDFIRE ? 12 : 0);
630 int err = 0;
631
632 if (FPU_IS_EMU) {
633 /* save fpu control register */
634 err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpcntl,
635 current->thread.fpcntl, 12);
636 /* save all other fpu register */
637 err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs,
638 current->thread.fp, 96);
639 return err;
640 }
641
642 if (CPU_IS_COLDFIRE) {
643 __asm__ volatile ("fsave %0" : : "m" (*fpstate) : "memory");
644 } else {
645 __asm__ volatile (".chip 68k/68881\n\t"
646 "fsave %0\n\t"
647 ".chip 68k"
648 : : "m" (*fpstate) : "memory");
649 }
650
651 err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate);
652 if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
653 fpregset_t fpregs;
654 if (!(CPU_IS_060 || CPU_IS_COLDFIRE))
655 context_size = fpstate[1];
656 fpu_version = fpstate[0];
657 if (CPU_IS_020_OR_030 &&
658 regs->vector >= (VEC_FPBRUC * 4) &&
659 regs->vector <= (VEC_FPNAN * 4)) {
660 /* Clear pending exception in 68882 idle frame */
661 if (*(unsigned short *) fpstate == 0x1f38)
662 fpstate[0x38] |= 1 << 3;
663 }
664 if (CPU_IS_COLDFIRE) {
665 __asm__ volatile ("fmovemd %%fp0-%%fp7,%0\n\t"
666 "fmovel %%fpcr,%1\n\t"
667 "fmovel %%fpsr,%2\n\t"
668 "fmovel %%fpiar,%3"
669 : "=m" (fpregs.f_fpregs[0]),
670 "=m" (fpregs.f_fpcntl[0]),
671 "=m" (fpregs.f_fpcntl[1]),
672 "=m" (fpregs.f_fpcntl[2])
673 : /* no inputs */
674 : "memory");
675 } else {
676 __asm__ volatile (".chip 68k/68881\n\t"
677 "fmovemx %%fp0-%%fp7,%0\n\t"
678 "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
679 ".chip 68k"
680 : "=m" (*fpregs.f_fpregs),
681 "=m" (*fpregs.f_fpcntl)
682 : /* no inputs */
683 : "memory");
684 }
685 err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs,
686 sizeof(fpregs));
687 }
688 if (context_size)
689 err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4,
690 context_size);
691 return err;
692}
693
694static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
695 unsigned long mask)
696{
697 sc->sc_mask = mask;
698 sc->sc_usp = rdusp();
699 sc->sc_d0 = regs->d0;
700 sc->sc_d1 = regs->d1;
701 sc->sc_a0 = regs->a0;
702 sc->sc_a1 = regs->a1;
703 sc->sc_sr = regs->sr;
704 sc->sc_pc = regs->pc;
705 sc->sc_formatvec = regs->format << 12 | regs->vector;
706 save_fpu_state(sc, regs);
707}
708
709static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs)
710{
711 struct switch_stack *sw = (struct switch_stack *)regs - 1;
712 greg_t __user *gregs = uc->uc_mcontext.gregs;
713 int err = 0;
714
715 err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
716 err |= __put_user(regs->d0, &gregs[0]);
717 err |= __put_user(regs->d1, &gregs[1]);
718 err |= __put_user(regs->d2, &gregs[2]);
719 err |= __put_user(regs->d3, &gregs[3]);
720 err |= __put_user(regs->d4, &gregs[4]);
721 err |= __put_user(regs->d5, &gregs[5]);
722 err |= __put_user(sw->d6, &gregs[6]);
723 err |= __put_user(sw->d7, &gregs[7]);
724 err |= __put_user(regs->a0, &gregs[8]);
725 err |= __put_user(regs->a1, &gregs[9]);
726 err |= __put_user(regs->a2, &gregs[10]);
727 err |= __put_user(sw->a3, &gregs[11]);
728 err |= __put_user(sw->a4, &gregs[12]);
729 err |= __put_user(sw->a5, &gregs[13]);
730 err |= __put_user(sw->a6, &gregs[14]);
731 err |= __put_user(rdusp(), &gregs[15]);
732 err |= __put_user(regs->pc, &gregs[16]);
733 err |= __put_user(regs->sr, &gregs[17]);
734 err |= __put_user((regs->format << 12) | regs->vector, &uc->uc_formatvec);
735 err |= rt_save_fpu_state(uc, regs);
736 return err;
737}
738
739static inline void push_cache (unsigned long vaddr)
740{
741 /*
742 * Using the old cache_push_v() was really a big waste.
743 *
744 * What we are trying to do is to flush 8 bytes to ram.
745 * Flushing 2 cache lines of 16 bytes is much cheaper than
746 * flushing 1 or 2 pages, as previously done in
747 * cache_push_v().
748 * Jes
749 */
750 if (CPU_IS_040) {
751 unsigned long temp;
752
753 __asm__ __volatile__ (".chip 68040\n\t"
754 "nop\n\t"
755 "ptestr (%1)\n\t"
756 "movec %%mmusr,%0\n\t"
757 ".chip 68k"
758 : "=r" (temp)
759 : "a" (vaddr));
760
761 temp &= PAGE_MASK;
762 temp |= vaddr & ~PAGE_MASK;
763
764 __asm__ __volatile__ (".chip 68040\n\t"
765 "nop\n\t"
766 "cpushl %%bc,(%0)\n\t"
767 ".chip 68k"
768 : : "a" (temp));
769 }
770 else if (CPU_IS_060) {
771 unsigned long temp;
772 __asm__ __volatile__ (".chip 68060\n\t"
773 "plpar (%0)\n\t"
774 ".chip 68k"
775 : "=a" (temp)
776 : "0" (vaddr));
777 __asm__ __volatile__ (".chip 68060\n\t"
778 "cpushl %%bc,(%0)\n\t"
779 ".chip 68k"
780 : : "a" (temp));
781 } else if (!CPU_IS_COLDFIRE) {
782 /*
783 * 68030/68020 have no writeback cache;
784 * still need to clear icache.
785 * Note that vaddr is guaranteed to be long word aligned.
786 */
787 unsigned long temp;
788 asm volatile ("movec %%cacr,%0" : "=r" (temp));
789 temp += 4;
790 asm volatile ("movec %0,%%caar\n\t"
791 "movec %1,%%cacr"
792 : : "r" (vaddr), "r" (temp));
793 asm volatile ("movec %0,%%caar\n\t"
794 "movec %1,%%cacr"
795 : : "r" (vaddr + 4), "r" (temp));
796 }
797}
798
799static inline void __user *
800get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
801{
802 unsigned long usp;
803
804 /* Default to using normal stack. */
805 usp = rdusp();
806
807 /* This is the X/Open sanctioned signal stack switching. */
808 if (ka->sa.sa_flags & SA_ONSTACK) {
809 if (!sas_ss_flags(usp))
810 usp = current->sas_ss_sp + current->sas_ss_size;
811 }
812 return (void __user *)((usp - frame_size) & -8UL);
813}
814
815static int setup_frame (int sig, struct k_sigaction *ka,
816 sigset_t *set, struct pt_regs *regs)
817{
818 struct sigframe __user *frame;
819 int fsize = frame_extra_sizes[regs->format];
820 struct sigcontext context;
821 int err = 0;
822
823 if (fsize < 0) {
824#ifdef DEBUG
825 printk ("setup_frame: Unknown frame format %#x\n",
826 regs->format);
827#endif
828 goto give_sigsegv;
829 }
830
831 frame = get_sigframe(ka, regs, sizeof(*frame) + fsize);
832
833 if (fsize)
834 err |= copy_to_user (frame + 1, regs + 1, fsize);
835
836 err |= __put_user((current_thread_info()->exec_domain
837 && current_thread_info()->exec_domain->signal_invmap
838 && sig < 32
839 ? current_thread_info()->exec_domain->signal_invmap[sig]
840 : sig),
841 &frame->sig);
842
843 err |= __put_user(regs->vector, &frame->code);
844 err |= __put_user(&frame->sc, &frame->psc);
845
846 if (_NSIG_WORDS > 1)
847 err |= copy_to_user(frame->extramask, &set->sig[1],
848 sizeof(frame->extramask));
849
850 setup_sigcontext(&context, regs, set->sig[0]);
851 err |= copy_to_user (&frame->sc, &context, sizeof(context));
852
853 /* Set up to return from userspace. */
854 err |= __put_user(frame->retcode, &frame->pretcode);
855 /* moveq #,d0; trap #0 */
856 err |= __put_user(0x70004e40 + (__NR_sigreturn << 16),
857 (long __user *)(frame->retcode));
858
859 if (err)
860 goto give_sigsegv;
861
862 push_cache ((unsigned long) &frame->retcode);
863
864 /*
865 * Set up registers for signal handler. All the state we are about
866 * to destroy is successfully copied to sigframe.
867 */
868 wrusp ((unsigned long) frame);
869 regs->pc = (unsigned long) ka->sa.sa_handler;
870
871 /*
872 * This is subtle; if we build more than one sigframe, all but the
873 * first one will see frame format 0 and have fsize == 0, so we won't
874 * screw stkadj.
875 */
876 if (fsize)
877 regs->stkadj = fsize;
878
879 /* Prepare to skip over the extra stuff in the exception frame. */
880 if (regs->stkadj) {
881 struct pt_regs *tregs =
882 (struct pt_regs *)((ulong)regs + regs->stkadj);
883#ifdef DEBUG
884 printk("Performing stackadjust=%04x\n", regs->stkadj);
885#endif
886 /* This must be copied with decreasing addresses to
887 handle overlaps. */
888 tregs->vector = 0;
889 tregs->format = 0;
890 tregs->pc = regs->pc;
891 tregs->sr = regs->sr;
892 }
893 return 0;
894
895give_sigsegv:
896 force_sigsegv(sig, current);
897 return err;
898}
899
900static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
901 sigset_t *set, struct pt_regs *regs)
902{
903 struct rt_sigframe __user *frame;
904 int fsize = frame_extra_sizes[regs->format];
905 int err = 0;
906
907 if (fsize < 0) {
908#ifdef DEBUG
909 printk ("setup_frame: Unknown frame format %#x\n",
910 regs->format);
911#endif
912 goto give_sigsegv;
913 }
914
915 frame = get_sigframe(ka, regs, sizeof(*frame));
916
917 if (fsize)
918 err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize);
919
920 err |= __put_user((current_thread_info()->exec_domain
921 && current_thread_info()->exec_domain->signal_invmap
922 && sig < 32
923 ? current_thread_info()->exec_domain->signal_invmap[sig]
924 : sig),
925 &frame->sig);
926 err |= __put_user(&frame->info, &frame->pinfo);
927 err |= __put_user(&frame->uc, &frame->puc);
928 err |= copy_siginfo_to_user(&frame->info, info);
929
930 /* Create the ucontext. */
931 err |= __put_user(0, &frame->uc.uc_flags);
932 err |= __put_user(NULL, &frame->uc.uc_link);
933 err |= __put_user((void __user *)current->sas_ss_sp,
934 &frame->uc.uc_stack.ss_sp);
935 err |= __put_user(sas_ss_flags(rdusp()),
936 &frame->uc.uc_stack.ss_flags);
937 err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
938 err |= rt_setup_ucontext(&frame->uc, regs);
939 err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set));
940
941 /* Set up to return from userspace. */
942 err |= __put_user(frame->retcode, &frame->pretcode);
943#ifdef __mcoldfire__
944 /* movel #__NR_rt_sigreturn,d0; trap #0 */
945 err |= __put_user(0x203c0000, (long __user *)(frame->retcode + 0));
946 err |= __put_user(0x00004e40 + (__NR_rt_sigreturn << 16),
947 (long __user *)(frame->retcode + 4));
948#else
949 /* moveq #,d0; notb d0; trap #0 */
950 err |= __put_user(0x70004600 + ((__NR_rt_sigreturn ^ 0xff) << 16),
951 (long __user *)(frame->retcode + 0));
952 err |= __put_user(0x4e40, (short __user *)(frame->retcode + 4));
953#endif
954
955 if (err)
956 goto give_sigsegv;
957
958 push_cache ((unsigned long) &frame->retcode);
959
960 /*
961 * Set up registers for signal handler. All the state we are about
962 * to destroy is successfully copied to sigframe.
963 */
964 wrusp ((unsigned long) frame);
965 regs->pc = (unsigned long) ka->sa.sa_handler;
966
967 /*
968 * This is subtle; if we build more than one sigframe, all but the
969 * first one will see frame format 0 and have fsize == 0, so we won't
970 * screw stkadj.
971 */
972 if (fsize)
973 regs->stkadj = fsize;
974
975 /* Prepare to skip over the extra stuff in the exception frame. */
976 if (regs->stkadj) {
977 struct pt_regs *tregs =
978 (struct pt_regs *)((ulong)regs + regs->stkadj);
979#ifdef DEBUG
980 printk("Performing stackadjust=%04x\n", regs->stkadj);
981#endif
982 /* This must be copied with decreasing addresses to
983 handle overlaps. */
984 tregs->vector = 0;
985 tregs->format = 0;
986 tregs->pc = regs->pc;
987 tregs->sr = regs->sr;
988 }
989 return 0;
990
991give_sigsegv:
992 force_sigsegv(sig, current);
993 return err;
994}
995
996static inline void
997handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
998{
999 switch (regs->d0) {
1000 case -ERESTARTNOHAND:
1001 if (!has_handler)
1002 goto do_restart;
1003 regs->d0 = -EINTR;
1004 break;
1005
1006 case -ERESTART_RESTARTBLOCK:
1007 if (!has_handler) {
1008 regs->d0 = __NR_restart_syscall;
1009 regs->pc -= 2;
1010 break;
1011 }
1012 regs->d0 = -EINTR;
1013 break;
1014
1015 case -ERESTARTSYS:
1016 if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
1017 regs->d0 = -EINTR;
1018 break;
1019 }
1020 /* fallthrough */
1021 case -ERESTARTNOINTR:
1022 do_restart:
1023 regs->d0 = regs->orig_d0;
1024 regs->pc -= 2;
1025 break;
1026 }
1027}
1028
1029void ptrace_signal_deliver(struct pt_regs *regs, void *cookie)
1030{
1031 if (regs->orig_d0 < 0)
1032 return;
1033 switch (regs->d0) {
1034 case -ERESTARTNOHAND:
1035 case -ERESTARTSYS:
1036 case -ERESTARTNOINTR:
1037 regs->d0 = regs->orig_d0;
1038 regs->orig_d0 = -1;
1039 regs->pc -= 2;
1040 break;
1041 }
1042}
1043
1044/*
1045 * OK, we're invoking a handler
1046 */
1047static void
1048handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
1049 sigset_t *oldset, struct pt_regs *regs)
1050{
1051 int err;
1052 /* are we from a system call? */
1053 if (regs->orig_d0 >= 0)
1054 /* If so, check system call restarting.. */
1055 handle_restart(regs, ka, 1);
1056
1057 /* set up the stack frame */
1058 if (ka->sa.sa_flags & SA_SIGINFO)
1059 err = setup_rt_frame(sig, ka, info, oldset, regs);
1060 else
1061 err = setup_frame(sig, ka, oldset, regs);
1062
1063 if (err)
1064 return;
1065
1066 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
1067 if (!(ka->sa.sa_flags & SA_NODEFER))
1068 sigaddset(&current->blocked,sig);
1069 recalc_sigpending();
1070
1071 if (test_thread_flag(TIF_DELAYED_TRACE)) {
1072 regs->sr &= ~0x8000;
1073 send_sig(SIGTRAP, current, 1);
1074 }
1075
1076 clear_thread_flag(TIF_RESTORE_SIGMASK);
1077}
1078
1079/*
1080 * Note that 'init' is a special process: it doesn't get signals it doesn't
1081 * want to handle. Thus you cannot kill init even with a SIGKILL even by
1082 * mistake.
1083 */
1084asmlinkage void do_signal(struct pt_regs *regs)
1085{
1086 siginfo_t info;
1087 struct k_sigaction ka;
1088 int signr;
1089 sigset_t *oldset;
1090
1091 current->thread.esp0 = (unsigned long) regs;
1092
1093 if (test_thread_flag(TIF_RESTORE_SIGMASK))
1094 oldset = &current->saved_sigmask;
1095 else
1096 oldset = &current->blocked;
1097
1098 signr = get_signal_to_deliver(&info, &ka, regs, NULL);
1099 if (signr > 0) {
1100 /* Whee! Actually deliver the signal. */
1101 handle_signal(signr, &ka, &info, oldset, regs);
1102 return;
1103 }
1104
1105 /* Did we come from a system call? */
1106 if (regs->orig_d0 >= 0)
1107 /* Restart the system call - no handlers present */
1108 handle_restart(regs, NULL, 0);
1109
1110 /* If there's no signal to deliver, we just restore the saved mask. */
1111 if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
1112 clear_thread_flag(TIF_RESTORE_SIGMASK);
1113 sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
1114 }
1115}
diff --git a/arch/m68k/kernel/signal_no.c b/arch/m68k/kernel/signal_no.c
deleted file mode 100644
index 36a81bb6835..00000000000
--- a/arch/m68k/kernel/signal_no.c
+++ /dev/null
@@ -1,765 +0,0 @@
1/*
2 * linux/arch/m68knommu/kernel/signal.c
3 *
4 * Copyright (C) 1991, 1992 Linus Torvalds
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11/*
12 * Linux/m68k support by Hamish Macdonald
13 *
14 * 68060 fixes by Jesper Skov
15 *
16 * 1997-12-01 Modified for POSIX.1b signals by Andreas Schwab
17 *
18 * mathemu support by Roman Zippel
19 * (Note: fpstate in the signal context is completely ignored for the emulator
20 * and the internal floating point format is put on stack)
21 */
22
23/*
24 * ++roman (07/09/96): implemented signal stacks (specially for tosemu on
25 * Atari :-) Current limitation: Only one sigstack can be active at one time.
26 * If a second signal with SA_ONSTACK set arrives while working on a sigstack,
27 * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested
28 * signal handlers!
29 */
30
31#include <linux/sched.h>
32#include <linux/mm.h>
33#include <linux/kernel.h>
34#include <linux/signal.h>
35#include <linux/syscalls.h>
36#include <linux/errno.h>
37#include <linux/wait.h>
38#include <linux/ptrace.h>
39#include <linux/unistd.h>
40#include <linux/stddef.h>
41#include <linux/highuid.h>
42#include <linux/tty.h>
43#include <linux/personality.h>
44#include <linux/binfmts.h>
45
46#include <asm/setup.h>
47#include <asm/uaccess.h>
48#include <asm/pgtable.h>
49#include <asm/traps.h>
50#include <asm/ucontext.h>
51
52#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
53
54void ret_from_user_signal(void);
55void ret_from_user_rt_signal(void);
56
57/*
58 * Atomically swap in the new signal mask, and wait for a signal.
59 */
60asmlinkage int
61sys_sigsuspend(int unused0, int unused1, old_sigset_t mask)
62{
63 mask &= _BLOCKABLE;
64 spin_lock_irq(&current->sighand->siglock);
65 current->saved_sigmask = current->blocked;
66 siginitset(&current->blocked, mask);
67 recalc_sigpending();
68 spin_unlock_irq(&current->sighand->siglock);
69
70 current->state = TASK_INTERRUPTIBLE;
71 schedule();
72 set_restore_sigmask();
73
74 return -ERESTARTNOHAND;
75}
76
77asmlinkage int
78sys_sigaction(int sig, const struct old_sigaction __user *act,
79 struct old_sigaction __user *oact)
80{
81 struct k_sigaction new_ka, old_ka;
82 int ret;
83
84 if (act) {
85 old_sigset_t mask;
86 if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
87 __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
88 __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
89 __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
90 __get_user(mask, &act->sa_mask))
91 return -EFAULT;
92 siginitset(&new_ka.sa.sa_mask, mask);
93 }
94
95 ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
96
97 if (!ret && oact) {
98 if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
99 __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
100 __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
101 __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
102 __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
103 return -EFAULT;
104 }
105
106 return ret;
107}
108
109asmlinkage int
110sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss)
111{
112 return do_sigaltstack(uss, uoss, rdusp());
113}
114
115
116/*
117 * Do a signal return; undo the signal stack.
118 *
119 * Keep the return code on the stack quadword aligned!
120 * That makes the cache flush below easier.
121 */
122
123struct sigframe
124{
125 char __user *pretcode;
126 int sig;
127 int code;
128 struct sigcontext __user *psc;
129 char retcode[8];
130 unsigned long extramask[_NSIG_WORDS-1];
131 struct sigcontext sc;
132};
133
134struct rt_sigframe
135{
136 char __user *pretcode;
137 int sig;
138 struct siginfo __user *pinfo;
139 void __user *puc;
140 char retcode[8];
141 struct siginfo info;
142 struct ucontext uc;
143};
144
145#ifdef CONFIG_FPU
146
147static unsigned char fpu_version = 0; /* version number of fpu, set by setup_frame */
148
149static inline int restore_fpu_state(struct sigcontext *sc)
150{
151 int err = 1;
152
153 if (FPU_IS_EMU) {
154 /* restore registers */
155 memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12);
156 memcpy(current->thread.fp, sc->sc_fpregs, 24);
157 return 0;
158 }
159
160 if (sc->sc_fpstate[0]) {
161 /* Verify the frame format. */
162 if (sc->sc_fpstate[0] != fpu_version)
163 goto out;
164
165 __asm__ volatile (".chip 68k/68881\n\t"
166 "fmovemx %0,%%fp0-%%fp1\n\t"
167 "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
168 ".chip 68k"
169 : /* no outputs */
170 : "m" (*sc->sc_fpregs), "m" (*sc->sc_fpcntl));
171 }
172 __asm__ volatile (".chip 68k/68881\n\t"
173 "frestore %0\n\t"
174 ".chip 68k" : : "m" (*sc->sc_fpstate));
175 err = 0;
176
177out:
178 return err;
179}
180
181#define FPCONTEXT_SIZE 216
182#define uc_fpstate uc_filler[0]
183#define uc_formatvec uc_filler[FPCONTEXT_SIZE/4]
184#define uc_extra uc_filler[FPCONTEXT_SIZE/4+1]
185
186static inline int rt_restore_fpu_state(struct ucontext __user *uc)
187{
188 unsigned char fpstate[FPCONTEXT_SIZE];
189 int context_size = 0;
190 fpregset_t fpregs;
191 int err = 1;
192
193 if (FPU_IS_EMU) {
194 /* restore fpu control register */
195 if (__copy_from_user(current->thread.fpcntl,
196 uc->uc_mcontext.fpregs.f_fpcntl, 12))
197 goto out;
198 /* restore all other fpu register */
199 if (__copy_from_user(current->thread.fp,
200 uc->uc_mcontext.fpregs.f_fpregs, 96))
201 goto out;
202 return 0;
203 }
204
205 if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate))
206 goto out;
207 if (fpstate[0]) {
208 context_size = fpstate[1];
209
210 /* Verify the frame format. */
211 if (fpstate[0] != fpu_version)
212 goto out;
213 if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs,
214 sizeof(fpregs)))
215 goto out;
216 __asm__ volatile (".chip 68k/68881\n\t"
217 "fmovemx %0,%%fp0-%%fp7\n\t"
218 "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
219 ".chip 68k"
220 : /* no outputs */
221 : "m" (*fpregs.f_fpregs),
222 "m" (*fpregs.f_fpcntl));
223 }
224 if (context_size &&
225 __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1,
226 context_size))
227 goto out;
228 __asm__ volatile (".chip 68k/68881\n\t"
229 "frestore %0\n\t"
230 ".chip 68k" : : "m" (*fpstate));
231 err = 0;
232
233out:
234 return err;
235}
236
237#endif
238
239static inline int
240restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp,
241 int *pd0)
242{
243 int formatvec;
244 struct sigcontext context;
245 int err = 0;
246
247 /* Always make any pending restarted system calls return -EINTR */
248 current_thread_info()->restart_block.fn = do_no_restart_syscall;
249
250 /* get previous context */
251 if (copy_from_user(&context, usc, sizeof(context)))
252 goto badframe;
253
254 /* restore passed registers */
255 regs->d1 = context.sc_d1;
256 regs->a0 = context.sc_a0;
257 regs->a1 = context.sc_a1;
258 ((struct switch_stack *)regs - 1)->a5 = context.sc_a5;
259 regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff);
260 regs->pc = context.sc_pc;
261 regs->orig_d0 = -1; /* disable syscall checks */
262 wrusp(context.sc_usp);
263 formatvec = context.sc_formatvec;
264 regs->format = formatvec >> 12;
265 regs->vector = formatvec & 0xfff;
266
267#ifdef CONFIG_FPU
268 err = restore_fpu_state(&context);
269#endif
270
271 *pd0 = context.sc_d0;
272 return err;
273
274badframe:
275 return 1;
276}
277
278static inline int
279rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
280 struct ucontext __user *uc, int *pd0)
281{
282 int temp;
283 greg_t __user *gregs = uc->uc_mcontext.gregs;
284 unsigned long usp;
285 int err;
286
287 /* Always make any pending restarted system calls return -EINTR */
288 current_thread_info()->restart_block.fn = do_no_restart_syscall;
289
290 err = __get_user(temp, &uc->uc_mcontext.version);
291 if (temp != MCONTEXT_VERSION)
292 goto badframe;
293 /* restore passed registers */
294 err |= __get_user(regs->d0, &gregs[0]);
295 err |= __get_user(regs->d1, &gregs[1]);
296 err |= __get_user(regs->d2, &gregs[2]);
297 err |= __get_user(regs->d3, &gregs[3]);
298 err |= __get_user(regs->d4, &gregs[4]);
299 err |= __get_user(regs->d5, &gregs[5]);
300 err |= __get_user(sw->d6, &gregs[6]);
301 err |= __get_user(sw->d7, &gregs[7]);
302 err |= __get_user(regs->a0, &gregs[8]);
303 err |= __get_user(regs->a1, &gregs[9]);
304 err |= __get_user(regs->a2, &gregs[10]);
305 err |= __get_user(sw->a3, &gregs[11]);
306 err |= __get_user(sw->a4, &gregs[12]);
307 err |= __get_user(sw->a5, &gregs[13]);
308 err |= __get_user(sw->a6, &gregs[14]);
309 err |= __get_user(usp, &gregs[15]);
310 wrusp(usp);
311 err |= __get_user(regs->pc, &gregs[16]);
312 err |= __get_user(temp, &gregs[17]);
313 regs->sr = (regs->sr & 0xff00) | (temp & 0xff);
314 regs->orig_d0 = -1; /* disable syscall checks */
315 regs->format = temp >> 12;
316 regs->vector = temp & 0xfff;
317
318 if (do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT)
319 goto badframe;
320
321 *pd0 = regs->d0;
322 return err;
323
324badframe:
325 return 1;
326}
327
328asmlinkage int do_sigreturn(unsigned long __unused)
329{
330 struct switch_stack *sw = (struct switch_stack *) &__unused;
331 struct pt_regs *regs = (struct pt_regs *) (sw + 1);
332 unsigned long usp = rdusp();
333 struct sigframe __user *frame = (struct sigframe __user *)(usp - 4);
334 sigset_t set;
335 int d0;
336
337 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
338 goto badframe;
339 if (__get_user(set.sig[0], &frame->sc.sc_mask) ||
340 (_NSIG_WORDS > 1 &&
341 __copy_from_user(&set.sig[1], &frame->extramask,
342 sizeof(frame->extramask))))
343 goto badframe;
344
345 sigdelsetmask(&set, ~_BLOCKABLE);
346 spin_lock_irq(&current->sighand->siglock);
347 current->blocked = set;
348 recalc_sigpending();
349 spin_unlock_irq(&current->sighand->siglock);
350
351 if (restore_sigcontext(regs, &frame->sc, frame + 1, &d0))
352 goto badframe;
353 return d0;
354
355badframe:
356 force_sig(SIGSEGV, current);
357 return 0;
358}
359
360asmlinkage int do_rt_sigreturn(unsigned long __unused)
361{
362 struct switch_stack *sw = (struct switch_stack *) &__unused;
363 struct pt_regs *regs = (struct pt_regs *) (sw + 1);
364 unsigned long usp = rdusp();
365 struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4);
366 sigset_t set;
367 int d0;
368
369 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
370 goto badframe;
371 if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
372 goto badframe;
373
374 sigdelsetmask(&set, ~_BLOCKABLE);
375 spin_lock_irq(&current->sighand->siglock);
376 current->blocked = set;
377 recalc_sigpending();
378 spin_unlock_irq(&current->sighand->siglock);
379
380 if (rt_restore_ucontext(regs, sw, &frame->uc, &d0))
381 goto badframe;
382 return d0;
383
384badframe:
385 force_sig(SIGSEGV, current);
386 return 0;
387}
388
389#ifdef CONFIG_FPU
390/*
391 * Set up a signal frame.
392 */
393
394static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
395{
396 if (FPU_IS_EMU) {
397 /* save registers */
398 memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12);
399 memcpy(sc->sc_fpregs, current->thread.fp, 24);
400 return;
401 }
402
403 __asm__ volatile (".chip 68k/68881\n\t"
404 "fsave %0\n\t"
405 ".chip 68k"
406 : : "m" (*sc->sc_fpstate) : "memory");
407
408 if (sc->sc_fpstate[0]) {
409 fpu_version = sc->sc_fpstate[0];
410 __asm__ volatile (".chip 68k/68881\n\t"
411 "fmovemx %%fp0-%%fp1,%0\n\t"
412 "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
413 ".chip 68k"
414 : "=m" (*sc->sc_fpregs),
415 "=m" (*sc->sc_fpcntl)
416 : /* no inputs */
417 : "memory");
418 }
419}
420
421static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs)
422{
423 unsigned char fpstate[FPCONTEXT_SIZE];
424 int context_size = 0;
425 int err = 0;
426
427 if (FPU_IS_EMU) {
428 /* save fpu control register */
429 err |= copy_to_user(uc->uc_mcontext.fpregs.f_pcntl,
430 current->thread.fpcntl, 12);
431 /* save all other fpu register */
432 err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs,
433 current->thread.fp, 96);
434 return err;
435 }
436
437 __asm__ volatile (".chip 68k/68881\n\t"
438 "fsave %0\n\t"
439 ".chip 68k"
440 : : "m" (*fpstate) : "memory");
441
442 err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate);
443 if (fpstate[0]) {
444 fpregset_t fpregs;
445 context_size = fpstate[1];
446 fpu_version = fpstate[0];
447 __asm__ volatile (".chip 68k/68881\n\t"
448 "fmovemx %%fp0-%%fp7,%0\n\t"
449 "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
450 ".chip 68k"
451 : "=m" (*fpregs.f_fpregs),
452 "=m" (*fpregs.f_fpcntl)
453 : /* no inputs */
454 : "memory");
455 err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs,
456 sizeof(fpregs));
457 }
458 if (context_size)
459 err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4,
460 context_size);
461 return err;
462}
463
464#endif
465
466static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
467 unsigned long mask)
468{
469 sc->sc_mask = mask;
470 sc->sc_usp = rdusp();
471 sc->sc_d0 = regs->d0;
472 sc->sc_d1 = regs->d1;
473 sc->sc_a0 = regs->a0;
474 sc->sc_a1 = regs->a1;
475 sc->sc_a5 = ((struct switch_stack *)regs - 1)->a5;
476 sc->sc_sr = regs->sr;
477 sc->sc_pc = regs->pc;
478 sc->sc_formatvec = regs->format << 12 | regs->vector;
479#ifdef CONFIG_FPU
480 save_fpu_state(sc, regs);
481#endif
482}
483
484static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs)
485{
486 struct switch_stack *sw = (struct switch_stack *)regs - 1;
487 greg_t __user *gregs = uc->uc_mcontext.gregs;
488 int err = 0;
489
490 err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
491 err |= __put_user(regs->d0, &gregs[0]);
492 err |= __put_user(regs->d1, &gregs[1]);
493 err |= __put_user(regs->d2, &gregs[2]);
494 err |= __put_user(regs->d3, &gregs[3]);
495 err |= __put_user(regs->d4, &gregs[4]);
496 err |= __put_user(regs->d5, &gregs[5]);
497 err |= __put_user(sw->d6, &gregs[6]);
498 err |= __put_user(sw->d7, &gregs[7]);
499 err |= __put_user(regs->a0, &gregs[8]);
500 err |= __put_user(regs->a1, &gregs[9]);
501 err |= __put_user(regs->a2, &gregs[10]);
502 err |= __put_user(sw->a3, &gregs[11]);
503 err |= __put_user(sw->a4, &gregs[12]);
504 err |= __put_user(sw->a5, &gregs[13]);
505 err |= __put_user(sw->a6, &gregs[14]);
506 err |= __put_user(rdusp(), &gregs[15]);
507 err |= __put_user(regs->pc, &gregs[16]);
508 err |= __put_user(regs->sr, &gregs[17]);
509#ifdef CONFIG_FPU
510 err |= rt_save_fpu_state(uc, regs);
511#endif
512 return err;
513}
514
515static inline void __user *
516get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
517{
518 unsigned long usp;
519
520 /* Default to using normal stack. */
521 usp = rdusp();
522
523 /* This is the X/Open sanctioned signal stack switching. */
524 if (ka->sa.sa_flags & SA_ONSTACK) {
525 if (!sas_ss_flags(usp))
526 usp = current->sas_ss_sp + current->sas_ss_size;
527 }
528 return (void __user *)((usp - frame_size) & -8UL);
529}
530
531static int setup_frame (int sig, struct k_sigaction *ka,
532 sigset_t *set, struct pt_regs *regs)
533{
534 struct sigframe __user *frame;
535 struct sigcontext context;
536 int err = 0;
537
538 frame = get_sigframe(ka, regs, sizeof(*frame));
539
540 err |= __put_user((current_thread_info()->exec_domain
541 && current_thread_info()->exec_domain->signal_invmap
542 && sig < 32
543 ? current_thread_info()->exec_domain->signal_invmap[sig]
544 : sig),
545 &frame->sig);
546
547 err |= __put_user(regs->vector, &frame->code);
548 err |= __put_user(&frame->sc, &frame->psc);
549
550 if (_NSIG_WORDS > 1)
551 err |= copy_to_user(frame->extramask, &set->sig[1],
552 sizeof(frame->extramask));
553
554 setup_sigcontext(&context, regs, set->sig[0]);
555 err |= copy_to_user (&frame->sc, &context, sizeof(context));
556
557 /* Set up to return from userspace. */
558 err |= __put_user((void *) ret_from_user_signal, &frame->pretcode);
559
560 if (err)
561 goto give_sigsegv;
562
563 /* Set up registers for signal handler */
564 wrusp ((unsigned long) frame);
565 regs->pc = (unsigned long) ka->sa.sa_handler;
566 ((struct switch_stack *)regs - 1)->a5 = current->mm->start_data;
567 regs->format = 0x4; /*set format byte to make stack appear modulo 4
568 which it will be when doing the rte */
569
570adjust_stack:
571 /* Prepare to skip over the extra stuff in the exception frame. */
572 if (regs->stkadj) {
573 struct pt_regs *tregs =
574 (struct pt_regs *)((ulong)regs + regs->stkadj);
575#if defined(DEBUG)
576 printk(KERN_DEBUG "Performing stackadjust=%04x\n", regs->stkadj);
577#endif
578 /* This must be copied with decreasing addresses to
579 handle overlaps. */
580 tregs->vector = 0;
581 tregs->format = 0;
582 tregs->pc = regs->pc;
583 tregs->sr = regs->sr;
584 }
585 return err;
586
587give_sigsegv:
588 force_sigsegv(sig, current);
589 goto adjust_stack;
590}
591
592static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
593 sigset_t *set, struct pt_regs *regs)
594{
595 struct rt_sigframe __user *frame;
596 int err = 0;
597
598 frame = get_sigframe(ka, regs, sizeof(*frame));
599
600 err |= __put_user((current_thread_info()->exec_domain
601 && current_thread_info()->exec_domain->signal_invmap
602 && sig < 32
603 ? current_thread_info()->exec_domain->signal_invmap[sig]
604 : sig),
605 &frame->sig);
606 err |= __put_user(&frame->info, &frame->pinfo);
607 err |= __put_user(&frame->uc, &frame->puc);
608 err |= copy_siginfo_to_user(&frame->info, info);
609
610 /* Create the ucontext. */
611 err |= __put_user(0, &frame->uc.uc_flags);
612 err |= __put_user(NULL, &frame->uc.uc_link);
613 err |= __put_user((void __user *)current->sas_ss_sp,
614 &frame->uc.uc_stack.ss_sp);
615 err |= __put_user(sas_ss_flags(rdusp()),
616 &frame->uc.uc_stack.ss_flags);
617 err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
618 err |= rt_setup_ucontext(&frame->uc, regs);
619 err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set));
620
621 /* Set up to return from userspace. */
622 err |= __put_user((void *) ret_from_user_rt_signal, &frame->pretcode);
623
624 if (err)
625 goto give_sigsegv;
626
627 /* Set up registers for signal handler */
628 wrusp ((unsigned long) frame);
629 regs->pc = (unsigned long) ka->sa.sa_handler;
630 ((struct switch_stack *)regs - 1)->a5 = current->mm->start_data;
631 regs->format = 0x4; /*set format byte to make stack appear modulo 4
632 which it will be when doing the rte */
633
634adjust_stack:
635 /* Prepare to skip over the extra stuff in the exception frame. */
636 if (regs->stkadj) {
637 struct pt_regs *tregs =
638 (struct pt_regs *)((ulong)regs + regs->stkadj);
639#if defined(DEBUG)
640 printk(KERN_DEBUG "Performing stackadjust=%04x\n", regs->stkadj);
641#endif
642 /* This must be copied with decreasing addresses to
643 handle overlaps. */
644 tregs->vector = 0;
645 tregs->format = 0;
646 tregs->pc = regs->pc;
647 tregs->sr = regs->sr;
648 }
649 return err;
650
651give_sigsegv:
652 force_sigsegv(sig, current);
653 goto adjust_stack;
654}
655
656static inline void
657handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
658{
659 switch (regs->d0) {
660 case -ERESTARTNOHAND:
661 if (!has_handler)
662 goto do_restart;
663 regs->d0 = -EINTR;
664 break;
665
666 case -ERESTART_RESTARTBLOCK:
667 if (!has_handler) {
668 regs->d0 = __NR_restart_syscall;
669 regs->pc -= 2;
670 break;
671 }
672 regs->d0 = -EINTR;
673 break;
674
675 case -ERESTARTSYS:
676 if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
677 regs->d0 = -EINTR;
678 break;
679 }
680 /* fallthrough */
681 case -ERESTARTNOINTR:
682 do_restart:
683 regs->d0 = regs->orig_d0;
684 regs->pc -= 2;
685 break;
686 }
687}
688
689/*
690 * OK, we're invoking a handler
691 */
692static void
693handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
694 sigset_t *oldset, struct pt_regs *regs)
695{
696 int err;
697 /* are we from a system call? */
698 if (regs->orig_d0 >= 0)
699 /* If so, check system call restarting.. */
700 handle_restart(regs, ka, 1);
701
702 /* set up the stack frame */
703 if (ka->sa.sa_flags & SA_SIGINFO)
704 err = setup_rt_frame(sig, ka, info, oldset, regs);
705 else
706 err = setup_frame(sig, ka, oldset, regs);
707
708 if (err)
709 return;
710
711 spin_lock_irq(&current->sighand->siglock);
712 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
713 if (!(ka->sa.sa_flags & SA_NODEFER))
714 sigaddset(&current->blocked,sig);
715 recalc_sigpending();
716 spin_unlock_irq(&current->sighand->siglock);
717
718 clear_thread_flag(TIF_RESTORE_SIGMASK);
719}
720
721/*
722 * Note that 'init' is a special process: it doesn't get signals it doesn't
723 * want to handle. Thus you cannot kill init even with a SIGKILL even by
724 * mistake.
725 */
726asmlinkage void do_signal(struct pt_regs *regs)
727{
728 struct k_sigaction ka;
729 siginfo_t info;
730 int signr;
731 sigset_t *oldset;
732
733 /*
734 * We want the common case to go fast, which
735 * is why we may in certain cases get here from
736 * kernel mode. Just return without doing anything
737 * if so.
738 */
739 if (!user_mode(regs))
740 return;
741
742 if (test_thread_flag(TIF_RESTORE_SIGMASK))
743 oldset = &current->saved_sigmask;
744 else
745 oldset = &current->blocked;
746
747 signr = get_signal_to_deliver(&info, &ka, regs, NULL);
748 if (signr > 0) {
749 /* Whee! Actually deliver the signal. */
750 handle_signal(signr, &ka, &info, oldset, regs);
751 return;
752 }
753
754 /* Did we come from a system call? */
755 if (regs->orig_d0 >= 0) {
756 /* Restart the system call - no handlers present */
757 handle_restart(regs, NULL, 0);
758 }
759
760 /* If there's no signal to deliver, we just restore the saved mask. */
761 if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
762 clear_thread_flag(TIF_RESTORE_SIGMASK);
763 sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
764 }
765}
diff --git a/arch/m68k/platform/5206/Makefile b/arch/m68k/platform/5206/Makefile
deleted file mode 100644
index b5db05625cf..00000000000
--- a/arch/m68k/platform/5206/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
18
diff --git a/arch/m68k/platform/5206/gpio.c b/arch/m68k/platform/5206/gpio.c
deleted file mode 100644
index b9ab4a120f2..00000000000
--- a/arch/m68k/platform/5206/gpio.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/520x/Makefile b/arch/m68k/platform/520x/Makefile
deleted file mode 100644
index ad3f4e5a57c..00000000000
--- a/arch/m68k/platform/520x/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
1#
2# Makefile for the M5208 specific file.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/520x/gpio.c b/arch/m68k/platform/520x/gpio.c
deleted file mode 100644
index 9bcc3e4b60c..00000000000
--- a/arch/m68k/platform/520x/gpio.c
+++ /dev/null
@@ -1,175 +0,0 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = (void __iomem *) MCFEPORT_EPDDR,
36 .podr = (void __iomem *) MCFEPORT_EPDR,
37 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
38 },
39 {
40 .gpio_chip = {
41 .label = "CS",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value_fast,
48 .base = 9,
49 .ngpio = 3,
50 },
51 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
52 .podr = (void __iomem *) MCFGPIO_PODR_CS,
53 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
54 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
55 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
56 },
57 {
58 .gpio_chip = {
59 .label = "FECI2C",
60 .request = mcf_gpio_request,
61 .free = mcf_gpio_free,
62 .direction_input = mcf_gpio_direction_input,
63 .direction_output = mcf_gpio_direction_output,
64 .get = mcf_gpio_get_value,
65 .set = mcf_gpio_set_value_fast,
66 .base = 16,
67 .ngpio = 4,
68 },
69 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
70 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
71 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
72 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
73 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
74 },
75 {
76 .gpio_chip = {
77 .label = "QSPI",
78 .request = mcf_gpio_request,
79 .free = mcf_gpio_free,
80 .direction_input = mcf_gpio_direction_input,
81 .direction_output = mcf_gpio_direction_output,
82 .get = mcf_gpio_get_value,
83 .set = mcf_gpio_set_value_fast,
84 .base = 24,
85 .ngpio = 4,
86 },
87 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
88 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
89 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
90 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
91 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
92 },
93 {
94 .gpio_chip = {
95 .label = "TIMER",
96 .request = mcf_gpio_request,
97 .free = mcf_gpio_free,
98 .direction_input = mcf_gpio_direction_input,
99 .direction_output = mcf_gpio_direction_output,
100 .get = mcf_gpio_get_value,
101 .set = mcf_gpio_set_value_fast,
102 .base = 32,
103 .ngpio = 4,
104 },
105 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
106 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
107 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
108 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
109 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
110 },
111 {
112 .gpio_chip = {
113 .label = "UART",
114 .request = mcf_gpio_request,
115 .free = mcf_gpio_free,
116 .direction_input = mcf_gpio_direction_input,
117 .direction_output = mcf_gpio_direction_output,
118 .get = mcf_gpio_get_value,
119 .set = mcf_gpio_set_value_fast,
120 .base = 40,
121 .ngpio = 8,
122 },
123 .pddr = (void __iomem *) MCFGPIO_PDDR_UART,
124 .podr = (void __iomem *) MCFGPIO_PODR_UART,
125 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART,
126 .setr = (void __iomem *) MCFGPIO_PPDSDR_UART,
127 .clrr = (void __iomem *) MCFGPIO_PCLRR_UART,
128 },
129 {
130 .gpio_chip = {
131 .label = "FECH",
132 .request = mcf_gpio_request,
133 .free = mcf_gpio_free,
134 .direction_input = mcf_gpio_direction_input,
135 .direction_output = mcf_gpio_direction_output,
136 .get = mcf_gpio_get_value,
137 .set = mcf_gpio_set_value_fast,
138 .base = 48,
139 .ngpio = 8,
140 },
141 .pddr = (void __iomem *) MCFGPIO_PDDR_FECH,
142 .podr = (void __iomem *) MCFGPIO_PODR_FECH,
143 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
144 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
145 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH,
146 },
147 {
148 .gpio_chip = {
149 .label = "FECL",
150 .request = mcf_gpio_request,
151 .free = mcf_gpio_free,
152 .direction_input = mcf_gpio_direction_input,
153 .direction_output = mcf_gpio_direction_output,
154 .get = mcf_gpio_get_value,
155 .set = mcf_gpio_set_value_fast,
156 .base = 56,
157 .ngpio = 8,
158 },
159 .pddr = (void __iomem *) MCFGPIO_PDDR_FECL,
160 .podr = (void __iomem *) MCFGPIO_PODR_FECL,
161 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
162 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
163 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL,
164 },
165};
166
167static int __init mcf_gpio_init(void)
168{
169 unsigned i = 0;
170 while (i < ARRAY_SIZE(mcf_gpio_chips))
171 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
172 return 0;
173}
174
175core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/523x/Makefile b/arch/m68k/platform/523x/Makefile
deleted file mode 100644
index c04b8f71c88..00000000000
--- a/arch/m68k/platform/523x/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/523x/gpio.c b/arch/m68k/platform/523x/gpio.c
deleted file mode 100644
index 327ebf142c8..00000000000
--- a/arch/m68k/platform/523x/gpio.c
+++ /dev/null
@@ -1,284 +0,0 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .base = 1,
34 .ngpio = 7,
35 },
36 .pddr = (void __iomem *) MCFEPORT_EPDDR,
37 .podr = (void __iomem *) MCFEPORT_EPDR,
38 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
39 },
40 {
41 .gpio_chip = {
42 .label = "ADDR",
43 .request = mcf_gpio_request,
44 .free = mcf_gpio_free,
45 .direction_input = mcf_gpio_direction_input,
46 .direction_output = mcf_gpio_direction_output,
47 .get = mcf_gpio_get_value,
48 .set = mcf_gpio_set_value_fast,
49 .base = 13,
50 .ngpio = 3,
51 },
52 .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
53 .podr = (void __iomem *) MCFGPIO_PODR_ADDR,
54 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
55 .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
56 .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
57 },
58 {
59 .gpio_chip = {
60 .label = "DATAH",
61 .request = mcf_gpio_request,
62 .free = mcf_gpio_free,
63 .direction_input = mcf_gpio_direction_input,
64 .direction_output = mcf_gpio_direction_output,
65 .get = mcf_gpio_get_value,
66 .set = mcf_gpio_set_value_fast,
67 .base = 16,
68 .ngpio = 8,
69 },
70 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH,
71 .podr = (void __iomem *) MCFGPIO_PODR_DATAH,
72 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
73 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
74 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH,
75 },
76 {
77 .gpio_chip = {
78 .label = "DATAL",
79 .request = mcf_gpio_request,
80 .free = mcf_gpio_free,
81 .direction_input = mcf_gpio_direction_input,
82 .direction_output = mcf_gpio_direction_output,
83 .get = mcf_gpio_get_value,
84 .set = mcf_gpio_set_value_fast,
85 .base = 24,
86 .ngpio = 8,
87 },
88 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL,
89 .podr = (void __iomem *) MCFGPIO_PODR_DATAL,
90 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
91 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
92 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL,
93 },
94 {
95 .gpio_chip = {
96 .label = "BUSCTL",
97 .request = mcf_gpio_request,
98 .free = mcf_gpio_free,
99 .direction_input = mcf_gpio_direction_input,
100 .direction_output = mcf_gpio_direction_output,
101 .get = mcf_gpio_get_value,
102 .set = mcf_gpio_set_value_fast,
103 .base = 32,
104 .ngpio = 8,
105 },
106 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
107 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
108 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
109 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
110 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
111 },
112 {
113 .gpio_chip = {
114 .label = "BS",
115 .request = mcf_gpio_request,
116 .free = mcf_gpio_free,
117 .direction_input = mcf_gpio_direction_input,
118 .direction_output = mcf_gpio_direction_output,
119 .get = mcf_gpio_get_value,
120 .set = mcf_gpio_set_value_fast,
121 .base = 40,
122 .ngpio = 4,
123 },
124 .pddr = (void __iomem *) MCFGPIO_PDDR_BS,
125 .podr = (void __iomem *) MCFGPIO_PODR_BS,
126 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
127 .setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
128 .clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
129 },
130 {
131 .gpio_chip = {
132 .label = "CS",
133 .request = mcf_gpio_request,
134 .free = mcf_gpio_free,
135 .direction_input = mcf_gpio_direction_input,
136 .direction_output = mcf_gpio_direction_output,
137 .get = mcf_gpio_get_value,
138 .set = mcf_gpio_set_value_fast,
139 .base = 49,
140 .ngpio = 7,
141 },
142 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
143 .podr = (void __iomem *) MCFGPIO_PODR_CS,
144 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
145 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
146 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
147 },
148 {
149 .gpio_chip = {
150 .label = "SDRAM",
151 .request = mcf_gpio_request,
152 .free = mcf_gpio_free,
153 .direction_input = mcf_gpio_direction_input,
154 .direction_output = mcf_gpio_direction_output,
155 .get = mcf_gpio_get_value,
156 .set = mcf_gpio_set_value_fast,
157 .base = 56,
158 .ngpio = 6,
159 },
160 .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
161 .podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
162 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
163 .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
164 .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
165 },
166 {
167 .gpio_chip = {
168 .label = "FECI2C",
169 .request = mcf_gpio_request,
170 .free = mcf_gpio_free,
171 .direction_input = mcf_gpio_direction_input,
172 .direction_output = mcf_gpio_direction_output,
173 .get = mcf_gpio_get_value,
174 .set = mcf_gpio_set_value_fast,
175 .base = 64,
176 .ngpio = 4,
177 },
178 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
179 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
180 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
181 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
182 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
183 },
184 {
185 .gpio_chip = {
186 .label = "UARTH",
187 .request = mcf_gpio_request,
188 .free = mcf_gpio_free,
189 .direction_input = mcf_gpio_direction_input,
190 .direction_output = mcf_gpio_direction_output,
191 .get = mcf_gpio_get_value,
192 .set = mcf_gpio_set_value_fast,
193 .base = 72,
194 .ngpio = 2,
195 },
196 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
197 .podr = (void __iomem *) MCFGPIO_PODR_UARTH,
198 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
199 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
200 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
201 },
202 {
203 .gpio_chip = {
204 .label = "UARTL",
205 .request = mcf_gpio_request,
206 .free = mcf_gpio_free,
207 .direction_input = mcf_gpio_direction_input,
208 .direction_output = mcf_gpio_direction_output,
209 .get = mcf_gpio_get_value,
210 .set = mcf_gpio_set_value_fast,
211 .base = 80,
212 .ngpio = 8,
213 },
214 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
215 .podr = (void __iomem *) MCFGPIO_PODR_UARTL,
216 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
217 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
218 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
219 },
220 {
221 .gpio_chip = {
222 .label = "QSPI",
223 .request = mcf_gpio_request,
224 .free = mcf_gpio_free,
225 .direction_input = mcf_gpio_direction_input,
226 .direction_output = mcf_gpio_direction_output,
227 .get = mcf_gpio_get_value,
228 .set = mcf_gpio_set_value_fast,
229 .base = 88,
230 .ngpio = 5,
231 },
232 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
233 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
234 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
235 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
236 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
237 },
238 {
239 .gpio_chip = {
240 .label = "TIMER",
241 .request = mcf_gpio_request,
242 .free = mcf_gpio_free,
243 .direction_input = mcf_gpio_direction_input,
244 .direction_output = mcf_gpio_direction_output,
245 .get = mcf_gpio_get_value,
246 .set = mcf_gpio_set_value_fast,
247 .base = 96,
248 .ngpio = 8,
249 },
250 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
251 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
252 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
253 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
254 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
255 },
256 {
257 .gpio_chip = {
258 .label = "ETPU",
259 .request = mcf_gpio_request,
260 .free = mcf_gpio_free,
261 .direction_input = mcf_gpio_direction_input,
262 .direction_output = mcf_gpio_direction_output,
263 .get = mcf_gpio_get_value,
264 .set = mcf_gpio_set_value_fast,
265 .base = 104,
266 .ngpio = 3,
267 },
268 .pddr = (void __iomem *) MCFGPIO_PDDR_ETPU,
269 .podr = (void __iomem *) MCFGPIO_PODR_ETPU,
270 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ETPU,
271 .setr = (void __iomem *) MCFGPIO_PPDSDR_ETPU,
272 .clrr = (void __iomem *) MCFGPIO_PCLRR_ETPU,
273 },
274};
275
276static int __init mcf_gpio_init(void)
277{
278 unsigned i = 0;
279 while (i < ARRAY_SIZE(mcf_gpio_chips))
280 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
281 return 0;
282}
283
284core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5249/Makefile b/arch/m68k/platform/5249/Makefile
deleted file mode 100644
index 4bed30fd007..00000000000
--- a/arch/m68k/platform/5249/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o intc2.o
18
diff --git a/arch/m68k/platform/5249/gpio.c b/arch/m68k/platform/5249/gpio.c
deleted file mode 100644
index 2b56c6ef65b..00000000000
--- a/arch/m68k/platform/5249/gpio.c
+++ /dev/null
@@ -1,65 +0,0 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "GPIO0",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 32,
34 },
35 .pddr = (void __iomem *) MCFSIM2_GPIOENABLE,
36 .podr = (void __iomem *) MCFSIM2_GPIOWRITE,
37 .ppdr = (void __iomem *) MCFSIM2_GPIOREAD,
38 },
39 {
40 .gpio_chip = {
41 .label = "GPIO1",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value,
48 .base = 32,
49 .ngpio = 32,
50 },
51 .pddr = (void __iomem *) MCFSIM2_GPIO1ENABLE,
52 .podr = (void __iomem *) MCFSIM2_GPIO1WRITE,
53 .ppdr = (void __iomem *) MCFSIM2_GPIO1READ,
54 },
55};
56
57static int __init mcf_gpio_init(void)
58{
59 unsigned i = 0;
60 while (i < ARRAY_SIZE(mcf_gpio_chips))
61 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
62 return 0;
63}
64
65core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5272/Makefile b/arch/m68k/platform/5272/Makefile
deleted file mode 100644
index 34110fc1430..00000000000
--- a/arch/m68k/platform/5272/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o intc.o
18
diff --git a/arch/m68k/platform/5272/gpio.c b/arch/m68k/platform/5272/gpio.c
deleted file mode 100644
index 57ac10a5d7f..00000000000
--- a/arch/m68k/platform/5272/gpio.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PA",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 },
39 {
40 .gpio_chip = {
41 .label = "PB",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value,
48 .base = 16,
49 .ngpio = 16,
50 },
51 .pddr = (void __iomem *) MCFSIM_PBDDR,
52 .podr = (void __iomem *) MCFSIM_PBDAT,
53 .ppdr = (void __iomem *) MCFSIM_PBDAT,
54 },
55 {
56 .gpio_chip = {
57 .label = "PC",
58 .request = mcf_gpio_request,
59 .free = mcf_gpio_free,
60 .direction_input = mcf_gpio_direction_input,
61 .direction_output = mcf_gpio_direction_output,
62 .get = mcf_gpio_get_value,
63 .set = mcf_gpio_set_value,
64 .base = 32,
65 .ngpio = 16,
66 },
67 .pddr = (void __iomem *) MCFSIM_PCDDR,
68 .podr = (void __iomem *) MCFSIM_PCDAT,
69 .ppdr = (void __iomem *) MCFSIM_PCDAT,
70 },
71};
72
73static int __init mcf_gpio_init(void)
74{
75 unsigned i = 0;
76 while (i < ARRAY_SIZE(mcf_gpio_chips))
77 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
78 return 0;
79}
80
81core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/527x/Makefile b/arch/m68k/platform/527x/Makefile
deleted file mode 100644
index 6ac4b57370e..00000000000
--- a/arch/m68k/platform/527x/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
18
diff --git a/arch/m68k/platform/527x/gpio.c b/arch/m68k/platform/527x/gpio.c
deleted file mode 100644
index 205da0aa0f2..00000000000
--- a/arch/m68k/platform/527x/gpio.c
+++ /dev/null
@@ -1,609 +0,0 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24#if defined(CONFIG_M5271)
25 {
26 .gpio_chip = {
27 .label = "PIRQ",
28 .request = mcf_gpio_request,
29 .free = mcf_gpio_free,
30 .direction_input = mcf_gpio_direction_input,
31 .direction_output = mcf_gpio_direction_output,
32 .get = mcf_gpio_get_value,
33 .set = mcf_gpio_set_value,
34 .base = 1,
35 .ngpio = 7,
36 },
37 .pddr = (void __iomem *) MCFEPORT_EPDDR,
38 .podr = (void __iomem *) MCFEPORT_EPDR,
39 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
40 },
41 {
42 .gpio_chip = {
43 .label = "ADDR",
44 .request = mcf_gpio_request,
45 .free = mcf_gpio_free,
46 .direction_input = mcf_gpio_direction_input,
47 .direction_output = mcf_gpio_direction_output,
48 .get = mcf_gpio_get_value,
49 .set = mcf_gpio_set_value_fast,
50 .base = 13,
51 .ngpio = 3,
52 },
53 .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
54 .podr = (void __iomem *) MCFGPIO_PODR_ADDR,
55 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
56 .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
57 .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
58 },
59 {
60 .gpio_chip = {
61 .label = "DATAH",
62 .request = mcf_gpio_request,
63 .free = mcf_gpio_free,
64 .direction_input = mcf_gpio_direction_input,
65 .direction_output = mcf_gpio_direction_output,
66 .get = mcf_gpio_get_value,
67 .set = mcf_gpio_set_value_fast,
68 .base = 16,
69 .ngpio = 8,
70 },
71 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH,
72 .podr = (void __iomem *) MCFGPIO_PODR_DATAH,
73 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
74 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
75 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH,
76 },
77 {
78 .gpio_chip = {
79 .label = "DATAL",
80 .request = mcf_gpio_request,
81 .free = mcf_gpio_free,
82 .direction_input = mcf_gpio_direction_input,
83 .direction_output = mcf_gpio_direction_output,
84 .get = mcf_gpio_get_value,
85 .set = mcf_gpio_set_value_fast,
86 .base = 24,
87 .ngpio = 8,
88 },
89 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL,
90 .podr = (void __iomem *) MCFGPIO_PODR_DATAL,
91 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
92 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
93 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL,
94 },
95 {
96 .gpio_chip = {
97 .label = "BUSCTL",
98 .request = mcf_gpio_request,
99 .free = mcf_gpio_free,
100 .direction_input = mcf_gpio_direction_input,
101 .direction_output = mcf_gpio_direction_output,
102 .get = mcf_gpio_get_value,
103 .set = mcf_gpio_set_value_fast,
104 .base = 32,
105 .ngpio = 8,
106 },
107 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
108 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
109 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
110 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
111 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
112 },
113 {
114 .gpio_chip = {
115 .label = "BS",
116 .request = mcf_gpio_request,
117 .free = mcf_gpio_free,
118 .direction_input = mcf_gpio_direction_input,
119 .direction_output = mcf_gpio_direction_output,
120 .get = mcf_gpio_get_value,
121 .set = mcf_gpio_set_value_fast,
122 .base = 40,
123 .ngpio = 4,
124 },
125 .pddr = (void __iomem *) MCFGPIO_PDDR_BS,
126 .podr = (void __iomem *) MCFGPIO_PODR_BS,
127 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
128 .setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
129 .clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
130 },
131 {
132 .gpio_chip = {
133 .label = "CS",
134 .request = mcf_gpio_request,
135 .free = mcf_gpio_free,
136 .direction_input = mcf_gpio_direction_input,
137 .direction_output = mcf_gpio_direction_output,
138 .get = mcf_gpio_get_value,
139 .set = mcf_gpio_set_value_fast,
140 .base = 49,
141 .ngpio = 7,
142 },
143 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
144 .podr = (void __iomem *) MCFGPIO_PODR_CS,
145 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
146 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
147 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
148 },
149 {
150 .gpio_chip = {
151 .label = "SDRAM",
152 .request = mcf_gpio_request,
153 .free = mcf_gpio_free,
154 .direction_input = mcf_gpio_direction_input,
155 .direction_output = mcf_gpio_direction_output,
156 .get = mcf_gpio_get_value,
157 .set = mcf_gpio_set_value_fast,
158 .base = 56,
159 .ngpio = 6,
160 },
161 .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
162 .podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
163 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
164 .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
165 .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
166 },
167 {
168 .gpio_chip = {
169 .label = "FECI2C",
170 .request = mcf_gpio_request,
171 .free = mcf_gpio_free,
172 .direction_input = mcf_gpio_direction_input,
173 .direction_output = mcf_gpio_direction_output,
174 .get = mcf_gpio_get_value,
175 .set = mcf_gpio_set_value_fast,
176 .base = 64,
177 .ngpio = 4,
178 },
179 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
180 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
181 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
182 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
183 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
184 },
185 {
186 .gpio_chip = {
187 .label = "UARTH",
188 .request = mcf_gpio_request,
189 .free = mcf_gpio_free,
190 .direction_input = mcf_gpio_direction_input,
191 .direction_output = mcf_gpio_direction_output,
192 .get = mcf_gpio_get_value,
193 .set = mcf_gpio_set_value_fast,
194 .base = 72,
195 .ngpio = 2,
196 },
197 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
198 .podr = (void __iomem *) MCFGPIO_PODR_UARTH,
199 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
200 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
201 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
202 },
203 {
204 .gpio_chip = {
205 .label = "UARTL",
206 .request = mcf_gpio_request,
207 .free = mcf_gpio_free,
208 .direction_input = mcf_gpio_direction_input,
209 .direction_output = mcf_gpio_direction_output,
210 .get = mcf_gpio_get_value,
211 .set = mcf_gpio_set_value_fast,
212 .base = 80,
213 .ngpio = 8,
214 },
215 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
216 .podr = (void __iomem *) MCFGPIO_PODR_UARTL,
217 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
218 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
219 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
220 },
221 {
222 .gpio_chip = {
223 .label = "QSPI",
224 .request = mcf_gpio_request,
225 .free = mcf_gpio_free,
226 .direction_input = mcf_gpio_direction_input,
227 .direction_output = mcf_gpio_direction_output,
228 .get = mcf_gpio_get_value,
229 .set = mcf_gpio_set_value_fast,
230 .base = 88,
231 .ngpio = 5,
232 },
233 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
234 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
235 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
236 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
237 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
238 },
239 {
240 .gpio_chip = {
241 .label = "TIMER",
242 .request = mcf_gpio_request,
243 .free = mcf_gpio_free,
244 .direction_input = mcf_gpio_direction_input,
245 .direction_output = mcf_gpio_direction_output,
246 .get = mcf_gpio_get_value,
247 .set = mcf_gpio_set_value_fast,
248 .base = 96,
249 .ngpio = 8,
250 },
251 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
252 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
253 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
254 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
255 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
256 },
257#elif defined(CONFIG_M5275)
258 {
259 .gpio_chip = {
260 .label = "PIRQ",
261 .request = mcf_gpio_request,
262 .free = mcf_gpio_free,
263 .direction_input = mcf_gpio_direction_input,
264 .direction_output = mcf_gpio_direction_output,
265 .get = mcf_gpio_get_value,
266 .set = mcf_gpio_set_value,
267 .base = 1,
268 .ngpio = 7,
269 },
270 .pddr = (void __iomem *) MCFEPORT_EPDDR,
271 .podr = (void __iomem *) MCFEPORT_EPDR,
272 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
273 },
274 {
275 .gpio_chip = {
276 .label = "BUSCTL",
277 .request = mcf_gpio_request,
278 .free = mcf_gpio_free,
279 .direction_input = mcf_gpio_direction_input,
280 .direction_output = mcf_gpio_direction_output,
281 .get = mcf_gpio_get_value,
282 .set = mcf_gpio_set_value_fast,
283 .base = 8,
284 .ngpio = 8,
285 },
286 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
287 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
288 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
289 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
290 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
291 },
292 {
293 .gpio_chip = {
294 .label = "ADDR",
295 .request = mcf_gpio_request,
296 .free = mcf_gpio_free,
297 .direction_input = mcf_gpio_direction_input,
298 .direction_output = mcf_gpio_direction_output,
299 .get = mcf_gpio_get_value,
300 .set = mcf_gpio_set_value_fast,
301 .base = 21,
302 .ngpio = 3,
303 },
304 .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
305 .podr = (void __iomem *) MCFGPIO_PODR_ADDR,
306 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
307 .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
308 .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
309 },
310 {
311 .gpio_chip = {
312 .label = "CS",
313 .request = mcf_gpio_request,
314 .free = mcf_gpio_free,
315 .direction_input = mcf_gpio_direction_input,
316 .direction_output = mcf_gpio_direction_output,
317 .get = mcf_gpio_get_value,
318 .set = mcf_gpio_set_value_fast,
319 .base = 25,
320 .ngpio = 7,
321 },
322 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
323 .podr = (void __iomem *) MCFGPIO_PODR_CS,
324 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
325 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
326 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
327 },
328 {
329 .gpio_chip = {
330 .label = "FEC0H",
331 .request = mcf_gpio_request,
332 .free = mcf_gpio_free,
333 .direction_input = mcf_gpio_direction_input,
334 .direction_output = mcf_gpio_direction_output,
335 .get = mcf_gpio_get_value,
336 .set = mcf_gpio_set_value_fast,
337 .base = 32,
338 .ngpio = 8,
339 },
340 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0H,
341 .podr = (void __iomem *) MCFGPIO_PODR_FEC0H,
342 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
343 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
344 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0H,
345 },
346 {
347 .gpio_chip = {
348 .label = "FEC0L",
349 .request = mcf_gpio_request,
350 .free = mcf_gpio_free,
351 .direction_input = mcf_gpio_direction_input,
352 .direction_output = mcf_gpio_direction_output,
353 .get = mcf_gpio_get_value,
354 .set = mcf_gpio_set_value_fast,
355 .base = 40,
356 .ngpio = 8,
357 },
358 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0L,
359 .podr = (void __iomem *) MCFGPIO_PODR_FEC0L,
360 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
361 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
362 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0L,
363 },
364 {
365 .gpio_chip = {
366 .label = "FECI2C",
367 .request = mcf_gpio_request,
368 .free = mcf_gpio_free,
369 .direction_input = mcf_gpio_direction_input,
370 .direction_output = mcf_gpio_direction_output,
371 .get = mcf_gpio_get_value,
372 .set = mcf_gpio_set_value_fast,
373 .base = 48,
374 .ngpio = 6,
375 },
376 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
377 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
378 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
379 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
380 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
381 },
382 {
383 .gpio_chip = {
384 .label = "QSPI",
385 .request = mcf_gpio_request,
386 .free = mcf_gpio_free,
387 .direction_input = mcf_gpio_direction_input,
388 .direction_output = mcf_gpio_direction_output,
389 .get = mcf_gpio_get_value,
390 .set = mcf_gpio_set_value_fast,
391 .base = 56,
392 .ngpio = 7,
393 },
394 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
395 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
396 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
397 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
398 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
399 },
400 {
401 .gpio_chip = {
402 .label = "SDRAM",
403 .request = mcf_gpio_request,
404 .free = mcf_gpio_free,
405 .direction_input = mcf_gpio_direction_input,
406 .direction_output = mcf_gpio_direction_output,
407 .get = mcf_gpio_get_value,
408 .set = mcf_gpio_set_value_fast,
409 .base = 64,
410 .ngpio = 8,
411 },
412 .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
413 .podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
414 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
415 .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
416 .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
417 },
418 {
419 .gpio_chip = {
420 .label = "TIMERH",
421 .request = mcf_gpio_request,
422 .free = mcf_gpio_free,
423 .direction_input = mcf_gpio_direction_input,
424 .direction_output = mcf_gpio_direction_output,
425 .get = mcf_gpio_get_value,
426 .set = mcf_gpio_set_value_fast,
427 .base = 72,
428 .ngpio = 4,
429 },
430 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERH,
431 .podr = (void __iomem *) MCFGPIO_PODR_TIMERH,
432 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
433 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
434 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERH,
435 },
436 {
437 .gpio_chip = {
438 .label = "TIMERL",
439 .request = mcf_gpio_request,
440 .free = mcf_gpio_free,
441 .direction_input = mcf_gpio_direction_input,
442 .direction_output = mcf_gpio_direction_output,
443 .get = mcf_gpio_get_value,
444 .set = mcf_gpio_set_value_fast,
445 .base = 80,
446 .ngpio = 4,
447 },
448 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERL,
449 .podr = (void __iomem *) MCFGPIO_PODR_TIMERL,
450 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
451 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
452 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERL,
453 },
454 {
455 .gpio_chip = {
456 .label = "UARTL",
457 .request = mcf_gpio_request,
458 .free = mcf_gpio_free,
459 .direction_input = mcf_gpio_direction_input,
460 .direction_output = mcf_gpio_direction_output,
461 .get = mcf_gpio_get_value,
462 .set = mcf_gpio_set_value_fast,
463 .base = 88,
464 .ngpio = 8,
465 },
466 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
467 .podr = (void __iomem *) MCFGPIO_PODR_UARTL,
468 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
469 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
470 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
471 },
472 {
473 .gpio_chip = {
474 .label = "FEC1H",
475 .request = mcf_gpio_request,
476 .free = mcf_gpio_free,
477 .direction_input = mcf_gpio_direction_input,
478 .direction_output = mcf_gpio_direction_output,
479 .get = mcf_gpio_get_value,
480 .set = mcf_gpio_set_value_fast,
481 .base = 96,
482 .ngpio = 8,
483 },
484 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1H,
485 .podr = (void __iomem *) MCFGPIO_PODR_FEC1H,
486 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
487 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
488 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1H,
489 },
490 {
491 .gpio_chip = {
492 .label = "FEC1L",
493 .request = mcf_gpio_request,
494 .free = mcf_gpio_free,
495 .direction_input = mcf_gpio_direction_input,
496 .direction_output = mcf_gpio_direction_output,
497 .get = mcf_gpio_get_value,
498 .set = mcf_gpio_set_value_fast,
499 .base = 104,
500 .ngpio = 8,
501 },
502 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1L,
503 .podr = (void __iomem *) MCFGPIO_PODR_FEC1L,
504 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
505 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
506 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1L,
507 },
508 {
509 .gpio_chip = {
510 .label = "BS",
511 .request = mcf_gpio_request,
512 .free = mcf_gpio_free,
513 .direction_input = mcf_gpio_direction_input,
514 .direction_output = mcf_gpio_direction_output,
515 .get = mcf_gpio_get_value,
516 .set = mcf_gpio_set_value_fast,
517 .base = 114,
518 .ngpio = 2,
519 },
520 .pddr = (void __iomem *) MCFGPIO_PDDR_BS,
521 .podr = (void __iomem *) MCFGPIO_PODR_BS,
522 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
523 .setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
524 .clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
525 },
526 {
527 .gpio_chip = {
528 .label = "IRQ",
529 .request = mcf_gpio_request,
530 .free = mcf_gpio_free,
531 .direction_input = mcf_gpio_direction_input,
532 .direction_output = mcf_gpio_direction_output,
533 .get = mcf_gpio_get_value,
534 .set = mcf_gpio_set_value_fast,
535 .base = 121,
536 .ngpio = 7,
537 },
538 .pddr = (void __iomem *) MCFGPIO_PDDR_IRQ,
539 .podr = (void __iomem *) MCFGPIO_PODR_IRQ,
540 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
541 .setr = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
542 .clrr = (void __iomem *) MCFGPIO_PCLRR_IRQ,
543 },
544 {
545 .gpio_chip = {
546 .label = "USBH",
547 .request = mcf_gpio_request,
548 .free = mcf_gpio_free,
549 .direction_input = mcf_gpio_direction_input,
550 .direction_output = mcf_gpio_direction_output,
551 .get = mcf_gpio_get_value,
552 .set = mcf_gpio_set_value_fast,
553 .base = 128,
554 .ngpio = 1,
555 },
556 .pddr = (void __iomem *) MCFGPIO_PDDR_USBH,
557 .podr = (void __iomem *) MCFGPIO_PODR_USBH,
558 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBH,
559 .setr = (void __iomem *) MCFGPIO_PPDSDR_USBH,
560 .clrr = (void __iomem *) MCFGPIO_PCLRR_USBH,
561 },
562 {
563 .gpio_chip = {
564 .label = "USBL",
565 .request = mcf_gpio_request,
566 .free = mcf_gpio_free,
567 .direction_input = mcf_gpio_direction_input,
568 .direction_output = mcf_gpio_direction_output,
569 .get = mcf_gpio_get_value,
570 .set = mcf_gpio_set_value_fast,
571 .base = 136,
572 .ngpio = 8,
573 },
574 .pddr = (void __iomem *) MCFGPIO_PDDR_USBL,
575 .podr = (void __iomem *) MCFGPIO_PODR_USBL,
576 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBL,
577 .setr = (void __iomem *) MCFGPIO_PPDSDR_USBL,
578 .clrr = (void __iomem *) MCFGPIO_PCLRR_USBL,
579 },
580 {
581 .gpio_chip = {
582 .label = "UARTH",
583 .request = mcf_gpio_request,
584 .free = mcf_gpio_free,
585 .direction_input = mcf_gpio_direction_input,
586 .direction_output = mcf_gpio_direction_output,
587 .get = mcf_gpio_get_value,
588 .set = mcf_gpio_set_value_fast,
589 .base = 144,
590 .ngpio = 4,
591 },
592 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
593 .podr = (void __iomem *) MCFGPIO_PODR_UARTH,
594 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
595 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
596 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
597 },
598#endif
599};
600
601static int __init mcf_gpio_init(void)
602{
603 unsigned i = 0;
604 while (i < ARRAY_SIZE(mcf_gpio_chips))
605 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
606 return 0;
607}
608
609core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/528x/Makefile b/arch/m68k/platform/528x/Makefile
deleted file mode 100644
index 6ac4b57370e..00000000000
--- a/arch/m68k/platform/528x/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
18
diff --git a/arch/m68k/platform/528x/gpio.c b/arch/m68k/platform/528x/gpio.c
deleted file mode 100644
index 526db665d87..00000000000
--- a/arch/m68k/platform/528x/gpio.c
+++ /dev/null
@@ -1,438 +0,0 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "NQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .base = 1,
34 .ngpio = 7,
35 },
36 .pddr = (void __iomem *)MCFEPORT_EPDDR,
37 .podr = (void __iomem *)MCFEPORT_EPDR,
38 .ppdr = (void __iomem *)MCFEPORT_EPPDR,
39 },
40 {
41 .gpio_chip = {
42 .label = "TA",
43 .request = mcf_gpio_request,
44 .free = mcf_gpio_free,
45 .direction_input = mcf_gpio_direction_input,
46 .direction_output = mcf_gpio_direction_output,
47 .get = mcf_gpio_get_value,
48 .set = mcf_gpio_set_value_fast,
49 .base = 8,
50 .ngpio = 4,
51 },
52 .pddr = (void __iomem *)MCFGPTA_GPTDDR,
53 .podr = (void __iomem *)MCFGPTA_GPTPORT,
54 .ppdr = (void __iomem *)MCFGPTB_GPTPORT,
55 },
56 {
57 .gpio_chip = {
58 .label = "TB",
59 .request = mcf_gpio_request,
60 .free = mcf_gpio_free,
61 .direction_input = mcf_gpio_direction_input,
62 .direction_output = mcf_gpio_direction_output,
63 .get = mcf_gpio_get_value,
64 .set = mcf_gpio_set_value_fast,
65 .base = 16,
66 .ngpio = 4,
67 },
68 .pddr = (void __iomem *)MCFGPTB_GPTDDR,
69 .podr = (void __iomem *)MCFGPTB_GPTPORT,
70 .ppdr = (void __iomem *)MCFGPTB_GPTPORT,
71 },
72 {
73 .gpio_chip = {
74 .label = "QA",
75 .request = mcf_gpio_request,
76 .free = mcf_gpio_free,
77 .direction_input = mcf_gpio_direction_input,
78 .direction_output = mcf_gpio_direction_output,
79 .get = mcf_gpio_get_value,
80 .set = mcf_gpio_set_value_fast,
81 .base = 24,
82 .ngpio = 4,
83 },
84 .pddr = (void __iomem *)MCFQADC_DDRQA,
85 .podr = (void __iomem *)MCFQADC_PORTQA,
86 .ppdr = (void __iomem *)MCFQADC_PORTQA,
87 },
88 {
89 .gpio_chip = {
90 .label = "QB",
91 .request = mcf_gpio_request,
92 .free = mcf_gpio_free,
93 .direction_input = mcf_gpio_direction_input,
94 .direction_output = mcf_gpio_direction_output,
95 .get = mcf_gpio_get_value,
96 .set = mcf_gpio_set_value_fast,
97 .base = 32,
98 .ngpio = 4,
99 },
100 .pddr = (void __iomem *)MCFQADC_DDRQB,
101 .podr = (void __iomem *)MCFQADC_PORTQB,
102 .ppdr = (void __iomem *)MCFQADC_PORTQB,
103 },
104 {
105 .gpio_chip = {
106 .label = "A",
107 .request = mcf_gpio_request,
108 .free = mcf_gpio_free,
109 .direction_input = mcf_gpio_direction_input,
110 .direction_output = mcf_gpio_direction_output,
111 .get = mcf_gpio_get_value,
112 .set = mcf_gpio_set_value_fast,
113 .base = 40,
114 .ngpio = 8,
115 },
116 .pddr = (void __iomem *)MCFGPIO_DDRA,
117 .podr = (void __iomem *)MCFGPIO_PORTA,
118 .ppdr = (void __iomem *)MCFGPIO_PORTAP,
119 .setr = (void __iomem *)MCFGPIO_SETA,
120 .clrr = (void __iomem *)MCFGPIO_CLRA,
121 },
122 {
123 .gpio_chip = {
124 .label = "B",
125 .request = mcf_gpio_request,
126 .free = mcf_gpio_free,
127 .direction_input = mcf_gpio_direction_input,
128 .direction_output = mcf_gpio_direction_output,
129 .get = mcf_gpio_get_value,
130 .set = mcf_gpio_set_value_fast,
131 .base = 48,
132 .ngpio = 8,
133 },
134 .pddr = (void __iomem *)MCFGPIO_DDRB,
135 .podr = (void __iomem *)MCFGPIO_PORTB,
136 .ppdr = (void __iomem *)MCFGPIO_PORTBP,
137 .setr = (void __iomem *)MCFGPIO_SETB,
138 .clrr = (void __iomem *)MCFGPIO_CLRB,
139 },
140 {
141 .gpio_chip = {
142 .label = "C",
143 .request = mcf_gpio_request,
144 .free = mcf_gpio_free,
145 .direction_input = mcf_gpio_direction_input,
146 .direction_output = mcf_gpio_direction_output,
147 .get = mcf_gpio_get_value,
148 .set = mcf_gpio_set_value_fast,
149 .base = 56,
150 .ngpio = 8,
151 },
152 .pddr = (void __iomem *)MCFGPIO_DDRC,
153 .podr = (void __iomem *)MCFGPIO_PORTC,
154 .ppdr = (void __iomem *)MCFGPIO_PORTCP,
155 .setr = (void __iomem *)MCFGPIO_SETC,
156 .clrr = (void __iomem *)MCFGPIO_CLRC,
157 },
158 {
159 .gpio_chip = {
160 .label = "D",
161 .request = mcf_gpio_request,
162 .free = mcf_gpio_free,
163 .direction_input = mcf_gpio_direction_input,
164 .direction_output = mcf_gpio_direction_output,
165 .get = mcf_gpio_get_value,
166 .set = mcf_gpio_set_value_fast,
167 .base = 64,
168 .ngpio = 8,
169 },
170 .pddr = (void __iomem *)MCFGPIO_DDRD,
171 .podr = (void __iomem *)MCFGPIO_PORTD,
172 .ppdr = (void __iomem *)MCFGPIO_PORTDP,
173 .setr = (void __iomem *)MCFGPIO_SETD,
174 .clrr = (void __iomem *)MCFGPIO_CLRD,
175 },
176 {
177 .gpio_chip = {
178 .label = "E",
179 .request = mcf_gpio_request,
180 .free = mcf_gpio_free,
181 .direction_input = mcf_gpio_direction_input,
182 .direction_output = mcf_gpio_direction_output,
183 .get = mcf_gpio_get_value,
184 .set = mcf_gpio_set_value_fast,
185 .base = 72,
186 .ngpio = 8,
187 },
188 .pddr = (void __iomem *)MCFGPIO_DDRE,
189 .podr = (void __iomem *)MCFGPIO_PORTE,
190 .ppdr = (void __iomem *)MCFGPIO_PORTEP,
191 .setr = (void __iomem *)MCFGPIO_SETE,
192 .clrr = (void __iomem *)MCFGPIO_CLRE,
193 },
194 {
195 .gpio_chip = {
196 .label = "F",
197 .request = mcf_gpio_request,
198 .free = mcf_gpio_free,
199 .direction_input = mcf_gpio_direction_input,
200 .direction_output = mcf_gpio_direction_output,
201 .get = mcf_gpio_get_value,
202 .set = mcf_gpio_set_value_fast,
203 .base = 80,
204 .ngpio = 8,
205 },
206 .pddr = (void __iomem *)MCFGPIO_DDRF,
207 .podr = (void __iomem *)MCFGPIO_PORTF,
208 .ppdr = (void __iomem *)MCFGPIO_PORTFP,
209 .setr = (void __iomem *)MCFGPIO_SETF,
210 .clrr = (void __iomem *)MCFGPIO_CLRF,
211 },
212 {
213 .gpio_chip = {
214 .label = "G",
215 .request = mcf_gpio_request,
216 .free = mcf_gpio_free,
217 .direction_input = mcf_gpio_direction_input,
218 .direction_output = mcf_gpio_direction_output,
219 .get = mcf_gpio_get_value,
220 .set = mcf_gpio_set_value_fast,
221 .base = 88,
222 .ngpio = 8,
223 },
224 .pddr = (void __iomem *)MCFGPIO_DDRG,
225 .podr = (void __iomem *)MCFGPIO_PORTG,
226 .ppdr = (void __iomem *)MCFGPIO_PORTGP,
227 .setr = (void __iomem *)MCFGPIO_SETG,
228 .clrr = (void __iomem *)MCFGPIO_CLRG,
229 },
230 {
231 .gpio_chip = {
232 .label = "H",
233 .request = mcf_gpio_request,
234 .free = mcf_gpio_free,
235 .direction_input = mcf_gpio_direction_input,
236 .direction_output = mcf_gpio_direction_output,
237 .get = mcf_gpio_get_value,
238 .set = mcf_gpio_set_value_fast,
239 .base = 96,
240 .ngpio = 8,
241 },
242 .pddr = (void __iomem *)MCFGPIO_DDRH,
243 .podr = (void __iomem *)MCFGPIO_PORTH,
244 .ppdr = (void __iomem *)MCFGPIO_PORTHP,
245 .setr = (void __iomem *)MCFGPIO_SETH,
246 .clrr = (void __iomem *)MCFGPIO_CLRH,
247 },
248 {
249 .gpio_chip = {
250 .label = "J",
251 .request = mcf_gpio_request,
252 .free = mcf_gpio_free,
253 .direction_input = mcf_gpio_direction_input,
254 .direction_output = mcf_gpio_direction_output,
255 .get = mcf_gpio_get_value,
256 .set = mcf_gpio_set_value_fast,
257 .base = 104,
258 .ngpio = 8,
259 },
260 .pddr = (void __iomem *)MCFGPIO_DDRJ,
261 .podr = (void __iomem *)MCFGPIO_PORTJ,
262 .ppdr = (void __iomem *)MCFGPIO_PORTJP,
263 .setr = (void __iomem *)MCFGPIO_SETJ,
264 .clrr = (void __iomem *)MCFGPIO_CLRJ,
265 },
266 {
267 .gpio_chip = {
268 .label = "DD",
269 .request = mcf_gpio_request,
270 .free = mcf_gpio_free,
271 .direction_input = mcf_gpio_direction_input,
272 .direction_output = mcf_gpio_direction_output,
273 .get = mcf_gpio_get_value,
274 .set = mcf_gpio_set_value_fast,
275 .base = 112,
276 .ngpio = 8,
277 },
278 .pddr = (void __iomem *)MCFGPIO_DDRDD,
279 .podr = (void __iomem *)MCFGPIO_PORTDD,
280 .ppdr = (void __iomem *)MCFGPIO_PORTDDP,
281 .setr = (void __iomem *)MCFGPIO_SETDD,
282 .clrr = (void __iomem *)MCFGPIO_CLRDD,
283 },
284 {
285 .gpio_chip = {
286 .label = "EH",
287 .request = mcf_gpio_request,
288 .free = mcf_gpio_free,
289 .direction_input = mcf_gpio_direction_input,
290 .direction_output = mcf_gpio_direction_output,
291 .get = mcf_gpio_get_value,
292 .set = mcf_gpio_set_value_fast,
293 .base = 120,
294 .ngpio = 8,
295 },
296 .pddr = (void __iomem *)MCFGPIO_DDREH,
297 .podr = (void __iomem *)MCFGPIO_PORTEH,
298 .ppdr = (void __iomem *)MCFGPIO_PORTEHP,
299 .setr = (void __iomem *)MCFGPIO_SETEH,
300 .clrr = (void __iomem *)MCFGPIO_CLREH,
301 },
302 {
303 .gpio_chip = {
304 .label = "EL",
305 .request = mcf_gpio_request,
306 .free = mcf_gpio_free,
307 .direction_input = mcf_gpio_direction_input,
308 .direction_output = mcf_gpio_direction_output,
309 .get = mcf_gpio_get_value,
310 .set = mcf_gpio_set_value_fast,
311 .base = 128,
312 .ngpio = 8,
313 },
314 .pddr = (void __iomem *)MCFGPIO_DDREL,
315 .podr = (void __iomem *)MCFGPIO_PORTEL,
316 .ppdr = (void __iomem *)MCFGPIO_PORTELP,
317 .setr = (void __iomem *)MCFGPIO_SETEL,
318 .clrr = (void __iomem *)MCFGPIO_CLREL,
319 },
320 {
321 .gpio_chip = {
322 .label = "AS",
323 .request = mcf_gpio_request,
324 .free = mcf_gpio_free,
325 .direction_input = mcf_gpio_direction_input,
326 .direction_output = mcf_gpio_direction_output,
327 .get = mcf_gpio_get_value,
328 .set = mcf_gpio_set_value_fast,
329 .base = 136,
330 .ngpio = 6,
331 },
332 .pddr = (void __iomem *)MCFGPIO_DDRAS,
333 .podr = (void __iomem *)MCFGPIO_PORTAS,
334 .ppdr = (void __iomem *)MCFGPIO_PORTASP,
335 .setr = (void __iomem *)MCFGPIO_SETAS,
336 .clrr = (void __iomem *)MCFGPIO_CLRAS,
337 },
338 {
339 .gpio_chip = {
340 .label = "QS",
341 .request = mcf_gpio_request,
342 .free = mcf_gpio_free,
343 .direction_input = mcf_gpio_direction_input,
344 .direction_output = mcf_gpio_direction_output,
345 .get = mcf_gpio_get_value,
346 .set = mcf_gpio_set_value_fast,
347 .base = 144,
348 .ngpio = 7,
349 },
350 .pddr = (void __iomem *)MCFGPIO_DDRQS,
351 .podr = (void __iomem *)MCFGPIO_PORTQS,
352 .ppdr = (void __iomem *)MCFGPIO_PORTQSP,
353 .setr = (void __iomem *)MCFGPIO_SETQS,
354 .clrr = (void __iomem *)MCFGPIO_CLRQS,
355 },
356 {
357 .gpio_chip = {
358 .label = "SD",
359 .request = mcf_gpio_request,
360 .free = mcf_gpio_free,
361 .direction_input = mcf_gpio_direction_input,
362 .direction_output = mcf_gpio_direction_output,
363 .get = mcf_gpio_get_value,
364 .set = mcf_gpio_set_value_fast,
365 .base = 152,
366 .ngpio = 6,
367 },
368 .pddr = (void __iomem *)MCFGPIO_DDRSD,
369 .podr = (void __iomem *)MCFGPIO_PORTSD,
370 .ppdr = (void __iomem *)MCFGPIO_PORTSDP,
371 .setr = (void __iomem *)MCFGPIO_SETSD,
372 .clrr = (void __iomem *)MCFGPIO_CLRSD,
373 },
374 {
375 .gpio_chip = {
376 .label = "TC",
377 .request = mcf_gpio_request,
378 .free = mcf_gpio_free,
379 .direction_input = mcf_gpio_direction_input,
380 .direction_output = mcf_gpio_direction_output,
381 .get = mcf_gpio_get_value,
382 .set = mcf_gpio_set_value_fast,
383 .base = 160,
384 .ngpio = 4,
385 },
386 .pddr = (void __iomem *)MCFGPIO_DDRTC,
387 .podr = (void __iomem *)MCFGPIO_PORTTC,
388 .ppdr = (void __iomem *)MCFGPIO_PORTTCP,
389 .setr = (void __iomem *)MCFGPIO_SETTC,
390 .clrr = (void __iomem *)MCFGPIO_CLRTC,
391 },
392 {
393 .gpio_chip = {
394 .label = "TD",
395 .request = mcf_gpio_request,
396 .free = mcf_gpio_free,
397 .direction_input = mcf_gpio_direction_input,
398 .direction_output = mcf_gpio_direction_output,
399 .get = mcf_gpio_get_value,
400 .set = mcf_gpio_set_value_fast,
401 .base = 168,
402 .ngpio = 4,
403 },
404 .pddr = (void __iomem *)MCFGPIO_DDRTD,
405 .podr = (void __iomem *)MCFGPIO_PORTTD,
406 .ppdr = (void __iomem *)MCFGPIO_PORTTDP,
407 .setr = (void __iomem *)MCFGPIO_SETTD,
408 .clrr = (void __iomem *)MCFGPIO_CLRTD,
409 },
410 {
411 .gpio_chip = {
412 .label = "UA",
413 .request = mcf_gpio_request,
414 .free = mcf_gpio_free,
415 .direction_input = mcf_gpio_direction_input,
416 .direction_output = mcf_gpio_direction_output,
417 .get = mcf_gpio_get_value,
418 .set = mcf_gpio_set_value_fast,
419 .base = 176,
420 .ngpio = 4,
421 },
422 .pddr = (void __iomem *)MCFGPIO_DDRUA,
423 .podr = (void __iomem *)MCFGPIO_PORTUA,
424 .ppdr = (void __iomem *)MCFGPIO_PORTUAP,
425 .setr = (void __iomem *)MCFGPIO_SETUA,
426 .clrr = (void __iomem *)MCFGPIO_CLRUA,
427 },
428};
429
430static int __init mcf_gpio_init(void)
431{
432 unsigned i = 0;
433 while (i < ARRAY_SIZE(mcf_gpio_chips))
434 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
435 return 0;
436}
437
438core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5307/Makefile b/arch/m68k/platform/5307/Makefile
deleted file mode 100644
index d4293b791f2..00000000000
--- a/arch/m68k/platform/5307/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
1#
2# Makefile for the m68knommu kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y += config.o gpio.o
18obj-$(CONFIG_NETtel) += nettel.o
19obj-$(CONFIG_CLEOPATRA) += nettel.o
20
diff --git a/arch/m68k/platform/5307/gpio.c b/arch/m68k/platform/5307/gpio.c
deleted file mode 100644
index 5850612b4a3..00000000000
--- a/arch/m68k/platform/5307/gpio.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/532x/Makefile b/arch/m68k/platform/532x/Makefile
deleted file mode 100644
index ce01669399c..00000000000
--- a/arch/m68k/platform/532x/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17#obj-y := config.o usb-mcf532x.o spi-mcf532x.o
18obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/532x/gpio.c b/arch/m68k/platform/532x/gpio.c
deleted file mode 100644
index 212a85deac9..00000000000
--- a/arch/m68k/platform/532x/gpio.c
+++ /dev/null
@@ -1,337 +0,0 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = (void __iomem *) MCFEPORT_EPDDR,
36 .podr = (void __iomem *) MCFEPORT_EPDR,
37 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
38 },
39 {
40 .gpio_chip = {
41 .label = "FECH",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value_fast,
48 .base = 8,
49 .ngpio = 8,
50 },
51 .pddr = (void __iomem *) MCFGPIO_PDDR_FECH,
52 .podr = (void __iomem *) MCFGPIO_PODR_FECH,
53 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
54 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
55 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH,
56 },
57 {
58 .gpio_chip = {
59 .label = "FECL",
60 .request = mcf_gpio_request,
61 .free = mcf_gpio_free,
62 .direction_input = mcf_gpio_direction_input,
63 .direction_output = mcf_gpio_direction_output,
64 .get = mcf_gpio_get_value,
65 .set = mcf_gpio_set_value_fast,
66 .base = 16,
67 .ngpio = 8,
68 },
69 .pddr = (void __iomem *) MCFGPIO_PDDR_FECL,
70 .podr = (void __iomem *) MCFGPIO_PODR_FECL,
71 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
72 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
73 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL,
74 },
75 {
76 .gpio_chip = {
77 .label = "SSI",
78 .request = mcf_gpio_request,
79 .free = mcf_gpio_free,
80 .direction_input = mcf_gpio_direction_input,
81 .direction_output = mcf_gpio_direction_output,
82 .get = mcf_gpio_get_value,
83 .set = mcf_gpio_set_value_fast,
84 .base = 24,
85 .ngpio = 5,
86 },
87 .pddr = (void __iomem *) MCFGPIO_PDDR_SSI,
88 .podr = (void __iomem *) MCFGPIO_PODR_SSI,
89 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SSI,
90 .setr = (void __iomem *) MCFGPIO_PPDSDR_SSI,
91 .clrr = (void __iomem *) MCFGPIO_PCLRR_SSI,
92 },
93 {
94 .gpio_chip = {
95 .label = "BUSCTL",
96 .request = mcf_gpio_request,
97 .free = mcf_gpio_free,
98 .direction_input = mcf_gpio_direction_input,
99 .direction_output = mcf_gpio_direction_output,
100 .get = mcf_gpio_get_value,
101 .set = mcf_gpio_set_value_fast,
102 .base = 32,
103 .ngpio = 4,
104 },
105 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
106 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
107 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
108 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
109 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
110 },
111 {
112 .gpio_chip = {
113 .label = "BE",
114 .request = mcf_gpio_request,
115 .free = mcf_gpio_free,
116 .direction_input = mcf_gpio_direction_input,
117 .direction_output = mcf_gpio_direction_output,
118 .get = mcf_gpio_get_value,
119 .set = mcf_gpio_set_value_fast,
120 .base = 40,
121 .ngpio = 4,
122 },
123 .pddr = (void __iomem *) MCFGPIO_PDDR_BE,
124 .podr = (void __iomem *) MCFGPIO_PODR_BE,
125 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE,
126 .setr = (void __iomem *) MCFGPIO_PPDSDR_BE,
127 .clrr = (void __iomem *) MCFGPIO_PCLRR_BE,
128 },
129 {
130 .gpio_chip = {
131 .label = "CS",
132 .request = mcf_gpio_request,
133 .free = mcf_gpio_free,
134 .direction_input = mcf_gpio_direction_input,
135 .direction_output = mcf_gpio_direction_output,
136 .get = mcf_gpio_get_value,
137 .set = mcf_gpio_set_value_fast,
138 .base = 49,
139 .ngpio = 5,
140 },
141 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
142 .podr = (void __iomem *) MCFGPIO_PODR_CS,
143 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
144 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
145 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
146 },
147 {
148 .gpio_chip = {
149 .label = "PWM",
150 .request = mcf_gpio_request,
151 .free = mcf_gpio_free,
152 .direction_input = mcf_gpio_direction_input,
153 .direction_output = mcf_gpio_direction_output,
154 .get = mcf_gpio_get_value,
155 .set = mcf_gpio_set_value_fast,
156 .base = 58,
157 .ngpio = 4,
158 },
159 .pddr = (void __iomem *) MCFGPIO_PDDR_PWM,
160 .podr = (void __iomem *) MCFGPIO_PODR_PWM,
161 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_PWM,
162 .setr = (void __iomem *) MCFGPIO_PPDSDR_PWM,
163 .clrr = (void __iomem *) MCFGPIO_PCLRR_PWM,
164 },
165 {
166 .gpio_chip = {
167 .label = "FECI2C",
168 .request = mcf_gpio_request,
169 .free = mcf_gpio_free,
170 .direction_input = mcf_gpio_direction_input,
171 .direction_output = mcf_gpio_direction_output,
172 .get = mcf_gpio_get_value,
173 .set = mcf_gpio_set_value_fast,
174 .base = 64,
175 .ngpio = 4,
176 },
177 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
178 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
179 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
180 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
181 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
182 },
183 {
184 .gpio_chip = {
185 .label = "UART",
186 .request = mcf_gpio_request,
187 .free = mcf_gpio_free,
188 .direction_input = mcf_gpio_direction_input,
189 .direction_output = mcf_gpio_direction_output,
190 .get = mcf_gpio_get_value,
191 .set = mcf_gpio_set_value_fast,
192 .base = 72,
193 .ngpio = 8,
194 },
195 .pddr = (void __iomem *) MCFGPIO_PDDR_UART,
196 .podr = (void __iomem *) MCFGPIO_PODR_UART,
197 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART,
198 .setr = (void __iomem *) MCFGPIO_PPDSDR_UART,
199 .clrr = (void __iomem *) MCFGPIO_PCLRR_UART,
200 },
201 {
202 .gpio_chip = {
203 .label = "QSPI",
204 .request = mcf_gpio_request,
205 .free = mcf_gpio_free,
206 .direction_input = mcf_gpio_direction_input,
207 .direction_output = mcf_gpio_direction_output,
208 .get = mcf_gpio_get_value,
209 .set = mcf_gpio_set_value_fast,
210 .base = 80,
211 .ngpio = 6,
212 },
213 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
214 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
215 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
216 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
217 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
218 },
219 {
220 .gpio_chip = {
221 .label = "TIMER",
222 .request = mcf_gpio_request,
223 .free = mcf_gpio_free,
224 .direction_input = mcf_gpio_direction_input,
225 .direction_output = mcf_gpio_direction_output,
226 .get = mcf_gpio_get_value,
227 .set = mcf_gpio_set_value_fast,
228 .base = 88,
229 .ngpio = 4,
230 },
231 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
232 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
233 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
234 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
235 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
236 },
237 {
238 .gpio_chip = {
239 .label = "LCDDATAH",
240 .request = mcf_gpio_request,
241 .free = mcf_gpio_free,
242 .direction_input = mcf_gpio_direction_input,
243 .direction_output = mcf_gpio_direction_output,
244 .get = mcf_gpio_get_value,
245 .set = mcf_gpio_set_value_fast,
246 .base = 96,
247 .ngpio = 2,
248 },
249 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAH,
250 .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAH,
251 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
252 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
253 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAH,
254 },
255 {
256 .gpio_chip = {
257 .label = "LCDDATAM",
258 .request = mcf_gpio_request,
259 .free = mcf_gpio_free,
260 .direction_input = mcf_gpio_direction_input,
261 .direction_output = mcf_gpio_direction_output,
262 .get = mcf_gpio_get_value,
263 .set = mcf_gpio_set_value_fast,
264 .base = 104,
265 .ngpio = 8,
266 },
267 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAM,
268 .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAM,
269 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
270 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
271 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAM,
272 },
273 {
274 .gpio_chip = {
275 .label = "LCDDATAL",
276 .request = mcf_gpio_request,
277 .free = mcf_gpio_free,
278 .direction_input = mcf_gpio_direction_input,
279 .direction_output = mcf_gpio_direction_output,
280 .get = mcf_gpio_get_value,
281 .set = mcf_gpio_set_value_fast,
282 .base = 112,
283 .ngpio = 8,
284 },
285 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAL,
286 .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAL,
287 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
288 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
289 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAL,
290 },
291 {
292 .gpio_chip = {
293 .label = "LCDCTLH",
294 .request = mcf_gpio_request,
295 .free = mcf_gpio_free,
296 .direction_input = mcf_gpio_direction_input,
297 .direction_output = mcf_gpio_direction_output,
298 .get = mcf_gpio_get_value,
299 .set = mcf_gpio_set_value_fast,
300 .base = 120,
301 .ngpio = 1,
302 },
303 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLH,
304 .podr = (void __iomem *) MCFGPIO_PODR_LCDCTLH,
305 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
306 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
307 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLH,
308 },
309 {
310 .gpio_chip = {
311 .label = "LCDCTLL",
312 .request = mcf_gpio_request,
313 .free = mcf_gpio_free,
314 .direction_input = mcf_gpio_direction_input,
315 .direction_output = mcf_gpio_direction_output,
316 .get = mcf_gpio_get_value,
317 .set = mcf_gpio_set_value_fast,
318 .base = 128,
319 .ngpio = 8,
320 },
321 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLL,
322 .podr = (void __iomem *) MCFGPIO_PODR_LCDCTLL,
323 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
324 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
325 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLL,
326 },
327};
328
329static int __init mcf_gpio_init(void)
330{
331 unsigned i = 0;
332 while (i < ARRAY_SIZE(mcf_gpio_chips))
333 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
334 return 0;
335}
336
337core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5407/Makefile b/arch/m68k/platform/5407/Makefile
deleted file mode 100644
index e83fe148edd..00000000000
--- a/arch/m68k/platform/5407/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
18
diff --git a/arch/m68k/platform/5407/gpio.c b/arch/m68k/platform/5407/gpio.c
deleted file mode 100644
index 5850612b4a3..00000000000
--- a/arch/m68k/platform/5407/gpio.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/54xx/Makefile b/arch/m68k/platform/54xx/Makefile
deleted file mode 100644
index 6cfd090ec3c..00000000000
--- a/arch/m68k/platform/54xx/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o
18obj-$(CONFIG_FIREBEE) += firebee.o
19
diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile
index a0815c61dec..76d389d9a84 100644
--- a/arch/m68k/platform/coldfire/Makefile
+++ b/arch/m68k/platform/coldfire/Makefile
@@ -15,18 +15,22 @@
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-$(CONFIG_COLDFIRE) += cache.o clk.o device.o dma.o entry.o vectors.o 17obj-$(CONFIG_COLDFIRE) += cache.o clk.o device.o dma.o entry.o vectors.o
18obj-$(CONFIG_M5206) += timers.o intc.o reset.o 18obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o
19obj-$(CONFIG_M5206e) += timers.o intc.o reset.o 19obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o
20obj-$(CONFIG_M520x) += pit.o intc-simr.o reset.o 20obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o
21obj-$(CONFIG_M523x) += pit.o dma_timer.o intc-2.o reset.o 21obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o
22obj-$(CONFIG_M5249) += timers.o intc.o reset.o 22obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o
23obj-$(CONFIG_M527x) += pit.o intc-2.o reset.o 23obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
24obj-$(CONFIG_M5272) += timers.o 24obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
25obj-$(CONFIG_M528x) += pit.o intc-2.o reset.o 25obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
26obj-$(CONFIG_M5307) += timers.o intc.o reset.o 26obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
27obj-$(CONFIG_M532x) += timers.o intc-simr.o reset.o 27obj-$(CONFIG_M532x) += m532x.o timers.o intc-simr.o reset.o
28obj-$(CONFIG_M5407) += timers.o intc.o reset.o 28obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o
29obj-$(CONFIG_M54xx) += sltimers.o intc-2.o 29obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o
30
31obj-$(CONFIG_NETtel) += nettel.o
32obj-$(CONFIG_CLEOPATRA) += nettel.o
33obj-$(CONFIG_FIREBEE) += firebee.o
30 34
31obj-y += pinmux.o gpio.o 35obj-y += pinmux.o gpio.o
32extra-y := head.o 36extra-y := head.o
diff --git a/arch/m68k/platform/54xx/firebee.c b/arch/m68k/platform/coldfire/firebee.c
index 46d50534f98..46d50534f98 100644
--- a/arch/m68k/platform/54xx/firebee.c
+++ b/arch/m68k/platform/coldfire/firebee.c
diff --git a/arch/m68k/platform/coldfire/gpio.c b/arch/m68k/platform/coldfire/gpio.c
index 292a1a5a2d7..4c8c42450a4 100644
--- a/arch/m68k/platform/coldfire/gpio.c
+++ b/arch/m68k/platform/coldfire/gpio.c
@@ -122,6 +122,10 @@ struct bus_type mcf_gpio_subsys = {
122 122
123static int __init mcf_gpio_sysinit(void) 123static int __init mcf_gpio_sysinit(void)
124{ 124{
125 unsigned int i = 0;
126
127 while (i < mcf_gpio_chips_size)
128 gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
125 return subsys_system_register(&mcf_gpio_subsys, NULL); 129 return subsys_system_register(&mcf_gpio_subsys, NULL);
126} 130}
127 131
diff --git a/arch/m68k/platform/5249/intc2.c b/arch/m68k/platform/coldfire/intc-5249.c
index f343bf7bf5b..f343bf7bf5b 100644
--- a/arch/m68k/platform/5249/intc2.c
+++ b/arch/m68k/platform/coldfire/intc-5249.c
diff --git a/arch/m68k/platform/5272/intc.c b/arch/m68k/platform/coldfire/intc-5272.c
index 7160e618b0a..7160e618b0a 100644
--- a/arch/m68k/platform/5272/intc.c
+++ b/arch/m68k/platform/coldfire/intc-5272.c
diff --git a/arch/m68k/platform/5206/config.c b/arch/m68k/platform/coldfire/m5206.c
index 6bfbeebd231..a8b81df653f 100644
--- a/arch/m68k/platform/5206/config.c
+++ b/arch/m68k/platform/coldfire/m5206.c
@@ -16,6 +16,15 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfgpio.h>
20
21/***************************************************************************/
22
23struct mcf_gpio_chip mcf_gpio_chips[] = {
24 MCFGPS(PP, 0, 8, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
25};
26
27unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
19 28
20/***************************************************************************/ 29/***************************************************************************/
21 30
diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/coldfire/m520x.c
index 09df4b89e8b..3264b8883d5 100644
--- a/arch/m68k/platform/520x/config.c
+++ b/arch/m68k/platform/coldfire/m520x.c
@@ -19,6 +19,22 @@
19#include <asm/coldfire.h> 19#include <asm/coldfire.h>
20#include <asm/mcfsim.h> 20#include <asm/mcfsim.h>
21#include <asm/mcfuart.h> 21#include <asm/mcfuart.h>
22#include <asm/mcfgpio.h>
23
24/***************************************************************************/
25
26struct mcf_gpio_chip mcf_gpio_chips[] = {
27 MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
28 MCFGPF(CS, 9, 3),
29 MCFGPF(FECI2C, 16, 4),
30 MCFGPF(QSPI, 24, 4),
31 MCFGPF(TIMER, 32, 4),
32 MCFGPF(UART, 40, 8),
33 MCFGPF(FECH, 48, 8),
34 MCFGPF(FECL, 56, 8),
35};
36
37unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
22 38
23/***************************************************************************/ 39/***************************************************************************/
24 40
diff --git a/arch/m68k/platform/523x/config.c b/arch/m68k/platform/coldfire/m523x.c
index d47dfd8f50a..5d57a424941 100644
--- a/arch/m68k/platform/523x/config.c
+++ b/arch/m68k/platform/coldfire/m523x.c
@@ -19,6 +19,28 @@
19#include <asm/machdep.h> 19#include <asm/machdep.h>
20#include <asm/coldfire.h> 20#include <asm/coldfire.h>
21#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
22#include <asm/mcfgpio.h>
23
24/***************************************************************************/
25
26struct mcf_gpio_chip mcf_gpio_chips[] = {
27 MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
28 MCFGPF(ADDR, 13, 3),
29 MCFGPF(DATAH, 16, 8),
30 MCFGPF(DATAL, 24, 8),
31 MCFGPF(BUSCTL, 32, 8),
32 MCFGPF(BS, 40, 4),
33 MCFGPF(CS, 49, 7),
34 MCFGPF(SDRAM, 56, 6),
35 MCFGPF(FECI2C, 64, 4),
36 MCFGPF(UARTH, 72, 2),
37 MCFGPF(UARTL, 80, 8),
38 MCFGPF(QSPI, 88, 5),
39 MCFGPF(TIMER, 96, 8),
40 MCFGPF(ETPU, 104, 3),
41};
42
43unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
22 44
23/***************************************************************************/ 45/***************************************************************************/
24 46
diff --git a/arch/m68k/platform/5249/config.c b/arch/m68k/platform/coldfire/m5249.c
index 300e729a58d..fdfa1edfd1a 100644
--- a/arch/m68k/platform/5249/config.c
+++ b/arch/m68k/platform/coldfire/m5249.c
@@ -16,6 +16,16 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfgpio.h>
20
21/***************************************************************************/
22
23struct mcf_gpio_chip mcf_gpio_chips[] = {
24 MCFGPS(GPIO0, 0, 32, MCFSIM2_GPIOENABLE, MCFSIM2_GPIOWRITE, MCFSIM2_GPIOREAD),
25 MCFGPS(GPIO1, 32, 32, MCFSIM2_GPIO1ENABLE, MCFSIM2_GPIO1WRITE, MCFSIM2_GPIO1READ),
26};
27
28unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
19 29
20/***************************************************************************/ 30/***************************************************************************/
21 31
diff --git a/arch/m68k/platform/5272/config.c b/arch/m68k/platform/coldfire/m5272.c
index e68bc7a148e..43e36060da1 100644
--- a/arch/m68k/platform/5272/config.c
+++ b/arch/m68k/platform/coldfire/m5272.c
@@ -19,6 +19,7 @@
19#include <asm/coldfire.h> 19#include <asm/coldfire.h>
20#include <asm/mcfsim.h> 20#include <asm/mcfsim.h>
21#include <asm/mcfuart.h> 21#include <asm/mcfuart.h>
22#include <asm/mcfgpio.h>
22 23
23/***************************************************************************/ 24/***************************************************************************/
24 25
@@ -30,6 +31,16 @@ unsigned char ledbank = 0xff;
30 31
31/***************************************************************************/ 32/***************************************************************************/
32 33
34struct mcf_gpio_chip mcf_gpio_chips[] = {
35 MCFGPS(PA, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
36 MCFGPS(PB, 16, 16, MCFSIM_PBDDR, MCFSIM_PBDAT, MCFSIM_PBDAT),
37 MCFGPS(Pc, 32, 16, MCFSIM_PCDDR, MCFSIM_PCDAT, MCFSIM_PCDAT),
38};
39
40unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
41
42/***************************************************************************/
43
33static void __init m5272_uarts_init(void) 44static void __init m5272_uarts_init(void)
34{ 45{
35 u32 v; 46 u32 v;
diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/coldfire/m527x.c
index b3cb378c5e9..9b0b66aabd1 100644
--- a/arch/m68k/platform/527x/config.c
+++ b/arch/m68k/platform/coldfire/m527x.c
@@ -20,6 +20,49 @@
20#include <asm/coldfire.h> 20#include <asm/coldfire.h>
21#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
22#include <asm/mcfuart.h> 22#include <asm/mcfuart.h>
23#include <asm/mcfgpio.h>
24
25/***************************************************************************/
26
27struct mcf_gpio_chip mcf_gpio_chips[] = {
28#if defined(CONFIG_M5271)
29 MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
30 MCFGPF(ADDR, 13, 3),
31 MCFGPF(DATAH, 16, 8),
32 MCFGPF(DATAL, 24, 8),
33 MCFGPF(BUSCTL, 32, 8),
34 MCFGPF(BS, 40, 4),
35 MCFGPF(CS, 49, 7),
36 MCFGPF(SDRAM, 56, 6),
37 MCFGPF(FECI2C, 64, 4),
38 MCFGPF(UARTH, 72, 2),
39 MCFGPF(UARTL, 80, 8),
40 MCFGPF(QSPI, 88, 5),
41 MCFGPF(TIMER, 96, 8),
42#elif defined(CONFIG_M5275)
43 MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
44 MCFGPF(BUSCTL, 8, 8),
45 MCFGPF(ADDR, 21, 3),
46 MCFGPF(CS, 25, 7),
47 MCFGPF(FEC0H, 32, 8),
48 MCFGPF(FEC0L, 40, 8),
49 MCFGPF(FECI2C, 48, 6),
50 MCFGPF(QSPI, 56, 7),
51 MCFGPF(SDRAM, 64, 8),
52 MCFGPF(TIMERH, 72, 4),
53 MCFGPF(TIMERL, 80, 4),
54 MCFGPF(UARTL, 88, 8),
55 MCFGPF(FEC1H, 96, 8),
56 MCFGPF(FEC1L, 104, 8),
57 MCFGPF(BS, 114, 2),
58 MCFGPF(IRQ, 121, 7),
59 MCFGPF(USBH, 128, 1),
60 MCFGPF(USBL, 136, 8),
61 MCFGPF(UARTH, 144, 4),
62#endif
63};
64
65unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
23 66
24/***************************************************************************/ 67/***************************************************************************/
25 68
diff --git a/arch/m68k/platform/528x/config.c b/arch/m68k/platform/coldfire/m528x.c
index c5f11ba49be..7ed1276b29d 100644
--- a/arch/m68k/platform/528x/config.c
+++ b/arch/m68k/platform/coldfire/m528x.c
@@ -21,6 +21,37 @@
21#include <asm/coldfire.h> 21#include <asm/coldfire.h>
22#include <asm/mcfsim.h> 22#include <asm/mcfsim.h>
23#include <asm/mcfuart.h> 23#include <asm/mcfuart.h>
24#include <asm/mcfgpio.h>
25
26/***************************************************************************/
27
28struct mcf_gpio_chip mcf_gpio_chips[] = {
29 MCFGPS(NQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
30 MCFGPS(TA, 8, 4, MCFGPTA_GPTDDR, MCFGPTA_GPTPORT, MCFGPTB_GPTPORT),
31 MCFGPS(TB, 16, 4, MCFGPTB_GPTDDR, MCFGPTB_GPTPORT, MCFGPTB_GPTPORT),
32 MCFGPS(QA, 24, 4, MCFQADC_DDRQA, MCFQADC_PORTQA, MCFQADC_PORTQA),
33 MCFGPS(QB, 32, 4, MCFQADC_DDRQB, MCFQADC_PORTQB, MCFQADC_PORTQB),
34 MCFGPF(A, 40, 8),
35 MCFGPF(B, 48, 8),
36 MCFGPF(C, 56, 8),
37 MCFGPF(D, 64, 8),
38 MCFGPF(E, 72, 8),
39 MCFGPF(F, 80, 8),
40 MCFGPF(G, 88, 8),
41 MCFGPF(H, 96, 8),
42 MCFGPF(J, 104, 8),
43 MCFGPF(DD, 112, 8),
44 MCFGPF(EH, 120, 8),
45 MCFGPF(EL, 128, 8),
46 MCFGPF(AS, 136, 6),
47 MCFGPF(QS, 144, 7),
48 MCFGPF(SD, 152, 6),
49 MCFGPF(TC, 160, 4),
50 MCFGPF(TD, 168, 4),
51 MCFGPF(UA, 176, 4),
52};
53
54unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
24 55
25/***************************************************************************/ 56/***************************************************************************/
26 57
diff --git a/arch/m68k/platform/5307/config.c b/arch/m68k/platform/coldfire/m5307.c
index a568d2870d1..93b484976ab 100644
--- a/arch/m68k/platform/5307/config.c
+++ b/arch/m68k/platform/coldfire/m5307.c
@@ -16,6 +16,7 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfgpio.h>
19#include <asm/mcfwdebug.h> 20#include <asm/mcfwdebug.h>
20 21
21/***************************************************************************/ 22/***************************************************************************/
@@ -28,6 +29,14 @@ unsigned char ledbank = 0xff;
28 29
29/***************************************************************************/ 30/***************************************************************************/
30 31
32struct mcf_gpio_chip mcf_gpio_chips[] = {
33 MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
34};
35
36unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
37
38/***************************************************************************/
39
31void __init config_BSP(char *commandp, int size) 40void __init config_BSP(char *commandp, int size)
32{ 41{
33#if defined(CONFIG_NETtel) || \ 42#if defined(CONFIG_NETtel) || \
diff --git a/arch/m68k/platform/532x/config.c b/arch/m68k/platform/coldfire/m532x.c
index 37082d02f2b..8e9476d59a6 100644
--- a/arch/m68k/platform/532x/config.c
+++ b/arch/m68k/platform/coldfire/m532x.c
@@ -26,10 +26,35 @@
26#include <asm/mcfsim.h> 26#include <asm/mcfsim.h>
27#include <asm/mcfuart.h> 27#include <asm/mcfuart.h>
28#include <asm/mcfdma.h> 28#include <asm/mcfdma.h>
29#include <asm/mcfgpio.h>
29#include <asm/mcfwdebug.h> 30#include <asm/mcfwdebug.h>
30 31
31/***************************************************************************/ 32/***************************************************************************/
32 33
34struct mcf_gpio_chip mcf_gpio_chips[] = {
35 MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
36 MCFGPF(FECH, 8, 8),
37 MCFGPF(FECL, 16, 8),
38 MCFGPF(SSI, 24, 5),
39 MCFGPF(BUSCTL, 32, 4),
40 MCFGPF(BE, 40, 4),
41 MCFGPF(CS, 49, 5),
42 MCFGPF(PWM, 58, 4),
43 MCFGPF(FECI2C, 64, 4),
44 MCFGPF(UART, 72, 8),
45 MCFGPF(QSPI, 80, 6),
46 MCFGPF(TIMER, 88, 4),
47 MCFGPF(LCDDATAH, 96, 2),
48 MCFGPF(LCDDATAM, 104, 8),
49 MCFGPF(LCDDATAL, 112, 8),
50 MCFGPF(LCDCTLH, 120, 1),
51 MCFGPF(LCDCTLL, 128, 8),
52};
53
54unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
55
56/***************************************************************************/
57
33#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 58#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
34 59
35static void __init m532x_qspi_init(void) 60static void __init m532x_qspi_init(void)
diff --git a/arch/m68k/platform/5407/config.c b/arch/m68k/platform/coldfire/m5407.c
index bb6c746ae81..faa6680b340 100644
--- a/arch/m68k/platform/5407/config.c
+++ b/arch/m68k/platform/coldfire/m5407.c
@@ -16,6 +16,15 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfgpio.h>
20
21/***************************************************************************/
22
23struct mcf_gpio_chip mcf_gpio_chips[] = {
24 MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
25};
26
27unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
19 28
20/***************************************************************************/ 29/***************************************************************************/
21 30
diff --git a/arch/m68k/platform/54xx/config.c b/arch/m68k/platform/coldfire/m54xx.c
index 2081c6cbb3d..20672dadb25 100644
--- a/arch/m68k/platform/54xx/config.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -21,12 +21,19 @@
21#include <asm/m54xxsim.h> 21#include <asm/m54xxsim.h>
22#include <asm/mcfuart.h> 22#include <asm/mcfuart.h>
23#include <asm/m54xxgpt.h> 23#include <asm/m54xxgpt.h>
24#include <asm/mcfgpio.h>
24#ifdef CONFIG_MMU 25#ifdef CONFIG_MMU
25#include <asm/mmu_context.h> 26#include <asm/mmu_context.h>
26#endif 27#endif
27 28
28/***************************************************************************/ 29/***************************************************************************/
29 30
31struct mcf_gpio_chip mcf_gpio_chips[] = { };
32
33unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
34
35/***************************************************************************/
36
30static void __init m54xx_uarts_init(void) 37static void __init m54xx_uarts_init(void)
31{ 38{
32 /* enable io pins */ 39 /* enable io pins */
diff --git a/arch/m68k/platform/5307/nettel.c b/arch/m68k/platform/coldfire/nettel.c
index e925ea4602f..e925ea4602f 100644
--- a/arch/m68k/platform/5307/nettel.c
+++ b/arch/m68k/platform/coldfire/nettel.c
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-24 03:16:43 -0400