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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /arch/m68k/platform/coldfire
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'arch/m68k/platform/coldfire')
-rw-r--r--arch/m68k/platform/coldfire/Makefile37
-rw-r--r--arch/m68k/platform/coldfire/clk.c85
-rw-r--r--arch/m68k/platform/coldfire/device.c369
-rw-r--r--arch/m68k/platform/coldfire/dma_timer.c5
-rw-r--r--arch/m68k/platform/coldfire/entry.S19
-rw-r--r--arch/m68k/platform/coldfire/firebee.c86
-rw-r--r--arch/m68k/platform/coldfire/gpio.c173
-rw-r--r--arch/m68k/platform/coldfire/head.S75
-rw-r--r--arch/m68k/platform/coldfire/intc-5249.c61
-rw-r--r--arch/m68k/platform/coldfire/intc-525x.c91
-rw-r--r--arch/m68k/platform/coldfire/intc-5272.c185
-rw-r--r--arch/m68k/platform/coldfire/intc-simr.c26
-rw-r--r--arch/m68k/platform/coldfire/intc.c28
-rw-r--r--arch/m68k/platform/coldfire/m5206.c58
-rw-r--r--arch/m68k/platform/coldfire/m520x.c184
-rw-r--r--arch/m68k/platform/coldfire/m523x.c88
-rw-r--r--arch/m68k/platform/coldfire/m5249.c128
-rw-r--r--arch/m68k/platform/coldfire/m525x.c86
-rw-r--r--arch/m68k/platform/coldfire/m5272.c133
-rw-r--r--arch/m68k/platform/coldfire/m527x.c128
-rw-r--r--arch/m68k/platform/coldfire/m528x.c134
-rw-r--r--arch/m68k/platform/coldfire/m5307.c78
-rw-r--r--arch/m68k/platform/coldfire/m532x.c593
-rw-r--r--arch/m68k/platform/coldfire/m5407.c53
-rw-r--r--arch/m68k/platform/coldfire/m5441x.c261
-rw-r--r--arch/m68k/platform/coldfire/m54xx.c129
-rw-r--r--arch/m68k/platform/coldfire/mcf8390.c38
-rw-r--r--arch/m68k/platform/coldfire/nettel.c153
-rw-r--r--arch/m68k/platform/coldfire/pci.c327
-rw-r--r--arch/m68k/platform/coldfire/pit.c10
-rw-r--r--arch/m68k/platform/coldfire/reset.c50
-rw-r--r--arch/m68k/platform/coldfire/sltimers.c24
-rw-r--r--arch/m68k/platform/coldfire/timers.c33
-rw-r--r--arch/m68k/platform/coldfire/vectors.c2
34 files changed, 153 insertions, 3777 deletions
diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile
index 02591a109f8..a8967baabd7 100644
--- a/arch/m68k/platform/coldfire/Makefile
+++ b/arch/m68k/platform/coldfire/Makefile
@@ -14,28 +14,19 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-$(CONFIG_COLDFIRE) += cache.o clk.o device.o dma.o entry.o vectors.o 17obj-$(CONFIG_COLDFIRE) += cache.o clk.o dma.o entry.o vectors.o
18obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o 18obj-$(CONFIG_M5206) += timers.o intc.o
19obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o 19obj-$(CONFIG_M5206e) += timers.o intc.o
20obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o 20obj-$(CONFIG_M520x) += pit.o intc-simr.o
21obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o 21obj-$(CONFIG_M523x) += pit.o dma_timer.o intc-2.o
22obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o 22obj-$(CONFIG_M5249) += timers.o intc.o
23obj-$(CONFIG_M525x) += m525x.o timers.o intc.o intc-525x.o reset.o 23obj-$(CONFIG_M527x) += pit.o intc-2.o
24obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o 24obj-$(CONFIG_M5272) += timers.o
25obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o 25obj-$(CONFIG_M528x) += pit.o intc-2.o
26obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o 26obj-$(CONFIG_M5307) += timers.o intc.o
27obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o 27obj-$(CONFIG_M532x) += timers.o intc-simr.o
28obj-$(CONFIG_M532x) += m532x.o timers.o intc-simr.o reset.o 28obj-$(CONFIG_M5407) += timers.o intc.o
29obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o 29obj-$(CONFIG_M54xx) += sltimers.o intc-2.o
30obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o
31obj-$(CONFIG_M5441x) += m5441x.o pit.o intc-simr.o reset.o
32 30
33obj-$(CONFIG_NETtel) += nettel.o 31obj-y += pinmux.o gpio.o
34obj-$(CONFIG_CLEOPATRA) += nettel.o
35obj-$(CONFIG_FIREBEE) += firebee.o
36obj-$(CONFIG_MCF8390) += mcf8390.o
37
38obj-$(CONFIG_PCI) += pci.o
39
40obj-y += gpio.o
41extra-y := head.o 32extra-y := head.o
diff --git a/arch/m68k/platform/coldfire/clk.c b/arch/m68k/platform/coldfire/clk.c
index fddfdccae63..9f1260c5e2a 100644
--- a/arch/m68k/platform/coldfire/clk.c
+++ b/arch/m68k/platform/coldfire/clk.c
@@ -10,115 +10,36 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/mutex.h>
15#include <linux/clk.h> 13#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include <asm/coldfire.h> 14#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20#include <asm/mcfclk.h>
21 15
22static DEFINE_SPINLOCK(clk_lock); 16/***************************************************************************/
23
24#ifdef MCFPM_PPMCR0
25/*
26 * For more advanced ColdFire parts that have clocks that can be enabled
27 * we supply enable/disable functions. These must properly define their
28 * clocks in their platform specific code.
29 */
30void __clk_init_enabled(struct clk *clk)
31{
32 clk->enabled = 1;
33 clk->clk_ops->enable(clk);
34}
35
36void __clk_init_disabled(struct clk *clk)
37{
38 clk->enabled = 0;
39 clk->clk_ops->disable(clk);
40}
41
42static void __clk_enable0(struct clk *clk)
43{
44 __raw_writeb(clk->slot, MCFPM_PPMCR0);
45}
46
47static void __clk_disable0(struct clk *clk)
48{
49 __raw_writeb(clk->slot, MCFPM_PPMSR0);
50}
51
52struct clk_ops clk_ops0 = {
53 .enable = __clk_enable0,
54 .disable = __clk_disable0,
55};
56
57#ifdef MCFPM_PPMCR1
58static void __clk_enable1(struct clk *clk)
59{
60 __raw_writeb(clk->slot, MCFPM_PPMCR1);
61}
62
63static void __clk_disable1(struct clk *clk)
64{
65 __raw_writeb(clk->slot, MCFPM_PPMSR1);
66}
67
68struct clk_ops clk_ops1 = {
69 .enable = __clk_enable1,
70 .disable = __clk_disable1,
71};
72#endif /* MCFPM_PPMCR1 */
73#endif /* MCFPM_PPMCR0 */
74 17
75struct clk *clk_get(struct device *dev, const char *id) 18struct clk *clk_get(struct device *dev, const char *id)
76{ 19{
77 const char *clk_name = dev ? dev_name(dev) : id ? id : NULL; 20 return NULL;
78 struct clk *clk;
79 unsigned i;
80
81 for (i = 0; (clk = mcf_clks[i]) != NULL; ++i)
82 if (!strcmp(clk->name, clk_name))
83 return clk;
84 pr_warn("clk_get: didn't find clock %s\n", clk_name);
85 return ERR_PTR(-ENOENT);
86} 21}
87EXPORT_SYMBOL(clk_get); 22EXPORT_SYMBOL(clk_get);
88 23
89int clk_enable(struct clk *clk) 24int clk_enable(struct clk *clk)
90{ 25{
91 unsigned long flags;
92 spin_lock_irqsave(&clk_lock, flags);
93 if ((clk->enabled++ == 0) && clk->clk_ops)
94 clk->clk_ops->enable(clk);
95 spin_unlock_irqrestore(&clk_lock, flags);
96
97 return 0; 26 return 0;
98} 27}
99EXPORT_SYMBOL(clk_enable); 28EXPORT_SYMBOL(clk_enable);
100 29
101void clk_disable(struct clk *clk) 30void clk_disable(struct clk *clk)
102{ 31{
103 unsigned long flags;
104 spin_lock_irqsave(&clk_lock, flags);
105 if ((--clk->enabled == 0) && clk->clk_ops)
106 clk->clk_ops->disable(clk);
107 spin_unlock_irqrestore(&clk_lock, flags);
108} 32}
109EXPORT_SYMBOL(clk_disable); 33EXPORT_SYMBOL(clk_disable);
110 34
111void clk_put(struct clk *clk) 35void clk_put(struct clk *clk)
112{ 36{
113 if (clk->enabled != 0)
114 pr_warn("clk_put %s still enabled\n", clk->name);
115} 37}
116EXPORT_SYMBOL(clk_put); 38EXPORT_SYMBOL(clk_put);
117 39
118unsigned long clk_get_rate(struct clk *clk) 40unsigned long clk_get_rate(struct clk *clk)
119{ 41{
120 return clk->rate; 42 return MCF_CLK;
121} 43}
122EXPORT_SYMBOL(clk_get_rate); 44EXPORT_SYMBOL(clk_get_rate);
123
124/***************************************************************************/ 45/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c
deleted file mode 100644
index 71ea4c02795..00000000000
--- a/arch/m68k/platform/coldfire/device.c
+++ /dev/null
@@ -1,369 +0,0 @@
1/*
2 * device.c -- common ColdFire SoC device support
3 *
4 * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/spi/spi.h>
15#include <linux/gpio.h>
16#include <linux/fec.h>
17#include <asm/traps.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20#include <asm/mcfuart.h>
21#include <asm/mcfqspi.h>
22
23/*
24 * All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
25 */
26static struct mcf_platform_uart mcf_uart_platform_data[] = {
27 {
28 .mapbase = MCFUART_BASE0,
29 .irq = MCF_IRQ_UART0,
30 },
31 {
32 .mapbase = MCFUART_BASE1,
33 .irq = MCF_IRQ_UART1,
34 },
35#ifdef MCFUART_BASE2
36 {
37 .mapbase = MCFUART_BASE2,
38 .irq = MCF_IRQ_UART2,
39 },
40#endif
41#ifdef MCFUART_BASE3
42 {
43 .mapbase = MCFUART_BASE3,
44 .irq = MCF_IRQ_UART3,
45 },
46#endif
47#ifdef MCFUART_BASE4
48 {
49 .mapbase = MCFUART_BASE4,
50 .irq = MCF_IRQ_UART4,
51 },
52#endif
53#ifdef MCFUART_BASE5
54 {
55 .mapbase = MCFUART_BASE5,
56 .irq = MCF_IRQ_UART5,
57 },
58#endif
59#ifdef MCFUART_BASE6
60 {
61 .mapbase = MCFUART_BASE6,
62 .irq = MCF_IRQ_UART6,
63 },
64#endif
65#ifdef MCFUART_BASE7
66 {
67 .mapbase = MCFUART_BASE7,
68 .irq = MCF_IRQ_UART7,
69 },
70#endif
71#ifdef MCFUART_BASE8
72 {
73 .mapbase = MCFUART_BASE8,
74 .irq = MCF_IRQ_UART8,
75 },
76#endif
77#ifdef MCFUART_BASE9
78 {
79 .mapbase = MCFUART_BASE9,
80 .irq = MCF_IRQ_UART9,
81 },
82#endif
83 { },
84};
85
86static struct platform_device mcf_uart = {
87 .name = "mcfuart",
88 .id = 0,
89 .dev.platform_data = mcf_uart_platform_data,
90};
91
92#ifdef CONFIG_FEC
93
94#ifdef CONFIG_M5441x
95#define FEC_NAME "enet-fec"
96static struct fec_platform_data fec_pdata = {
97 .phy = PHY_INTERFACE_MODE_RMII,
98};
99#define FEC_PDATA (&fec_pdata)
100#else
101#define FEC_NAME "fec"
102#define FEC_PDATA NULL
103#endif
104
105/*
106 * Some ColdFire cores contain the Fast Ethernet Controller (FEC)
107 * block. It is Freescale's own hardware block. Some ColdFires
108 * have 2 of these.
109 */
110static struct resource mcf_fec0_resources[] = {
111 {
112 .start = MCFFEC_BASE0,
113 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .start = MCF_IRQ_FECRX0,
118 .end = MCF_IRQ_FECRX0,
119 .flags = IORESOURCE_IRQ,
120 },
121 {
122 .start = MCF_IRQ_FECTX0,
123 .end = MCF_IRQ_FECTX0,
124 .flags = IORESOURCE_IRQ,
125 },
126 {
127 .start = MCF_IRQ_FECENTC0,
128 .end = MCF_IRQ_FECENTC0,
129 .flags = IORESOURCE_IRQ,
130 },
131};
132
133static struct platform_device mcf_fec0 = {
134 .name = FEC_NAME,
135 .id = 0,
136 .num_resources = ARRAY_SIZE(mcf_fec0_resources),
137 .resource = mcf_fec0_resources,
138 .dev.platform_data = FEC_PDATA,
139};
140
141#ifdef MCFFEC_BASE1
142static struct resource mcf_fec1_resources[] = {
143 {
144 .start = MCFFEC_BASE1,
145 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
146 .flags = IORESOURCE_MEM,
147 },
148 {
149 .start = MCF_IRQ_FECRX1,
150 .end = MCF_IRQ_FECRX1,
151 .flags = IORESOURCE_IRQ,
152 },
153 {
154 .start = MCF_IRQ_FECTX1,
155 .end = MCF_IRQ_FECTX1,
156 .flags = IORESOURCE_IRQ,
157 },
158 {
159 .start = MCF_IRQ_FECENTC1,
160 .end = MCF_IRQ_FECENTC1,
161 .flags = IORESOURCE_IRQ,
162 },
163};
164
165static struct platform_device mcf_fec1 = {
166 .name = FEC_NAME,
167 .id = 1,
168 .num_resources = ARRAY_SIZE(mcf_fec1_resources),
169 .resource = mcf_fec1_resources,
170 .dev.platform_data = FEC_PDATA,
171};
172#endif /* MCFFEC_BASE1 */
173#endif /* CONFIG_FEC */
174
175#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
176/*
177 * The ColdFire QSPI module is an SPI protocol hardware block used
178 * on a number of different ColdFire CPUs.
179 */
180static struct resource mcf_qspi_resources[] = {
181 {
182 .start = MCFQSPI_BASE,
183 .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
184 .flags = IORESOURCE_MEM,
185 },
186 {
187 .start = MCF_IRQ_QSPI,
188 .end = MCF_IRQ_QSPI,
189 .flags = IORESOURCE_IRQ,
190 },
191};
192
193static int mcf_cs_setup(struct mcfqspi_cs_control *cs_control)
194{
195 int status;
196
197 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
198 if (status) {
199 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
200 goto fail0;
201 }
202 status = gpio_direction_output(MCFQSPI_CS0, 1);
203 if (status) {
204 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
205 goto fail1;
206 }
207
208 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
209 if (status) {
210 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
211 goto fail1;
212 }
213 status = gpio_direction_output(MCFQSPI_CS1, 1);
214 if (status) {
215 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
216 goto fail2;
217 }
218
219 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
220 if (status) {
221 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
222 goto fail2;
223 }
224 status = gpio_direction_output(MCFQSPI_CS2, 1);
225 if (status) {
226 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
227 goto fail3;
228 }
229
230#ifdef MCFQSPI_CS3
231 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
232 if (status) {
233 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
234 goto fail3;
235 }
236 status = gpio_direction_output(MCFQSPI_CS3, 1);
237 if (status) {
238 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
239 gpio_free(MCFQSPI_CS3);
240 goto fail3;
241 }
242#endif
243
244 return 0;
245
246fail3:
247 gpio_free(MCFQSPI_CS2);
248fail2:
249 gpio_free(MCFQSPI_CS1);
250fail1:
251 gpio_free(MCFQSPI_CS0);
252fail0:
253 return status;
254}
255
256static void mcf_cs_teardown(struct mcfqspi_cs_control *cs_control)
257{
258#ifdef MCFQSPI_CS3
259 gpio_free(MCFQSPI_CS3);
260#endif
261 gpio_free(MCFQSPI_CS2);
262 gpio_free(MCFQSPI_CS1);
263 gpio_free(MCFQSPI_CS0);
264}
265
266static void mcf_cs_select(struct mcfqspi_cs_control *cs_control,
267 u8 chip_select, bool cs_high)
268{
269 switch (chip_select) {
270 case 0:
271 gpio_set_value(MCFQSPI_CS0, cs_high);
272 break;
273 case 1:
274 gpio_set_value(MCFQSPI_CS1, cs_high);
275 break;
276 case 2:
277 gpio_set_value(MCFQSPI_CS2, cs_high);
278 break;
279#ifdef MCFQSPI_CS3
280 case 3:
281 gpio_set_value(MCFQSPI_CS3, cs_high);
282 break;
283#endif
284 }
285}
286
287static void mcf_cs_deselect(struct mcfqspi_cs_control *cs_control,
288 u8 chip_select, bool cs_high)
289{
290 switch (chip_select) {
291 case 0:
292 gpio_set_value(MCFQSPI_CS0, !cs_high);
293 break;
294 case 1:
295 gpio_set_value(MCFQSPI_CS1, !cs_high);
296 break;
297 case 2:
298 gpio_set_value(MCFQSPI_CS2, !cs_high);
299 break;
300#ifdef MCFQSPI_CS3
301 case 3:
302 gpio_set_value(MCFQSPI_CS3, !cs_high);
303 break;
304#endif
305 }
306}
307
308static struct mcfqspi_cs_control mcf_cs_control = {
309 .setup = mcf_cs_setup,
310 .teardown = mcf_cs_teardown,
311 .select = mcf_cs_select,
312 .deselect = mcf_cs_deselect,
313};
314
315static struct mcfqspi_platform_data mcf_qspi_data = {
316 .bus_num = 0,
317 .num_chipselect = 4,
318 .cs_control = &mcf_cs_control,
319};
320
321static struct platform_device mcf_qspi = {
322 .name = "mcfqspi",
323 .id = 0,
324 .num_resources = ARRAY_SIZE(mcf_qspi_resources),
325 .resource = mcf_qspi_resources,
326 .dev.platform_data = &mcf_qspi_data,
327};
328#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
329
330static struct platform_device *mcf_devices[] __initdata = {
331 &mcf_uart,
332#ifdef CONFIG_FEC
333 &mcf_fec0,
334#ifdef MCFFEC_BASE1
335 &mcf_fec1,
336#endif
337#endif
338#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
339 &mcf_qspi,
340#endif
341};
342
343/*
344 * Some ColdFire UARTs let you set the IRQ line to use.
345 */
346static void __init mcf_uart_set_irq(void)
347{
348#ifdef MCFUART_UIVR
349 /* UART0 interrupt setup */
350 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
351 writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
352 mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
353
354 /* UART1 interrupt setup */
355 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
356 writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
357 mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
358#endif
359}
360
361static int __init mcf_init_devices(void)
362{
363 mcf_uart_set_irq();
364 platform_add_devices(mcf_devices, ARRAY_SIZE(mcf_devices));
365 return 0;
366}
367
368arch_initcall(mcf_init_devices);
369
diff --git a/arch/m68k/platform/coldfire/dma_timer.c b/arch/m68k/platform/coldfire/dma_timer.c
index 235ad57c470..a5f562823d7 100644
--- a/arch/m68k/platform/coldfire/dma_timer.c
+++ b/arch/m68k/platform/coldfire/dma_timer.c
@@ -44,6 +44,7 @@ static struct clocksource clocksource_cf_dt = {
44 .rating = 200, 44 .rating = 200,
45 .read = cf_dt_get_cycles, 45 .read = cf_dt_get_cycles,
46 .mask = CLOCKSOURCE_MASK(32), 46 .mask = CLOCKSOURCE_MASK(32),
47 .shift = 20,
47 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 48 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
48}; 49};
49 50
@@ -59,7 +60,9 @@ static int __init init_cf_dt_clocksource(void)
59 __raw_writeb(0x00, DTER0); 60 __raw_writeb(0x00, DTER0);
60 __raw_writel(0x00000000, DTRR0); 61 __raw_writel(0x00000000, DTRR0);
61 __raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0); 62 __raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
62 return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ); 63 clocksource_cf_dt.mult = clocksource_hz2mult(DMA_FREQ,
64 clocksource_cf_dt.shift);
65 return clocksource_register(&clocksource_cf_dt);
63} 66}
64 67
65arch_initcall(init_cf_dt_clocksource); 68arch_initcall(init_cf_dt_clocksource);
diff --git a/arch/m68k/platform/coldfire/entry.S b/arch/m68k/platform/coldfire/entry.S
index 881ab8e379d..bd27242c2f4 100644
--- a/arch/m68k/platform/coldfire/entry.S
+++ b/arch/m68k/platform/coldfire/entry.S
@@ -54,15 +54,15 @@ sw_usp:
54.globl ret_from_signal 54.globl ret_from_signal
55.globl sys_call_table 55.globl sys_call_table
56.globl inthandler 56.globl inthandler
57.globl fasthandler
57 58
58enosys: 59enosys:
59 mov.l #sys_ni_syscall,%d3 60 mov.l #sys_ni_syscall,%d3
60 bra 1f 61 bra 1f
61 62
62ENTRY(system_call) 63ENTRY(system_call)
63 SAVE_ALL_SYS 64 SAVE_ALL
64 move #0x2000,%sr /* enable intrs again */ 65 move #0x2000,%sr /* enable intrs again */
65 GET_CURRENT(%d2)
66 66
67 cmpl #NR_syscalls,%d0 67 cmpl #NR_syscalls,%d0
68 jcc enosys 68 jcc enosys
@@ -136,7 +136,7 @@ Luser_return:
136 movel %sp,%d1 /* get thread_info pointer */ 136 movel %sp,%d1 /* get thread_info pointer */
137 andl #-THREAD_SIZE,%d1 /* at base of kernel stack */ 137 andl #-THREAD_SIZE,%d1 /* at base of kernel stack */
138 movel %d1,%a0 138 movel %d1,%a0
139 moveb %a0@(TINFO_FLAGS+3),%d1 /* thread_info->flags (low 8 bits) */ 139 movel %a0@(TINFO_FLAGS),%d1 /* get thread_info->flags */
140 jne Lwork_to_do /* still work to do */ 140 jne Lwork_to_do /* still work to do */
141 141
142Lreturn: 142Lreturn:
@@ -148,11 +148,13 @@ Lwork_to_do:
148 btst #TIF_NEED_RESCHED,%d1 148 btst #TIF_NEED_RESCHED,%d1
149 jne reschedule 149 jne reschedule
150 150
151 /* GERG: do we need something here for TRACEing?? */
152
151Lsignal_return: 153Lsignal_return:
152 subql #4,%sp /* dummy return address */ 154 subql #4,%sp /* dummy return address */
153 SAVE_SWITCH_STACK 155 SAVE_SWITCH_STACK
154 pea %sp@(SWITCH_STACK_SIZE) 156 pea %sp@(SWITCH_STACK_SIZE)
155 jsr do_notify_resume 157 jsr do_signal
156 addql #4,%sp 158 addql #4,%sp
157 RESTORE_SWITCH_STACK 159 RESTORE_SWITCH_STACK
158 addql #4,%sp 160 addql #4,%sp
@@ -163,8 +165,9 @@ Lsignal_return:
163 * sources). Calls up to high level code to do all the work. 165 * sources). Calls up to high level code to do all the work.
164 */ 166 */
165ENTRY(inthandler) 167ENTRY(inthandler)
166 SAVE_ALL_INT 168 SAVE_ALL
167 GET_CURRENT(%d2) 169 moveq #-1,%d0
170 movel %d0,%sp@(PT_OFF_ORIG_D0)
168 171
169 movew %sp@(PT_OFF_FORMATVEC),%d0 /* put exception # in d0 */ 172 movew %sp@(PT_OFF_FORMATVEC),%d0 /* put exception # in d0 */
170 andl #0x03fc,%d0 /* mask out vector only */ 173 andl #0x03fc,%d0 /* mask out vector only */
@@ -190,9 +193,7 @@ ENTRY(resume)
190 movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack pointer */ 193 movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack pointer */
191 RDUSP /* movel %usp,%a3 */ 194 RDUSP /* movel %usp,%a3 */
192 movel %a3,%a0@(TASK_THREAD+THREAD_USP) /* save thread user stack */ 195 movel %a3,%a0@(TASK_THREAD+THREAD_USP) /* save thread user stack */
193#ifdef CONFIG_MMU 196
194 movel %a1,%a2 /* set new current */
195#endif
196 movel %a1@(TASK_THREAD+THREAD_USP),%a3 /* restore thread user stack */ 197 movel %a1@(TASK_THREAD+THREAD_USP),%a3 /* restore thread user stack */
197 WRUSP /* movel %a3,%usp */ 198 WRUSP /* movel %a3,%usp */
198 movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new kernel stack */ 199 movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new kernel stack */
diff --git a/arch/m68k/platform/coldfire/firebee.c b/arch/m68k/platform/coldfire/firebee.c
deleted file mode 100644
index 46d50534f98..00000000000
--- a/arch/m68k/platform/coldfire/firebee.c
+++ /dev/null
@@ -1,86 +0,0 @@
1/***************************************************************************/
2
3/*
4 * firebee.c -- extra startup code support for the FireBee boards
5 *
6 * Copyright (C) 2011, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/platform_device.h>
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/partitions.h>
17#include <linux/mtd/physmap.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20
21/***************************************************************************/
22
23/*
24 * 8MB of NOR flash fitted to the FireBee board.
25 */
26#define FLASH_PHYS_ADDR 0xe0000000 /* Physical address of flash */
27#define FLASH_PHYS_SIZE 0x00800000 /* Size of flash */
28
29#define PART_BOOT_START 0x00000000 /* Start at bottom of flash */
30#define PART_BOOT_SIZE 0x00040000 /* 256k in size */
31#define PART_IMAGE_START 0x00040000 /* Start after boot loader */
32#define PART_IMAGE_SIZE 0x006c0000 /* Most of flash */
33#define PART_FPGA_START 0x00700000 /* Start at offset 7MB */
34#define PART_FPGA_SIZE 0x00100000 /* 1MB in size */
35
36static struct mtd_partition firebee_flash_parts[] = {
37 {
38 .name = "dBUG",
39 .offset = PART_BOOT_START,
40 .size = PART_BOOT_SIZE,
41 },
42 {
43 .name = "FPGA",
44 .offset = PART_FPGA_START,
45 .size = PART_FPGA_SIZE,
46 },
47 {
48 .name = "image",
49 .offset = PART_IMAGE_START,
50 .size = PART_IMAGE_SIZE,
51 },
52};
53
54static struct physmap_flash_data firebee_flash_data = {
55 .width = 2,
56 .nr_parts = ARRAY_SIZE(firebee_flash_parts),
57 .parts = firebee_flash_parts,
58};
59
60static struct resource firebee_flash_resource = {
61 .start = FLASH_PHYS_ADDR,
62 .end = FLASH_PHYS_ADDR + FLASH_PHYS_SIZE,
63 .flags = IORESOURCE_MEM,
64};
65
66static struct platform_device firebee_flash = {
67 .name = "physmap-flash",
68 .id = 0,
69 .dev = {
70 .platform_data = &firebee_flash_data,
71 },
72 .num_resources = 1,
73 .resource = &firebee_flash_resource,
74};
75
76/***************************************************************************/
77
78static int __init init_firebee(void)
79{
80 platform_device_register(&firebee_flash);
81 return 0;
82}
83
84arch_initcall(init_firebee);
85
86/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/gpio.c b/arch/m68k/platform/coldfire/gpio.c
index 9cd2b5c7051..ff004579345 100644
--- a/arch/m68k/platform/coldfire/gpio.c
+++ b/arch/m68k/platform/coldfire/gpio.c
@@ -14,161 +14,114 @@
14 */ 14 */
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h> 17#include <linux/init.h>
19#include <linux/device.h> 18#include <linux/sysdev.h>
20 19
21#include <linux/io.h> 20#include <asm/gpio.h>
22#include <asm/coldfire.h> 21#include <asm/pinmux.h>
23#include <asm/mcfsim.h>
24#include <asm/mcfgpio.h> 22#include <asm/mcfgpio.h>
25 23
26int __mcfgpio_get_value(unsigned gpio) 24#define MCF_CHIP(chip) container_of(chip, struct mcf_gpio_chip, gpio_chip)
27{
28 return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);
29}
30EXPORT_SYMBOL(__mcfgpio_get_value);
31
32void __mcfgpio_set_value(unsigned gpio, int value)
33{
34 if (gpio < MCFGPIO_SCR_START) {
35 unsigned long flags;
36 MCFGPIO_PORTTYPE data;
37
38 local_irq_save(flags);
39 data = mcfgpio_read(__mcfgpio_podr(gpio));
40 if (value)
41 data |= mcfgpio_bit(gpio);
42 else
43 data &= ~mcfgpio_bit(gpio);
44 mcfgpio_write(data, __mcfgpio_podr(gpio));
45 local_irq_restore(flags);
46 } else {
47 if (value)
48 mcfgpio_write(mcfgpio_bit(gpio),
49 MCFGPIO_SETR_PORT(gpio));
50 else
51 mcfgpio_write(~mcfgpio_bit(gpio),
52 MCFGPIO_CLRR_PORT(gpio));
53 }
54}
55EXPORT_SYMBOL(__mcfgpio_set_value);
56 25
57int __mcfgpio_direction_input(unsigned gpio) 26int mcf_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
58{ 27{
59 unsigned long flags; 28 unsigned long flags;
60 MCFGPIO_PORTTYPE dir; 29 MCFGPIO_PORTTYPE dir;
30 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
61 31
62 local_irq_save(flags); 32 local_irq_save(flags);
63 dir = mcfgpio_read(__mcfgpio_pddr(gpio)); 33 dir = mcfgpio_read(mcf_chip->pddr);
64 dir &= ~mcfgpio_bit(gpio); 34 dir &= ~mcfgpio_bit(chip->base + offset);
65 mcfgpio_write(dir, __mcfgpio_pddr(gpio)); 35 mcfgpio_write(dir, mcf_chip->pddr);
66 local_irq_restore(flags); 36 local_irq_restore(flags);
67 37
68 return 0; 38 return 0;
69} 39}
70EXPORT_SYMBOL(__mcfgpio_direction_input);
71 40
72int __mcfgpio_direction_output(unsigned gpio, int value) 41int mcf_gpio_get_value(struct gpio_chip *chip, unsigned offset)
42{
43 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
44
45 return mcfgpio_read(mcf_chip->ppdr) & mcfgpio_bit(chip->base + offset);
46}
47
48int mcf_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
49 int value)
73{ 50{
74 unsigned long flags; 51 unsigned long flags;
75 MCFGPIO_PORTTYPE data; 52 MCFGPIO_PORTTYPE data;
53 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
76 54
77 local_irq_save(flags); 55 local_irq_save(flags);
78 data = mcfgpio_read(__mcfgpio_pddr(gpio)); 56 /* write the value to the output latch */
57 data = mcfgpio_read(mcf_chip->podr);
79 if (value) 58 if (value)
80 data |= mcfgpio_bit(gpio); 59 data |= mcfgpio_bit(chip->base + offset);
81 else 60 else
82 data &= mcfgpio_bit(gpio); 61 data &= ~mcfgpio_bit(chip->base + offset);
83 mcfgpio_write(data, __mcfgpio_pddr(gpio)); 62 mcfgpio_write(data, mcf_chip->podr);
84 63
85 /* now set the data to output */ 64 /* now set the direction to output */
86 if (gpio < MCFGPIO_SCR_START) { 65 data = mcfgpio_read(mcf_chip->pddr);
87 data = mcfgpio_read(__mcfgpio_podr(gpio)); 66 data |= mcfgpio_bit(chip->base + offset);
88 if (value) 67 mcfgpio_write(data, mcf_chip->pddr);
89 data |= mcfgpio_bit(gpio);
90 else
91 data &= ~mcfgpio_bit(gpio);
92 mcfgpio_write(data, __mcfgpio_podr(gpio));
93 } else {
94 if (value)
95 mcfgpio_write(mcfgpio_bit(gpio),
96 MCFGPIO_SETR_PORT(gpio));
97 else
98 mcfgpio_write(~mcfgpio_bit(gpio),
99 MCFGPIO_CLRR_PORT(gpio));
100 }
101 local_irq_restore(flags); 68 local_irq_restore(flags);
102 return 0;
103}
104EXPORT_SYMBOL(__mcfgpio_direction_output);
105 69
106int __mcfgpio_request(unsigned gpio)
107{
108 return 0; 70 return 0;
109} 71}
110EXPORT_SYMBOL(__mcfgpio_request);
111 72
112void __mcfgpio_free(unsigned gpio) 73void mcf_gpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
113{ 74{
114 __mcfgpio_direction_input(gpio); 75 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
115}
116EXPORT_SYMBOL(__mcfgpio_free);
117 76
118#ifdef CONFIG_GPIOLIB 77 unsigned long flags;
78 MCFGPIO_PORTTYPE data;
119 79
120int mcfgpio_direction_input(struct gpio_chip *chip, unsigned offset) 80 local_irq_save(flags);
121{ 81 data = mcfgpio_read(mcf_chip->podr);
122 return __mcfgpio_direction_input(offset); 82 if (value)
83 data |= mcfgpio_bit(chip->base + offset);
84 else
85 data &= ~mcfgpio_bit(chip->base + offset);
86 mcfgpio_write(data, mcf_chip->podr);
87 local_irq_restore(flags);
123} 88}
124 89
125int mcfgpio_get_value(struct gpio_chip *chip, unsigned offset) 90void mcf_gpio_set_value_fast(struct gpio_chip *chip, unsigned offset, int value)
126{ 91{
127 return __mcfgpio_get_value(offset); 92 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
128}
129 93
130int mcfgpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) 94 if (value)
131{ 95 mcfgpio_write(mcfgpio_bit(chip->base + offset), mcf_chip->setr);
132 return __mcfgpio_direction_output(offset, value); 96 else
97 mcfgpio_write(~mcfgpio_bit(chip->base + offset), mcf_chip->clrr);
133} 98}
134 99
135void mcfgpio_set_value(struct gpio_chip *chip, unsigned offset, int value) 100int mcf_gpio_request(struct gpio_chip *chip, unsigned offset)
136{ 101{
137 __mcfgpio_set_value(offset, value); 102 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
138}
139 103
140int mcfgpio_request(struct gpio_chip *chip, unsigned offset) 104 return mcf_chip->gpio_to_pinmux ?
141{ 105 mcf_pinmux_request(mcf_chip->gpio_to_pinmux[offset], 0) : 0;
142 return __mcfgpio_request(offset);
143} 106}
144 107
145void mcfgpio_free(struct gpio_chip *chip, unsigned offset) 108void mcf_gpio_free(struct gpio_chip *chip, unsigned offset)
146{ 109{
147 __mcfgpio_free(offset); 110 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
148}
149 111
150struct bus_type mcfgpio_subsys = { 112 mcf_gpio_direction_input(chip, offset);
151 .name = "gpio", 113
152 .dev_name = "gpio", 114 if (mcf_chip->gpio_to_pinmux)
153}; 115 mcf_pinmux_release(mcf_chip->gpio_to_pinmux[offset], 0);
116}
154 117
155static struct gpio_chip mcfgpio_chip = { 118struct sysdev_class mcf_gpio_sysclass = {
156 .label = "mcfgpio", 119 .name = "gpio",
157 .request = mcfgpio_request,
158 .free = mcfgpio_free,
159 .direction_input = mcfgpio_direction_input,
160 .direction_output = mcfgpio_direction_output,
161 .get = mcfgpio_get_value,
162 .set = mcfgpio_set_value,
163 .base = 0,
164 .ngpio = MCFGPIO_PIN_MAX,
165}; 120};
166 121
167static int __init mcfgpio_sysinit(void) 122static int __init mcf_gpio_sysinit(void)
168{ 123{
169 gpiochip_add(&mcfgpio_chip); 124 return sysdev_class_register(&mcf_gpio_sysclass);
170 return subsys_system_register(&mcfgpio_subsys, NULL);
171} 125}
172 126
173core_initcall(mcfgpio_sysinit); 127core_initcall(mcf_gpio_sysinit);
174#endif
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index fa31be297b8..c33483824a2 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -3,7 +3,7 @@
3/* 3/*
4 * head.S -- common startup code for ColdFire CPUs. 4 * head.S -- common startup code for ColdFire CPUs.
5 * 5 *
6 * (C) Copyright 1999-2011, Greg Ungerer <gerg@snapgear.com>. 6 * (C) Copyright 1999-2010, Greg Ungerer <gerg@snapgear.com>.
7 */ 7 */
8 8
9/*****************************************************************************/ 9/*****************************************************************************/
@@ -13,7 +13,6 @@
13#include <asm/asm-offsets.h> 13#include <asm/asm-offsets.h>
14#include <asm/coldfire.h> 14#include <asm/coldfire.h>
15#include <asm/mcfsim.h> 15#include <asm/mcfsim.h>
16#include <asm/mcfmmu.h>
17#include <asm/thread_info.h> 16#include <asm/thread_info.h>
18 17
19/*****************************************************************************/ 18/*****************************************************************************/
@@ -31,9 +30,9 @@
31.endm 30.endm
32 31
33#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 32#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
34 defined(CONFIG_M5249) || defined(CONFIG_M525x) || \ 33 defined(CONFIG_M5249) || defined(CONFIG_M527x) || \
35 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 34 defined(CONFIG_M528x) || defined(CONFIG_M5307) || \
36 defined(CONFIG_M5307) || defined(CONFIG_M5407) 35 defined(CONFIG_M5407)
37/* 36/*
38 * Not all these devices have exactly the same DRAM controller, 37 * Not all these devices have exactly the same DRAM controller,
39 * but the DCMR register is virtually identical - give or take 38 * but the DCMR register is virtually identical - give or take
@@ -60,7 +59,7 @@
60 59
61#elif defined(CONFIG_M5272) 60#elif defined(CONFIG_M5272)
62.macro GET_MEM_SIZE 61.macro GET_MEM_SIZE
63 movel MCFSIM_CSOR7,%d0 /* get SDRAM address mask */ 62 movel MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
64 andil #0xfffff000,%d0 /* mask out chip select options */ 63 andil #0xfffff000,%d0 /* mask out chip select options */
65 negl %d0 /* negate bits */ 64 negl %d0 /* negate bits */
66.endm 65.endm
@@ -136,14 +135,6 @@ _init_sp:
136 135
137__HEAD 136__HEAD
138 137
139#ifdef CONFIG_MMU
140_start0:
141 jmp _start
142.global kernel_pg_dir
143.equ kernel_pg_dir,_start0
144.equ .,_start0+0x1000
145#endif
146
147/* 138/*
148 * This is the codes first entry point. This is where it all 139 * This is the codes first entry point. This is where it all
149 * begins... 140 * begins...
@@ -152,16 +143,9 @@ _start0:
152_start: 143_start:
153 nop /* filler */ 144 nop /* filler */
154 movew #0x2700, %sr /* no interrupts */ 145 movew #0x2700, %sr /* no interrupts */
155 movel #CACHE_INIT,%d0 /* disable cache */
156 movec %d0,%CACR
157 nop
158#if defined(CONFIG_UBOOT) 146#if defined(CONFIG_UBOOT)
159 movel %sp,_init_sp /* save initial stack pointer */ 147 movel %sp,_init_sp /* save initial stack pointer */
160#endif 148#endif
161#ifdef CONFIG_MBAR
162 movel #CONFIG_MBAR+1,%d0 /* configured MBAR address */
163 movec %d0,%MBAR /* set it */
164#endif
165 149
166 /* 150 /*
167 * Do any platform or board specific setup now. Most boards 151 * Do any platform or board specific setup now. Most boards
@@ -192,6 +176,9 @@ _start:
192 * it is very similar. Define the exact settings in the headers 176 * it is very similar. Define the exact settings in the headers
193 * then the code here is the same for all. 177 * then the code here is the same for all.
194 */ 178 */
179 movel #CACHE_INIT,%d0 /* invalidate whole cache */
180 movec %d0,%CACR
181 nop
195 movel #ACR0_MODE,%d0 /* set RAM region for caching */ 182 movel #ACR0_MODE,%d0 /* set RAM region for caching */
196 movec %d0,%ACR0 183 movec %d0,%ACR0
197 movel #ACR1_MODE,%d0 /* anything else to cache? */ 184 movel #ACR1_MODE,%d0 /* anything else to cache? */
@@ -206,32 +193,12 @@ _start:
206 movec %d0,%CACR 193 movec %d0,%CACR
207 nop 194 nop
208 195
209#ifdef CONFIG_MMU
210 /*
211 * Identity mapping for the kernel region.
212 */
213 movel #(MMUBASE+1),%d0 /* enable MMUBAR registers */
214 movec %d0,%MMUBAR
215 movel #MMUOR_CA,%d0 /* clear TLB entries */
216 movel %d0,MMUOR
217 movel #0,%d0 /* set ASID to 0 */
218 movec %d0,%asid
219
220 movel #MMUCR_EN,%d0 /* Enable the identity map */
221 movel %d0,MMUCR
222 nop /* sync i-pipeline */
223
224 movel #_vstart,%a0 /* jump to "virtual" space */
225 jmp %a0@
226_vstart:
227#endif /* CONFIG_MMU */
228
229#ifdef CONFIG_ROMFS_FS 196#ifdef CONFIG_ROMFS_FS
230 /* 197 /*
231 * Move ROM filesystem above bss :-) 198 * Move ROM filesystem above bss :-)
232 */ 199 */
233 lea __bss_start,%a0 /* get start of bss */ 200 lea _sbss,%a0 /* get start of bss */
234 lea __bss_stop,%a1 /* set up destination */ 201 lea _ebss,%a1 /* set up destination */
235 movel %a0,%a2 /* copy of bss start */ 202 movel %a0,%a2 /* copy of bss start */
236 203
237 movel 8(%a0),%d0 /* get size of ROMFS */ 204 movel 8(%a0),%d0 /* get size of ROMFS */
@@ -249,7 +216,7 @@ _copy_romfs:
249 bne _copy_romfs 216 bne _copy_romfs
250 217
251#else /* CONFIG_ROMFS_FS */ 218#else /* CONFIG_ROMFS_FS */
252 lea __bss_stop,%a1 219 lea _ebss,%a1
253 movel %a1,_ramstart 220 movel %a1,_ramstart
254#endif /* CONFIG_ROMFS_FS */ 221#endif /* CONFIG_ROMFS_FS */
255 222
@@ -257,8 +224,8 @@ _copy_romfs:
257 /* 224 /*
258 * Zero out the bss region. 225 * Zero out the bss region.
259 */ 226 */
260 lea __bss_start,%a0 /* get start of bss */ 227 lea _sbss,%a0 /* get start of bss */
261 lea __bss_stop,%a1 /* get end of bss */ 228 lea _ebss,%a1 /* get end of bss */
262 clrl %d0 /* set value */ 229 clrl %d0 /* set value */
263_clear_bss: 230_clear_bss:
264 movel %d0,(%a0)+ /* clear each word */ 231 movel %d0,(%a0)+ /* clear each word */
@@ -271,22 +238,6 @@ _clear_bss:
271 lea init_thread_union,%a0 238 lea init_thread_union,%a0
272 lea THREAD_SIZE(%a0),%sp 239 lea THREAD_SIZE(%a0),%sp
273 240
274#ifdef CONFIG_MMU
275.global m68k_cputype
276.global m68k_mmutype
277.global m68k_fputype
278.global m68k_machtype
279 movel #CPU_COLDFIRE,%d0
280 movel %d0,m68k_cputype /* Mark us as a ColdFire */
281 movel #MMU_COLDFIRE,%d0
282 movel %d0,m68k_mmutype
283 movel #FPU_COLDFIRE,%d0
284 movel %d0,m68k_fputype
285 movel #MACH_M54XX,%d0
286 movel %d0,m68k_machtype /* Mark us as a 54xx machine */
287 lea init_task,%a2 /* Set "current" init task */
288#endif
289
290 /* 241 /*
291 * Assember start up done, start code proper. 242 * Assember start up done, start code proper.
292 */ 243 */
diff --git a/arch/m68k/platform/coldfire/intc-5249.c b/arch/m68k/platform/coldfire/intc-5249.c
deleted file mode 100644
index b0d1641053e..00000000000
--- a/arch/m68k/platform/coldfire/intc-5249.c
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * intc2.c -- support for the 2nd INTC controller of the 5249
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19
20static void intc2_irq_gpio_mask(struct irq_data *d)
21{
22 u32 imr;
23 imr = readl(MCFSIM2_GPIOINTENABLE);
24 imr &= ~(0x1 << (d->irq - MCF_IRQ_GPIO0));
25 writel(imr, MCFSIM2_GPIOINTENABLE);
26}
27
28static void intc2_irq_gpio_unmask(struct irq_data *d)
29{
30 u32 imr;
31 imr = readl(MCFSIM2_GPIOINTENABLE);
32 imr |= (0x1 << (d->irq - MCF_IRQ_GPIO0));
33 writel(imr, MCFSIM2_GPIOINTENABLE);
34}
35
36static void intc2_irq_gpio_ack(struct irq_data *d)
37{
38 writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR);
39}
40
41static struct irq_chip intc2_irq_gpio_chip = {
42 .name = "CF-INTC2",
43 .irq_mask = intc2_irq_gpio_mask,
44 .irq_unmask = intc2_irq_gpio_unmask,
45 .irq_ack = intc2_irq_gpio_ack,
46};
47
48static int __init mcf_intc2_init(void)
49{
50 int irq;
51
52 /* GPIO interrupt sources */
53 for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO7); irq++) {
54 irq_set_chip(irq, &intc2_irq_gpio_chip);
55 irq_set_handler(irq, handle_edge_irq);
56 }
57
58 return 0;
59}
60
61arch_initcall(mcf_intc2_init);
diff --git a/arch/m68k/platform/coldfire/intc-525x.c b/arch/m68k/platform/coldfire/intc-525x.c
deleted file mode 100644
index b23204d059a..00000000000
--- a/arch/m68k/platform/coldfire/intc-525x.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * intc2.c -- support for the 2nd INTC controller of the 525x
3 *
4 * (C) Copyright 2012, Steven King <sfking@fdwdc.com>
5 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20
21static void intc2_irq_gpio_mask(struct irq_data *d)
22{
23 u32 imr = readl(MCFSIM2_GPIOINTENABLE);
24 u32 type = irqd_get_trigger_type(d);
25 int irq = d->irq - MCF_IRQ_GPIO0;
26
27 if (type & IRQ_TYPE_EDGE_RISING)
28 imr &= ~(0x001 << irq);
29 if (type & IRQ_TYPE_EDGE_FALLING)
30 imr &= ~(0x100 << irq);
31 writel(imr, MCFSIM2_GPIOINTENABLE);
32}
33
34static void intc2_irq_gpio_unmask(struct irq_data *d)
35{
36 u32 imr = readl(MCFSIM2_GPIOINTENABLE);
37 u32 type = irqd_get_trigger_type(d);
38 int irq = d->irq - MCF_IRQ_GPIO0;
39
40 if (type & IRQ_TYPE_EDGE_RISING)
41 imr |= (0x001 << irq);
42 if (type & IRQ_TYPE_EDGE_FALLING)
43 imr |= (0x100 << irq);
44 writel(imr, MCFSIM2_GPIOINTENABLE);
45}
46
47static void intc2_irq_gpio_ack(struct irq_data *d)
48{
49 u32 imr = 0;
50 u32 type = irqd_get_trigger_type(d);
51 int irq = d->irq - MCF_IRQ_GPIO0;
52
53 if (type & IRQ_TYPE_EDGE_RISING)
54 imr |= (0x001 << irq);
55 if (type & IRQ_TYPE_EDGE_FALLING)
56 imr |= (0x100 << irq);
57 writel(imr, MCFSIM2_GPIOINTCLEAR);
58}
59
60static int intc2_irq_gpio_set_type(struct irq_data *d, unsigned int f)
61{
62 if (f & ~IRQ_TYPE_EDGE_BOTH)
63 return -EINVAL;
64 return 0;
65}
66
67static struct irq_chip intc2_irq_gpio_chip = {
68 .name = "CF-INTC2",
69 .irq_mask = intc2_irq_gpio_mask,
70 .irq_unmask = intc2_irq_gpio_unmask,
71 .irq_ack = intc2_irq_gpio_ack,
72 .irq_set_type = intc2_irq_gpio_set_type,
73};
74
75static int __init mcf_intc2_init(void)
76{
77 int irq;
78
79 /* set the interrupt base for the second interrupt controller */
80 writel(MCFINTC2_VECBASE, MCFINTC2_INTBASE);
81
82 /* GPIO interrupt sources */
83 for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO6); irq++) {
84 irq_set_chip(irq, &intc2_irq_gpio_chip);
85 irq_set_handler(irq, handle_edge_irq);
86 }
87
88 return 0;
89}
90
91arch_initcall(mcf_intc2_init);
diff --git a/arch/m68k/platform/coldfire/intc-5272.c b/arch/m68k/platform/coldfire/intc-5272.c
deleted file mode 100644
index d7b695629a7..00000000000
--- a/arch/m68k/platform/coldfire/intc-5272.c
+++ /dev/null
@@ -1,185 +0,0 @@
1/*
2 * intc.c -- interrupt controller or ColdFire 5272 SoC
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/kernel_stat.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20#include <asm/traps.h>
21
22/*
23 * The 5272 ColdFire interrupt controller is nothing like any other
24 * ColdFire interrupt controller - it truly is completely different.
25 * Given its age it is unlikely to be used on any other ColdFire CPU.
26 */
27
28/*
29 * The masking and priproty setting of interrupts on the 5272 is done
30 * via a set of 4 "Interrupt Controller Registers" (ICR). There is a
31 * loose mapping of vector number to register and internal bits, but
32 * a table is the easiest and quickest way to map them.
33 *
34 * Note that the external interrupts are edge triggered (unlike the
35 * internal interrupt sources which are level triggered). Which means
36 * they also need acknowledging via acknowledge bits.
37 */
38struct irqmap {
39 unsigned char icr;
40 unsigned char index;
41 unsigned char ack;
42};
43
44static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
45 /*MCF_IRQ_SPURIOUS*/ { .icr = 0, .index = 0, .ack = 0, },
46 /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
47 /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
48 /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
49 /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
50 /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
51 /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
52 /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
53 /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
54 /*MCF_IRQ_UART1*/ { .icr = MCFSIM_ICR2, .index = 28, .ack = 0, },
55 /*MCF_IRQ_UART2*/ { .icr = MCFSIM_ICR2, .index = 24, .ack = 0, },
56 /*MCF_IRQ_PLIP*/ { .icr = MCFSIM_ICR2, .index = 20, .ack = 0, },
57 /*MCF_IRQ_PLIA*/ { .icr = MCFSIM_ICR2, .index = 16, .ack = 0, },
58 /*MCF_IRQ_USB0*/ { .icr = MCFSIM_ICR2, .index = 12, .ack = 0, },
59 /*MCF_IRQ_USB1*/ { .icr = MCFSIM_ICR2, .index = 8, .ack = 0, },
60 /*MCF_IRQ_USB2*/ { .icr = MCFSIM_ICR2, .index = 4, .ack = 0, },
61 /*MCF_IRQ_USB3*/ { .icr = MCFSIM_ICR2, .index = 0, .ack = 0, },
62 /*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, },
63 /*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, },
64 /*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, },
65 /*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, },
66 /*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, },
67 /*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, },
68 /*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, },
69 /*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, },
70 /*MCF_IRQ_QSPI*/ { .icr = MCFSIM_ICR4, .index = 28, .ack = 0, },
71 /*MCF_IRQ_EINT5*/ { .icr = MCFSIM_ICR4, .index = 24, .ack = 1, },
72 /*MCF_IRQ_EINT6*/ { .icr = MCFSIM_ICR4, .index = 20, .ack = 1, },
73 /*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, },
74};
75
76/*
77 * The act of masking the interrupt also has a side effect of 'ack'ing
78 * an interrupt on this irq (for the external irqs). So this mask function
79 * is also an ack_mask function.
80 */
81static void intc_irq_mask(struct irq_data *d)
82{
83 unsigned int irq = d->irq;
84
85 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
86 u32 v;
87 irq -= MCFINT_VECBASE;
88 v = 0x8 << intc_irqmap[irq].index;
89 writel(v, intc_irqmap[irq].icr);
90 }
91}
92
93static void intc_irq_unmask(struct irq_data *d)
94{
95 unsigned int irq = d->irq;
96
97 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
98 u32 v;
99 irq -= MCFINT_VECBASE;
100 v = 0xd << intc_irqmap[irq].index;
101 writel(v, intc_irqmap[irq].icr);
102 }
103}
104
105static void intc_irq_ack(struct irq_data *d)
106{
107 unsigned int irq = d->irq;
108
109 /* Only external interrupts are acked */
110 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
111 irq -= MCFINT_VECBASE;
112 if (intc_irqmap[irq].ack) {
113 u32 v;
114 v = readl(intc_irqmap[irq].icr);
115 v &= (0x7 << intc_irqmap[irq].index);
116 v |= (0x8 << intc_irqmap[irq].index);
117 writel(v, intc_irqmap[irq].icr);
118 }
119 }
120}
121
122static int intc_irq_set_type(struct irq_data *d, unsigned int type)
123{
124 unsigned int irq = d->irq;
125
126 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
127 irq -= MCFINT_VECBASE;
128 if (intc_irqmap[irq].ack) {
129 u32 v;
130 v = readl(MCFSIM_PITR);
131 if (type == IRQ_TYPE_EDGE_FALLING)
132 v &= ~(0x1 << (32 - irq));
133 else
134 v |= (0x1 << (32 - irq));
135 writel(v, MCFSIM_PITR);
136 }
137 }
138 return 0;
139}
140
141/*
142 * Simple flow handler to deal with the external edge triggered interrupts.
143 * We need to be careful with the masking/acking due to the side effects
144 * of masking an interrupt.
145 */
146static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
147{
148 irq_desc_get_chip(desc)->irq_ack(&desc->irq_data);
149 handle_simple_irq(irq, desc);
150}
151
152static struct irq_chip intc_irq_chip = {
153 .name = "CF-INTC",
154 .irq_mask = intc_irq_mask,
155 .irq_unmask = intc_irq_unmask,
156 .irq_mask_ack = intc_irq_mask,
157 .irq_ack = intc_irq_ack,
158 .irq_set_type = intc_irq_set_type,
159};
160
161void __init init_IRQ(void)
162{
163 int irq, edge;
164
165 /* Mask all interrupt sources */
166 writel(0x88888888, MCFSIM_ICR1);
167 writel(0x88888888, MCFSIM_ICR2);
168 writel(0x88888888, MCFSIM_ICR3);
169 writel(0x88888888, MCFSIM_ICR4);
170
171 for (irq = 0; (irq < NR_IRQS); irq++) {
172 irq_set_chip(irq, &intc_irq_chip);
173 edge = 0;
174 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX))
175 edge = intc_irqmap[irq - MCFINT_VECBASE].ack;
176 if (edge) {
177 irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
178 irq_set_handler(irq, intc_external_irq);
179 } else {
180 irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
181 irq_set_handler(irq, handle_level_irq);
182 }
183 }
184}
185
diff --git a/arch/m68k/platform/coldfire/intc-simr.c b/arch/m68k/platform/coldfire/intc-simr.c
index 7cf2c156f72..650d52e2927 100644
--- a/arch/m68k/platform/coldfire/intc-simr.c
+++ b/arch/m68k/platform/coldfire/intc-simr.c
@@ -59,18 +59,16 @@ static unsigned int inline irq2ebit(unsigned int irq)
59#endif 59#endif
60 60
61/* 61/*
62 * There maybe one, two or three interrupt control units, each has 64 62 * There maybe one or two interrupt control units, each has 64
63 * interrupts. If there is no second or third unit then MCFINTC1_* or 63 * interrupts. If there is no second unit then MCFINTC1_* defines
64 * MCFINTC2_* defines will be 0 (and code for them optimized away). 64 * will be 0 (and code for them optimized away).
65 */ 65 */
66 66
67static void intc_irq_mask(struct irq_data *d) 67static void intc_irq_mask(struct irq_data *d)
68{ 68{
69 unsigned int irq = d->irq - MCFINT_VECBASE; 69 unsigned int irq = d->irq - MCFINT_VECBASE;
70 70
71 if (MCFINTC2_SIMR && (irq > 128)) 71 if (MCFINTC1_SIMR && (irq > 64))
72 __raw_writeb(irq - 128, MCFINTC2_SIMR);
73 else if (MCFINTC1_SIMR && (irq > 64))
74 __raw_writeb(irq - 64, MCFINTC1_SIMR); 72 __raw_writeb(irq - 64, MCFINTC1_SIMR);
75 else 73 else
76 __raw_writeb(irq, MCFINTC0_SIMR); 74 __raw_writeb(irq, MCFINTC0_SIMR);
@@ -80,9 +78,7 @@ static void intc_irq_unmask(struct irq_data *d)
80{ 78{
81 unsigned int irq = d->irq - MCFINT_VECBASE; 79 unsigned int irq = d->irq - MCFINT_VECBASE;
82 80
83 if (MCFINTC2_CIMR && (irq > 128)) 81 if (MCFINTC1_CIMR && (irq > 64))
84 __raw_writeb(irq - 128, MCFINTC2_CIMR);
85 else if (MCFINTC1_CIMR && (irq > 64))
86 __raw_writeb(irq - 64, MCFINTC1_CIMR); 82 __raw_writeb(irq - 64, MCFINTC1_CIMR);
87 else 83 else
88 __raw_writeb(irq, MCFINTC0_CIMR); 84 __raw_writeb(irq, MCFINTC0_CIMR);
@@ -103,11 +99,9 @@ static unsigned int intc_irq_startup(struct irq_data *d)
103 unsigned int ebit = irq2ebit(irq); 99 unsigned int ebit = irq2ebit(irq);
104 u8 v; 100 u8 v;
105 101
106#if defined(MCFEPORT_EPDDR)
107 /* Set EPORT line as input */ 102 /* Set EPORT line as input */
108 v = __raw_readb(MCFEPORT_EPDDR); 103 v = __raw_readb(MCFEPORT_EPDDR);
109 __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR); 104 __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
110#endif
111 105
112 /* Set EPORT line as interrupt source */ 106 /* Set EPORT line as interrupt source */
113 v = __raw_readb(MCFEPORT_EPIER); 107 v = __raw_readb(MCFEPORT_EPIER);
@@ -115,13 +109,12 @@ static unsigned int intc_irq_startup(struct irq_data *d)
115 } 109 }
116 110
117 irq -= MCFINT_VECBASE; 111 irq -= MCFINT_VECBASE;
118 if (MCFINTC2_ICR0 && (irq > 128)) 112 if (MCFINTC1_ICR0 && (irq > 64))
119 __raw_writeb(5, MCFINTC2_ICR0 + irq - 128);
120 else if (MCFINTC1_ICR0 && (irq > 64))
121 __raw_writeb(5, MCFINTC1_ICR0 + irq - 64); 113 __raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
122 else 114 else
123 __raw_writeb(5, MCFINTC0_ICR0 + irq); 115 __raw_writeb(5, MCFINTC0_ICR0 + irq);
124 116
117
125 intc_irq_unmask(d); 118 intc_irq_unmask(d);
126 return 0; 119 return 0;
127} 120}
@@ -182,11 +175,8 @@ void __init init_IRQ(void)
182 __raw_writeb(0xff, MCFINTC0_SIMR); 175 __raw_writeb(0xff, MCFINTC0_SIMR);
183 if (MCFINTC1_SIMR) 176 if (MCFINTC1_SIMR)
184 __raw_writeb(0xff, MCFINTC1_SIMR); 177 __raw_writeb(0xff, MCFINTC1_SIMR);
185 if (MCFINTC2_SIMR)
186 __raw_writeb(0xff, MCFINTC2_SIMR);
187 178
188 eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) + 179 eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0);
189 (MCFINTC2_ICR0 ? 64 : 0);
190 for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { 180 for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
191 if ((irq >= EINT1) && (irq <= EINT7)) 181 if ((irq >= EINT1) && (irq <= EINT7))
192 irq_set_chip(irq, &intc_irq_chip_edge_port); 182 irq_set_chip(irq, &intc_irq_chip_edge_port);
diff --git a/arch/m68k/platform/coldfire/intc.c b/arch/m68k/platform/coldfire/intc.c
index cce25742038..5c0c150b406 100644
--- a/arch/m68k/platform/coldfire/intc.c
+++ b/arch/m68k/platform/coldfire/intc.c
@@ -45,23 +45,23 @@ unsigned char mcf_irq2imr[NR_IRQS];
45void mcf_setimr(int index) 45void mcf_setimr(int index)
46{ 46{
47 u16 imr; 47 u16 imr;
48 imr = __raw_readw(MCFSIM_IMR); 48 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
49 __raw_writew(imr | (0x1 << index), MCFSIM_IMR); 49 __raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
50} 50}
51 51
52void mcf_clrimr(int index) 52void mcf_clrimr(int index)
53{ 53{
54 u16 imr; 54 u16 imr;
55 imr = __raw_readw(MCFSIM_IMR); 55 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
56 __raw_writew(imr & ~(0x1 << index), MCFSIM_IMR); 56 __raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
57} 57}
58 58
59void mcf_maskimr(unsigned int mask) 59void mcf_maskimr(unsigned int mask)
60{ 60{
61 u16 imr; 61 u16 imr;
62 imr = __raw_readw(MCFSIM_IMR); 62 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
63 imr |= mask; 63 imr |= mask;
64 __raw_writew(imr, MCFSIM_IMR); 64 __raw_writew(imr, MCF_MBAR + MCFSIM_IMR);
65} 65}
66 66
67#else 67#else
@@ -69,23 +69,23 @@ void mcf_maskimr(unsigned int mask)
69void mcf_setimr(int index) 69void mcf_setimr(int index)
70{ 70{
71 u32 imr; 71 u32 imr;
72 imr = __raw_readl(MCFSIM_IMR); 72 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
73 __raw_writel(imr | (0x1 << index), MCFSIM_IMR); 73 __raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
74} 74}
75 75
76void mcf_clrimr(int index) 76void mcf_clrimr(int index)
77{ 77{
78 u32 imr; 78 u32 imr;
79 imr = __raw_readl(MCFSIM_IMR); 79 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
80 __raw_writel(imr & ~(0x1 << index), MCFSIM_IMR); 80 __raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
81} 81}
82 82
83void mcf_maskimr(unsigned int mask) 83void mcf_maskimr(unsigned int mask)
84{ 84{
85 u32 imr; 85 u32 imr;
86 imr = __raw_readl(MCFSIM_IMR); 86 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
87 imr |= mask; 87 imr |= mask;
88 __raw_writel(imr, MCFSIM_IMR); 88 __raw_writel(imr, MCF_MBAR + MCFSIM_IMR);
89} 89}
90 90
91#endif 91#endif
@@ -104,9 +104,9 @@ void mcf_autovector(int irq)
104#ifdef MCFSIM_AVR 104#ifdef MCFSIM_AVR
105 if ((irq >= EIRQ1) && (irq <= EIRQ7)) { 105 if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
106 u8 avec; 106 u8 avec;
107 avec = __raw_readb(MCFSIM_AVR); 107 avec = __raw_readb(MCF_MBAR + MCFSIM_AVR);
108 avec |= (0x1 << (irq - EIRQ1 + 1)); 108 avec |= (0x1 << (irq - EIRQ1 + 1));
109 __raw_writeb(avec, MCFSIM_AVR); 109 __raw_writeb(avec, MCF_MBAR + MCFSIM_AVR);
110 } 110 }
111#endif 111#endif
112} 112}
diff --git a/arch/m68k/platform/coldfire/m5206.c b/arch/m68k/platform/coldfire/m5206.c
deleted file mode 100644
index 0e55f449a88..00000000000
--- a/arch/m68k/platform/coldfire/m5206.c
+++ /dev/null
@@ -1,58 +0,0 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5206/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000-2001, Lineo Inc. (www.lineo.com)
8 */
9
10/***************************************************************************/
11
12#include <linux/kernel.h>
13#include <linux/param.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/mcfclk.h>
20
21/***************************************************************************/
22
23DEFINE_CLK(pll, "pll.0", MCF_CLK);
24DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29
30struct clk *mcf_clks[] = {
31 &clk_pll,
32 &clk_sys,
33 &clk_mcftmr0,
34 &clk_mcftmr1,
35 &clk_mcfuart0,
36 &clk_mcfuart1,
37 NULL
38};
39
40/***************************************************************************/
41
42void __init config_BSP(char *commandp, int size)
43{
44#if defined(CONFIG_NETtel)
45 /* Copy command line from FLASH to local buffer... */
46 memcpy(commandp, (char *) 0xf0004000, size);
47 commandp[size-1] = 0;
48#endif /* CONFIG_NETtel */
49
50 mach_sched_init = hw_timer_init;
51
52 /* Only support the external interrupts on their primary level */
53 mcf_mapirq2imr(25, MCFINTC_EINT1);
54 mcf_mapirq2imr(28, MCFINTC_EINT4);
55 mcf_mapirq2imr(31, MCFINTC_EINT7);
56}
57
58/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m520x.c b/arch/m68k/platform/coldfire/m520x.c
deleted file mode 100644
index ea1be0e98ad..00000000000
--- a/arch/m68k/platform/coldfire/m520x.c
+++ /dev/null
@@ -1,184 +0,0 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/520x/config.c
5 *
6 * Copyright (C) 2005, Freescale (www.freescale.com)
7 * Copyright (C) 2005, Intec Automation (mike@steroidmicros.com)
8 * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
9 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
10 */
11
12/***************************************************************************/
13
14#include <linux/kernel.h>
15#include <linux/param.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <asm/machdep.h>
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfuart.h>
22#include <asm/mcfclk.h>
23
24/***************************************************************************/
25
26DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
27DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
28DEFINE_CLK(0, "edma", 17, MCF_CLK);
29DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
30DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
31DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
32DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
33DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
34DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
35DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
36DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
37DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
38DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
39DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
40
41DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
42DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
43DEFINE_CLK(0, "mcfeport.0", 34, MCF_CLK);
44DEFINE_CLK(0, "mcfwdt.0", 35, MCF_CLK);
45DEFINE_CLK(0, "pll.0", 36, MCF_CLK);
46DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
47DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
48DEFINE_CLK(0, "sdram.0", 42, MCF_CLK);
49
50struct clk *mcf_clks[] = {
51 &__clk_0_2, /* flexbus */
52 &__clk_0_12, /* fec.0 */
53 &__clk_0_17, /* edma */
54 &__clk_0_18, /* intc.0 */
55 &__clk_0_21, /* iack.0 */
56 &__clk_0_22, /* mcfi2c.0 */
57 &__clk_0_23, /* mcfqspi.0 */
58 &__clk_0_24, /* mcfuart.0 */
59 &__clk_0_25, /* mcfuart.1 */
60 &__clk_0_26, /* mcfuart.2 */
61 &__clk_0_28, /* mcftmr.0 */
62 &__clk_0_29, /* mcftmr.1 */
63 &__clk_0_30, /* mcftmr.2 */
64 &__clk_0_31, /* mcftmr.3 */
65
66 &__clk_0_32, /* mcfpit.0 */
67 &__clk_0_33, /* mcfpit.1 */
68 &__clk_0_34, /* mcfeport.0 */
69 &__clk_0_35, /* mcfwdt.0 */
70 &__clk_0_36, /* pll.0 */
71 &__clk_0_40, /* sys.0 */
72 &__clk_0_41, /* gpio.0 */
73 &__clk_0_42, /* sdram.0 */
74NULL,
75};
76
77static struct clk * const enable_clks[] __initconst = {
78 &__clk_0_2, /* flexbus */
79 &__clk_0_18, /* intc.0 */
80 &__clk_0_21, /* iack.0 */
81 &__clk_0_24, /* mcfuart.0 */
82 &__clk_0_25, /* mcfuart.1 */
83 &__clk_0_26, /* mcfuart.2 */
84
85 &__clk_0_32, /* mcfpit.0 */
86 &__clk_0_33, /* mcfpit.1 */
87 &__clk_0_34, /* mcfeport.0 */
88 &__clk_0_36, /* pll.0 */
89 &__clk_0_40, /* sys.0 */
90 &__clk_0_41, /* gpio.0 */
91 &__clk_0_42, /* sdram.0 */
92};
93
94static struct clk * const disable_clks[] __initconst = {
95 &__clk_0_12, /* fec.0 */
96 &__clk_0_17, /* edma */
97 &__clk_0_22, /* mcfi2c.0 */
98 &__clk_0_23, /* mcfqspi.0 */
99 &__clk_0_28, /* mcftmr.0 */
100 &__clk_0_29, /* mcftmr.1 */
101 &__clk_0_30, /* mcftmr.2 */
102 &__clk_0_31, /* mcftmr.3 */
103 &__clk_0_35, /* mcfwdt.0 */
104};
105
106
107static void __init m520x_clk_init(void)
108{
109 unsigned i;
110
111 /* make sure these clocks are enabled */
112 for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
113 __clk_init_enabled(enable_clks[i]);
114 /* make sure these clocks are disabled */
115 for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
116 __clk_init_disabled(disable_clks[i]);
117}
118
119/***************************************************************************/
120
121#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
122
123static void __init m520x_qspi_init(void)
124{
125 u16 par;
126 /* setup Port QS for QSPI with gpio CS control */
127 writeb(0x3f, MCF_GPIO_PAR_QSPI);
128 /* make U1CTS and U2RTS gpio for cs_control */
129 par = readw(MCF_GPIO_PAR_UART);
130 par &= 0x00ff;
131 writew(par, MCF_GPIO_PAR_UART);
132}
133
134#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
135
136/***************************************************************************/
137
138static void __init m520x_uarts_init(void)
139{
140 u16 par;
141 u8 par2;
142
143 /* UART0 and UART1 GPIO pin setup */
144 par = readw(MCF_GPIO_PAR_UART);
145 par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
146 par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
147 writew(par, MCF_GPIO_PAR_UART);
148
149 /* UART1 GPIO pin setup */
150 par2 = readb(MCF_GPIO_PAR_FECI2C);
151 par2 &= ~0x0F;
152 par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
153 MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
154 writeb(par2, MCF_GPIO_PAR_FECI2C);
155}
156
157/***************************************************************************/
158
159static void __init m520x_fec_init(void)
160{
161 u8 v;
162
163 /* Set multi-function pins to ethernet mode */
164 v = readb(MCF_GPIO_PAR_FEC);
165 writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
166
167 v = readb(MCF_GPIO_PAR_FECI2C);
168 writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
169}
170
171/***************************************************************************/
172
173void __init config_BSP(char *commandp, int size)
174{
175 mach_sched_init = hw_timer_init;
176 m520x_clk_init();
177 m520x_uarts_init();
178 m520x_fec_init();
179#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
180 m520x_qspi_init();
181#endif
182}
183
184/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m523x.c b/arch/m68k/platform/coldfire/m523x.c
deleted file mode 100644
index 2b10e9f198c..00000000000
--- a/arch/m68k/platform/coldfire/m523x.c
+++ /dev/null
@@ -1,88 +0,0 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/523x/config.c
5 *
6 * Sub-architcture dependent initialization code for the Freescale
7 * 523x CPUs.
8 *
9 * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
11 */
12
13/***************************************************************************/
14
15#include <linux/kernel.h>
16#include <linux/param.h>
17#include <linux/init.h>
18#include <linux/io.h>
19#include <asm/machdep.h>
20#include <asm/coldfire.h>
21#include <asm/mcfsim.h>
22#include <asm/mcfclk.h>
23
24/***************************************************************************/
25
26DEFINE_CLK(pll, "pll.0", MCF_CLK);
27DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
28DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
29DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
30DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
31DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
32DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
33DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
34DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
35DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
36
37struct clk *mcf_clks[] = {
38 &clk_pll,
39 &clk_sys,
40 &clk_mcfpit0,
41 &clk_mcfpit1,
42 &clk_mcfpit2,
43 &clk_mcfpit3,
44 &clk_mcfuart0,
45 &clk_mcfuart1,
46 &clk_mcfuart2,
47 &clk_fec0,
48 NULL
49};
50
51/***************************************************************************/
52
53#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
54
55static void __init m523x_qspi_init(void)
56{
57 u16 par;
58
59 /* setup QSPS pins for QSPI with gpio CS control */
60 writeb(0x1f, MCFGPIO_PAR_QSPI);
61 /* and CS2 & CS3 as gpio */
62 par = readw(MCFGPIO_PAR_TIMER);
63 par &= 0x3f3f;
64 writew(par, MCFGPIO_PAR_TIMER);
65}
66
67#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
68
69/***************************************************************************/
70
71static void __init m523x_fec_init(void)
72{
73 /* Set multi-function pins to ethernet use */
74 writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
75}
76
77/***************************************************************************/
78
79void __init config_BSP(char *commandp, int size)
80{
81 mach_sched_init = hw_timer_init;
82 m523x_fec_init();
83#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
84 m523x_qspi_init();
85#endif
86}
87
88/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5249.c b/arch/m68k/platform/coldfire/m5249.c
deleted file mode 100644
index c80b5e51d29..00000000000
--- a/arch/m68k/platform/coldfire/m5249.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5249/config.c
5 *
6 * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/mcfclk.h>
20
21/***************************************************************************/
22
23DEFINE_CLK(pll, "pll.0", MCF_CLK);
24DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29
30struct clk *mcf_clks[] = {
31 &clk_pll,
32 &clk_sys,
33 &clk_mcftmr0,
34 &clk_mcftmr1,
35 &clk_mcfuart0,
36 &clk_mcfuart1,
37 NULL
38};
39
40/***************************************************************************/
41
42#ifdef CONFIG_M5249C3
43
44static struct resource m5249_smc91x_resources[] = {
45 {
46 .start = 0xe0000300,
47 .end = 0xe0000300 + 0x100,
48 .flags = IORESOURCE_MEM,
49 },
50 {
51 .start = MCF_IRQ_GPIO6,
52 .end = MCF_IRQ_GPIO6,
53 .flags = IORESOURCE_IRQ,
54 },
55};
56
57static struct platform_device m5249_smc91x = {
58 .name = "smc91x",
59 .id = 0,
60 .num_resources = ARRAY_SIZE(m5249_smc91x_resources),
61 .resource = m5249_smc91x_resources,
62};
63
64#endif /* CONFIG_M5249C3 */
65
66static struct platform_device *m5249_devices[] __initdata = {
67#ifdef CONFIG_M5249C3
68 &m5249_smc91x,
69#endif
70};
71
72/***************************************************************************/
73
74#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
75
76static void __init m5249_qspi_init(void)
77{
78 /* QSPI irq setup */
79 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
80 MCFSIM_QSPIICR);
81 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
82}
83
84#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
85
86/***************************************************************************/
87
88#ifdef CONFIG_M5249C3
89
90static void __init m5249_smc91x_init(void)
91{
92 u32 gpio;
93
94 /* Set the GPIO line as interrupt source for smc91x device */
95 gpio = readl(MCFSIM2_GPIOINTENABLE);
96 writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
97
98 gpio = readl(MCFINTC2_INTPRI5);
99 writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
100}
101
102#endif /* CONFIG_M5249C3 */
103
104/***************************************************************************/
105
106void __init config_BSP(char *commandp, int size)
107{
108 mach_sched_init = hw_timer_init;
109
110#ifdef CONFIG_M5249C3
111 m5249_smc91x_init();
112#endif
113#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
114 m5249_qspi_init();
115#endif
116}
117
118/***************************************************************************/
119
120static int __init init_BSP(void)
121{
122 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
123 return 0;
124}
125
126arch_initcall(init_BSP);
127
128/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m525x.c b/arch/m68k/platform/coldfire/m525x.c
deleted file mode 100644
index 5b9f657b2df..00000000000
--- a/arch/m68k/platform/coldfire/m525x.c
+++ /dev/null
@@ -1,86 +0,0 @@
1/***************************************************************************/
2
3/*
4 * 525x.c
5 *
6 * Copyright (C) 2012, Steven King <sfking@fdwdc.com>
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/mcfclk.h>
20
21/***************************************************************************/
22
23DEFINE_CLK(pll, "pll.0", MCF_CLK);
24DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29
30struct clk *mcf_clks[] = {
31 &clk_pll,
32 &clk_sys,
33 &clk_mcftmr0,
34 &clk_mcftmr1,
35 &clk_mcfuart0,
36 &clk_mcfuart1,
37 NULL
38};
39
40/***************************************************************************/
41
42static void __init m525x_qspi_init(void)
43{
44#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
45 /* set the GPIO function for the qspi cs gpios */
46 /* FIXME: replace with pinmux/pinctl support */
47 u32 f = readl(MCFSIM2_GPIOFUNC);
48 f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
49 writel(f, MCFSIM2_GPIOFUNC);
50
51 /* QSPI irq setup */
52 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
53 MCFSIM_QSPIICR);
54 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
55#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
56}
57
58static void __init m525x_i2c_init(void)
59{
60#if IS_ENABLED(CONFIG_I2C_COLDFIRE)
61 u32 r;
62
63 /* first I2C controller uses regular irq setup */
64 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
65 MCFSIM_I2CICR);
66 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
67
68 /* second I2C controller is completely different */
69 r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
70 r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
71 r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
72 writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
73#endif /* IS_ENABLED(CONFIG_I2C_COLDFIRE) */
74}
75
76/***************************************************************************/
77
78void __init config_BSP(char *commandp, int size)
79{
80 mach_sched_init = hw_timer_init;
81
82 m525x_qspi_init();
83 m525x_i2c_init();
84}
85
86/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5272.c b/arch/m68k/platform/coldfire/m5272.c
deleted file mode 100644
index a8c5856fe5e..00000000000
--- a/arch/m68k/platform/coldfire/m5272.c
+++ /dev/null
@@ -1,133 +0,0 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5272/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
8 */
9
10/***************************************************************************/
11
12#include <linux/kernel.h>
13#include <linux/param.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/phy.h>
17#include <linux/phy_fixed.h>
18#include <asm/machdep.h>
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfuart.h>
22#include <asm/mcfclk.h>
23
24/***************************************************************************/
25
26/*
27 * Some platforms need software versions of the GPIO data registers.
28 */
29unsigned short ppdata;
30unsigned char ledbank = 0xff;
31
32/***************************************************************************/
33
34DEFINE_CLK(pll, "pll.0", MCF_CLK);
35DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
36DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
37DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
38DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
39DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
40DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
41DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
42DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
43
44struct clk *mcf_clks[] = {
45 &clk_pll,
46 &clk_sys,
47 &clk_mcftmr0,
48 &clk_mcftmr1,
49 &clk_mcftmr2,
50 &clk_mcftmr3,
51 &clk_mcfuart0,
52 &clk_mcfuart1,
53 &clk_fec0,
54 NULL
55};
56
57/***************************************************************************/
58
59static void __init m5272_uarts_init(void)
60{
61 u32 v;
62
63 /* Enable the output lines for the serial ports */
64 v = readl(MCFSIM_PBCNT);
65 v = (v & ~0x000000ff) | 0x00000055;
66 writel(v, MCFSIM_PBCNT);
67
68 v = readl(MCFSIM_PDCNT);
69 v = (v & ~0x000003fc) | 0x000002a8;
70 writel(v, MCFSIM_PDCNT);
71}
72
73/***************************************************************************/
74
75static void m5272_cpu_reset(void)
76{
77 local_irq_disable();
78 /* Set watchdog to reset, and enabled */
79 __raw_writew(0, MCFSIM_WIRR);
80 __raw_writew(1, MCFSIM_WRRR);
81 __raw_writew(0, MCFSIM_WCR);
82 for (;;)
83 /* wait for watchdog to timeout */;
84}
85
86/***************************************************************************/
87
88void __init config_BSP(char *commandp, int size)
89{
90#if defined (CONFIG_MOD5272)
91 /* Set base of device vectors to be 64 */
92 writeb(0x40, MCFSIM_PIVR);
93#endif
94
95#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
96 /* Copy command line from FLASH to local buffer... */
97 memcpy(commandp, (char *) 0xf0004000, size);
98 commandp[size-1] = 0;
99#elif defined(CONFIG_CANCam)
100 /* Copy command line from FLASH to local buffer... */
101 memcpy(commandp, (char *) 0xf0010000, size);
102 commandp[size-1] = 0;
103#endif
104
105 mach_reset = m5272_cpu_reset;
106 mach_sched_init = hw_timer_init;
107}
108
109/***************************************************************************/
110
111/*
112 * Some 5272 based boards have the FEC ethernet diectly connected to
113 * an ethernet switch. In this case we need to use the fixed phy type,
114 * and we need to declare it early in boot.
115 */
116static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
117 .link = 1,
118 .speed = 100,
119 .duplex = 0,
120};
121
122/***************************************************************************/
123
124static int __init init_BSP(void)
125{
126 m5272_uarts_init();
127 fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
128 return 0;
129}
130
131arch_initcall(init_BSP);
132
133/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c
deleted file mode 100644
index 6fbfe9096c3..00000000000
--- a/arch/m68k/platform/coldfire/m527x.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/527x/config.c
5 *
6 * Sub-architcture dependent initialization code for the Freescale
7 * 5270/5271 CPUs.
8 *
9 * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
11 */
12
13/***************************************************************************/
14
15#include <linux/kernel.h>
16#include <linux/param.h>
17#include <linux/init.h>
18#include <linux/io.h>
19#include <asm/machdep.h>
20#include <asm/coldfire.h>
21#include <asm/mcfsim.h>
22#include <asm/mcfuart.h>
23#include <asm/mcfclk.h>
24
25/***************************************************************************/
26
27DEFINE_CLK(pll, "pll.0", MCF_CLK);
28DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
29DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
30DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
31DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
32DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
33DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
34DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
35DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
36DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
37DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
38
39struct clk *mcf_clks[] = {
40 &clk_pll,
41 &clk_sys,
42 &clk_mcfpit0,
43 &clk_mcfpit1,
44 &clk_mcfpit2,
45 &clk_mcfpit3,
46 &clk_mcfuart0,
47 &clk_mcfuart1,
48 &clk_mcfuart2,
49 &clk_fec0,
50 &clk_fec1,
51 NULL
52};
53
54/***************************************************************************/
55
56#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
57
58static void __init m527x_qspi_init(void)
59{
60#if defined(CONFIG_M5271)
61 u16 par;
62
63 /* setup QSPS pins for QSPI with gpio CS control */
64 writeb(0x1f, MCFGPIO_PAR_QSPI);
65 /* and CS2 & CS3 as gpio */
66 par = readw(MCFGPIO_PAR_TIMER);
67 par &= 0x3f3f;
68 writew(par, MCFGPIO_PAR_TIMER);
69#elif defined(CONFIG_M5275)
70 /* setup QSPS pins for QSPI with gpio CS control */
71 writew(0x003e, MCFGPIO_PAR_QSPI);
72#endif
73}
74
75#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
76
77/***************************************************************************/
78
79static void __init m527x_uarts_init(void)
80{
81 u16 sepmask;
82
83 /*
84 * External Pin Mask Setting & Enable External Pin for Interface
85 */
86 sepmask = readw(MCFGPIO_PAR_UART);
87 sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
88 writew(sepmask, MCFGPIO_PAR_UART);
89}
90
91/***************************************************************************/
92
93static void __init m527x_fec_init(void)
94{
95 u16 par;
96 u8 v;
97
98 /* Set multi-function pins to ethernet mode for fec0 */
99#if defined(CONFIG_M5271)
100 v = readb(MCFGPIO_PAR_FECI2C);
101 writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
102#else
103 par = readw(MCFGPIO_PAR_FECI2C);
104 writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
105 v = readb(MCFGPIO_PAR_FEC0HL);
106 writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
107
108 /* Set multi-function pins to ethernet mode for fec1 */
109 par = readw(MCFGPIO_PAR_FECI2C);
110 writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
111 v = readb(MCFGPIO_PAR_FEC1HL);
112 writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
113#endif
114}
115
116/***************************************************************************/
117
118void __init config_BSP(char *commandp, int size)
119{
120 mach_sched_init = hw_timer_init;
121 m527x_uarts_init();
122 m527x_fec_init();
123#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
124 m527x_qspi_init();
125#endif
126}
127
128/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m528x.c b/arch/m68k/platform/coldfire/m528x.c
deleted file mode 100644
index 83b7dad7a84..00000000000
--- a/arch/m68k/platform/coldfire/m528x.c
+++ /dev/null
@@ -1,134 +0,0 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/528x/config.c
5 *
6 * Sub-architcture dependent initialization code for the Freescale
7 * 5280, 5281 and 5282 CPUs.
8 *
9 * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
11 */
12
13/***************************************************************************/
14
15#include <linux/kernel.h>
16#include <linux/param.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20#include <asm/machdep.h>
21#include <asm/coldfire.h>
22#include <asm/mcfsim.h>
23#include <asm/mcfuart.h>
24#include <asm/mcfclk.h>
25
26/***************************************************************************/
27
28DEFINE_CLK(pll, "pll.0", MCF_CLK);
29DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
30DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
31DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
32DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
33DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
34DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
35DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
36DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
37DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
38
39struct clk *mcf_clks[] = {
40 &clk_pll,
41 &clk_sys,
42 &clk_mcfpit0,
43 &clk_mcfpit1,
44 &clk_mcfpit2,
45 &clk_mcfpit3,
46 &clk_mcfuart0,
47 &clk_mcfuart1,
48 &clk_mcfuart2,
49 &clk_fec0,
50 NULL
51};
52
53/***************************************************************************/
54
55#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
56
57static void __init m528x_qspi_init(void)
58{
59 /* setup Port QS for QSPI with gpio CS control */
60 __raw_writeb(0x07, MCFGPIO_PQSPAR);
61}
62
63#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
64
65/***************************************************************************/
66
67static void __init m528x_uarts_init(void)
68{
69 u8 port;
70
71 /* make sure PUAPAR is set for UART0 and UART1 */
72 port = readb(MCF5282_GPIO_PUAPAR);
73 port |= 0x03 | (0x03 << 2);
74 writeb(port, MCFGPIO_PUAPAR);
75}
76
77/***************************************************************************/
78
79static void __init m528x_fec_init(void)
80{
81 u16 v16;
82
83 /* Set multi-function pins to ethernet mode for fec0 */
84 v16 = readw(MCFGPIO_PASPAR);
85 writew(v16 | 0xf00, MCFGPIO_PASPAR);
86 writeb(0xc0, MCFGPIO_PEHLPAR);
87}
88
89/***************************************************************************/
90
91#ifdef CONFIG_WILDFIRE
92void wildfire_halt(void)
93{
94 writeb(0, 0x30000007);
95 writeb(0x2, 0x30000007);
96}
97#endif
98
99#ifdef CONFIG_WILDFIREMOD
100void wildfiremod_halt(void)
101{
102 printk(KERN_INFO "WildFireMod hibernating...\n");
103
104 /* Set portE.5 to Digital IO */
105 MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2));
106
107 /* Make portE.5 an output */
108 MCF5282_GPIO_DDRE |= (1 << 5);
109
110 /* Now toggle portE.5 from low to high */
111 MCF5282_GPIO_PORTE &= ~(1 << 5);
112 MCF5282_GPIO_PORTE |= (1 << 5);
113
114 printk(KERN_EMERG "Failed to hibernate. Halting!\n");
115}
116#endif
117
118void __init config_BSP(char *commandp, int size)
119{
120#ifdef CONFIG_WILDFIRE
121 mach_halt = wildfire_halt;
122#endif
123#ifdef CONFIG_WILDFIREMOD
124 mach_halt = wildfiremod_halt;
125#endif
126 mach_sched_init = hw_timer_init;
127 m528x_uarts_init();
128 m528x_fec_init();
129#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
130 m528x_qspi_init();
131#endif
132}
133
134/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5307.c b/arch/m68k/platform/coldfire/m5307.c
deleted file mode 100644
index 88743536138..00000000000
--- a/arch/m68k/platform/coldfire/m5307.c
+++ /dev/null
@@ -1,78 +0,0 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5307/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000, Lineo (www.lineo.com)
8 */
9
10/***************************************************************************/
11
12#include <linux/kernel.h>
13#include <linux/param.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/mcfwdebug.h>
20#include <asm/mcfclk.h>
21
22/***************************************************************************/
23
24/*
25 * Some platforms need software versions of the GPIO data registers.
26 */
27unsigned short ppdata;
28unsigned char ledbank = 0xff;
29
30/***************************************************************************/
31
32DEFINE_CLK(pll, "pll.0", MCF_CLK);
33DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
34DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
35DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
36DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
37DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
38
39struct clk *mcf_clks[] = {
40 &clk_pll,
41 &clk_sys,
42 &clk_mcftmr0,
43 &clk_mcftmr1,
44 &clk_mcfuart0,
45 &clk_mcfuart1,
46 NULL
47};
48
49/***************************************************************************/
50
51void __init config_BSP(char *commandp, int size)
52{
53#if defined(CONFIG_NETtel) || \
54 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
55 /* Copy command line from FLASH to local buffer... */
56 memcpy(commandp, (char *) 0xf0004000, size);
57 commandp[size-1] = 0;
58#endif
59
60 mach_sched_init = hw_timer_init;
61
62 /* Only support the external interrupts on their primary level */
63 mcf_mapirq2imr(25, MCFINTC_EINT1);
64 mcf_mapirq2imr(27, MCFINTC_EINT3);
65 mcf_mapirq2imr(29, MCFINTC_EINT5);
66 mcf_mapirq2imr(31, MCFINTC_EINT7);
67
68#ifdef CONFIG_BDM_DISABLE
69 /*
70 * Disable the BDM clocking. This also turns off most of the rest of
71 * the BDM device. This is good for EMC reasons. This option is not
72 * incompatible with the memory protection option.
73 */
74 wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
75#endif
76}
77
78/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m532x.c b/arch/m68k/platform/coldfire/m532x.c
deleted file mode 100644
index 7951d1d4335..00000000000
--- a/arch/m68k/platform/coldfire/m532x.c
+++ /dev/null
@@ -1,593 +0,0 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/532x/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000, Lineo (www.lineo.com)
8 * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
9 * Copyright Freescale Semiconductor, Inc 2006
10 * Copyright (c) 2006, emlix, Sebastian Hess <shess@hessware.de>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18/***************************************************************************/
19
20#include <linux/kernel.h>
21#include <linux/param.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <asm/machdep.h>
25#include <asm/coldfire.h>
26#include <asm/mcfsim.h>
27#include <asm/mcfuart.h>
28#include <asm/mcfdma.h>
29#include <asm/mcfwdebug.h>
30#include <asm/mcfclk.h>
31
32/***************************************************************************/
33
34DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
35DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
36DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
37DEFINE_CLK(0, "edma", 17, MCF_CLK);
38DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
39DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
40DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
41DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
42DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
43DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
44DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
45DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
46DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
47DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
48DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
49DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
50
51DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
52DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
53DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
54DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
55DEFINE_CLK(0, "mcfpwm.0", 36, MCF_CLK);
56DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
57DEFINE_CLK(0, "mcfwdt.0", 38, MCF_CLK);
58DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
59DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
60DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
61DEFINE_CLK(0, "mcflcd.0", 43, MCF_CLK);
62DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
63DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
64DEFINE_CLK(0, "sdram.0", 46, MCF_CLK);
65DEFINE_CLK(0, "ssi.0", 47, MCF_CLK);
66DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
67
68DEFINE_CLK(1, "mdha.0", 32, MCF_CLK);
69DEFINE_CLK(1, "skha.0", 33, MCF_CLK);
70DEFINE_CLK(1, "rng.0", 34, MCF_CLK);
71
72struct clk *mcf_clks[] = {
73 &__clk_0_2, /* flexbus */
74 &__clk_0_8, /* mcfcan.0 */
75 &__clk_0_12, /* fec.0 */
76 &__clk_0_17, /* edma */
77 &__clk_0_18, /* intc.0 */
78 &__clk_0_19, /* intc.1 */
79 &__clk_0_21, /* iack.0 */
80 &__clk_0_22, /* mcfi2c.0 */
81 &__clk_0_23, /* mcfqspi.0 */
82 &__clk_0_24, /* mcfuart.0 */
83 &__clk_0_25, /* mcfuart.1 */
84 &__clk_0_26, /* mcfuart.2 */
85 &__clk_0_28, /* mcftmr.0 */
86 &__clk_0_29, /* mcftmr.1 */
87 &__clk_0_30, /* mcftmr.2 */
88 &__clk_0_31, /* mcftmr.3 */
89
90 &__clk_0_32, /* mcfpit.0 */
91 &__clk_0_33, /* mcfpit.1 */
92 &__clk_0_34, /* mcfpit.2 */
93 &__clk_0_35, /* mcfpit.3 */
94 &__clk_0_36, /* mcfpwm.0 */
95 &__clk_0_37, /* mcfeport.0 */
96 &__clk_0_38, /* mcfwdt.0 */
97 &__clk_0_40, /* sys.0 */
98 &__clk_0_41, /* gpio.0 */
99 &__clk_0_42, /* mcfrtc.0 */
100 &__clk_0_43, /* mcflcd.0 */
101 &__clk_0_44, /* mcfusb-otg.0 */
102 &__clk_0_45, /* mcfusb-host.0 */
103 &__clk_0_46, /* sdram.0 */
104 &__clk_0_47, /* ssi.0 */
105 &__clk_0_48, /* pll.0 */
106
107 &__clk_1_32, /* mdha.0 */
108 &__clk_1_33, /* skha.0 */
109 &__clk_1_34, /* rng.0 */
110 NULL,
111};
112
113static struct clk * const enable_clks[] __initconst = {
114 &__clk_0_2, /* flexbus */
115 &__clk_0_18, /* intc.0 */
116 &__clk_0_19, /* intc.1 */
117 &__clk_0_21, /* iack.0 */
118 &__clk_0_24, /* mcfuart.0 */
119 &__clk_0_25, /* mcfuart.1 */
120 &__clk_0_26, /* mcfuart.2 */
121
122 &__clk_0_32, /* mcfpit.0 */
123 &__clk_0_33, /* mcfpit.1 */
124 &__clk_0_37, /* mcfeport.0 */
125 &__clk_0_40, /* sys.0 */
126 &__clk_0_41, /* gpio.0 */
127 &__clk_0_46, /* sdram.0 */
128 &__clk_0_48, /* pll.0 */
129};
130
131static struct clk * const disable_clks[] __initconst = {
132 &__clk_0_8, /* mcfcan.0 */
133 &__clk_0_12, /* fec.0 */
134 &__clk_0_17, /* edma */
135 &__clk_0_22, /* mcfi2c.0 */
136 &__clk_0_23, /* mcfqspi.0 */
137 &__clk_0_28, /* mcftmr.0 */
138 &__clk_0_29, /* mcftmr.1 */
139 &__clk_0_30, /* mcftmr.2 */
140 &__clk_0_31, /* mcftmr.3 */
141 &__clk_0_34, /* mcfpit.2 */
142 &__clk_0_35, /* mcfpit.3 */
143 &__clk_0_36, /* mcfpwm.0 */
144 &__clk_0_38, /* mcfwdt.0 */
145 &__clk_0_42, /* mcfrtc.0 */
146 &__clk_0_43, /* mcflcd.0 */
147 &__clk_0_44, /* mcfusb-otg.0 */
148 &__clk_0_45, /* mcfusb-host.0 */
149 &__clk_0_47, /* ssi.0 */
150 &__clk_1_32, /* mdha.0 */
151 &__clk_1_33, /* skha.0 */
152 &__clk_1_34, /* rng.0 */
153};
154
155
156static void __init m532x_clk_init(void)
157{
158 unsigned i;
159
160 /* make sure these clocks are enabled */
161 for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
162 __clk_init_enabled(enable_clks[i]);
163 /* make sure these clocks are disabled */
164 for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
165 __clk_init_disabled(disable_clks[i]);
166}
167
168/***************************************************************************/
169
170#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
171
172static void __init m532x_qspi_init(void)
173{
174 /* setup QSPS pins for QSPI with gpio CS control */
175 writew(0x01f0, MCFGPIO_PAR_QSPI);
176}
177
178#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
179
180/***************************************************************************/
181
182static void __init m532x_uarts_init(void)
183{
184 /* UART GPIO initialization */
185 writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
186}
187
188/***************************************************************************/
189
190static void __init m532x_fec_init(void)
191{
192 u8 v;
193
194 /* Set multi-function pins to ethernet mode for fec0 */
195 v = readb(MCFGPIO_PAR_FECI2C);
196 v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
197 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO;
198 writeb(v, MCFGPIO_PAR_FECI2C);
199
200 v = readb(MCFGPIO_PAR_FEC);
201 v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
202 writeb(v, MCFGPIO_PAR_FEC);
203}
204
205/***************************************************************************/
206
207void __init config_BSP(char *commandp, int size)
208{
209#if !defined(CONFIG_BOOTPARAM)
210 /* Copy command line from FLASH to local buffer... */
211 memcpy(commandp, (char *) 0x4000, 4);
212 if(strncmp(commandp, "kcl ", 4) == 0){
213 memcpy(commandp, (char *) 0x4004, size);
214 commandp[size-1] = 0;
215 } else {
216 memset(commandp, 0, size);
217 }
218#endif
219 mach_sched_init = hw_timer_init;
220 m532x_clk_init();
221 m532x_uarts_init();
222 m532x_fec_init();
223#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
224 m532x_qspi_init();
225#endif
226
227#ifdef CONFIG_BDM_DISABLE
228 /*
229 * Disable the BDM clocking. This also turns off most of the rest of
230 * the BDM device. This is good for EMC reasons. This option is not
231 * incompatible with the memory protection option.
232 */
233 wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
234#endif
235}
236
237/***************************************************************************/
238/* Board initialization */
239/***************************************************************************/
240/*
241 * PLL min/max specifications
242 */
243#define MAX_FVCO 500000 /* KHz */
244#define MAX_FSYS 80000 /* KHz */
245#define MIN_FSYS 58333 /* KHz */
246#define FREF 16000 /* KHz */
247
248
249#define MAX_MFD 135 /* Multiplier */
250#define MIN_MFD 88 /* Multiplier */
251#define BUSDIV 6 /* Divider */
252
253/*
254 * Low Power Divider specifications
255 */
256#define MIN_LPD (1 << 0) /* Divider (not encoded) */
257#define MAX_LPD (1 << 15) /* Divider (not encoded) */
258#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
259
260#define SYS_CLK_KHZ 80000
261#define SYSTEM_PERIOD 12.5
262/*
263 * SDRAM Timing Parameters
264 */
265#define SDRAM_BL 8 /* # of beats in a burst */
266#define SDRAM_TWR 2 /* in clocks */
267#define SDRAM_CASL 2.5 /* CASL in clocks */
268#define SDRAM_TRCD 2 /* in clocks */
269#define SDRAM_TRP 2 /* in clocks */
270#define SDRAM_TRFC 7 /* in clocks */
271#define SDRAM_TREFI 7800 /* in ns */
272
273#define EXT_SRAM_ADDRESS (0xC0000000)
274#define FLASH_ADDRESS (0x00000000)
275#define SDRAM_ADDRESS (0x40000000)
276
277#define NAND_FLASH_ADDRESS (0xD0000000)
278
279int sys_clk_khz = 0;
280int sys_clk_mhz = 0;
281
282void wtm_init(void);
283void scm_init(void);
284void gpio_init(void);
285void fbcs_init(void);
286void sdramc_init(void);
287int clock_pll (int fsys, int flags);
288int clock_limp (int);
289int clock_exit_limp (void);
290int get_sys_clock (void);
291
292asmlinkage void __init sysinit(void)
293{
294 sys_clk_khz = clock_pll(0, 0);
295 sys_clk_mhz = sys_clk_khz/1000;
296
297 wtm_init();
298 scm_init();
299 gpio_init();
300 fbcs_init();
301 sdramc_init();
302}
303
304void wtm_init(void)
305{
306 /* Disable watchdog timer */
307 writew(0, MCF_WTM_WCR);
308}
309
310#define MCF_SCM_BCR_GBW (0x00000100)
311#define MCF_SCM_BCR_GBR (0x00000200)
312
313void scm_init(void)
314{
315 /* All masters are trusted */
316 writel(0x77777777, MCF_SCM_MPR);
317
318 /* Allow supervisor/user, read/write, and trusted/untrusted
319 access to all slaves */
320 writel(0, MCF_SCM_PACRA);
321 writel(0, MCF_SCM_PACRB);
322 writel(0, MCF_SCM_PACRC);
323 writel(0, MCF_SCM_PACRD);
324 writel(0, MCF_SCM_PACRE);
325 writel(0, MCF_SCM_PACRF);
326
327 /* Enable bursts */
328 writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
329}
330
331
332void fbcs_init(void)
333{
334 writeb(0x3E, MCFGPIO_PAR_CS);
335
336 /* Latch chip select */
337 writel(0x10080000, MCF_FBCS1_CSAR);
338
339 writel(0x002A3780, MCF_FBCS1_CSCR);
340 writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
341
342 /* Initialize latch to drive signals to inactive states */
343 writew(0xffff, 0x10080000);
344
345 /* External SRAM */
346 writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
347 writel(MCF_FBCS_CSCR_PS_16 |
348 MCF_FBCS_CSCR_AA |
349 MCF_FBCS_CSCR_SBM |
350 MCF_FBCS_CSCR_WS(1),
351 MCF_FBCS1_CSCR);
352 writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
353
354 /* Boot Flash connected to FBCS0 */
355 writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
356 writel(MCF_FBCS_CSCR_PS_16 |
357 MCF_FBCS_CSCR_BEM |
358 MCF_FBCS_CSCR_AA |
359 MCF_FBCS_CSCR_SBM |
360 MCF_FBCS_CSCR_WS(7),
361 MCF_FBCS0_CSCR);
362 writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
363}
364
365void sdramc_init(void)
366{
367 /*
368 * Check to see if the SDRAM has already been initialized
369 * by a run control tool
370 */
371 if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
372 /* SDRAM chip select initialization */
373
374 /* Initialize SDRAM chip select */
375 writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
376 MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE),
377 MCF_SDRAMC_SDCS0);
378
379 /*
380 * Basic configuration and initialization
381 */
382 writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
383 MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
384 MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) |
385 MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) |
386 MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP + 0.5)) |
387 MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) |
388 MCF_SDRAMC_SDCFG1_WTLAT(3),
389 MCF_SDRAMC_SDCFG1);
390 writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
391 MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) |
392 MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |
393 MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),
394 MCF_SDRAMC_SDCFG2);
395
396
397 /*
398 * Precharge and enable write to SDMR
399 */
400 writel(MCF_SDRAMC_SDCR_MODE_EN |
401 MCF_SDRAMC_SDCR_CKE |
402 MCF_SDRAMC_SDCR_DDR |
403 MCF_SDRAMC_SDCR_MUX(1) |
404 MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) |
405 MCF_SDRAMC_SDCR_PS_16 |
406 MCF_SDRAMC_SDCR_IPALL,
407 MCF_SDRAMC_SDCR);
408
409 /*
410 * Write extended mode register
411 */
412 writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
413 MCF_SDRAMC_SDMR_AD(0x0) |
414 MCF_SDRAMC_SDMR_CMD,
415 MCF_SDRAMC_SDMR);
416
417 /*
418 * Write mode register and reset DLL
419 */
420 writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
421 MCF_SDRAMC_SDMR_AD(0x163) |
422 MCF_SDRAMC_SDMR_CMD,
423 MCF_SDRAMC_SDMR);
424
425 /*
426 * Execute a PALL command
427 */
428 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
429
430 /*
431 * Perform two REF cycles
432 */
433 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
434 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
435
436 /*
437 * Write mode register and clear reset DLL
438 */
439 writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
440 MCF_SDRAMC_SDMR_AD(0x063) |
441 MCF_SDRAMC_SDMR_CMD,
442 MCF_SDRAMC_SDMR);
443
444 /*
445 * Enable auto refresh and lock SDMR
446 */
447 writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
448 MCF_SDRAMC_SDCR);
449 writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
450 MCF_SDRAMC_SDCR);
451 }
452}
453
454void gpio_init(void)
455{
456 /* Enable UART0 pins */
457 writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0,
458 MCFGPIO_PAR_UART);
459
460 /*
461 * Initialize TIN3 as a GPIO output to enable the write
462 * half of the latch.
463 */
464 writeb(0x00, MCFGPIO_PAR_TIMER);
465 writeb(0x08, MCFGPIO_PDDR_TIMER);
466 writeb(0x00, MCFGPIO_PCLRR_TIMER);
467}
468
469int clock_pll(int fsys, int flags)
470{
471 int fref, temp, fout, mfd;
472 u32 i;
473
474 fref = FREF;
475
476 if (fsys == 0) {
477 /* Return current PLL output */
478 mfd = readb(MCF_PLL_PFDR);
479
480 return (fref * mfd / (BUSDIV * 4));
481 }
482
483 /* Check bounds of requested system clock */
484 if (fsys > MAX_FSYS)
485 fsys = MAX_FSYS;
486 if (fsys < MIN_FSYS)
487 fsys = MIN_FSYS;
488
489 /* Multiplying by 100 when calculating the temp value,
490 and then dividing by 100 to calculate the mfd allows
491 for exact values without needing to include floating
492 point libraries. */
493 temp = 100 * fsys / fref;
494 mfd = 4 * BUSDIV * temp / 100;
495
496 /* Determine the output frequency for selected values */
497 fout = (fref * mfd / (BUSDIV * 4));
498
499 /*
500 * Check to see if the SDRAM has already been initialized.
501 * If it has then the SDRAM needs to be put into self refresh
502 * mode before reprogramming the PLL.
503 */
504 if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
505 /* Put SDRAM into self refresh mode */
506 writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
507 MCF_SDRAMC_SDCR);
508
509 /*
510 * Initialize the PLL to generate the new system clock frequency.
511 * The device must be put into LIMP mode to reprogram the PLL.
512 */
513
514 /* Enter LIMP mode */
515 clock_limp(DEFAULT_LPD);
516
517 /* Reprogram PLL for desired fsys */
518 writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
519 MCF_PLL_PODR);
520
521 writeb(mfd, MCF_PLL_PFDR);
522
523 /* Exit LIMP mode */
524 clock_exit_limp();
525
526 /*
527 * Return the SDRAM to normal operation if it is in use.
528 */
529 if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
530 /* Exit self refresh mode */
531 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
532 MCF_SDRAMC_SDCR);
533
534 /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
535 writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
536
537 /* wait for DQS logic to relock */
538 for (i = 0; i < 0x200; i++)
539 ;
540
541 return fout;
542}
543
544int clock_limp(int div)
545{
546 u32 temp;
547
548 /* Check bounds of divider */
549 if (div < MIN_LPD)
550 div = MIN_LPD;
551 if (div > MAX_LPD)
552 div = MAX_LPD;
553
554 /* Save of the current value of the SSIDIV so we don't
555 overwrite the value*/
556 temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
557
558 /* Apply the divider to the system clock */
559 writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
560
561 writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
562
563 return (FREF/(3*(1 << div)));
564}
565
566int clock_exit_limp(void)
567{
568 int fout;
569
570 /* Exit LIMP mode */
571 writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
572
573 /* Wait for PLL to lock */
574 while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
575 ;
576
577 fout = get_sys_clock();
578
579 return fout;
580}
581
582int get_sys_clock(void)
583{
584 int divider;
585
586 /* Test to see if device is in LIMP mode */
587 if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
588 divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
589 return (FREF/(2 << divider));
590 }
591 else
592 return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
593}
diff --git a/arch/m68k/platform/coldfire/m5407.c b/arch/m68k/platform/coldfire/m5407.c
deleted file mode 100644
index 2fb3cdbfde3..00000000000
--- a/arch/m68k/platform/coldfire/m5407.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5407/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000, Lineo (www.lineo.com)
8 */
9
10/***************************************************************************/
11
12#include <linux/kernel.h>
13#include <linux/param.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/mcfclk.h>
20
21/***************************************************************************/
22
23DEFINE_CLK(pll, "pll.0", MCF_CLK);
24DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29
30struct clk *mcf_clks[] = {
31 &clk_pll,
32 &clk_sys,
33 &clk_mcftmr0,
34 &clk_mcftmr1,
35 &clk_mcfuart0,
36 &clk_mcfuart1,
37 NULL
38};
39
40/***************************************************************************/
41
42void __init config_BSP(char *commandp, int size)
43{
44 mach_sched_init = hw_timer_init;
45
46 /* Only support the external interrupts on their primary level */
47 mcf_mapirq2imr(25, MCFINTC_EINT1);
48 mcf_mapirq2imr(27, MCFINTC_EINT3);
49 mcf_mapirq2imr(29, MCFINTC_EINT5);
50 mcf_mapirq2imr(31, MCFINTC_EINT7);
51}
52
53/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5441x.c b/arch/m68k/platform/coldfire/m5441x.c
deleted file mode 100644
index 98a13cce93d..00000000000
--- a/arch/m68k/platform/coldfire/m5441x.c
+++ /dev/null
@@ -1,261 +0,0 @@
1/*
2 * m5441x.c -- support for Coldfire m5441x processors
3 *
4 * (C) Copyright Steven King <sfking@fdwdc.com>
5 */
6
7#include <linux/kernel.h>
8#include <linux/param.h>
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/clk.h>
12#include <asm/machdep.h>
13#include <asm/coldfire.h>
14#include <asm/mcfsim.h>
15#include <asm/mcfuart.h>
16#include <asm/mcfdma.h>
17#include <asm/mcfclk.h>
18
19DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
20DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
21DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK);
22DEFINE_CLK(0, "mcfi2c.1", 14, MCF_CLK);
23DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
24DEFINE_CLK(0, "edma", 17, MCF_CLK);
25DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
26DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
27DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
28DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
29DEFINE_CLK(0, "mcfdspi.0", 23, MCF_CLK);
30DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
31DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
32DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
33DEFINE_CLK(0, "mcfuart.3", 27, MCF_BUSCLK);
34DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
35DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
36DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
37DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
38DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
39DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
40DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
41DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
42DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
43DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK);
44DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK);
45DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
46DEFINE_CLK(0, "mcfsim.0", 43, MCF_CLK);
47DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
48DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
49DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK);
50DEFINE_CLK(0, "mcfssi.0", 47, MCF_CLK);
51DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
52DEFINE_CLK(0, "mcfrng.0", 49, MCF_CLK);
53DEFINE_CLK(0, "mcfssi.1", 50, MCF_CLK);
54DEFINE_CLK(0, "mcfsdhc.0", 51, MCF_CLK);
55DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK);
56DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK);
57DEFINE_CLK(0, "switch.0", 55, MCF_CLK);
58DEFINE_CLK(0, "switch.1", 56, MCF_CLK);
59DEFINE_CLK(0, "nand.0", 63, MCF_CLK);
60
61DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK);
62DEFINE_CLK(1, "mcfi2c.2", 4, MCF_CLK);
63DEFINE_CLK(1, "mcfi2c.3", 5, MCF_CLK);
64DEFINE_CLK(1, "mcfi2c.4", 6, MCF_CLK);
65DEFINE_CLK(1, "mcfi2c.5", 7, MCF_CLK);
66DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK);
67DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK);
68DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK);
69DEFINE_CLK(1, "mcfuart.7", 27, MCF_BUSCLK);
70DEFINE_CLK(1, "mcfuart.8", 28, MCF_BUSCLK);
71DEFINE_CLK(1, "mcfuart.9", 29, MCF_BUSCLK);
72DEFINE_CLK(1, "mcfpwm.0", 34, MCF_BUSCLK);
73DEFINE_CLK(1, "sys.0", 36, MCF_BUSCLK);
74DEFINE_CLK(1, "gpio.0", 37, MCF_BUSCLK);
75
76struct clk *mcf_clks[] = {
77 &__clk_0_2,
78 &__clk_0_8,
79 &__clk_0_9,
80 &__clk_0_14,
81 &__clk_0_15,
82 &__clk_0_17,
83 &__clk_0_18,
84 &__clk_0_19,
85 &__clk_0_20,
86 &__clk_0_22,
87 &__clk_0_23,
88 &__clk_0_24,
89 &__clk_0_25,
90 &__clk_0_26,
91 &__clk_0_27,
92 &__clk_0_28,
93 &__clk_0_29,
94 &__clk_0_30,
95 &__clk_0_31,
96 &__clk_0_32,
97 &__clk_0_33,
98 &__clk_0_34,
99 &__clk_0_35,
100 &__clk_0_37,
101 &__clk_0_38,
102 &__clk_0_39,
103 &__clk_0_42,
104 &__clk_0_43,
105 &__clk_0_44,
106 &__clk_0_45,
107 &__clk_0_46,
108 &__clk_0_47,
109 &__clk_0_48,
110 &__clk_0_49,
111 &__clk_0_50,
112 &__clk_0_51,
113 &__clk_0_53,
114 &__clk_0_54,
115 &__clk_0_55,
116 &__clk_0_56,
117 &__clk_0_63,
118
119 &__clk_1_2,
120 &__clk_1_4,
121 &__clk_1_5,
122 &__clk_1_6,
123 &__clk_1_7,
124 &__clk_1_24,
125 &__clk_1_25,
126 &__clk_1_26,
127 &__clk_1_27,
128 &__clk_1_28,
129 &__clk_1_29,
130 &__clk_1_34,
131 &__clk_1_36,
132 &__clk_1_37,
133 NULL,
134};
135
136
137static struct clk * const enable_clks[] __initconst = {
138 /* make sure these clocks are enabled */
139 &__clk_0_18, /* intc0 */
140 &__clk_0_19, /* intc0 */
141 &__clk_0_20, /* intc0 */
142 &__clk_0_24, /* uart0 */
143 &__clk_0_25, /* uart1 */
144 &__clk_0_26, /* uart2 */
145 &__clk_0_27, /* uart3 */
146
147 &__clk_0_33, /* pit.1 */
148 &__clk_0_37, /* eport */
149 &__clk_0_48, /* pll */
150
151 &__clk_1_36, /* CCM/reset module/Power management */
152 &__clk_1_37, /* gpio */
153};
154static struct clk * const disable_clks[] __initconst = {
155 &__clk_0_8, /* can.0 */
156 &__clk_0_9, /* can.1 */
157 &__clk_0_14, /* i2c.1 */
158 &__clk_0_15, /* dspi.1 */
159 &__clk_0_17, /* eDMA */
160 &__clk_0_22, /* i2c.0 */
161 &__clk_0_23, /* dspi.0 */
162 &__clk_0_28, /* tmr.1 */
163 &__clk_0_29, /* tmr.2 */
164 &__clk_0_30, /* tmr.2 */
165 &__clk_0_31, /* tmr.3 */
166 &__clk_0_32, /* pit.0 */
167 &__clk_0_34, /* pit.2 */
168 &__clk_0_35, /* pit.3 */
169 &__clk_0_38, /* adc */
170 &__clk_0_39, /* dac */
171 &__clk_0_44, /* usb otg */
172 &__clk_0_45, /* usb host */
173 &__clk_0_47, /* ssi.0 */
174 &__clk_0_49, /* rng */
175 &__clk_0_50, /* ssi.1 */
176 &__clk_0_51, /* eSDHC */
177 &__clk_0_53, /* enet-fec */
178 &__clk_0_54, /* enet-fec */
179 &__clk_0_55, /* switch.0 */
180 &__clk_0_56, /* switch.1 */
181
182 &__clk_1_2, /* 1-wire */
183 &__clk_1_4, /* i2c.2 */
184 &__clk_1_5, /* i2c.3 */
185 &__clk_1_6, /* i2c.4 */
186 &__clk_1_7, /* i2c.5 */
187 &__clk_1_24, /* uart 4 */
188 &__clk_1_25, /* uart 5 */
189 &__clk_1_26, /* uart 6 */
190 &__clk_1_27, /* uart 7 */
191 &__clk_1_28, /* uart 8 */
192 &__clk_1_29, /* uart 9 */
193};
194
195static void __init m5441x_clk_init(void)
196{
197 unsigned i;
198
199 for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
200 __clk_init_enabled(enable_clks[i]);
201 /* make sure these clocks are disabled */
202 for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
203 __clk_init_disabled(disable_clks[i]);
204}
205
206static void __init m5441x_uarts_init(void)
207{
208 __raw_writeb(0x0f, MCFGPIO_PAR_UART0);
209 __raw_writeb(0x00, MCFGPIO_PAR_UART1);
210 __raw_writeb(0x00, MCFGPIO_PAR_UART2);
211}
212
213static void __init m5441x_fec_init(void)
214{
215 __raw_writeb(0x03, MCFGPIO_PAR_FEC);
216}
217
218void __init config_BSP(char *commandp, int size)
219{
220 m5441x_clk_init();
221 mach_sched_init = hw_timer_init;
222 m5441x_uarts_init();
223 m5441x_fec_init();
224}
225
226
227#if IS_ENABLED(CONFIG_RTC_DRV_M5441x)
228static struct resource m5441x_rtc_resources[] = {
229 {
230 .start = MCFRTC_BASE,
231 .end = MCFRTC_BASE + MCFRTC_SIZE - 1,
232 .flags = IORESOURCE_MEM,
233 },
234 {
235 .start = MCF_IRQ_RTC,
236 .end = MCF_IRQ_RTC,
237 .flags = IORESOURCE_IRQ,
238 },
239};
240
241static struct platform_device m5441x_rtc = {
242 .name = "mcfrtc",
243 .id = 0,
244 .resource = m5441x_rtc_resources,
245 .num_resources = ARRAY_SIZE(m5441x_rtc_resources),
246};
247#endif
248
249static struct platform_device *m5441x_devices[] __initdata = {
250#if IS_ENABLED(CONFIG_RTC_DRV_M5441x)
251 &m5441x_rtc,
252#endif
253};
254
255static int __init init_BSP(void)
256{
257 platform_add_devices(m5441x_devices, ARRAY_SIZE(m5441x_devices));
258 return 0;
259}
260
261arch_initcall(init_BSP);
diff --git a/arch/m68k/platform/coldfire/m54xx.c b/arch/m68k/platform/coldfire/m54xx.c
deleted file mode 100644
index 952da53aa0b..00000000000
--- a/arch/m68k/platform/coldfire/m54xx.c
+++ /dev/null
@@ -1,129 +0,0 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/54xx/config.c
5 *
6 * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/mm.h>
17#include <linux/clk.h>
18#include <linux/bootmem.h>
19#include <asm/pgalloc.h>
20#include <asm/machdep.h>
21#include <asm/coldfire.h>
22#include <asm/m54xxsim.h>
23#include <asm/mcfuart.h>
24#include <asm/mcfclk.h>
25#include <asm/m54xxgpt.h>
26#include <asm/mcfclk.h>
27#ifdef CONFIG_MMU
28#include <asm/mmu_context.h>
29#endif
30
31/***************************************************************************/
32
33DEFINE_CLK(pll, "pll.0", MCF_CLK);
34DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
35DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK);
36DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK);
37DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
38DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
39DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
40DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
41
42struct clk *mcf_clks[] = {
43 &clk_pll,
44 &clk_sys,
45 &clk_mcfslt0,
46 &clk_mcfslt1,
47 &clk_mcfuart0,
48 &clk_mcfuart1,
49 &clk_mcfuart2,
50 &clk_mcfuart3,
51 NULL
52};
53
54/***************************************************************************/
55
56static void __init m54xx_uarts_init(void)
57{
58 /* enable io pins */
59 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
60 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
61 MCFGPIO_PAR_PSC1);
62 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
63 MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
64 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
65}
66
67/***************************************************************************/
68
69static void mcf54xx_reset(void)
70{
71 /* disable interrupts and enable the watchdog */
72 asm("movew #0x2700, %sr\n");
73 __raw_writel(0, MCF_GPT_GMS0);
74 __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
75 __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
76 MCF_GPT_GMS0);
77}
78
79/***************************************************************************/
80
81#ifdef CONFIG_MMU
82
83unsigned long num_pages;
84
85static void __init mcf54xx_bootmem_alloc(void)
86{
87 unsigned long start_pfn;
88 unsigned long memstart;
89
90 /* _rambase and _ramend will be naturally page aligned */
91 m68k_memory[0].addr = _rambase;
92 m68k_memory[0].size = _ramend - _rambase;
93
94 /* compute total pages in system */
95 num_pages = (_ramend - _rambase) >> PAGE_SHIFT;
96
97 /* page numbers */
98 memstart = PAGE_ALIGN(_ramstart);
99 min_low_pfn = _rambase >> PAGE_SHIFT;
100 start_pfn = memstart >> PAGE_SHIFT;
101 max_low_pfn = _ramend >> PAGE_SHIFT;
102 high_memory = (void *)_ramend;
103
104 m68k_virt_to_node_shift = fls(_ramend - _rambase - 1) - 6;
105 module_fixup(NULL, __start_fixup, __stop_fixup);
106
107 /* setup bootmem data */
108 m68k_setup_node(0);
109 memstart += init_bootmem_node(NODE_DATA(0), start_pfn,
110 min_low_pfn, max_low_pfn);
111 free_bootmem_node(NODE_DATA(0), memstart, _ramend - memstart);
112}
113
114#endif /* CONFIG_MMU */
115
116/***************************************************************************/
117
118void __init config_BSP(char *commandp, int size)
119{
120#ifdef CONFIG_MMU
121 mcf54xx_bootmem_alloc();
122 mmu_context_init();
123#endif
124 mach_reset = mcf54xx_reset;
125 mach_sched_init = hw_timer_init;
126 m54xx_uarts_init();
127}
128
129/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/mcf8390.c b/arch/m68k/platform/coldfire/mcf8390.c
deleted file mode 100644
index 23a6874a324..00000000000
--- a/arch/m68k/platform/coldfire/mcf8390.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * mcf8390.c -- platform support for 8390 ethernet on many boards
3 *
4 * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/resource.h>
15#include <linux/platform_device.h>
16#include <asm/mcf8390.h>
17
18static struct resource mcf8390_resources[] = {
19 {
20 .start = NE2000_ADDR,
21 .end = NE2000_ADDR + NE2000_ADDRSIZE - 1,
22 .flags = IORESOURCE_MEM,
23 },
24 {
25 .start = NE2000_IRQ_VECTOR,
26 .end = NE2000_IRQ_VECTOR,
27 .flags = IORESOURCE_IRQ,
28 },
29};
30
31static int __init mcf8390_platform_init(void)
32{
33 platform_device_register_simple("mcf8390", -1, mcf8390_resources,
34 ARRAY_SIZE(mcf8390_resources));
35 return 0;
36}
37
38arch_initcall(mcf8390_platform_init);
diff --git a/arch/m68k/platform/coldfire/nettel.c b/arch/m68k/platform/coldfire/nettel.c
deleted file mode 100644
index ddc48ec1b80..00000000000
--- a/arch/m68k/platform/coldfire/nettel.c
+++ /dev/null
@@ -1,153 +0,0 @@
1/***************************************************************************/
2
3/*
4 * nettel.c -- startup code support for the NETtel boards
5 *
6 * Copyright (C) 2009, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <asm/coldfire.h>
17#include <asm/mcfsim.h>
18#include <asm/nettel.h>
19
20/***************************************************************************/
21
22/*
23 * Define the IO and interrupt resources of the 2 SMC9196 interfaces.
24 */
25#define NETTEL_SMC0_ADDR 0x30600300
26#define NETTEL_SMC0_IRQ 29
27
28#define NETTEL_SMC1_ADDR 0x30600000
29#define NETTEL_SMC1_IRQ 27
30
31/*
32 * We need some access into the SMC9196 registers. Define those registers
33 * we will need here (including the smc91x.h doesn't seem to give us these
34 * in a simple form).
35 */
36#define SMC91xx_BANKSELECT 14
37#define SMC91xx_BASEADDR 2
38#define SMC91xx_BASEMAC 4
39
40/***************************************************************************/
41
42static struct resource nettel_smc91x_0_resources[] = {
43 {
44 .start = NETTEL_SMC0_ADDR,
45 .end = NETTEL_SMC0_ADDR + 0x20,
46 .flags = IORESOURCE_MEM,
47 },
48 {
49 .start = NETTEL_SMC0_IRQ,
50 .end = NETTEL_SMC0_IRQ,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55static struct resource nettel_smc91x_1_resources[] = {
56 {
57 .start = NETTEL_SMC1_ADDR,
58 .end = NETTEL_SMC1_ADDR + 0x20,
59 .flags = IORESOURCE_MEM,
60 },
61 {
62 .start = NETTEL_SMC1_IRQ,
63 .end = NETTEL_SMC1_IRQ,
64 .flags = IORESOURCE_IRQ,
65 },
66};
67
68static struct platform_device nettel_smc91x[] = {
69 {
70 .name = "smc91x",
71 .id = 0,
72 .num_resources = ARRAY_SIZE(nettel_smc91x_0_resources),
73 .resource = nettel_smc91x_0_resources,
74 },
75 {
76 .name = "smc91x",
77 .id = 1,
78 .num_resources = ARRAY_SIZE(nettel_smc91x_1_resources),
79 .resource = nettel_smc91x_1_resources,
80 },
81};
82
83static struct platform_device *nettel_devices[] __initdata = {
84 &nettel_smc91x[0],
85 &nettel_smc91x[1],
86};
87
88/***************************************************************************/
89
90static u8 nettel_macdefault[] __initdata = {
91 0x00, 0xd0, 0xcf, 0x00, 0x00, 0x01,
92};
93
94/*
95 * Set flash contained MAC address into SMC9196 core. Make sure the flash
96 * MAC address is sane, and not an empty flash. If no good use the Moreton
97 * Bay default MAC address instead.
98 */
99
100static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flashaddr)
101{
102 u16 *macp;
103
104 macp = (u16 *) flashaddr;
105 if ((macp[0] == 0xffff) && (macp[1] == 0xffff) && (macp[2] == 0xffff))
106 macp = (u16 *) &nettel_macdefault[0];
107
108 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
109 writew(macp[0], ioaddr + SMC91xx_BASEMAC);
110 writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2);
111 writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4);
112}
113
114/***************************************************************************/
115
116/*
117 * Re-map the address space of at least one of the SMC ethernet
118 * parts. Both parts power up decoding the same address, so we
119 * need to move one of them first, before doing anything else.
120 */
121
122static void __init nettel_smc91x_init(void)
123{
124 writew(0x00ec, MCFSIM_PADDR);
125 mcf_setppdata(0, 0x0080);
126 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
127 writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
128 mcf_setppdata(0x0080, 0);
129
130 /* Set correct chip select timing for SMC9196 accesses */
131 writew(0x1180, MCFSIM_CSCR3);
132
133 /* Set the SMC interrupts to be auto-vectored */
134 mcf_autovector(NETTEL_SMC0_IRQ);
135 mcf_autovector(NETTEL_SMC1_IRQ);
136
137 /* Set MAC addresses from flash for both interfaces */
138 nettel_smc91x_setmac(NETTEL_SMC0_ADDR, 0xf0006000);
139 nettel_smc91x_setmac(NETTEL_SMC1_ADDR, 0xf0006006);
140}
141
142/***************************************************************************/
143
144static int __init init_nettel(void)
145{
146 nettel_smc91x_init();
147 platform_add_devices(nettel_devices, ARRAY_SIZE(nettel_devices));
148 return 0;
149}
150
151arch_initcall(init_nettel);
152
153/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/pci.c b/arch/m68k/platform/coldfire/pci.c
deleted file mode 100644
index 8572246db84..00000000000
--- a/arch/m68k/platform/coldfire/pci.c
+++ /dev/null
@@ -1,327 +0,0 @@
1/*
2 * pci.c -- PCI bus support for ColdFire processors
3 *
4 * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <asm/coldfire.h>
21#include <asm/mcfsim.h>
22#include <asm/m54xxpci.h>
23
24/*
25 * Memory and IO mappings. We use a 1:1 mapping for local host memory to
26 * PCI bus memory (no reason not to really). IO space doesn't matter, we
27 * always use access functions for that. The device configuration space is
28 * mapped over the IO map space when we enable it in the PCICAR register.
29 */
30#define PCI_MEM_PA 0xf0000000 /* Host physical address */
31#define PCI_MEM_BA 0xf0000000 /* Bus physical address */
32#define PCI_MEM_SIZE 0x08000000 /* 128 MB */
33#define PCI_MEM_MASK (PCI_MEM_SIZE - 1)
34
35#define PCI_IO_PA 0xf8000000 /* Host physical address */
36#define PCI_IO_BA 0x00000000 /* Bus physical address */
37#define PCI_IO_SIZE 0x00010000 /* 64k */
38#define PCI_IO_MASK (PCI_IO_SIZE - 1)
39
40static struct pci_bus *rootbus;
41static unsigned long iospace;
42
43/*
44 * We need to be carefull probing on bus 0 (directly connected to host
45 * bridge). We should only acccess the well defined possible devices in
46 * use, ignore aliases and the like.
47 */
48static unsigned char mcf_host_slot2sid[32] = {
49 0, 0, 0, 0, 0, 0, 0, 0,
50 0, 0, 0, 0, 0, 0, 0, 0,
51 0, 1, 2, 0, 3, 4, 0, 0,
52 0, 0, 0, 0, 0, 0, 0, 0,
53};
54
55static unsigned char mcf_host_irq[] = {
56 0, 69, 69, 71, 71,
57};
58
59
60static inline void syncio(void)
61{
62 /* The ColdFire "nop" instruction waits for all bus IO to complete */
63 __asm__ __volatile__ ("nop");
64}
65
66/*
67 * Configuration space access functions. Configuration space access is
68 * through the IO mapping window, enabling it via the PCICAR register.
69 */
70static unsigned long mcf_mk_pcicar(int bus, unsigned int devfn, int where)
71{
72 return (bus << PCICAR_BUSN) | (devfn << PCICAR_DEVFNN) | (where & 0xfc);
73}
74
75static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
76 int where, int size, u32 *value)
77{
78 unsigned long addr;
79
80 *value = 0xffffffff;
81
82 if (bus->number == 0) {
83 if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
84 return PCIBIOS_SUCCESSFUL;
85 }
86
87 syncio();
88 addr = mcf_mk_pcicar(bus->number, devfn, where);
89 __raw_writel(PCICAR_E | addr, PCICAR);
90 addr = iospace + (where & 0x3);
91
92 switch (size) {
93 case 1:
94 *value = __raw_readb(addr);
95 break;
96 case 2:
97 *value = le16_to_cpu(__raw_readw(addr));
98 break;
99 default:
100 *value = le32_to_cpu(__raw_readl(addr));
101 break;
102 }
103
104 syncio();
105 __raw_writel(0, PCICAR);
106 return PCIBIOS_SUCCESSFUL;
107}
108
109static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
110 int where, int size, u32 value)
111{
112 unsigned long addr;
113
114 if (bus->number == 0) {
115 if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
116 return PCIBIOS_SUCCESSFUL;
117 }
118
119 syncio();
120 addr = mcf_mk_pcicar(bus->number, devfn, where);
121 __raw_writel(PCICAR_E | addr, PCICAR);
122 addr = iospace + (where & 0x3);
123
124 switch (size) {
125 case 1:
126 __raw_writeb(value, addr);
127 break;
128 case 2:
129 __raw_writew(cpu_to_le16(value), addr);
130 break;
131 default:
132 __raw_writel(cpu_to_le32(value), addr);
133 break;
134 }
135
136 syncio();
137 __raw_writel(0, PCICAR);
138 return PCIBIOS_SUCCESSFUL;
139}
140
141static struct pci_ops mcf_pci_ops = {
142 .read = mcf_pci_readconfig,
143 .write = mcf_pci_writeconfig,
144};
145
146/*
147 * IO address space access functions. Pretty strait forward, these are
148 * directly mapped in to the IO mapping window. And that is mapped into
149 * virtual address space.
150 */
151u8 mcf_pci_inb(u32 addr)
152{
153 return __raw_readb(iospace + (addr & PCI_IO_MASK));
154}
155EXPORT_SYMBOL(mcf_pci_inb);
156
157u16 mcf_pci_inw(u32 addr)
158{
159 return le16_to_cpu(__raw_readw(iospace + (addr & PCI_IO_MASK)));
160}
161EXPORT_SYMBOL(mcf_pci_inw);
162
163u32 mcf_pci_inl(u32 addr)
164{
165 return le32_to_cpu(__raw_readl(iospace + (addr & PCI_IO_MASK)));
166}
167EXPORT_SYMBOL(mcf_pci_inl);
168
169void mcf_pci_insb(u32 addr, u8 *buf, u32 len)
170{
171 for (; len; len--)
172 *buf++ = mcf_pci_inb(addr);
173}
174EXPORT_SYMBOL(mcf_pci_insb);
175
176void mcf_pci_insw(u32 addr, u16 *buf, u32 len)
177{
178 for (; len; len--)
179 *buf++ = mcf_pci_inw(addr);
180}
181EXPORT_SYMBOL(mcf_pci_insw);
182
183void mcf_pci_insl(u32 addr, u32 *buf, u32 len)
184{
185 for (; len; len--)
186 *buf++ = mcf_pci_inl(addr);
187}
188EXPORT_SYMBOL(mcf_pci_insl);
189
190void mcf_pci_outb(u8 v, u32 addr)
191{
192 __raw_writeb(v, iospace + (addr & PCI_IO_MASK));
193}
194EXPORT_SYMBOL(mcf_pci_outb);
195
196void mcf_pci_outw(u16 v, u32 addr)
197{
198 __raw_writew(cpu_to_le16(v), iospace + (addr & PCI_IO_MASK));
199}
200EXPORT_SYMBOL(mcf_pci_outw);
201
202void mcf_pci_outl(u32 v, u32 addr)
203{
204 __raw_writel(cpu_to_le32(v), iospace + (addr & PCI_IO_MASK));
205}
206EXPORT_SYMBOL(mcf_pci_outl);
207
208void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len)
209{
210 for (; len; len--)
211 mcf_pci_outb(*buf++, addr);
212}
213EXPORT_SYMBOL(mcf_pci_outsb);
214
215void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len)
216{
217 for (; len; len--)
218 mcf_pci_outw(*buf++, addr);
219}
220EXPORT_SYMBOL(mcf_pci_outsw);
221
222void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len)
223{
224 for (; len; len--)
225 mcf_pci_outl(*buf++, addr);
226}
227EXPORT_SYMBOL(mcf_pci_outsl);
228
229/*
230 * Initialize the PCI bus registers, and scan the bus.
231 */
232static struct resource mcf_pci_mem = {
233 .name = "PCI Memory space",
234 .start = PCI_MEM_PA,
235 .end = PCI_MEM_PA + PCI_MEM_SIZE - 1,
236 .flags = IORESOURCE_MEM,
237};
238
239static struct resource mcf_pci_io = {
240 .name = "PCI IO space",
241 .start = 0x400,
242 .end = 0x10000 - 1,
243 .flags = IORESOURCE_IO,
244};
245
246/*
247 * Interrupt mapping and setting.
248 */
249static int mcf_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
250{
251 int sid;
252
253 sid = mcf_host_slot2sid[slot];
254 if (sid)
255 return mcf_host_irq[sid];
256 return 0;
257}
258
259static int __init mcf_pci_init(void)
260{
261 pr_info("ColdFire: PCI bus initialization...\n");
262
263 /* Reset the external PCI bus */
264 __raw_writel(PCIGSCR_RESET, PCIGSCR);
265 __raw_writel(0, PCITCR);
266
267 request_resource(&iomem_resource, &mcf_pci_mem);
268 request_resource(&iomem_resource, &mcf_pci_io);
269
270 /* Configure PCI arbiter */
271 __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
272 PACR_EXTMINTE(0x1f), PACR);
273
274 /* Set required multi-function pins for PCI bus use */
275 __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
276 __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
277
278 /* Set up config space for local host bus controller */
279 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
280 PCI_COMMAND_INVALIDATE, PCISCR);
281 __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
282 __raw_writel(0, PCICR2);
283
284 /*
285 * Set up the initiator windows for memory and IO mapping.
286 * These give the CPU bus access onto the PCI bus. One for each of
287 * PCI memory and IO address spaces.
288 */
289 __raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
290 PCIIW0BTAR);
291 __raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
292 PCIIW1BTAR);
293 __raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
294 PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR);
295
296 /*
297 * Set up the target windows for access from the PCI bus back to the
298 * CPU bus. All we need is access to system RAM (for mastering).
299 */
300 __raw_writel(CONFIG_RAMBASE, PCIBAR1);
301 __raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
302
303 /* Keep a virtual mapping to IO/config space active */
304 iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE);
305 if (iospace == 0)
306 return -ENODEV;
307 pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n",
308 (u32) iospace);
309
310 /* Turn of PCI reset, and wait for devices to settle */
311 __raw_writel(0, PCIGSCR);
312 set_current_state(TASK_UNINTERRUPTIBLE);
313 schedule_timeout(msecs_to_jiffies(200));
314
315 rootbus = pci_scan_bus(0, &mcf_pci_ops, NULL);
316 rootbus->resource[0] = &mcf_pci_io;
317 rootbus->resource[1] = &mcf_pci_mem;
318
319 pci_fixup_irqs(pci_common_swizzle, mcf_pci_map_irq);
320 pci_bus_size_bridges(rootbus);
321 pci_bus_assign_resources(rootbus);
322 pci_enable_bridges(rootbus);
323 pci_bus_add_devices(rootbus);
324 return 0;
325}
326
327subsys_initcall(mcf_pci_init);
diff --git a/arch/m68k/platform/coldfire/pit.c b/arch/m68k/platform/coldfire/pit.c
index e8f3b97b0f7..c2b980926be 100644
--- a/arch/m68k/platform/coldfire/pit.c
+++ b/arch/m68k/platform/coldfire/pit.c
@@ -93,7 +93,7 @@ struct clock_event_device cf_pit_clockevent = {
93 .set_mode = init_cf_pit_timer, 93 .set_mode = init_cf_pit_timer,
94 .set_next_event = cf_pit_next_event, 94 .set_next_event = cf_pit_next_event,
95 .shift = 32, 95 .shift = 32,
96 .irq = MCF_IRQ_PIT1, 96 .irq = MCFINT_VECBASE + MCFINT_PIT1,
97}; 97};
98 98
99 99
@@ -144,12 +144,13 @@ static struct clocksource pit_clk = {
144 .name = "pit", 144 .name = "pit",
145 .rating = 100, 145 .rating = 100,
146 .read = pit_read_clk, 146 .read = pit_read_clk,
147 .shift = 20,
147 .mask = CLOCKSOURCE_MASK(32), 148 .mask = CLOCKSOURCE_MASK(32),
148}; 149};
149 150
150/***************************************************************************/ 151/***************************************************************************/
151 152
152void hw_timer_init(irq_handler_t handler) 153void hw_timer_init(void)
153{ 154{
154 cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id()); 155 cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
155 cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32); 156 cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
@@ -159,9 +160,10 @@ void hw_timer_init(irq_handler_t handler)
159 clockevent_delta2ns(0x3f, &cf_pit_clockevent); 160 clockevent_delta2ns(0x3f, &cf_pit_clockevent);
160 clockevents_register_device(&cf_pit_clockevent); 161 clockevents_register_device(&cf_pit_clockevent);
161 162
162 setup_irq(MCF_IRQ_PIT1, &pit_irq); 163 setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
163 164
164 clocksource_register_hz(&pit_clk, FREQ); 165 pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift);
166 clocksource_register(&pit_clk);
165} 167}
166 168
167/***************************************************************************/ 169/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/reset.c b/arch/m68k/platform/coldfire/reset.c
deleted file mode 100644
index f30952f0cbe..00000000000
--- a/arch/m68k/platform/coldfire/reset.c
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * reset.c -- common ColdFire SoC reset support
3 *
4 * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <asm/machdep.h>
15#include <asm/coldfire.h>
16#include <asm/mcfsim.h>
17
18/*
19 * There are 2 common methods amongst the ColdFure parts for reseting
20 * the CPU. But there are couple of exceptions, the 5272 and the 547x
21 * have something completely special to them, and we let their specific
22 * subarch code handle them.
23 */
24
25#ifdef MCFSIM_SYPCR
26static void mcf_cpu_reset(void)
27{
28 local_irq_disable();
29 /* Set watchdog to soft reset, and enabled */
30 __raw_writeb(0xc0, MCFSIM_SYPCR);
31 for (;;)
32 /* wait for watchdog to timeout */;
33}
34#endif
35
36#ifdef MCF_RCR
37static void mcf_cpu_reset(void)
38{
39 local_irq_disable();
40 __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
41}
42#endif
43
44static int __init mcf_setup_reset(void)
45{
46 mach_reset = mcf_cpu_reset;
47 return 0;
48}
49
50arch_initcall(mcf_setup_reset);
diff --git a/arch/m68k/platform/coldfire/sltimers.c b/arch/m68k/platform/coldfire/sltimers.c
index bb5a25ada84..6a85daf9a7f 100644
--- a/arch/m68k/platform/coldfire/sltimers.c
+++ b/arch/m68k/platform/coldfire/sltimers.c
@@ -32,7 +32,7 @@
32/* 32/*
33 * By default use Slice Timer 1 as the profiler clock timer. 33 * By default use Slice Timer 1 as the profiler clock timer.
34 */ 34 */
35#define PA(a) (MCFSLT_TIMER1 + (a)) 35#define PA(a) (MCF_MBAR + MCFSLT_TIMER1 + (a))
36 36
37/* 37/*
38 * Choose a reasonably fast profile timer. Make it an odd value to 38 * Choose a reasonably fast profile timer. Make it an odd value to
@@ -76,19 +76,17 @@ void mcfslt_profile_init(void)
76/* 76/*
77 * By default use Slice Timer 0 as the system clock timer. 77 * By default use Slice Timer 0 as the system clock timer.
78 */ 78 */
79#define TA(a) (MCFSLT_TIMER0 + (a)) 79#define TA(a) (MCF_MBAR + MCFSLT_TIMER0 + (a))
80 80
81static u32 mcfslt_cycles_per_jiffy; 81static u32 mcfslt_cycles_per_jiffy;
82static u32 mcfslt_cnt; 82static u32 mcfslt_cnt;
83 83
84static irq_handler_t timer_interrupt;
85
86static irqreturn_t mcfslt_tick(int irq, void *dummy) 84static irqreturn_t mcfslt_tick(int irq, void *dummy)
87{ 85{
88 /* Reset Slice Timer 0 */ 86 /* Reset Slice Timer 0 */
89 __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR)); 87 __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
90 mcfslt_cnt += mcfslt_cycles_per_jiffy; 88 mcfslt_cnt += mcfslt_cycles_per_jiffy;
91 return timer_interrupt(irq, dummy); 89 return arch_timer_interrupt(irq, dummy);
92} 90}
93 91
94static struct irqaction mcfslt_timer_irq = { 92static struct irqaction mcfslt_timer_irq = {
@@ -100,30 +98,28 @@ static struct irqaction mcfslt_timer_irq = {
100static cycle_t mcfslt_read_clk(struct clocksource *cs) 98static cycle_t mcfslt_read_clk(struct clocksource *cs)
101{ 99{
102 unsigned long flags; 100 unsigned long flags;
103 u32 cycles, scnt; 101 u32 cycles;
102 u16 scnt;
104 103
105 local_irq_save(flags); 104 local_irq_save(flags);
106 scnt = __raw_readl(TA(MCFSLT_SCNT)); 105 scnt = __raw_readl(TA(MCFSLT_SCNT));
107 cycles = mcfslt_cnt; 106 cycles = mcfslt_cnt;
108 if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) {
109 cycles += mcfslt_cycles_per_jiffy;
110 scnt = __raw_readl(TA(MCFSLT_SCNT));
111 }
112 local_irq_restore(flags); 107 local_irq_restore(flags);
113 108
114 /* subtract because slice timers count down */ 109 /* subtract because slice timers count down */
115 return cycles + ((mcfslt_cycles_per_jiffy - 1) - scnt); 110 return cycles - scnt;
116} 111}
117 112
118static struct clocksource mcfslt_clk = { 113static struct clocksource mcfslt_clk = {
119 .name = "slt", 114 .name = "slt",
120 .rating = 250, 115 .rating = 250,
121 .read = mcfslt_read_clk, 116 .read = mcfslt_read_clk,
117 .shift = 20,
122 .mask = CLOCKSOURCE_MASK(32), 118 .mask = CLOCKSOURCE_MASK(32),
123 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 119 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
124}; 120};
125 121
126void hw_timer_init(irq_handler_t handler) 122void hw_timer_init(void)
127{ 123{
128 mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ; 124 mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
129 /* 125 /*
@@ -138,10 +134,10 @@ void hw_timer_init(irq_handler_t handler)
138 /* initialize mcfslt_cnt knowing that slice timers count down */ 134 /* initialize mcfslt_cnt knowing that slice timers count down */
139 mcfslt_cnt = mcfslt_cycles_per_jiffy; 135 mcfslt_cnt = mcfslt_cycles_per_jiffy;
140 136
141 timer_interrupt = handler;
142 setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq); 137 setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
143 138
144 clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK); 139 mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift);
140 clocksource_register(&mcfslt_clk);
145 141
146#ifdef CONFIG_HIGHPROFILE 142#ifdef CONFIG_HIGHPROFILE
147 mcfslt_profile_init(); 143 mcfslt_profile_init();
diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c
index 51f6d2af807..60242f65fea 100644
--- a/arch/m68k/platform/coldfire/timers.c
+++ b/arch/m68k/platform/coldfire/timers.c
@@ -36,7 +36,7 @@
36 */ 36 */
37void coldfire_profile_init(void); 37void coldfire_profile_init(void);
38 38
39#if defined(CONFIG_M532x) || defined(CONFIG_M5441x) 39#if defined(CONFIG_M532x)
40#define __raw_readtrr __raw_readl 40#define __raw_readtrr __raw_readl
41#define __raw_writetrr __raw_writel 41#define __raw_writetrr __raw_writel
42#else 42#else
@@ -47,27 +47,6 @@ void coldfire_profile_init(void);
47static u32 mcftmr_cycles_per_jiffy; 47static u32 mcftmr_cycles_per_jiffy;
48static u32 mcftmr_cnt; 48static u32 mcftmr_cnt;
49 49
50static irq_handler_t timer_interrupt;
51
52/***************************************************************************/
53
54static void init_timer_irq(void)
55{
56#ifdef MCFSIM_ICR_AUTOVEC
57 /* Timer1 is always used as system timer */
58 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
59 MCFSIM_TIMER1ICR);
60 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
61
62#ifdef CONFIG_HIGHPROFILE
63 /* Timer2 is to be used as a high speed profile timer */
64 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
65 MCFSIM_TIMER2ICR);
66 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
67#endif
68#endif /* MCFSIM_ICR_AUTOVEC */
69}
70
71/***************************************************************************/ 50/***************************************************************************/
72 51
73static irqreturn_t mcftmr_tick(int irq, void *dummy) 52static irqreturn_t mcftmr_tick(int irq, void *dummy)
@@ -76,7 +55,7 @@ static irqreturn_t mcftmr_tick(int irq, void *dummy)
76 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER)); 55 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
77 56
78 mcftmr_cnt += mcftmr_cycles_per_jiffy; 57 mcftmr_cnt += mcftmr_cycles_per_jiffy;
79 return timer_interrupt(irq, dummy); 58 return arch_timer_interrupt(irq, dummy);
80} 59}
81 60
82/***************************************************************************/ 61/***************************************************************************/
@@ -109,13 +88,14 @@ static struct clocksource mcftmr_clk = {
109 .name = "tmr", 88 .name = "tmr",
110 .rating = 250, 89 .rating = 250,
111 .read = mcftmr_read_clk, 90 .read = mcftmr_read_clk,
91 .shift = 20,
112 .mask = CLOCKSOURCE_MASK(32), 92 .mask = CLOCKSOURCE_MASK(32),
113 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 93 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
114}; 94};
115 95
116/***************************************************************************/ 96/***************************************************************************/
117 97
118void hw_timer_init(irq_handler_t handler) 98void hw_timer_init(void)
119{ 99{
120 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR)); 100 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
121 mcftmr_cycles_per_jiffy = FREQ / HZ; 101 mcftmr_cycles_per_jiffy = FREQ / HZ;
@@ -129,10 +109,9 @@ void hw_timer_init(irq_handler_t handler)
129 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | 109 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
130 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR)); 110 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
131 111
132 clocksource_register_hz(&mcftmr_clk, FREQ); 112 mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
113 clocksource_register(&mcftmr_clk);
133 114
134 timer_interrupt = handler;
135 init_timer_irq();
136 setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq); 115 setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
137 116
138#ifdef CONFIG_HIGHPROFILE 117#ifdef CONFIG_HIGHPROFILE
diff --git a/arch/m68k/platform/coldfire/vectors.c b/arch/m68k/platform/coldfire/vectors.c
index a4dbdecbec7..3a7cc524ecd 100644
--- a/arch/m68k/platform/coldfire/vectors.c
+++ b/arch/m68k/platform/coldfire/vectors.c
@@ -33,6 +33,8 @@ asmlinkage void dbginterrupt_c(struct frame *fp)
33 33
34/***************************************************************************/ 34/***************************************************************************/
35 35
36extern e_vector *_ramvec;
37
36/* Assembler routines */ 38/* Assembler routines */
37asmlinkage void buserr(void); 39asmlinkage void buserr(void);
38asmlinkage void trap(void); 40asmlinkage void trap(void);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 15:58:05 -0400