Added missing tegra files.HEADmaster

3 files changed, 189 insertions, 0 deletions

diff --git a/arch/m68k/platform/5407/Makefile b/arch/m68k/platform/5407/Makefile
new file mode 100644
index 00000000000..e83fe148edd
--- /dev/null
+++ b/arch/m68k/platform/5407/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for the m68knommu linux kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs. You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o gpio.o
+
diff --git a/arch/m68k/platform/5407/config.c b/arch/m68k/platform/5407/config.c
new file mode 100644
index 00000000000..70ea789a400
--- /dev/null
+++ b/arch/m68k/platform/5407/config.c
@@ -0,0 +1,122 @@
+/***************************************************************************/
+
+/*
+ *      linux/arch/m68knommu/platform/5407/config.c
+ *
+ *      Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
+ *      Copyright (C) 2000, Lineo (www.lineo.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m5407_uart_platform[] = {
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE1,
+                .irq            = 73,
+        },
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE2,
+                .irq            = 74,
+        },
+        { },
+};
+
+static struct platform_device m5407_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m5407_uart_platform,
+};
+
+static struct platform_device *m5407_devices[] __initdata = {
+        &m5407_uart,
+};
+
+/***************************************************************************/
+
+static void __init m5407_uart_init_line(int line, int irq)
+{
+        if (line == 0) {
+                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+                writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
+                mcf_mapirq2imr(irq, MCFINTC_UART0);
+        } else if (line == 1) {
+                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+                writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
+                mcf_mapirq2imr(irq, MCFINTC_UART1);
+        }
+}
+
+static void __init m5407_uarts_init(void)
+{
+        const int nrlines = ARRAY_SIZE(m5407_uart_platform);
+        int line;
+
+        for (line = 0; (line < nrlines); line++)
+                m5407_uart_init_line(line, m5407_uart_platform[line].irq);
+}
+
+/***************************************************************************/
+
+static void __init m5407_timers_init(void)
+{
+        /* Timer1 is always used as system timer */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
+                MCF_MBAR + MCFSIM_TIMER1ICR);
+        mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
+
+#ifdef CONFIG_HIGHPROFILE
+        /* Timer2 is to be used as a high speed profile timer  */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
+                MCF_MBAR + MCFSIM_TIMER2ICR);
+        mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
+#endif
+}
+
+/***************************************************************************/
+
+void m5407_cpu_reset(void)
+{
+        local_irq_disable();
+        /* set watchdog to soft reset, and enabled */
+        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
+        for (;;)
+                /* wait for watchdog to timeout */;
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+        mach_reset = m5407_cpu_reset;
+        m5407_timers_init();
+        m5407_uarts_init();
+
+        /* Only support the external interrupts on their primary level */
+        mcf_mapirq2imr(25, MCFINTC_EINT1);
+        mcf_mapirq2imr(27, MCFINTC_EINT3);
+        mcf_mapirq2imr(29, MCFINTC_EINT5);
+        mcf_mapirq2imr(31, MCFINTC_EINT7);
+}
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+        platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/5407/gpio.c b/arch/m68k/platform/5407/gpio.c
new file mode 100644
index 00000000000..5850612b4a3
--- /dev/null
+++ b/arch/m68k/platform/5407/gpio.c
@@ -0,0 +1,49 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+        {
+                .gpio_chip                      = {
+                        .label                  = "PP",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .ngpio                  = 16,
+                },
+                .pddr                           = (void __iomem *) MCFSIM_PADDR,
+                .podr                           = (void __iomem *) MCFSIM_PADAT,
+                .ppdr                           = (void __iomem *) MCFSIM_PADAT,
+        },
+};
+
+static int __init mcf_gpio_init(void)
+{
+        unsigned i = 0;
+        while (i < ARRAY_SIZE(mcf_gpio_chips))
+                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+        return 0;
+}
+
+core_initcall(mcf_gpio_init);