diff options
| author | Steven King <sfking@fdwdc.com> | 2012-06-06 17:02:14 -0400 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2012-07-15 19:59:21 -0400 |
| commit | bdee4e26ba6568118f2376ebcfdeef3b7f527bce (patch) | |
| tree | 6a0c684b48ea98c606d634aac2c9cb1707f31095 /arch/m68k/include/asm | |
| parent | bce4d12bf88cc0748c7ebe2e1778636965b761a8 (diff) | |
m68knommu: use MCF_IRQ_PIT1 instead of MCFINT_VECBASE + MCFINT_PIT1
use MCF_IRQ_PIT1 instead of MCFINT_VECBASE + MCFINT_PIT1 so we can support
those parts that have the pit1 interrupt on other than the first interrupt
controller.
Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm')
| -rw-r--r-- | arch/m68k/include/asm/m520xsim.h | 1 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m523xsim.h | 1 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m527xsim.h | 1 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m528xsim.h | 2 |
4 files changed, 4 insertions, 1 deletions
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index 17f2aab9cf9..5a8b5e4da12 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h | |||
| @@ -62,6 +62,7 @@ | |||
| 62 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) | 62 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) |
| 63 | 63 | ||
| 64 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) | 64 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
| 65 | #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) | ||
| 65 | 66 | ||
| 66 | /* | 67 | /* |
| 67 | * SDRAM configuration registers. | 68 | * SDRAM configuration registers. |
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index 075062d4eec..91d3abc3f2a 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h | |||
| @@ -52,6 +52,7 @@ | |||
| 52 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) | 52 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) |
| 53 | 53 | ||
| 54 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) | 54 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
| 55 | #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) | ||
| 55 | 56 | ||
| 56 | /* | 57 | /* |
| 57 | * SDRAM configuration registers. | 58 | * SDRAM configuration registers. |
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 83db8106f50..71aa5104d3d 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h | |||
| @@ -60,6 +60,7 @@ | |||
| 60 | #define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) | 60 | #define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) |
| 61 | 61 | ||
| 62 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) | 62 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
| 63 | #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) | ||
| 63 | 64 | ||
| 64 | /* | 65 | /* |
| 65 | * SDRAM configuration registers. | 66 | * SDRAM configuration registers. |
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index 497c31c803f..4acb3c0a642 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h | |||
| @@ -52,7 +52,7 @@ | |||
| 52 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) | 52 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) |
| 53 | 53 | ||
| 54 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) | 54 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
| 55 | 55 | #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) | |
| 56 | /* | 56 | /* |
| 57 | * SDRAM configuration registers. | 57 | * SDRAM configuration registers. |
| 58 | */ | 58 | */ |