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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /arch/m68k/include/asm
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'arch/m68k/include/asm')
-rw-r--r--arch/m68k/include/asm/Kbuild36
-rw-r--r--arch/m68k/include/asm/apollohw.h14
-rw-r--r--arch/m68k/include/asm/atarihw.h2
-rw-r--r--arch/m68k/include/asm/atariints.h4
-rw-r--r--arch/m68k/include/asm/atomic.h13
-rw-r--r--arch/m68k/include/asm/barrier.h20
-rw-r--r--arch/m68k/include/asm/blinken.h8
-rw-r--r--arch/m68k/include/asm/cacheflush.h4
-rw-r--r--arch/m68k/include/asm/cacheflush_mm.h129
-rw-r--r--arch/m68k/include/asm/cacheflush_no.h49
-rw-r--r--arch/m68k/include/asm/checksum.h31
-rw-r--r--arch/m68k/include/asm/cmpxchg.h141
-rw-r--r--arch/m68k/include/asm/delay.h2
-rw-r--r--arch/m68k/include/asm/div64.h8
-rw-r--r--arch/m68k/include/asm/dma.h8
-rw-r--r--arch/m68k/include/asm/elf.h9
-rw-r--r--arch/m68k/include/asm/entry.h261
-rw-r--r--arch/m68k/include/asm/flat.h7
-rw-r--r--arch/m68k/include/asm/fpu.h2
-rw-r--r--arch/m68k/include/asm/gpio.h178
-rw-r--r--arch/m68k/include/asm/hardirq.h5
-rw-r--r--arch/m68k/include/asm/io.h4
-rw-r--r--arch/m68k/include/asm/io_mm.h57
-rw-r--r--arch/m68k/include/asm/irq.h87
-rw-r--r--arch/m68k/include/asm/m5206sim.h108
-rw-r--r--arch/m68k/include/asm/m520xsim.h73
-rw-r--r--arch/m68k/include/asm/m523xsim.h67
-rw-r--r--arch/m68k/include/asm/m525xsim.h308
-rw-r--r--arch/m68k/include/asm/m5272sim.h118
-rw-r--r--arch/m68k/include/asm/m527xsim.h138
-rw-r--r--arch/m68k/include/asm/m528xsim.h268
-rw-r--r--arch/m68k/include/asm/m5307sim.h146
-rw-r--r--arch/m68k/include/asm/m532xsim.h1237
-rw-r--r--arch/m68k/include/asm/m5407sim.h116
-rw-r--r--arch/m68k/include/asm/m5441xsim.h276
-rw-r--r--arch/m68k/include/asm/m54xxacr.h36
-rw-r--r--arch/m68k/include/asm/m54xxgpt.h40
-rw-r--r--arch/m68k/include/asm/m54xxpci.h138
-rw-r--r--arch/m68k/include/asm/m54xxsim.h40
-rw-r--r--arch/m68k/include/asm/m68360.h8
-rw-r--r--arch/m68k/include/asm/m68360_enet.h2
-rw-r--r--arch/m68k/include/asm/mac_baboon.h6
-rw-r--r--arch/m68k/include/asm/mac_iop.h2
-rw-r--r--arch/m68k/include/asm/mac_oss.h23
-rw-r--r--arch/m68k/include/asm/mac_psc.h4
-rw-r--r--arch/m68k/include/asm/mac_via.h9
-rw-r--r--arch/m68k/include/asm/machdep.h5
-rw-r--r--arch/m68k/include/asm/macintosh.h10
-rw-r--r--arch/m68k/include/asm/macints.h6
-rw-r--r--arch/m68k/include/asm/mcf8390.h131
-rw-r--r--arch/m68k/include/asm/mcf_pgalloc.h102
-rw-r--r--arch/m68k/include/asm/mcf_pgtable.h426
-rw-r--r--arch/m68k/include/asm/mcfclk.h50
-rw-r--r--arch/m68k/include/asm/mcfgpio.h300
-rw-r--r--arch/m68k/include/asm/mcfmmu.h112
-rw-r--r--arch/m68k/include/asm/mcfqspi.h9
-rw-r--r--arch/m68k/include/asm/mcfsim.h6
-rw-r--r--arch/m68k/include/asm/mcfslt.h7
-rw-r--r--arch/m68k/include/asm/mcftimer.h2
-rw-r--r--arch/m68k/include/asm/mcfuart.h5
-rw-r--r--arch/m68k/include/asm/mmu_context.h250
-rw-r--r--arch/m68k/include/asm/module.h6
-rw-r--r--arch/m68k/include/asm/motorola_pgtable.h1
-rw-r--r--arch/m68k/include/asm/nettel.h9
-rw-r--r--arch/m68k/include/asm/page.h14
-rw-r--r--arch/m68k/include/asm/page_no.h2
-rw-r--r--arch/m68k/include/asm/page_offset.h10
-rw-r--r--arch/m68k/include/asm/parport.h4
-rw-r--r--arch/m68k/include/asm/pci.h6
-rw-r--r--arch/m68k/include/asm/pgalloc.h4
-rw-r--r--arch/m68k/include/asm/pgtable.h4
-rw-r--r--arch/m68k/include/asm/pgtable_mm.h30
-rw-r--r--arch/m68k/include/asm/processor.h52
-rw-r--r--arch/m68k/include/asm/ptrace.h78
-rw-r--r--arch/m68k/include/asm/q40_master.h2
-rw-r--r--arch/m68k/include/asm/q40ints.h3
-rw-r--r--arch/m68k/include/asm/segment.h30
-rw-r--r--arch/m68k/include/asm/serial.h2
-rw-r--r--arch/m68k/include/asm/setup.h82
-rw-r--r--arch/m68k/include/asm/signal.h132
-rw-r--r--arch/m68k/include/asm/sun3xflop.h1
-rw-r--r--arch/m68k/include/asm/switch_to.h41
-rw-r--r--arch/m68k/include/asm/thread_info.h35
-rw-r--r--arch/m68k/include/asm/tlbflush.h23
-rw-r--r--arch/m68k/include/asm/traps.h1
-rw-r--r--arch/m68k/include/asm/uaccess.h4
-rw-r--r--arch/m68k/include/asm/uaccess_mm.h53
-rw-r--r--arch/m68k/include/asm/ucontext.h4
-rw-r--r--arch/m68k/include/asm/unaligned.h4
-rw-r--r--arch/m68k/include/asm/unistd.h357
-rw-r--r--arch/m68k/include/asm/vga.h27
91 files changed, 2824 insertions, 3860 deletions
diff --git a/arch/m68k/include/asm/Kbuild b/arch/m68k/include/asm/Kbuild
index c7933e41f10..1a922fad76f 100644
--- a/arch/m68k/include/asm/Kbuild
+++ b/arch/m68k/include/asm/Kbuild
@@ -1,34 +1,2 @@
1 1include include/asm-generic/Kbuild.asm
2generic-y += bitsperlong.h 2header-y += cachectl.h
3generic-y += clkdev.h
4generic-y += cputime.h
5generic-y += device.h
6generic-y += emergency-restart.h
7generic-y += errno.h
8generic-y += exec.h
9generic-y += futex.h
10generic-y += hw_irq.h
11generic-y += ioctl.h
12generic-y += ipcbuf.h
13generic-y += irq_regs.h
14generic-y += kdebug.h
15generic-y += kmap_types.h
16generic-y += kvm_para.h
17generic-y += local64.h
18generic-y += local.h
19generic-y += mman.h
20generic-y += mutex.h
21generic-y += percpu.h
22generic-y += resource.h
23generic-y += scatterlist.h
24generic-y += sections.h
25generic-y += shmparam.h
26generic-y += siginfo.h
27generic-y += spinlock.h
28generic-y += statfs.h
29generic-y += termios.h
30generic-y += topology.h
31generic-y += trace_clock.h
32generic-y += types.h
33generic-y += word-at-a-time.h
34generic-y += xor.h
diff --git a/arch/m68k/include/asm/apollohw.h b/arch/m68k/include/asm/apollohw.h
index 6c19e0c2241..a1373b9aa28 100644
--- a/arch/m68k/include/asm/apollohw.h
+++ b/arch/m68k/include/asm/apollohw.h
@@ -46,6 +46,18 @@ struct SCN2681 {
46 46
47}; 47};
48 48
49#if 0
50struct mc146818 {
51
52 unsigned int second1:4, second2:4, alarm_second1:4, alarm_second2:4,
53 minute1:4, minute2:4, alarm_minute1:4, alarm_minute2:4;
54 unsigned int hours1:4, hours2:4, alarm_hours1:4, alarm_hours2:4,
55 day_of_week1:4, day_of_week2:4, day_of_month1:4, day_of_month2:4;
56 unsigned int month1:4, month2:4, year1:4, year2:4, :16;
57
58};
59#endif
60
49struct mc146818 { 61struct mc146818 {
50 unsigned char second, alarm_second; 62 unsigned char second, alarm_second;
51 unsigned char minute, alarm_minute; 63 unsigned char minute, alarm_minute;
@@ -86,7 +98,7 @@ extern u_long timer_physaddr;
86#define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr)) 98#define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr))
87#define pica (IO_BASE + pica_physaddr) 99#define pica (IO_BASE + pica_physaddr)
88#define picb (IO_BASE + picb_physaddr) 100#define picb (IO_BASE + picb_physaddr)
89#define apollo_timer (IO_BASE + timer_physaddr) 101#define timer (IO_BASE + timer_physaddr)
90#define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000)) 102#define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000))
91 103
92#define isaIO2mem(x) (((((x) & 0x3f8) << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE) 104#define isaIO2mem(x) (((((x) & 0x3f8) << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE)
diff --git a/arch/m68k/include/asm/atarihw.h b/arch/m68k/include/asm/atarihw.h
index c0cb3635077..0392b28656a 100644
--- a/arch/m68k/include/asm/atarihw.h
+++ b/arch/m68k/include/asm/atarihw.h
@@ -30,8 +30,6 @@ extern u_long atari_switches;
30extern int atari_rtc_year_offset; 30extern int atari_rtc_year_offset;
31extern int atari_dont_touch_floppy_select; 31extern int atari_dont_touch_floppy_select;
32 32
33extern int atari_SCC_reset_done;
34
35/* convenience macros for testing machine type */ 33/* convenience macros for testing machine type */
36#define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST) 34#define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST)
37#define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ 35#define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h
index 5fc13bdf904..656bbbf5a6f 100644
--- a/arch/m68k/include/asm/atariints.h
+++ b/arch/m68k/include/asm/atariints.h
@@ -198,7 +198,7 @@ static inline int atari_irq_pending( unsigned irq )
198 return( get_mfp_bit( irq, MFP_PENDING ) ); 198 return( get_mfp_bit( irq, MFP_PENDING ) );
199} 199}
200 200
201unsigned int atari_register_vme_int(void); 201unsigned long atari_register_vme_int( void );
202void atari_unregister_vme_int(unsigned int); 202void atari_unregister_vme_int( unsigned long );
203 203
204#endif /* linux/atariints.h */ 204#endif /* linux/atariints.h */
diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h
index f4e32de263a..65c6be6c818 100644
--- a/arch/m68k/include/asm/atomic.h
+++ b/arch/m68k/include/asm/atomic.h
@@ -2,8 +2,7 @@
2#define __ARCH_M68K_ATOMIC__ 2#define __ARCH_M68K_ATOMIC__
3 3
4#include <linux/types.h> 4#include <linux/types.h>
5#include <linux/irqflags.h> 5#include <asm/system.h>
6#include <asm/cmpxchg.h>
7 6
8/* 7/*
9 * Atomic operations that C can't guarantee us. Useful for 8 * Atomic operations that C can't guarantee us. Useful for
@@ -56,16 +55,6 @@ static inline int atomic_dec_and_test(atomic_t *v)
56 return c != 0; 55 return c != 0;
57} 56}
58 57
59static inline int atomic_dec_and_test_lt(atomic_t *v)
60{
61 char c;
62 __asm__ __volatile__(
63 "subql #1,%1; slt %0"
64 : "=d" (c), "=m" (*v)
65 : "m" (*v));
66 return c != 0;
67}
68
69static inline int atomic_inc_and_test(atomic_t *v) 58static inline int atomic_inc_and_test(atomic_t *v)
70{ 59{
71 char c; 60 char c;
diff --git a/arch/m68k/include/asm/barrier.h b/arch/m68k/include/asm/barrier.h
deleted file mode 100644
index 445ce22c23c..00000000000
--- a/arch/m68k/include/asm/barrier.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef _M68K_BARRIER_H
2#define _M68K_BARRIER_H
3
4/*
5 * Force strict CPU ordering.
6 * Not really required on m68k...
7 */
8#define nop() do { asm volatile ("nop"); barrier(); } while (0)
9#define mb() barrier()
10#define rmb() barrier()
11#define wmb() barrier()
12#define read_barrier_depends() ((void)0)
13#define set_mb(var, value) ({ (var) = (value); wmb(); })
14
15#define smp_mb() barrier()
16#define smp_rmb() barrier()
17#define smp_wmb() barrier()
18#define smp_read_barrier_depends() ((void)0)
19
20#endif /* _M68K_BARRIER_H */
diff --git a/arch/m68k/include/asm/blinken.h b/arch/m68k/include/asm/blinken.h
index 0626582a7db..1a749cf7b06 100644
--- a/arch/m68k/include/asm/blinken.h
+++ b/arch/m68k/include/asm/blinken.h
@@ -17,15 +17,15 @@
17 17
18#define HP300_LEDS 0xf001ffff 18#define HP300_LEDS 0xf001ffff
19 19
20extern unsigned char hp300_ledstate; 20extern unsigned char ledstate;
21 21
22static __inline__ void blinken_leds(int on, int off) 22static __inline__ void blinken_leds(int on, int off)
23{ 23{
24 if (MACH_IS_HP300) 24 if (MACH_IS_HP300)
25 { 25 {
26 hp300_ledstate |= on; 26 ledstate |= on;
27 hp300_ledstate &= ~off; 27 ledstate &= ~off;
28 out_8(HP300_LEDS, ~hp300_ledstate); 28 out_8(HP300_LEDS, ~ledstate);
29 } 29 }
30} 30}
31 31
diff --git a/arch/m68k/include/asm/cacheflush.h b/arch/m68k/include/asm/cacheflush.h
index 4fc738209bd..a70d7319630 100644
--- a/arch/m68k/include/asm/cacheflush.h
+++ b/arch/m68k/include/asm/cacheflush.h
@@ -1,5 +1,5 @@
1#ifdef __uClinux__ 1#ifdef __uClinux__
2#include <asm/cacheflush_no.h> 2#include "cacheflush_no.h"
3#else 3#else
4#include <asm/cacheflush_mm.h> 4#include "cacheflush_mm.h"
5#endif 5#endif
diff --git a/arch/m68k/include/asm/cacheflush_mm.h b/arch/m68k/include/asm/cacheflush_mm.h
index fa2c3d681d8..73de7c89d8e 100644
--- a/arch/m68k/include/asm/cacheflush_mm.h
+++ b/arch/m68k/include/asm/cacheflush_mm.h
@@ -2,130 +2,23 @@
2#define _M68K_CACHEFLUSH_H 2#define _M68K_CACHEFLUSH_H
3 3
4#include <linux/mm.h> 4#include <linux/mm.h>
5#ifdef CONFIG_COLDFIRE
6#include <asm/mcfsim.h>
7#endif
8 5
9/* cache code */ 6/* cache code */
10#define FLUSH_I_AND_D (0x00000808) 7#define FLUSH_I_AND_D (0x00000808)
11#define FLUSH_I (0x00000008) 8#define FLUSH_I (0x00000008)
12 9
13#ifndef ICACHE_MAX_ADDR
14#define ICACHE_MAX_ADDR 0
15#define ICACHE_SET_MASK 0
16#define DCACHE_MAX_ADDR 0
17#define DCACHE_SETMASK 0
18#endif
19#ifndef CACHE_MODE
20#define CACHE_MODE 0
21#define CACR_ICINVA 0
22#define CACR_DCINVA 0
23#define CACR_BCINVA 0
24#endif
25
26/*
27 * ColdFire architecture has no way to clear individual cache lines, so we
28 * are stuck invalidating all the cache entries when we want a clear operation.
29 */
30static inline void clear_cf_icache(unsigned long start, unsigned long end)
31{
32 __asm__ __volatile__ (
33 "movec %0,%%cacr\n\t"
34 "nop"
35 :
36 : "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA));
37}
38
39static inline void clear_cf_dcache(unsigned long start, unsigned long end)
40{
41 __asm__ __volatile__ (
42 "movec %0,%%cacr\n\t"
43 "nop"
44 :
45 : "r" (CACHE_MODE | CACR_DCINVA));
46}
47
48static inline void clear_cf_bcache(unsigned long start, unsigned long end)
49{
50 __asm__ __volatile__ (
51 "movec %0,%%cacr\n\t"
52 "nop"
53 :
54 : "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA | CACR_DCINVA));
55}
56
57/*
58 * Use the ColdFire cpushl instruction to push (and invalidate) cache lines.
59 * The start and end addresses are cache line numbers not memory addresses.
60 */
61static inline void flush_cf_icache(unsigned long start, unsigned long end)
62{
63 unsigned long set;
64
65 for (set = start; set <= end; set += (0x10 - 3)) {
66 __asm__ __volatile__ (
67 "cpushl %%ic,(%0)\n\t"
68 "addq%.l #1,%0\n\t"
69 "cpushl %%ic,(%0)\n\t"
70 "addq%.l #1,%0\n\t"
71 "cpushl %%ic,(%0)\n\t"
72 "addq%.l #1,%0\n\t"
73 "cpushl %%ic,(%0)"
74 : "=a" (set)
75 : "a" (set));
76 }
77}
78
79static inline void flush_cf_dcache(unsigned long start, unsigned long end)
80{
81 unsigned long set;
82
83 for (set = start; set <= end; set += (0x10 - 3)) {
84 __asm__ __volatile__ (
85 "cpushl %%dc,(%0)\n\t"
86 "addq%.l #1,%0\n\t"
87 "cpushl %%dc,(%0)\n\t"
88 "addq%.l #1,%0\n\t"
89 "cpushl %%dc,(%0)\n\t"
90 "addq%.l #1,%0\n\t"
91 "cpushl %%dc,(%0)"
92 : "=a" (set)
93 : "a" (set));
94 }
95}
96
97static inline void flush_cf_bcache(unsigned long start, unsigned long end)
98{
99 unsigned long set;
100
101 for (set = start; set <= end; set += (0x10 - 3)) {
102 __asm__ __volatile__ (
103 "cpushl %%bc,(%0)\n\t"
104 "addq%.l #1,%0\n\t"
105 "cpushl %%bc,(%0)\n\t"
106 "addq%.l #1,%0\n\t"
107 "cpushl %%bc,(%0)\n\t"
108 "addq%.l #1,%0\n\t"
109 "cpushl %%bc,(%0)"
110 : "=a" (set)
111 : "a" (set));
112 }
113}
114
115/* 10/*
116 * Cache handling functions 11 * Cache handling functions
117 */ 12 */
118 13
119static inline void flush_icache(void) 14static inline void flush_icache(void)
120{ 15{
121 if (CPU_IS_COLDFIRE) { 16 if (CPU_IS_040_OR_060)
122 flush_cf_icache(0, ICACHE_MAX_ADDR);
123 } else if (CPU_IS_040_OR_060) {
124 asm volatile ( "nop\n" 17 asm volatile ( "nop\n"
125 " .chip 68040\n" 18 " .chip 68040\n"
126 " cpusha %bc\n" 19 " cpusha %bc\n"
127 " .chip 68k"); 20 " .chip 68k");
128 } else { 21 else {
129 unsigned long tmp; 22 unsigned long tmp;
130 asm volatile ( "movec %%cacr,%0\n" 23 asm volatile ( "movec %%cacr,%0\n"
131 " or.w %1,%0\n" 24 " or.w %1,%0\n"
@@ -158,14 +51,12 @@ extern void cache_push_v(unsigned long vaddr, int len);
158 process changes. */ 51 process changes. */
159#define __flush_cache_all() \ 52#define __flush_cache_all() \
160({ \ 53({ \
161 if (CPU_IS_COLDFIRE) { \ 54 if (CPU_IS_040_OR_060) \
162 flush_cf_dcache(0, DCACHE_MAX_ADDR); \
163 } else if (CPU_IS_040_OR_060) { \
164 __asm__ __volatile__("nop\n\t" \ 55 __asm__ __volatile__("nop\n\t" \
165 ".chip 68040\n\t" \ 56 ".chip 68040\n\t" \
166 "cpusha %dc\n\t" \ 57 "cpusha %dc\n\t" \
167 ".chip 68k"); \ 58 ".chip 68k"); \
168 } else { \ 59 else { \
169 unsigned long _tmp; \ 60 unsigned long _tmp; \
170 __asm__ __volatile__("movec %%cacr,%0\n\t" \ 61 __asm__ __volatile__("movec %%cacr,%0\n\t" \
171 "orw %1,%0\n\t" \ 62 "orw %1,%0\n\t" \
@@ -221,17 +112,7 @@ static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vm
221/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ 112/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
222static inline void __flush_page_to_ram(void *vaddr) 113static inline void __flush_page_to_ram(void *vaddr)
223{ 114{
224 if (CPU_IS_COLDFIRE) { 115 if (CPU_IS_040_OR_060) {
225 unsigned long addr, start, end;
226 addr = ((unsigned long) vaddr) & ~(PAGE_SIZE - 1);
227 start = addr & ICACHE_SET_MASK;
228 end = (addr + PAGE_SIZE - 1) & ICACHE_SET_MASK;
229 if (start > end) {
230 flush_cf_bcache(0, end);
231 end = ICACHE_MAX_ADDR;
232 }
233 flush_cf_bcache(start, end);
234 } else if (CPU_IS_040_OR_060) {
235 __asm__ __volatile__("nop\n\t" 116 __asm__ __volatile__("nop\n\t"
236 ".chip 68040\n\t" 117 ".chip 68040\n\t"
237 "cpushp %%bc,(%0)\n\t" 118 "cpushp %%bc,(%0)\n\t"
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index d2b3935ae14..cb88aa96c4f 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -30,22 +30,18 @@
30 30
31void mcf_cache_push(void); 31void mcf_cache_push(void);
32 32
33static inline void __clear_cache_all(void)
34{
35#ifdef CACHE_INVALIDATE
36 __asm__ __volatile__ (
37 "movec %0, %%CACR\n\t"
38 "nop\n\t"
39 : : "r" (CACHE_INVALIDATE) );
40#endif
41}
42
43static inline void __flush_cache_all(void) 33static inline void __flush_cache_all(void)
44{ 34{
45#ifdef CACHE_PUSH 35#ifdef CACHE_PUSH
46 mcf_cache_push(); 36 mcf_cache_push();
47#endif 37#endif
48 __clear_cache_all(); 38#ifdef CACHE_INVALIDATE
39 __asm__ __volatile__ (
40 "movel %0, %%d0\n\t"
41 "movec %%d0, %%CACR\n\t"
42 "nop\n\t"
43 : : "i" (CACHE_INVALIDATE) : "d0" );
44#endif
49} 45}
50 46
51/* 47/*
@@ -57,9 +53,10 @@ static inline void __flush_icache_all(void)
57{ 53{
58#ifdef CACHE_INVALIDATEI 54#ifdef CACHE_INVALIDATEI
59 __asm__ __volatile__ ( 55 __asm__ __volatile__ (
60 "movec %0, %%CACR\n\t" 56 "movel %0, %%d0\n\t"
57 "movec %%d0, %%CACR\n\t"
61 "nop\n\t" 58 "nop\n\t"
62 : : "r" (CACHE_INVALIDATEI) ); 59 : : "i" (CACHE_INVALIDATEI) : "d0" );
63#endif 60#endif
64} 61}
65 62
@@ -70,31 +67,13 @@ static inline void __flush_dcache_all(void)
70#endif 67#endif
71#ifdef CACHE_INVALIDATED 68#ifdef CACHE_INVALIDATED
72 __asm__ __volatile__ ( 69 __asm__ __volatile__ (
73 "movec %0, %%CACR\n\t" 70 "movel %0, %%d0\n\t"
71 "movec %%d0, %%CACR\n\t"
74 "nop\n\t" 72 "nop\n\t"
75 : : "r" (CACHE_INVALIDATED) ); 73 : : "i" (CACHE_INVALIDATED) : "d0" );
76#else 74#else
77 /* Flush the write buffer */ 75 /* Flush the wrtite buffer */
78 __asm__ __volatile__ ( "nop" ); 76 __asm__ __volatile__ ( "nop" );
79#endif 77#endif
80} 78}
81
82/*
83 * Push cache entries at supplied address. We want to write back any dirty
84 * data and then invalidate the cache lines associated with this address.
85 */
86static inline void cache_push(unsigned long paddr, int len)
87{
88 __flush_cache_all();
89}
90
91/*
92 * Clear cache entries at supplied address (that is don't write back any
93 * dirty data).
94 */
95static inline void cache_clear(unsigned long paddr, int len)
96{
97 __clear_cache_all();
98}
99
100#endif /* _M68KNOMMU_CACHEFLUSH_H */ 79#endif /* _M68KNOMMU_CACHEFLUSH_H */
diff --git a/arch/m68k/include/asm/checksum.h b/arch/m68k/include/asm/checksum.h
index 2f88d867c71..ec514485c8b 100644
--- a/arch/m68k/include/asm/checksum.h
+++ b/arch/m68k/include/asm/checksum.h
@@ -3,10 +3,6 @@
3 3
4#include <linux/in6.h> 4#include <linux/in6.h>
5 5
6#ifdef CONFIG_GENERIC_CSUM
7#include <asm-generic/checksum.h>
8#else
9
10/* 6/*
11 * computes the checksum of a memory block at buff, length len, 7 * computes the checksum of a memory block at buff, length len,
12 * and adds in "sum" (32-bit) 8 * and adds in "sum" (32-bit)
@@ -38,6 +34,30 @@ extern __wsum csum_partial_copy_nocheck(const void *src,
38 void *dst, int len, 34 void *dst, int len,
39 __wsum sum); 35 __wsum sum);
40 36
37
38#ifdef CONFIG_COLDFIRE
39
40/*
41 * The ColdFire cores don't support all the 68k instructions used
42 * in the optimized checksum code below. So it reverts back to using
43 * more standard C coded checksums. The fast checksum code is
44 * significantly larger than the optimized version, so it is not
45 * inlined here.
46 */
47__sum16 ip_fast_csum(const void *iph, unsigned int ihl);
48
49static inline __sum16 csum_fold(__wsum sum)
50{
51 unsigned int tmp = (__force u32)sum;
52
53 tmp = (tmp & 0xffff) + (tmp >> 16);
54 tmp = (tmp & 0xffff) + (tmp >> 16);
55
56 return (__force __sum16)~tmp;
57}
58
59#else
60
41/* 61/*
42 * This is a version of ip_fast_csum() optimized for IP headers, 62 * This is a version of ip_fast_csum() optimized for IP headers,
43 * which always checksum on 4 octet boundaries. 63 * which always checksum on 4 octet boundaries.
@@ -77,6 +97,8 @@ static inline __sum16 csum_fold(__wsum sum)
77 return (__force __sum16)~sum; 97 return (__force __sum16)~sum;
78} 98}
79 99
100#endif /* CONFIG_COLDFIRE */
101
80static inline __wsum 102static inline __wsum
81csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, 103csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
82 unsigned short proto, __wsum sum) 104 unsigned short proto, __wsum sum)
@@ -145,5 +167,4 @@ csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
145 return csum_fold(sum); 167 return csum_fold(sum);
146} 168}
147 169
148#endif /* CONFIG_GENERIC_CSUM */
149#endif /* _M68K_CHECKSUM_H */ 170#endif /* _M68K_CHECKSUM_H */
diff --git a/arch/m68k/include/asm/cmpxchg.h b/arch/m68k/include/asm/cmpxchg.h
deleted file mode 100644
index 5c81d0eae5c..00000000000
--- a/arch/m68k/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,141 +0,0 @@
1#ifndef __ARCH_M68K_CMPXCHG__
2#define __ARCH_M68K_CMPXCHG__
3
4#include <linux/irqflags.h>
5
6struct __xchg_dummy { unsigned long a[100]; };
7#define __xg(x) ((volatile struct __xchg_dummy *)(x))
8
9extern unsigned long __invalid_xchg_size(unsigned long, volatile void *, int);
10
11#ifndef CONFIG_RMW_INSNS
12static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
13{
14 unsigned long flags, tmp;
15
16 local_irq_save(flags);
17
18 switch (size) {
19 case 1:
20 tmp = *(u8 *)ptr;
21 *(u8 *)ptr = x;
22 x = tmp;
23 break;
24 case 2:
25 tmp = *(u16 *)ptr;
26 *(u16 *)ptr = x;
27 x = tmp;
28 break;
29 case 4:
30 tmp = *(u32 *)ptr;
31 *(u32 *)ptr = x;
32 x = tmp;
33 break;
34 default:
35 tmp = __invalid_xchg_size(x, ptr, size);
36 break;
37 }
38
39 local_irq_restore(flags);
40 return x;
41}
42#else
43static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
44{
45 switch (size) {
46 case 1:
47 __asm__ __volatile__
48 ("moveb %2,%0\n\t"
49 "1:\n\t"
50 "casb %0,%1,%2\n\t"
51 "jne 1b"
52 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
53 break;
54 case 2:
55 __asm__ __volatile__
56 ("movew %2,%0\n\t"
57 "1:\n\t"
58 "casw %0,%1,%2\n\t"
59 "jne 1b"
60 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
61 break;
62 case 4:
63 __asm__ __volatile__
64 ("movel %2,%0\n\t"
65 "1:\n\t"
66 "casl %0,%1,%2\n\t"
67 "jne 1b"
68 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
69 break;
70 default:
71 x = __invalid_xchg_size(x, ptr, size);
72 break;
73 }
74 return x;
75}
76#endif
77
78#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
79
80#include <asm-generic/cmpxchg-local.h>
81
82#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
83
84extern unsigned long __invalid_cmpxchg_size(volatile void *,
85 unsigned long, unsigned long, int);
86
87/*
88 * Atomic compare and exchange. Compare OLD with MEM, if identical,
89 * store NEW in MEM. Return the initial value in MEM. Success is
90 * indicated by comparing RETURN with OLD.
91 */
92#ifdef CONFIG_RMW_INSNS
93#define __HAVE_ARCH_CMPXCHG 1
94
95static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
96 unsigned long new, int size)
97{
98 switch (size) {
99 case 1:
100 __asm__ __volatile__ ("casb %0,%2,%1"
101 : "=d" (old), "=m" (*(char *)p)
102 : "d" (new), "0" (old), "m" (*(char *)p));
103 break;
104 case 2:
105 __asm__ __volatile__ ("casw %0,%2,%1"
106 : "=d" (old), "=m" (*(short *)p)
107 : "d" (new), "0" (old), "m" (*(short *)p));
108 break;
109 case 4:
110 __asm__ __volatile__ ("casl %0,%2,%1"
111 : "=d" (old), "=m" (*(int *)p)
112 : "d" (new), "0" (old), "m" (*(int *)p));
113 break;
114 default:
115 old = __invalid_cmpxchg_size(p, old, new, size);
116 break;
117 }
118 return old;
119}
120
121#define cmpxchg(ptr, o, n) \
122 ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
123 (unsigned long)(n), sizeof(*(ptr))))
124#define cmpxchg_local(ptr, o, n) \
125 ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
126 (unsigned long)(n), sizeof(*(ptr))))
127#else
128
129/*
130 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
131 * them available.
132 */
133#define cmpxchg_local(ptr, o, n) \
134 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
135 (unsigned long)(n), sizeof(*(ptr))))
136
137#include <asm-generic/cmpxchg.h>
138
139#endif
140
141#endif /* __ARCH_M68K_CMPXCHG__ */
diff --git a/arch/m68k/include/asm/delay.h b/arch/m68k/include/asm/delay.h
index 12d8fe4f1d3..9c09becfd4c 100644
--- a/arch/m68k/include/asm/delay.h
+++ b/arch/m68k/include/asm/delay.h
@@ -43,7 +43,7 @@ static inline void __delay(unsigned long loops)
43extern void __bad_udelay(void); 43extern void __bad_udelay(void);
44 44
45 45
46#ifdef CONFIG_CPU_HAS_NO_MULDIV64 46#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE)
47/* 47/*
48 * The simpler m68k and ColdFire processors do not have a 32*32->64 48 * The simpler m68k and ColdFire processors do not have a 32*32->64
49 * multiply instruction. So we need to handle them a little differently. 49 * multiply instruction. So we need to handle them a little differently.
diff --git a/arch/m68k/include/asm/div64.h b/arch/m68k/include/asm/div64.h
index 444ea8a09e9..edb66148a71 100644
--- a/arch/m68k/include/asm/div64.h
+++ b/arch/m68k/include/asm/div64.h
@@ -1,9 +1,7 @@
1#ifndef _M68K_DIV64_H 1#ifndef _M68K_DIV64_H
2#define _M68K_DIV64_H 2#define _M68K_DIV64_H
3 3
4#ifdef CONFIG_CPU_HAS_NO_MULDIV64 4#ifdef CONFIG_MMU
5#include <asm-generic/div64.h>
6#else
7 5
8#include <linux/types.h> 6#include <linux/types.h>
9 7
@@ -29,6 +27,8 @@
29 __rem; \ 27 __rem; \
30}) 28})
31 29
32#endif /* CONFIG_CPU_HAS_NO_MULDIV64 */ 30#else
31#include <asm-generic/div64.h>
32#endif /* CONFIG_MMU */
33 33
34#endif /* _M68K_DIV64_H */ 34#endif /* _M68K_DIV64_H */
diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h
index 0ff3fc6a6d9..6fbdfe89510 100644
--- a/arch/m68k/include/asm/dma.h
+++ b/arch/m68k/include/asm/dma.h
@@ -33,9 +33,7 @@
33 * Set number of channels of DMA on ColdFire for different implementations. 33 * Set number of channels of DMA on ColdFire for different implementations.
34 */ 34 */
35#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \ 35#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
36 defined(CONFIG_M523x) || defined(CONFIG_M527x) || \ 36 defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
37 defined(CONFIG_M528x) || defined(CONFIG_M525x)
38
39#define MAX_M68K_DMA_CHANNELS 4 37#define MAX_M68K_DMA_CHANNELS 4
40#elif defined(CONFIG_M5272) 38#elif defined(CONFIG_M5272)
41#define MAX_M68K_DMA_CHANNELS 1 39#define MAX_M68K_DMA_CHANNELS 1
@@ -488,10 +486,6 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
488extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ 486extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
489extern void free_dma(unsigned int dmanr); /* release it again */ 487extern void free_dma(unsigned int dmanr); /* release it again */
490 488
491#ifdef CONFIG_PCI
492extern int isa_dma_bridge_buggy;
493#else
494#define isa_dma_bridge_buggy (0) 489#define isa_dma_bridge_buggy (0)
495#endif
496 490
497#endif /* _M68K_DMA_H */ 491#endif /* _M68K_DMA_H */
diff --git a/arch/m68k/include/asm/elf.h b/arch/m68k/include/asm/elf.h
index f83c1d0a87c..01c193d9141 100644
--- a/arch/m68k/include/asm/elf.h
+++ b/arch/m68k/include/asm/elf.h
@@ -59,10 +59,10 @@ typedef struct user_m68kfp_struct elf_fpregset_t;
59 is actually used on ASV. */ 59 is actually used on ASV. */
60#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 60#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0
61 61
62#if defined(CONFIG_SUN3) || defined(CONFIG_COLDFIRE) 62#ifndef CONFIG_SUN3
63#define ELF_EXEC_PAGESIZE 8192
64#else
65#define ELF_EXEC_PAGESIZE 4096 63#define ELF_EXEC_PAGESIZE 4096
64#else
65#define ELF_EXEC_PAGESIZE 8192
66#endif 66#endif
67 67
68/* This is the location that an ET_DYN program is loaded if exec'ed. Typical 68/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
@@ -113,7 +113,6 @@ typedef struct user_m68kfp_struct elf_fpregset_t;
113 113
114#define ELF_PLATFORM (NULL) 114#define ELF_PLATFORM (NULL)
115 115
116#define SET_PERSONALITY(ex) \ 116#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
117 set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
118 117
119#endif 118#endif
diff --git a/arch/m68k/include/asm/entry.h b/arch/m68k/include/asm/entry.h
index d7de0f1a895..876eec6f2b5 100644
--- a/arch/m68k/include/asm/entry.h
+++ b/arch/m68k/include/asm/entry.h
@@ -1,260 +1,5 @@
1#ifndef __M68K_ENTRY_H 1#ifdef __uClinux__
2#define __M68K_ENTRY_H 2#include "entry_no.h"
3
4#include <asm/setup.h>
5#include <asm/page.h>
6#ifdef __ASSEMBLY__
7#include <asm/thread_info.h>
8#endif
9
10/*
11 * Stack layout in 'ret_from_exception':
12 *
13 * This allows access to the syscall arguments in registers d1-d5
14 *
15 * 0(sp) - d1
16 * 4(sp) - d2
17 * 8(sp) - d3
18 * C(sp) - d4
19 * 10(sp) - d5
20 * 14(sp) - a0
21 * 18(sp) - a1
22 * 1C(sp) - a2
23 * 20(sp) - d0
24 * 24(sp) - orig_d0
25 * 28(sp) - stack adjustment
26 * 2C(sp) - [ sr ] [ format & vector ]
27 * 2E(sp) - [ pc-hiword ] [ sr ]
28 * 30(sp) - [ pc-loword ] [ pc-hiword ]
29 * 32(sp) - [ format & vector ] [ pc-loword ]
30 * ^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^
31 * M68K COLDFIRE
32 */
33
34/* the following macro is used when enabling interrupts */
35#if defined(MACH_ATARI_ONLY)
36 /* block out HSYNC = ipl 2 on the atari */
37#define ALLOWINT (~0x500)
38#else
39 /* portable version */
40#define ALLOWINT (~0x700)
41#endif /* machine compilation types */
42
43#ifdef __ASSEMBLY__
44/*
45 * This defines the normal kernel pt-regs layout.
46 *
47 * regs a3-a6 and d6-d7 are preserved by C code
48 * the kernel doesn't mess with usp unless it needs to
49 */
50#define SWITCH_STACK_SIZE (6*4+4) /* includes return address */
51
52#ifdef CONFIG_COLDFIRE
53#ifdef CONFIG_COLDFIRE_SW_A7
54/*
55 * This is made a little more tricky on older ColdFires. There is no
56 * separate supervisor and user stack pointers. Need to artificially
57 * construct a usp in software... When doing this we need to disable
58 * interrupts, otherwise bad things will happen.
59 */
60.globl sw_usp
61.globl sw_ksp
62
63.macro SAVE_ALL_SYS
64 move #0x2700,%sr /* disable intrs */
65 btst #5,%sp@(2) /* from user? */
66 bnes 6f /* no, skip */
67 movel %sp,sw_usp /* save user sp */
68 addql #8,sw_usp /* remove exception */
69 movel sw_ksp,%sp /* kernel sp */
70 subql #8,%sp /* room for exception */
71 clrl %sp@- /* stkadj */
72 movel %d0,%sp@- /* orig d0 */
73 movel %d0,%sp@- /* d0 */
74 lea %sp@(-32),%sp /* space for 8 regs */
75 moveml %d1-%d5/%a0-%a2,%sp@
76 movel sw_usp,%a0 /* get usp */
77 movel %a0@-,%sp@(PT_OFF_PC) /* copy exception program counter */
78 movel %a0@-,%sp@(PT_OFF_FORMATVEC)/*copy exception format/vector/sr */
79 bra 7f
80 6:
81 clrl %sp@- /* stkadj */
82 movel %d0,%sp@- /* orig d0 */
83 movel %d0,%sp@- /* d0 */
84 lea %sp@(-32),%sp /* space for 8 regs */
85 moveml %d1-%d5/%a0-%a2,%sp@
86 7:
87.endm
88
89.macro SAVE_ALL_INT
90 SAVE_ALL_SYS
91 moveq #-1,%d0 /* not system call entry */
92 movel %d0,%sp@(PT_OFF_ORIG_D0)
93.endm
94
95.macro RESTORE_USER
96 move #0x2700,%sr /* disable intrs */
97 movel sw_usp,%a0 /* get usp */
98 movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */
99 movel %sp@(PT_OFF_FORMATVEC),%a0@-/*copy exception format/vector/sr */
100 moveml %sp@,%d1-%d5/%a0-%a2
101 lea %sp@(32),%sp /* space for 8 regs */
102 movel %sp@+,%d0
103 addql #4,%sp /* orig d0 */
104 addl %sp@+,%sp /* stkadj */
105 addql #8,%sp /* remove exception */
106 movel %sp,sw_ksp /* save ksp */
107 subql #8,sw_usp /* set exception */
108 movel sw_usp,%sp /* restore usp */
109 rte
110.endm
111
112.macro RDUSP
113 movel sw_usp,%a3
114.endm
115
116.macro WRUSP
117 movel %a3,sw_usp
118.endm
119
120#else /* !CONFIG_COLDFIRE_SW_A7 */
121/*
122 * Modern ColdFire parts have separate supervisor and user stack
123 * pointers. Simple load and restore macros for this case.
124 */
125.macro SAVE_ALL_SYS
126 move #0x2700,%sr /* disable intrs */
127 clrl %sp@- /* stkadj */
128 movel %d0,%sp@- /* orig d0 */
129 movel %d0,%sp@- /* d0 */
130 lea %sp@(-32),%sp /* space for 8 regs */
131 moveml %d1-%d5/%a0-%a2,%sp@
132.endm
133
134.macro SAVE_ALL_INT
135 move #0x2700,%sr /* disable intrs */
136 clrl %sp@- /* stkadj */
137 pea -1:w /* orig d0 */
138 movel %d0,%sp@- /* d0 */
139 lea %sp@(-32),%sp /* space for 8 regs */
140 moveml %d1-%d5/%a0-%a2,%sp@
141.endm
142
143.macro RESTORE_USER
144 moveml %sp@,%d1-%d5/%a0-%a2
145 lea %sp@(32),%sp /* space for 8 regs */
146 movel %sp@+,%d0
147 addql #4,%sp /* orig d0 */
148 addl %sp@+,%sp /* stkadj */
149 rte
150.endm
151
152.macro RDUSP
153 /*move %usp,%a3*/
154 .word 0x4e6b
155.endm
156
157.macro WRUSP
158 /*move %a3,%usp*/
159 .word 0x4e63
160.endm
161
162#endif /* !CONFIG_COLDFIRE_SW_A7 */
163
164.macro SAVE_SWITCH_STACK
165 lea %sp@(-24),%sp /* 6 regs */
166 moveml %a3-%a6/%d6-%d7,%sp@
167.endm
168
169.macro RESTORE_SWITCH_STACK
170 moveml %sp@,%a3-%a6/%d6-%d7
171 lea %sp@(24),%sp /* 6 regs */
172.endm
173
174#else /* !CONFIG_COLDFIRE */
175
176/*
177 * All other types of m68k parts (68000, 680x0, CPU32) have the same
178 * entry and exit code.
179 */
180
181/*
182 * a -1 in the orig_d0 field signifies
183 * that the stack frame is NOT for syscall
184 */
185.macro SAVE_ALL_INT
186 clrl %sp@- /* stk_adj */
187 pea -1:w /* orig d0 */
188 movel %d0,%sp@- /* d0 */
189 moveml %d1-%d5/%a0-%a2,%sp@-
190.endm
191
192.macro SAVE_ALL_SYS
193 clrl %sp@- /* stk_adj */
194 movel %d0,%sp@- /* orig d0 */
195 movel %d0,%sp@- /* d0 */
196 moveml %d1-%d5/%a0-%a2,%sp@-
197.endm
198
199.macro RESTORE_ALL
200 moveml %sp@+,%a0-%a2/%d1-%d5
201 movel %sp@+,%d0
202 addql #4,%sp /* orig d0 */
203 addl %sp@+,%sp /* stk adj */
204 rte
205.endm
206
207
208.macro SAVE_SWITCH_STACK
209 moveml %a3-%a6/%d6-%d7,%sp@-
210.endm
211
212.macro RESTORE_SWITCH_STACK
213 moveml %sp@+,%a3-%a6/%d6-%d7
214.endm
215
216#endif /* !CONFIG_COLDFIRE */
217
218/*
219 * Register %a2 is reserved and set to current task on MMU enabled systems.
220 * Non-MMU systems do not reserve %a2 in this way, and this definition is
221 * not used for them.
222 */
223#ifdef CONFIG_MMU
224
225#define curptr a2
226
227#define GET_CURRENT(tmp) get_current tmp
228.macro get_current reg=%d0
229 movel %sp,\reg
230 andl #-THREAD_SIZE,\reg
231 movel \reg,%curptr
232 movel %curptr@,%curptr
233.endm
234
235#else 3#else
236 4#include "entry_mm.h"
237#define GET_CURRENT(tmp)
238
239#endif /* CONFIG_MMU */
240
241#else /* C source */
242
243#define STR(X) STR1(X)
244#define STR1(X) #X
245
246#define SAVE_ALL_INT \
247 "clrl %%sp@-;" /* stk_adj */ \
248 "pea -1:w;" /* orig d0 = -1 */ \
249 "movel %%d0,%%sp@-;" /* d0 */ \
250 "moveml %%d1-%%d5/%%a0-%%a2,%%sp@-"
251
252#define GET_CURRENT(tmp) \
253 "movel %%sp,"#tmp"\n\t" \
254 "andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \
255 "movel "#tmp",%%a2\n\t" \
256 "movel %%a2@,%%a2"
257
258#endif 5#endif
259
260#endif /* __M68K_ENTRY_H */
diff --git a/arch/m68k/include/asm/flat.h b/arch/m68k/include/asm/flat.h
index f9454b89a51..a0e29079397 100644
--- a/arch/m68k/include/asm/flat.h
+++ b/arch/m68k/include/asm/flat.h
@@ -11,11 +11,6 @@
11#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp) 11#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp)
12#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) 12#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp)
13#define flat_get_relocate_addr(rel) (rel) 13#define flat_get_relocate_addr(rel) (rel)
14 14#define flat_set_persistent(relval, p) 0
15static inline int flat_set_persistent(unsigned long relval,
16 unsigned long *persistent)
17{
18 return 0;
19}
20 15
21#endif /* __M68KNOMMU_FLAT_H__ */ 16#endif /* __M68KNOMMU_FLAT_H__ */
diff --git a/arch/m68k/include/asm/fpu.h b/arch/m68k/include/asm/fpu.h
index 526db9da9e4..ffb6b8cfc6d 100644
--- a/arch/m68k/include/asm/fpu.h
+++ b/arch/m68k/include/asm/fpu.h
@@ -12,8 +12,6 @@
12#define FPSTATESIZE (96) 12#define FPSTATESIZE (96)
13#elif defined(CONFIG_M68KFPU_EMU) 13#elif defined(CONFIG_M68KFPU_EMU)
14#define FPSTATESIZE (28) 14#define FPSTATESIZE (28)
15#elif defined(CONFIG_COLDFIRE) && defined(CONFIG_MMU)
16#define FPSTATESIZE (16)
17#elif defined(CONFIG_M68060) 15#elif defined(CONFIG_M68060)
18#define FPSTATESIZE (12) 16#define FPSTATESIZE (12)
19#else 17#else
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index 4395ffc51fd..b2046839f4b 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -17,9 +17,170 @@
17#define coldfire_gpio_h 17#define coldfire_gpio_h
18 18
19#include <linux/io.h> 19#include <linux/io.h>
20#include <asm-generic/gpio.h>
20#include <asm/coldfire.h> 21#include <asm/coldfire.h>
21#include <asm/mcfsim.h> 22#include <asm/mcfsim.h>
22#include <asm/mcfgpio.h> 23
24/*
25 * The Freescale Coldfire family is quite varied in how they implement GPIO.
26 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
27 * only one port, others have multiple ports; some have a single data latch
28 * for both input and output, others have a separate pin data register to read
29 * input; some require a read-modify-write access to change an output, others
30 * have set and clear registers for some of the outputs; Some have all the
31 * GPIOs in a single control area, others have some GPIOs implemented in
32 * different modules.
33 *
34 * This implementation attempts accommodate the differences while presenting
35 * a generic interface that will optimize to as few instructions as possible.
36 */
37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
40 defined(CONFIG_M532x) || defined(CONFIG_M54xx)
41
42/* These parts have GPIO organized by 8 bit ports */
43
44#define MCFGPIO_PORTTYPE u8
45#define MCFGPIO_PORTSIZE 8
46#define mcfgpio_read(port) __raw_readb(port)
47#define mcfgpio_write(data, port) __raw_writeb(data, port)
48
49#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
50
51/* These parts have GPIO organized by 16 bit ports */
52
53#define MCFGPIO_PORTTYPE u16
54#define MCFGPIO_PORTSIZE 16
55#define mcfgpio_read(port) __raw_readw(port)
56#define mcfgpio_write(data, port) __raw_writew(data, port)
57
58#elif defined(CONFIG_M5249)
59
60/* These parts have GPIO organized by 32 bit ports */
61
62#define MCFGPIO_PORTTYPE u32
63#define MCFGPIO_PORTSIZE 32
64#define mcfgpio_read(port) __raw_readl(port)
65#define mcfgpio_write(data, port) __raw_writel(data, port)
66
67#endif
68
69#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
70#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
71
72#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
73 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
74/*
75 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
76 * read-modify-write to change an output and a GPIO module which has separate
77 * set/clr registers to directly change outputs with a single write access.
78 */
79#if defined(CONFIG_M528x)
80/*
81 * The 528x also has GPIOs in other modules (GPT, QADC) which use
82 * read-modify-write as well as those controlled by the EPORT and GPIO modules.
83 */
84#define MCFGPIO_SCR_START 40
85#else
86#define MCFGPIO_SCR_START 8
87#endif
88
89#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
90 mcfgpio_port(gpio - MCFGPIO_SCR_START))
91
92#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
93 mcfgpio_port(gpio - MCFGPIO_SCR_START))
94#else
95
96#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
97/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
98#define MCFGPIO_SETR_PORT(gpio) 0
99#define MCFGPIO_CLRR_PORT(gpio) 0
100
101#endif
102/*
103 * Coldfire specific helper functions
104 */
105
106/* return the port pin data register for a gpio */
107static inline u32 __mcf_gpio_ppdr(unsigned gpio)
108{
109#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
110 defined(CONFIG_M5307) || defined(CONFIG_M5407)
111 return MCFSIM_PADAT;
112#elif defined(CONFIG_M5272)
113 if (gpio < 16)
114 return MCFSIM_PADAT;
115 else if (gpio < 32)
116 return MCFSIM_PBDAT;
117 else
118 return MCFSIM_PCDAT;
119#elif defined(CONFIG_M5249)
120 if (gpio < 32)
121 return MCFSIM2_GPIOREAD;
122 else
123 return MCFSIM2_GPIO1READ;
124#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
125 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
126 if (gpio < 8)
127 return MCFEPORT_EPPDR;
128#if defined(CONFIG_M528x)
129 else if (gpio < 16)
130 return MCFGPTA_GPTPORT;
131 else if (gpio < 24)
132 return MCFGPTB_GPTPORT;
133 else if (gpio < 32)
134 return MCFQADC_PORTQA;
135 else if (gpio < 40)
136 return MCFQADC_PORTQB;
137#endif
138 else
139 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
140#else
141 return 0;
142#endif
143}
144
145/* return the port output data register for a gpio */
146static inline u32 __mcf_gpio_podr(unsigned gpio)
147{
148#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
149 defined(CONFIG_M5307) || defined(CONFIG_M5407)
150 return MCFSIM_PADAT;
151#elif defined(CONFIG_M5272)
152 if (gpio < 16)
153 return MCFSIM_PADAT;
154 else if (gpio < 32)
155 return MCFSIM_PBDAT;
156 else
157 return MCFSIM_PCDAT;
158#elif defined(CONFIG_M5249)
159 if (gpio < 32)
160 return MCFSIM2_GPIOWRITE;
161 else
162 return MCFSIM2_GPIO1WRITE;
163#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
164 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
165 if (gpio < 8)
166 return MCFEPORT_EPDR;
167#if defined(CONFIG_M528x)
168 else if (gpio < 16)
169 return MCFGPTA_GPTPORT;
170 else if (gpio < 24)
171 return MCFGPTB_GPTPORT;
172 else if (gpio < 32)
173 return MCFQADC_PORTQA;
174 else if (gpio < 40)
175 return MCFQADC_PORTQB;
176#endif
177 else
178 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
179#else
180 return 0;
181#endif
182}
183
23/* 184/*
24 * The Generic GPIO functions 185 * The Generic GPIO functions
25 * 186 *
@@ -30,7 +191,7 @@
30static inline int gpio_get_value(unsigned gpio) 191static inline int gpio_get_value(unsigned gpio)
31{ 192{
32 if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX) 193 if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX)
33 return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio); 194 return mcfgpio_read(__mcf_gpio_ppdr(gpio)) & mcfgpio_bit(gpio);
34 else 195 else
35 return __gpio_get_value(gpio); 196 return __gpio_get_value(gpio);
36} 197}
@@ -43,12 +204,12 @@ static inline void gpio_set_value(unsigned gpio, int value)
43 MCFGPIO_PORTTYPE data; 204 MCFGPIO_PORTTYPE data;
44 205
45 local_irq_save(flags); 206 local_irq_save(flags);
46 data = mcfgpio_read(__mcfgpio_podr(gpio)); 207 data = mcfgpio_read(__mcf_gpio_podr(gpio));
47 if (value) 208 if (value)
48 data |= mcfgpio_bit(gpio); 209 data |= mcfgpio_bit(gpio);
49 else 210 else
50 data &= ~mcfgpio_bit(gpio); 211 data &= ~mcfgpio_bit(gpio);
51 mcfgpio_write(data, __mcfgpio_podr(gpio)); 212 mcfgpio_write(data, __mcf_gpio_podr(gpio));
52 local_irq_restore(flags); 213 local_irq_restore(flags);
53 } else { 214 } else {
54 if (value) 215 if (value)
@@ -64,14 +225,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
64 225
65static inline int gpio_to_irq(unsigned gpio) 226static inline int gpio_to_irq(unsigned gpio)
66{ 227{
67#if defined(MCFGPIO_IRQ_MIN) 228 return (gpio < MCFGPIO_IRQ_MAX) ? gpio + MCFGPIO_IRQ_VECBASE : -EINVAL;
68 if ((gpio >= MCFGPIO_IRQ_MIN) && (gpio < MCFGPIO_IRQ_MAX))
69#else
70 if (gpio < MCFGPIO_IRQ_MAX)
71#endif
72 return gpio + MCFGPIO_IRQ_VECBASE;
73 else
74 return __gpio_to_irq(gpio);
75} 229}
76 230
77static inline int irq_to_gpio(unsigned irq) 231static inline int irq_to_gpio(unsigned irq)
diff --git a/arch/m68k/include/asm/hardirq.h b/arch/m68k/include/asm/hardirq.h
index db30ed27687..870e5347155 100644
--- a/arch/m68k/include/asm/hardirq.h
+++ b/arch/m68k/include/asm/hardirq.h
@@ -18,11 +18,6 @@
18 18
19#ifdef CONFIG_MMU 19#ifdef CONFIG_MMU
20 20
21static inline void ack_bad_irq(unsigned int irq)
22{
23 pr_crit("unexpected IRQ trap at vector %02x\n", irq);
24}
25
26/* entry.S is sensitive to the offsets of these fields */ 21/* entry.S is sensitive to the offsets of these fields */
27typedef struct { 22typedef struct {
28 unsigned int __softirq_pending; 23 unsigned int __softirq_pending;
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h
index c70cc915500..c7210ba184e 100644
--- a/arch/m68k/include/asm/io.h
+++ b/arch/m68k/include/asm/io.h
@@ -1,5 +1,5 @@
1#ifdef __uClinux__ 1#ifdef __uClinux__
2#include <asm/io_no.h> 2#include "io_no.h"
3#else 3#else
4#include <asm/io_mm.h> 4#include "io_mm.h"
5#endif 5#endif
diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
index a6686d26fe1..0fb3468000e 100644
--- a/arch/m68k/include/asm/io_mm.h
+++ b/arch/m68k/include/asm/io_mm.h
@@ -65,53 +65,7 @@
65 65
66 66
67 67
68#if defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE) 68#ifdef CONFIG_ISA
69
70#define HAVE_ARCH_PIO_SIZE
71#define PIO_OFFSET 0
72#define PIO_MASK 0xffff
73#define PIO_RESERVED 0x10000
74
75u8 mcf_pci_inb(u32 addr);
76u16 mcf_pci_inw(u32 addr);
77u32 mcf_pci_inl(u32 addr);
78void mcf_pci_insb(u32 addr, u8 *buf, u32 len);
79void mcf_pci_insw(u32 addr, u16 *buf, u32 len);
80void mcf_pci_insl(u32 addr, u32 *buf, u32 len);
81
82void mcf_pci_outb(u8 v, u32 addr);
83void mcf_pci_outw(u16 v, u32 addr);
84void mcf_pci_outl(u32 v, u32 addr);
85void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len);
86void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len);
87void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len);
88
89#define inb mcf_pci_inb
90#define inb_p mcf_pci_inb
91#define inw mcf_pci_inw
92#define inw_p mcf_pci_inw
93#define inl mcf_pci_inl
94#define inl_p mcf_pci_inl
95#define insb mcf_pci_insb
96#define insw mcf_pci_insw
97#define insl mcf_pci_insl
98
99#define outb mcf_pci_outb
100#define outb_p mcf_pci_outb
101#define outw mcf_pci_outw
102#define outw_p mcf_pci_outw
103#define outl mcf_pci_outl
104#define outl_p mcf_pci_outl
105#define outsb mcf_pci_outsb
106#define outsw mcf_pci_outsw
107#define outsl mcf_pci_outsl
108
109#define readb(addr) in_8(addr)
110#define writeb(v, addr) out_8((addr), (v))
111#define readw(addr) in_le16(addr)
112#define writew(v, addr) out_le16((addr), (v))
113
114#elif defined(CONFIG_ISA)
115 69
116#if MULTI_ISA == 0 70#if MULTI_ISA == 0
117#undef MULTI_ISA 71#undef MULTI_ISA
@@ -324,13 +278,6 @@ static inline void isa_delay(void)
324#define readl(addr) in_le32(addr) 278#define readl(addr) in_le32(addr)
325#define writel(val,addr) out_le32((addr),(val)) 279#define writel(val,addr) out_le32((addr),(val))
326 280
327#define readsb(port, buf, nr) raw_insb((port), (u8 *)(buf), (nr))
328#define readsw(port, buf, nr) raw_insw((port), (u16 *)(buf), (nr))
329#define readsl(port, buf, nr) raw_insl((port), (u32 *)(buf), (nr))
330#define writesb(port, buf, nr) raw_outsb((port), (u8 *)(buf), (nr))
331#define writesw(port, buf, nr) raw_outsw((port), (u16 *)(buf), (nr))
332#define writesl(port, buf, nr) raw_outsl((port), (u32 *)(buf), (nr))
333
334#define mmiowb() 281#define mmiowb()
335 282
336static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size) 283static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
@@ -386,6 +333,4 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
386 */ 333 */
387#define xlate_dev_kmem_ptr(p) p 334#define xlate_dev_kmem_ptr(p) p
388 335
389#define ioport_map(port, nr) ((void __iomem *)(port))
390
391#endif /* _IO_H */ 336#endif /* _IO_H */
diff --git a/arch/m68k/include/asm/irq.h b/arch/m68k/include/asm/irq.h
index c1155f0e22c..69ed0d74d53 100644
--- a/arch/m68k/include/asm/irq.h
+++ b/arch/m68k/include/asm/irq.h
@@ -25,8 +25,12 @@
25#define NR_IRQS 0 25#define NR_IRQS 0
26#endif 26#endif
27 27
28#if defined(CONFIG_M68020) || defined(CONFIG_M68030) || \ 28#ifdef CONFIG_MMU
29 defined(CONFIG_M68040) || defined(CONFIG_M68060) 29
30#include <linux/linkage.h>
31#include <linux/hardirq.h>
32#include <linux/irqreturn.h>
33#include <linux/spinlock_types.h>
30 34
31/* 35/*
32 * Interrupt source definitions 36 * Interrupt source definitions
@@ -50,27 +54,74 @@
50 54
51#define IRQ_USER 8 55#define IRQ_USER 8
52 56
53struct irq_data;
54struct irq_chip;
55struct irq_desc;
56extern unsigned int m68k_irq_startup(struct irq_data *data);
57extern unsigned int m68k_irq_startup_irq(unsigned int irq);
58extern void m68k_irq_shutdown(struct irq_data *data);
59extern void m68k_setup_auto_interrupt(void (*handler)(unsigned int,
60 struct pt_regs *));
61extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt);
62extern void m68k_setup_irq_controller(struct irq_chip *,
63 void (*handle)(unsigned int irq,
64 struct irq_desc *desc),
65 unsigned int irq, unsigned int cnt);
66
67extern unsigned int irq_canonicalize(unsigned int irq); 57extern unsigned int irq_canonicalize(unsigned int irq);
68 58
59struct pt_regs;
60
61/*
62 * various flags for request_irq() - the Amiga now uses the standard
63 * mechanism like all other architectures - IRQF_DISABLED and
64 * IRQF_SHARED are your friends.
65 */
66#ifndef MACH_AMIGA_ONLY
67#define IRQ_FLG_LOCK (0x0001) /* handler is not replaceable */
68#define IRQ_FLG_REPLACE (0x0002) /* replace existing handler */
69#define IRQ_FLG_FAST (0x0004)
70#define IRQ_FLG_SLOW (0x0008)
71#define IRQ_FLG_STD (0x8000) /* internally used */
72#endif
73
74/*
75 * This structure is used to chain together the ISRs for a particular
76 * interrupt source (if it supports chaining).
77 */
78typedef struct irq_node {
79 irqreturn_t (*handler)(int, void *);
80 void *dev_id;
81 struct irq_node *next;
82 unsigned long flags;
83 const char *devname;
84} irq_node_t;
85
86/*
87 * This structure has only 4 elements for speed reasons
88 */
89struct irq_handler {
90 int (*handler)(int, void *);
91 unsigned long flags;
92 void *dev_id;
93 const char *devname;
94};
95
96struct irq_controller {
97 const char *name;
98 spinlock_t lock;
99 int (*startup)(unsigned int irq);
100 void (*shutdown)(unsigned int irq);
101 void (*enable)(unsigned int irq);
102 void (*disable)(unsigned int irq);
103};
104
105extern int m68k_irq_startup(unsigned int);
106extern void m68k_irq_shutdown(unsigned int);
107
108/*
109 * This function returns a new irq_node_t
110 */
111extern irq_node_t *new_irq_node(void);
112
113extern void m68k_setup_auto_interrupt(void (*handler)(unsigned int, struct pt_regs *));
114extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt,
115 void (*handler)(unsigned int, struct pt_regs *));
116extern void m68k_setup_irq_controller(struct irq_controller *, unsigned int, unsigned int);
117
118asmlinkage void m68k_handle_int(unsigned int);
119asmlinkage void __m68k_handle_int(unsigned int, struct pt_regs *);
120
69#else 121#else
70#define irq_canonicalize(irq) (irq) 122#define irq_canonicalize(irq) (irq)
71#endif /* !(CONFIG_M68020 || CONFIG_M68030 || CONFIG_M68040 || CONFIG_M68060) */ 123#endif /* CONFIG_MMU */
72 124
73asmlinkage void do_IRQ(int irq, struct pt_regs *regs); 125asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
74extern atomic_t irq_err_count;
75 126
76#endif /* _M68K_IRQ_H_ */ 127#endif /* _M68K_IRQ_H_ */
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 4cf864f5ea7..9015eadd5c0 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -21,33 +21,33 @@
21/* 21/*
22 * Define the 5206 SIM register set addresses. 22 * Define the 5206 SIM register set addresses.
23 */ 23 */
24#define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */ 24#define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */
25#define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */ 25#define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */
26#define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */ 26#define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */
27#define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */ 27#define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */
28#define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */ 28#define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */
29#define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */ 29#define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */
30#define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */ 30#define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */
31#define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */ 31#define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */
32#define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */ 32#define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */
33#define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */ 33#define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */
34#define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */ 34#define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */
35#define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */ 35#define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */
36#define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */ 36#define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */
37#define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */ 37#define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */
38#ifdef CONFIG_M5206e 38#ifdef CONFIG_M5206e
39#define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */ 39#define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */
40#define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */ 40#define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */
41#endif 41#endif
42 42
43#define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */ 43#define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */
44#define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */ 44#define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */
45 45
46#define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */ 46#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */
47#define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */ 47#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/
48 48
49#define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */ 49#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
50#define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */ 50#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
51 51
52#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */ 52#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
53#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */ 53#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
@@ -58,36 +58,36 @@
58#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */ 58#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
59#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */ 59#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
60 60
61#define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */ 61#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
62#define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */ 62#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
63#define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */ 63#define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */
64#define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */ 64#define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */
65#define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */ 65#define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */
66#define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */ 66#define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */
67#define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */ 67#define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */
68#define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */ 68#define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */
69#define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */ 69#define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */
70#define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */ 70#define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */
71#define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */ 71#define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */
72#define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */ 72#define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */
73#define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */ 73#define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */
74#define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */ 74#define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */
75#define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */ 75#define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */
76#define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */ 76#define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */
77#define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */ 77#define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */
78#define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */ 78#define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */
79#define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */ 79#define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */
80#define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */ 80#define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */
81#define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */ 81#define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */
82#define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */ 82#define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */
83#define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */ 83#define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */
84#define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */ 84#define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */
85#define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */ 85#define MCFSIM_DMCR 0xc6 /* Default control */
86 86
87#ifdef CONFIG_M5206e 87#ifdef CONFIG_M5206e
88#define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */ 88#define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */
89#else 89#else
90#define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */ 90#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
91#endif 91#endif
92 92
93#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */ 93#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
@@ -100,11 +100,11 @@
100#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */ 100#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
101 101
102#if defined(CONFIG_NETtel) 102#if defined(CONFIG_NETtel)
103#define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */ 103#define MCFUART_BASE1 0x180 /* Base address of UART1 */
104#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ 104#define MCFUART_BASE2 0x140 /* Base address of UART2 */
105#else 105#else
106#define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */ 106#define MCFUART_BASE1 0x140 /* Base address of UART1 */
107#define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */ 107#define MCFUART_BASE2 0x180 /* Base address of UART2 */
108#endif 108#endif
109 109
110/* 110/*
@@ -112,8 +112,6 @@
112 */ 112 */
113#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 113#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
114#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 114#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
115#define MCF_IRQ_UART0 73 /* UART0 */
116#define MCF_IRQ_UART1 74 /* UART1 */
117 115
118/* 116/*
119 * Generic GPIO 117 * Generic GPIO
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index db3f8ee4a6c..b6bf2c518ba 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -42,31 +42,14 @@
42#define MCFINTC1_SIMR (0) 42#define MCFINTC1_SIMR (0)
43#define MCFINTC1_CIMR (0) 43#define MCFINTC1_CIMR (0)
44#define MCFINTC1_ICR0 (0) 44#define MCFINTC1_ICR0 (0)
45#define MCFINTC2_SIMR (0)
46#define MCFINTC2_CIMR (0)
47#define MCFINTC2_ICR0 (0)
48 45
49#define MCFINT_VECBASE 64 46#define MCFINT_VECBASE 64
50#define MCFINT_UART0 26 /* Interrupt number for UART0 */ 47#define MCFINT_UART0 26 /* Interrupt number for UART0 */
51#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 48#define MCFINT_UART1 27 /* Interrupt number for UART1 */
52#define MCFINT_UART2 28 /* Interrupt number for UART2 */ 49#define MCFINT_UART2 28 /* Interrupt number for UART2 */
53#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 50#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
54#define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */
55#define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */
56#define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */
57#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 51#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
58 52
59#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
60#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
61#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
62
63#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
64#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
65#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
66
67#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
68#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
69
70/* 53/*
71 * SDRAM configuration registers. 54 * SDRAM configuration registers.
72 */ 55 */
@@ -107,13 +90,15 @@
107#define MCFGPIO_PDDR_FECH 0xFC0A4013 90#define MCFGPIO_PDDR_FECH 0xFC0A4013
108#define MCFGPIO_PDDR_FECL 0xFC0A4014 91#define MCFGPIO_PDDR_FECL 0xFC0A4014
109 92
110#define MCFGPIO_PPDSDR_CS 0xFC0A401A 93#define MCFGPIO_PPDSDR_BUSCTL 0xFC0A401A
111#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B 94#define MCFGPIO_PPDSDR_BE 0xFC0A401B
112#define MCFGPIO_PPDSDR_QSPI 0xFC0A401C 95#define MCFGPIO_PPDSDR_CS 0xFC0A401C
113#define MCFGPIO_PPDSDR_TIMER 0xFC0A401D 96#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401D
114#define MCFGPIO_PPDSDR_UART 0xFC0A401E 97#define MCFGPIO_PPDSDR_QSPI 0xFC0A401E
115#define MCFGPIO_PPDSDR_FECH 0xFC0A401F 98#define MCFGPIO_PPDSDR_TIMER 0xFC0A401F
116#define MCFGPIO_PPDSDR_FECL 0xFC0A4020 99#define MCFGPIO_PPDSDR_UART 0xFC0A4021
100#define MCFGPIO_PPDSDR_FECH 0xFC0A4021
101#define MCFGPIO_PPDSDR_FECL 0xFC0A4022
117 102
118#define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 103#define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024
119#define MCFGPIO_PCLRR_BE 0xFC0A4025 104#define MCFGPIO_PCLRR_BE 0xFC0A4025
@@ -128,11 +113,11 @@
128/* 113/*
129 * Generic GPIO support 114 * Generic GPIO support
130 */ 115 */
131#define MCFGPIO_PODR MCFGPIO_PODR_CS 116#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
132#define MCFGPIO_PDDR MCFGPIO_PDDR_CS 117#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
133#define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS 118#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
134#define MCFGPIO_SETR MCFGPIO_PPDSDR_CS 119#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
135#define MCFGPIO_CLRR MCFGPIO_PCLRR_CS 120#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
136 121
137#define MCFGPIO_PIN_MAX 80 122#define MCFGPIO_PIN_MAX 80
138#define MCFGPIO_IRQ_MAX 8 123#define MCFGPIO_IRQ_MAX 8
@@ -161,25 +146,15 @@
161/* 146/*
162 * UART module. 147 * UART module.
163 */ 148 */
164#define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */ 149#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
165#define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */ 150#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
166#define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */ 151#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */
167 152
168/* 153/*
169 * FEC module. 154 * FEC module.
170 */ 155 */
171#define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */ 156#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */
172#define MCFFEC_SIZE0 0x800 /* Register set size */ 157#define MCFFEC_SIZE 0x800 /* Register set size */
173
174/*
175 * QSPI module.
176 */
177#define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */
178#define MCFQSPI_SIZE 0x40 /* Register set size */
179
180#define MCFQSPI_CS0 46
181#define MCFQSPI_CS1 47
182#define MCFQSPI_CS2 27
183 158
184/* 159/*
185 * Reset Control Unit. 160 * Reset Control Unit.
@@ -190,15 +165,5 @@
190#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 165#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
191#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 166#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
192 167
193/*
194 * Power Management.
195 */
196#define MCFPM_WCR 0xfc040013
197#define MCFPM_PPMSR0 0xfc04002c
198#define MCFPM_PPMCR0 0xfc04002d
199#define MCFPM_PPMHR0 0xfc040030
200#define MCFPM_PPMLR0 0xfc040034
201#define MCFPM_LPCR 0xfc0a0007
202
203/****************************************************************************/ 168/****************************************************************************/
204#endif /* m520xsim_h */ 169#endif /* m520xsim_h */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 5e06b4eb57f..6235921eca4 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -35,24 +35,8 @@
35 35
36#define MCFINT_VECBASE 64 /* Vector base number */ 36#define MCFINT_VECBASE 64 /* Vector base number */
37#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 37#define MCFINT_UART0 13 /* Interrupt number for UART0 */
38#define MCFINT_UART1 14 /* Interrupt number for UART1 */
39#define MCFINT_UART2 15 /* Interrupt number for UART2 */
40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
41#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
42#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
43#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
44#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 38#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
45 39#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
46#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
47#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
48#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
49
50#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
51#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
53
54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
55#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
56 40
57/* 41/*
58 * SDRAM configuration registers. 42 * SDRAM configuration registers.
@@ -66,8 +50,8 @@
66/* 50/*
67 * Reset Control Unit (relative to IPSBAR). 51 * Reset Control Unit (relative to IPSBAR).
68 */ 52 */
69#define MCF_RCR (MCF_IPSBAR + 0x110000) 53#define MCF_RCR 0x110000
70#define MCF_RSR (MCF_IPSBAR + 0x110001) 54#define MCF_RSR 0x110001
71 55
72#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 56#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
73#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 57#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
@@ -75,26 +59,15 @@
75/* 59/*
76 * UART module. 60 * UART module.
77 */ 61 */
78#define MCFUART_BASE0 (MCF_IPSBAR + 0x200) 62#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
79#define MCFUART_BASE1 (MCF_IPSBAR + 0x240) 63#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
80#define MCFUART_BASE2 (MCF_IPSBAR + 0x280) 64#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
81 65
82/* 66/*
83 * FEC ethernet module. 67 * FEC ethernet module.
84 */ 68 */
85#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) 69#define MCFFEC_BASE (MCF_IPSBAR + 0x1000)
86#define MCFFEC_SIZE0 0x800 70#define MCFFEC_SIZE 0x800
87
88/*
89 * QSPI module.
90 */
91#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
92#define MCFQSPI_SIZE 0x40
93
94#define MCFQSPI_CS0 91
95#define MCFQSPI_CS1 92
96#define MCFQSPI_CS2 103
97#define MCFQSPI_CS3 99
98 71
99/* 72/*
100 * GPIO module. 73 * GPIO module.
@@ -176,29 +149,21 @@
176/* 149/*
177 * Generic GPIO support 150 * Generic GPIO support
178 */ 151 */
179#define MCFGPIO_PODR MCFGPIO_PODR_ADDR 152#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
180#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR 153#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
181#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR 154#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
182#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR 155#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
183#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR 156#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
184 157
185#define MCFGPIO_PIN_MAX 107 158#define MCFGPIO_PIN_MAX 107
186#define MCFGPIO_IRQ_MAX 8 159#define MCFGPIO_IRQ_MAX 8
187#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 160#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
188 161
189/* 162/*
190 * Pin Assignment 163 * Pin Assignment
191*/ 164*/
192#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
193#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
194#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
195#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
196#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046)
197#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
198#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048)
199#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 165#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
200#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 166#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
201#define MCFGPIO_PAR_ETPU (MCF_IPSBAR + 0x10004E)
202 167
203/* 168/*
204 * DMA unit base addresses. 169 * DMA unit base addresses.
diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
deleted file mode 100644
index e33f5bb6aca..00000000000
--- a/arch/m68k/include/asm/m525xsim.h
+++ /dev/null
@@ -1,308 +0,0 @@
1/****************************************************************************/
2
3/*
4 * m525xsim.h -- ColdFire 525x System Integration Module support.
5 *
6 * (C) Copyright 2012, Steven king <sfking@fdwdc.com>
7 * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
8 */
9
10/****************************************************************************/
11#ifndef m525xsim_h
12#define m525xsim_h
13/****************************************************************************/
14
15/*
16 * This header supports ColdFire 5249, 5251 and 5253. There are a few
17 * little differences between them, but most of the peripheral support
18 * can be used by all of them.
19 */
20#define CPU_NAME "COLDFIRE(m525x)"
21#define CPU_INSTR_PER_JIFFY 3
22#define MCF_BUSCLK (MCF_CLK / 2)
23
24#include <asm/m52xxacr.h>
25
26/*
27 * The 525x has a second MBAR region, define its address.
28 */
29#define MCF_MBAR2 0x80000000
30
31/*
32 * Define the 525x SIM register set addresses.
33 */
34#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
35#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
36#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
37#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
38#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
39#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
40#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
41#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
42#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
43#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
44#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
45#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
46#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
47#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
48#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
49#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
50#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
51#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
52#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
53
54#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
55#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
56#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
57#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
58#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
59#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
60#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
61#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
62#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
63#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
64#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
65#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
66#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
67#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
68#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
69
70#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
71#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
72#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
73#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
74#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
75
76/*
77 * Secondary Interrupt Controller (in MBAR2)
78*/
79#define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */
80#define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
81#define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */
82#define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */
83#define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */
84#define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
85#define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */
86#define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */
87#define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */
88
89#define MCFINTC2_INTPRI_REG(i) (MCFINTC2_INTPRI1 + \
90 ((((i) - MCFINTC2_VECBASE) / 8) * 4))
91#define MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4))
92
93/*
94 * Timer module.
95 */
96#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
97#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
98
99/*
100 * UART module.
101 */
102#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
103#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
104
105/*
106 * QSPI module.
107 */
108#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
109#define MCFQSPI_SIZE 0x40 /* Register set size */
110
111#ifdef CONFIG_M5249
112#define MCFQSPI_CS0 29
113#define MCFQSPI_CS1 24
114#define MCFQSPI_CS2 21
115#define MCFQSPI_CS3 22
116#else
117#define MCFQSPI_CS0 15
118#define MCFQSPI_CS1 16
119#define MCFQSPI_CS2 24
120#define MCFQSPI_CS3 28
121#endif
122
123/*
124 * I2C module.
125 */
126#define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base addreess I2C0 */
127#define MCFI2C_SIZE0 0x20 /* Register set size */
128
129#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */
130#define MCFI2C_SIZE1 0x20 /* Register set size */
131
132/*
133 * DMA unit base addresses.
134 */
135#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
136#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
137#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
138#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
139
140/*
141 * Some symbol defines for the above...
142 */
143#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
144#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
145#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
146#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
147#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
148#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
149#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
150#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
151#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
152#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
153#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
154
155/*
156 * Define system peripheral IRQ usage.
157 */
158#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
159#define MCF_IRQ_I2C0 29
160#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
161#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
162
163#define MCF_IRQ_UART0 73 /* UART0 */
164#define MCF_IRQ_UART1 74 /* UART1 */
165
166/*
167 * Define the base interrupt for the second interrupt controller.
168 * We set it to 128, out of the way of the base interrupts, and plenty
169 * of room for its 64 interrupts.
170 */
171#define MCFINTC2_VECBASE 128
172
173#define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32)
174#define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33)
175#define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34)
176#define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35)
177#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36)
178#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37)
179#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38)
180#define MCF_IRQ_GPIO7 (MCFINTC2_VECBASE + 39)
181
182#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40)
183#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62)
184
185/*
186 * General purpose IO registers (in MBAR2).
187 */
188#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
189#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
190#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
191#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
192#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
193#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
194#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
195#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
196
197#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
198#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
199#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
200
201#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
202#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
203#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
204
205/*
206 * Generic GPIO support
207 */
208#define MCFGPIO_PIN_MAX 64
209#ifdef CONFIG_M5249
210#define MCFGPIO_IRQ_MAX -1
211#define MCFGPIO_IRQ_VECBASE -1
212#else
213#define MCFGPIO_IRQ_MAX 7
214#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0
215#endif
216
217/****************************************************************************/
218
219#ifdef __ASSEMBLER__
220#ifdef CONFIG_M5249C3
221/*
222 * The M5249C3 board needs a little help getting all its SIM devices
223 * initialized at kernel start time. dBUG doesn't set much up, so
224 * we need to do it manually.
225 */
226.macro m5249c3_setup
227 /*
228 * Set MBAR1 and MBAR2, just incase they are not set.
229 */
230 movel #0x10000001,%a0
231 movec %a0,%MBAR /* map MBAR region */
232 subql #1,%a0 /* get MBAR address in a0 */
233
234 movel #0x80000001,%a1
235 movec %a1,#3086 /* map MBAR2 region */
236 subql #1,%a1 /* get MBAR2 address in a1 */
237
238 /*
239 * Move secondary interrupts to their base (128).
240 */
241 moveb #MCFINTC2_VECBASE,%d0
242 moveb %d0,0x16b(%a1) /* interrupt base register */
243
244 /*
245 * Work around broken CSMR0/DRAM vector problem.
246 */
247 movel #0x001F0021,%d0 /* disable C/I bit */
248 movel %d0,0x84(%a0) /* set CSMR0 */
249
250 /*
251 * Disable the PLL firstly. (Who knows what state it is
252 * in here!).
253 */
254 movel 0x180(%a1),%d0 /* get current PLL value */
255 andl #0xfffffffe,%d0 /* PLL bypass first */
256 movel %d0,0x180(%a1) /* set PLL register */
257 nop
258
259#if CONFIG_CLOCK_FREQ == 140000000
260 /*
261 * Set initial clock frequency. This assumes M5249C3 board
262 * is fitted with 11.2896MHz crystal. It will program the
263 * PLL for 140MHz. Lets go fast :-)
264 */
265 movel #0x125a40f0,%d0 /* set for 140MHz */
266 movel %d0,0x180(%a1) /* set PLL register */
267 orl #0x1,%d0
268 movel %d0,0x180(%a1) /* set PLL register */
269#endif
270
271 /*
272 * Setup CS1 for ethernet controller.
273 * (Setup as per M5249C3 doco).
274 */
275 movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
276 movel %d0,0x8c(%a0)
277 movel #0x001f0021,%d0 /* CS1 size of 1Mb */
278 movel %d0,0x90(%a0)
279 movew #0x0080,%d0 /* CS1 = 16bit port, AA */
280 movew %d0,0x96(%a0)
281
282 /*
283 * Setup CS2 for IDE interface.
284 */
285 movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
286 movel %d0,0x98(%a0)
287 movel #0x001f0001,%d0 /* CS2 size of 1MB */
288 movel %d0,0x9c(%a0)
289 movew #0x0080,%d0 /* CS2 = 16bit, TA */
290 movew %d0,0xa2(%a0)
291
292 movel #0x00107000,%d0 /* IDEconfig1 */
293 movel %d0,0x18c(%a1)
294 movel #0x000c0400,%d0 /* IDEconfig2 */
295 movel %d0,0x190(%a1)
296
297 movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
298 orl %d0,0xc(%a1) /* function GPIO19 */
299 orl %d0,0x8(%a1) /* enable GPIO19 as output */
300 orl %d0,0x4(%a1) /* de-assert IDE reset */
301.endm
302
303#define PLATFORM_SETUP m5249c3_setup
304
305#endif /* CONFIG_M5249C3 */
306#endif /* __ASSEMBLER__ */
307/****************************************************************************/
308#endif /* m525xsim_h */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 1fb01bb05d6..759c2b07a99 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -21,55 +21,55 @@
21/* 21/*
22 * Define the 5272 SIM register set addresses. 22 * Define the 5272 SIM register set addresses.
23 */ 23 */
24#define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */ 24#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
25#define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */ 25#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
26#define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */ 26#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
27#define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */ 27#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
28#define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */ 28#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
29 29
30#define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */ 30#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
31#define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */ 31#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
32#define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */ 32#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
33#define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */ 33#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
34 34
35#define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */ 35#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
36#define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */ 36#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
37#define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */ 37#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
38#define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */ 38#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
39 39
40#define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */ 40#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
41#define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */ 41#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
42#define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */ 42#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
43#define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */ 43#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
44 44
45#define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */ 45#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
46#define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */ 46#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
47#define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */ 47#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
48#define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */ 48#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
49#define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */ 49#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
50#define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */ 50#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
51#define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */ 51#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
52#define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */ 52#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
53#define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */ 53#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
54#define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */ 54#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
55#define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */ 55#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
56#define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */ 56#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
57#define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */ 57#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
58#define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */ 58#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
59#define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */ 59#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
60#define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */ 60#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
61 61
62#define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */ 62#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
63#define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */ 63#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
64#define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */ 64#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
65#define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */ 65#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
66#define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */ 66#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
67#define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */ 67#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
68#define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */ 68#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
69#define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */ 69#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
70 70
71#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */ 71#define MCFUART_BASE1 0x100 /* Base address of UART1 */
72#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ 72#define MCFUART_BASE2 0x140 /* Base address of UART2 */
73 73
74#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ 74#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
75#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ 75#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
@@ -88,9 +88,6 @@
88#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ 88#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
89#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ 89#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
90 90
91#define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */
92#define MCFFEC_SIZE0 0x1d0
93
94/* 91/*
95 * Define system peripheral IRQ usage. 92 * Define system peripheral IRQ usage.
96 */ 93 */
@@ -104,8 +101,8 @@
104#define MCF_IRQ_TIMER2 70 /* Timer 2 */ 101#define MCF_IRQ_TIMER2 70 /* Timer 2 */
105#define MCF_IRQ_TIMER3 71 /* Timer 3 */ 102#define MCF_IRQ_TIMER3 71 /* Timer 3 */
106#define MCF_IRQ_TIMER4 72 /* Timer 4 */ 103#define MCF_IRQ_TIMER4 72 /* Timer 4 */
107#define MCF_IRQ_UART0 73 /* UART 0 */ 104#define MCF_IRQ_UART1 73 /* UART 1 */
108#define MCF_IRQ_UART1 74 /* UART 1 */ 105#define MCF_IRQ_UART2 74 /* UART 2 */
109#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */ 106#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
110#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */ 107#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
111#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */ 108#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
@@ -117,9 +114,9 @@
117#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */ 114#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */
118#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */ 115#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */
119#define MCF_IRQ_DMA 85 /* DMA Controller */ 116#define MCF_IRQ_DMA 85 /* DMA Controller */
120#define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */ 117#define MCF_IRQ_ERX 86 /* Ethernet Receiver */
121#define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */ 118#define MCF_IRQ_ETX 87 /* Ethernet Transmitter */
122#define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */ 119#define MCF_IRQ_ENTC 88 /* Ethernet Non-Time Critical */
123#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */ 120#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */
124#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */ 121#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */
125#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */ 122#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */
@@ -132,9 +129,8 @@
132/* 129/*
133 * Generic GPIO support 130 * Generic GPIO support
134 */ 131 */
135#define MCFGPIO_PIN_MAX 48 132#define MCFGPIO_PIN_MAX 48
136#define MCFGPIO_IRQ_MAX -1 133#define MCFGPIO_IRQ_MAX -1
137#define MCFGPIO_IRQ_VECBASE -1 134#define MCFGPIO_IRQ_VECBASE -1
138
139/****************************************************************************/ 135/****************************************************************************/
140#endif /* m5272sim_h */ 136#endif /* m5272sim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 1bebbe78055..758810ef91e 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -38,30 +38,8 @@
38#define MCFINT_UART1 14 /* Interrupt number for UART1 */ 38#define MCFINT_UART1 14 /* Interrupt number for UART1 */
39#define MCFINT_UART2 15 /* Interrupt number for UART2 */ 39#define MCFINT_UART2 15 /* Interrupt number for UART2 */
40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
41#define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */
42#define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */
43#define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */
44#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 41#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
45 42
46#define MCFINT2_VECBASE 128 /* Vector base number 2 */
47#define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */
48#define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */
49#define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */
50
51#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
52#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
53#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
54
55#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
56#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
57#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
58#define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1)
59#define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1)
60#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1)
61
62#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
63#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
64
65/* 43/*
66 * SDRAM configuration registers. 44 * SDRAM configuration registers.
67 */ 45 */
@@ -94,9 +72,9 @@
94/* 72/*
95 * UART module. 73 * UART module.
96 */ 74 */
97#define MCFUART_BASE0 (MCF_IPSBAR + 0x200) 75#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
98#define MCFUART_BASE1 (MCF_IPSBAR + 0x240) 76#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
99#define MCFUART_BASE2 (MCF_IPSBAR + 0x280) 77#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
100 78
101/* 79/*
102 * FEC ethernet module. 80 * FEC ethernet module.
@@ -106,28 +84,6 @@
106#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) 84#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
107#define MCFFEC_SIZE1 0x800 85#define MCFFEC_SIZE1 0x800
108 86
109/*
110 * QSPI module.
111 */
112#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
113#define MCFQSPI_SIZE 0x40
114
115#ifdef CONFIG_M5271
116#define MCFQSPI_CS0 91
117#define MCFQSPI_CS1 92
118#define MCFQSPI_CS2 99
119#define MCFQSPI_CS3 103
120#endif
121#ifdef CONFIG_M5275
122#define MCFQSPI_CS0 59
123#define MCFQSPI_CS1 60
124#define MCFQSPI_CS2 61
125#define MCFQSPI_CS3 62
126#endif
127
128/*
129 * GPIO module.
130 */
131#ifdef CONFIG_M5271 87#ifdef CONFIG_M5271
132#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 88#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
133#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 89#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
@@ -184,33 +140,19 @@
184/* 140/*
185 * Generic GPIO support 141 * Generic GPIO support
186 */ 142 */
187#define MCFGPIO_PODR MCFGPIO_PODR_ADDR 143#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
188#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR 144#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
189#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR 145#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
190#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR 146#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
191#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR 147#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
192 148
193#define MCFGPIO_PIN_MAX 100 149#define MCFGPIO_PIN_MAX 100
194#define MCFGPIO_IRQ_MAX 8 150#define MCFGPIO_IRQ_MAX 8
195#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 151#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
196 152
197/*
198 * Port Pin Assignment registers.
199 */
200#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
201#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
202#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
203#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
204#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046)
205#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
206#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048)
207#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 153#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
208#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 154#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
209 155#endif
210#define UART0_ENABLE_MASK 0x000f
211#define UART1_ENABLE_MASK 0x0ff0
212#define UART2_ENABLE_MASK 0x3000
213#endif /* CONFIG_M5271 */
214 156
215#ifdef CONFIG_M5275 157#ifdef CONFIG_M5275
216#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) 158#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004)
@@ -293,36 +235,18 @@
293/* 235/*
294 * Generic GPIO support 236 * Generic GPIO support
295 */ 237 */
296#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 238#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
297#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 239#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
298#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 240#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
299#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 241#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
300#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 242#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
301 243
302#define MCFGPIO_PIN_MAX 148 244#define MCFGPIO_PIN_MAX 148
303#define MCFGPIO_IRQ_MAX 8 245#define MCFGPIO_IRQ_MAX 8
304#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 246#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
305 247
306/*
307 * Port Pin Assignment registers.
308 */
309#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070)
310#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071)
311#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072)
312#define MCFGPIO_PAR_USB (MCF_IPSBAR + 0x100076)
313#define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078)
314#define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079)
315#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10007A)
316#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x10007C)
317#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) 248#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
318#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100080) 249#endif
319#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082)
320#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084)
321
322#define UART0_ENABLE_MASK 0x000f
323#define UART1_ENABLE_MASK 0x00f0
324#define UART2_ENABLE_MASK 0x3f00
325#endif /* CONFIG_M5275 */
326 250
327/* 251/*
328 * PIT timer base addresses. 252 * PIT timer base addresses.
@@ -343,10 +267,26 @@
343#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) 267#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
344 268
345/* 269/*
270 * GPIO pins setups to enable the UARTs.
271 */
272#ifdef CONFIG_M5271
273#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */
274#define UART0_ENABLE_MASK 0x000f
275#define UART1_ENABLE_MASK 0x0ff0
276#define UART2_ENABLE_MASK 0x3000
277#endif
278#ifdef CONFIG_M5275
279#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */
280#define UART0_ENABLE_MASK 0x000f
281#define UART1_ENABLE_MASK 0x00f0
282#define UART2_ENABLE_MASK 0x3f00
283#endif
284
285/*
346 * Reset Control Unit (relative to IPSBAR). 286 * Reset Control Unit (relative to IPSBAR).
347 */ 287 */
348#define MCF_RCR (MCF_IPSBAR + 0x110000) 288#define MCF_RCR 0x110000
349#define MCF_RSR (MCF_IPSBAR + 0x110001) 289#define MCF_RSR 0x110001
350 290
351#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 291#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
352#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 292#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index cf68ca0ac3a..d798bd5df56 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -35,24 +35,9 @@
35 35
36#define MCFINT_VECBASE 64 /* Vector base number */ 36#define MCFINT_VECBASE 64 /* Vector base number */
37#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 37#define MCFINT_UART0 13 /* Interrupt number for UART0 */
38#define MCFINT_UART1 14 /* Interrupt number for UART1 */
39#define MCFINT_UART2 15 /* Interrupt number for UART2 */
40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 38#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
41#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
42#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
43#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
44#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ 39#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
45 40
46#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
47#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
48#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
49
50#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
51#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
53
54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
55#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
56/* 41/*
57 * SDRAM configuration registers. 42 * SDRAM configuration registers.
58 */ 43 */
@@ -73,105 +58,113 @@
73/* 58/*
74 * UART module. 59 * UART module.
75 */ 60 */
76#define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200) 61#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200)
77#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240) 62#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240)
78#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280) 63#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280)
79 64
80/* 65/*
81 * FEC ethernet module. 66 * FEC ethernet module.
82 */ 67 */
83#define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000) 68#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000)
84#define MCFFEC_SIZE0 0x800 69#define MCFFEC_SIZE 0x800
85 70
86/* 71/*
87 * QSPI module. 72 * GPIO registers
88 */ 73 */
89#define MCFQSPI_BASE (MCF_IPSBAR + 0x340) 74#define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000)
90#define MCFQSPI_SIZE 0x40 75#define MCFGPIO_PORTB (MCF_IPSBAR + 0x00100001)
76#define MCFGPIO_PORTC (MCF_IPSBAR + 0x00100002)
77#define MCFGPIO_PORTD (MCF_IPSBAR + 0x00100003)
78#define MCFGPIO_PORTE (MCF_IPSBAR + 0x00100004)
79#define MCFGPIO_PORTF (MCF_IPSBAR + 0x00100005)
80#define MCFGPIO_PORTG (MCF_IPSBAR + 0x00100006)
81#define MCFGPIO_PORTH (MCF_IPSBAR + 0x00100007)
82#define MCFGPIO_PORTJ (MCF_IPSBAR + 0x00100008)
83#define MCFGPIO_PORTDD (MCF_IPSBAR + 0x00100009)
84#define MCFGPIO_PORTEH (MCF_IPSBAR + 0x0010000A)
85#define MCFGPIO_PORTEL (MCF_IPSBAR + 0x0010000B)
86#define MCFGPIO_PORTAS (MCF_IPSBAR + 0x0010000C)
87#define MCFGPIO_PORTQS (MCF_IPSBAR + 0x0010000D)
88#define MCFGPIO_PORTSD (MCF_IPSBAR + 0x0010000E)
89#define MCFGPIO_PORTTC (MCF_IPSBAR + 0x0010000F)
90#define MCFGPIO_PORTTD (MCF_IPSBAR + 0x00100010)
91#define MCFGPIO_PORTUA (MCF_IPSBAR + 0x00100011)
91 92
92#define MCFQSPI_CS0 147 93#define MCFGPIO_DDRA (MCF_IPSBAR + 0x00100014)
93#define MCFQSPI_CS1 148 94#define MCFGPIO_DDRB (MCF_IPSBAR + 0x00100015)
94#define MCFQSPI_CS2 149 95#define MCFGPIO_DDRC (MCF_IPSBAR + 0x00100016)
95#define MCFQSPI_CS3 150 96#define MCFGPIO_DDRD (MCF_IPSBAR + 0x00100017)
97#define MCFGPIO_DDRE (MCF_IPSBAR + 0x00100018)
98#define MCFGPIO_DDRF (MCF_IPSBAR + 0x00100019)
99#define MCFGPIO_DDRG (MCF_IPSBAR + 0x0010001A)
100#define MCFGPIO_DDRH (MCF_IPSBAR + 0x0010001B)
101#define MCFGPIO_DDRJ (MCF_IPSBAR + 0x0010001C)
102#define MCFGPIO_DDRDD (MCF_IPSBAR + 0x0010001D)
103#define MCFGPIO_DDREH (MCF_IPSBAR + 0x0010001E)
104#define MCFGPIO_DDREL (MCF_IPSBAR + 0x0010001F)
105#define MCFGPIO_DDRAS (MCF_IPSBAR + 0x00100020)
106#define MCFGPIO_DDRQS (MCF_IPSBAR + 0x00100021)
107#define MCFGPIO_DDRSD (MCF_IPSBAR + 0x00100022)
108#define MCFGPIO_DDRTC (MCF_IPSBAR + 0x00100023)
109#define MCFGPIO_DDRTD (MCF_IPSBAR + 0x00100024)
110#define MCFGPIO_DDRUA (MCF_IPSBAR + 0x00100025)
96 111
97/* 112#define MCFGPIO_PORTAP (MCF_IPSBAR + 0x00100028)
98 * GPIO registers 113#define MCFGPIO_PORTBP (MCF_IPSBAR + 0x00100029)
99 */ 114#define MCFGPIO_PORTCP (MCF_IPSBAR + 0x0010002A)
100#define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000) 115#define MCFGPIO_PORTDP (MCF_IPSBAR + 0x0010002B)
101#define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001) 116#define MCFGPIO_PORTEP (MCF_IPSBAR + 0x0010002C)
102#define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002) 117#define MCFGPIO_PORTFP (MCF_IPSBAR + 0x0010002D)
103#define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003) 118#define MCFGPIO_PORTGP (MCF_IPSBAR + 0x0010002E)
104#define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004) 119#define MCFGPIO_PORTHP (MCF_IPSBAR + 0x0010002F)
105#define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005) 120#define MCFGPIO_PORTJP (MCF_IPSBAR + 0x00100030)
106#define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006) 121#define MCFGPIO_PORTDDP (MCF_IPSBAR + 0x00100031)
107#define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007) 122#define MCFGPIO_PORTEHP (MCF_IPSBAR + 0x00100032)
108#define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008) 123#define MCFGPIO_PORTELP (MCF_IPSBAR + 0x00100033)
109#define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009) 124#define MCFGPIO_PORTASP (MCF_IPSBAR + 0x00100034)
110#define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A) 125#define MCFGPIO_PORTQSP (MCF_IPSBAR + 0x00100035)
111#define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B) 126#define MCFGPIO_PORTSDP (MCF_IPSBAR + 0x00100036)
112#define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C) 127#define MCFGPIO_PORTTCP (MCF_IPSBAR + 0x00100037)
113#define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D) 128#define MCFGPIO_PORTTDP (MCF_IPSBAR + 0x00100038)
114#define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E) 129#define MCFGPIO_PORTUAP (MCF_IPSBAR + 0x00100039)
115#define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F) 130
116#define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010) 131#define MCFGPIO_SETA (MCF_IPSBAR + 0x00100028)
117#define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011) 132#define MCFGPIO_SETB (MCF_IPSBAR + 0x00100029)
118 133#define MCFGPIO_SETC (MCF_IPSBAR + 0x0010002A)
119#define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014) 134#define MCFGPIO_SETD (MCF_IPSBAR + 0x0010002B)
120#define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015) 135#define MCFGPIO_SETE (MCF_IPSBAR + 0x0010002C)
121#define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016) 136#define MCFGPIO_SETF (MCF_IPSBAR + 0x0010002D)
122#define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017) 137#define MCFGPIO_SETG (MCF_IPSBAR + 0x0010002E)
123#define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018) 138#define MCFGPIO_SETH (MCF_IPSBAR + 0x0010002F)
124#define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019) 139#define MCFGPIO_SETJ (MCF_IPSBAR + 0x00100030)
125#define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A) 140#define MCFGPIO_SETDD (MCF_IPSBAR + 0x00100031)
126#define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B) 141#define MCFGPIO_SETEH (MCF_IPSBAR + 0x00100032)
127#define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C) 142#define MCFGPIO_SETEL (MCF_IPSBAR + 0x00100033)
128#define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D) 143#define MCFGPIO_SETAS (MCF_IPSBAR + 0x00100034)
129#define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E) 144#define MCFGPIO_SETQS (MCF_IPSBAR + 0x00100035)
130#define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F) 145#define MCFGPIO_SETSD (MCF_IPSBAR + 0x00100036)
131#define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020) 146#define MCFGPIO_SETTC (MCF_IPSBAR + 0x00100037)
132#define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021) 147#define MCFGPIO_SETTD (MCF_IPSBAR + 0x00100038)
133#define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022) 148#define MCFGPIO_SETUA (MCF_IPSBAR + 0x00100039)
134#define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023) 149
135#define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024) 150#define MCFGPIO_CLRA (MCF_IPSBAR + 0x0010003C)
136#define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025) 151#define MCFGPIO_CLRB (MCF_IPSBAR + 0x0010003D)
137 152#define MCFGPIO_CLRC (MCF_IPSBAR + 0x0010003E)
138#define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028) 153#define MCFGPIO_CLRD (MCF_IPSBAR + 0x0010003F)
139#define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029) 154#define MCFGPIO_CLRE (MCF_IPSBAR + 0x00100040)
140#define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A) 155#define MCFGPIO_CLRF (MCF_IPSBAR + 0x00100041)
141#define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B) 156#define MCFGPIO_CLRG (MCF_IPSBAR + 0x00100042)
142#define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C) 157#define MCFGPIO_CLRH (MCF_IPSBAR + 0x00100043)
143#define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D) 158#define MCFGPIO_CLRJ (MCF_IPSBAR + 0x00100044)
144#define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E) 159#define MCFGPIO_CLRDD (MCF_IPSBAR + 0x00100045)
145#define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F) 160#define MCFGPIO_CLREH (MCF_IPSBAR + 0x00100046)
146#define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030) 161#define MCFGPIO_CLREL (MCF_IPSBAR + 0x00100047)
147#define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031) 162#define MCFGPIO_CLRAS (MCF_IPSBAR + 0x00100048)
148#define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032) 163#define MCFGPIO_CLRQS (MCF_IPSBAR + 0x00100049)
149#define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033) 164#define MCFGPIO_CLRSD (MCF_IPSBAR + 0x0010004A)
150#define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034) 165#define MCFGPIO_CLRTC (MCF_IPSBAR + 0x0010004B)
151#define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035) 166#define MCFGPIO_CLRTD (MCF_IPSBAR + 0x0010004C)
152#define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036) 167#define MCFGPIO_CLRUA (MCF_IPSBAR + 0x0010004D)
153#define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037)
154#define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038)
155#define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039)
156
157#define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C)
158#define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D)
159#define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E)
160#define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F)
161#define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040)
162#define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041)
163#define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042)
164#define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043)
165#define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044)
166#define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045)
167#define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046)
168#define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047)
169#define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048)
170#define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049)
171#define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A)
172#define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B)
173#define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C)
174#define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D)
175 168
176#define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050) 169#define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050)
177#define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051) 170#define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051)
@@ -223,24 +216,73 @@
223 * definitions for generic gpio support 216 * definitions for generic gpio support
224 * 217 *
225 */ 218 */
226#define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */ 219#define MCFGPIO_PODR MCFGPIO_PORTA /* port output data */
227#define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */ 220#define MCFGPIO_PDDR MCFGPIO_DDRA /* port data direction */
228#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */ 221#define MCFGPIO_PPDR MCFGPIO_PORTAP /* port pin data */
229#define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */ 222#define MCFGPIO_SETR MCFGPIO_SETA /* set output */
230#define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */ 223#define MCFGPIO_CLRR MCFGPIO_CLRA /* clr output */
231 224
232#define MCFGPIO_IRQ_MAX 8 225#define MCFGPIO_IRQ_MAX 8
233#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 226#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
234#define MCFGPIO_PIN_MAX 180 227#define MCFGPIO_PIN_MAX 180
235 228
229
230/*
231 * Derek Cheung - 6 Feb 2005
232 * add I2C and QSPI register definition using Freescale's MCF5282
233 */
234/* set Port AS pin for I2C or UART */
235#define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056)
236
237/* Port UA Pin Assignment Register (8 Bit) */
238#define MCF5282_GPIO_PUAPAR 0x10005C
239
240/* Interrupt Mask Register Register Low */
241#define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
242/* Interrupt Control Register 7 */
243#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51)
244
245
236/* 246/*
237 * Reset Control Unit (relative to IPSBAR). 247 * Reset Control Unit (relative to IPSBAR).
238 */ 248 */
239#define MCF_RCR (MCF_IPSBAR + 0x110000) 249#define MCF_RCR 0x110000
240#define MCF_RSR (MCF_IPSBAR + 0x110001) 250#define MCF_RSR 0x110001
241 251
242#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 252#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
243#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 253#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
244 254
245/****************************************************************************/ 255/*********************************************************************
256*
257* Inter-IC (I2C) Module
258*
259*********************************************************************/
260/* Read/Write access macros for general use */
261#define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address
262#define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
263#define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
264#define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
265#define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
266
267/* Bit level definitions and macros */
268#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
269
270#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F))
271
272#define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable
273#define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable
274#define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode
275#define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode
276#define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
277#define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start
278
279#define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit
280#define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
281#define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy
282#define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost
283#define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write
284#define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt
285#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
286
287
246#endif /* m528xsim_h */ 288#endif /* m528xsim_h */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 5d0bb7ec31f..8f8609fcc9b 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -23,71 +23,71 @@
23/* 23/*
24 * Define the 5307 SIM register set addresses. 24 * Define the 5307 SIM register set addresses.
25 */ 25 */
26#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */ 26#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
27#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ 27#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
28#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ 28#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
29#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/ 29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
30#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */ 30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
31#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */ 31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
32#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */ 32#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
33#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ 33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
34#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */ 34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
35#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ 35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
36#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */ 36#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
37#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ 37#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
38#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ 38#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
39#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ 39#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
40#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ 40#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
41#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ 41#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
42#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ 42#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
43#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ 43#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
44#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ 44#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
45#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ 45#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
46#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ 46#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
47#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ 47#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
48#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ 48#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
49 49
50#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ 50#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
51#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ 51#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
52#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ 52#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
53#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ 53#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
54#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ 54#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
55#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ 55#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
56 56
57#ifdef CONFIG_OLDMASK 57#ifdef CONFIG_OLDMASK
58#define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */ 58#define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */
59#define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */ 59#define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */
60#define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */ 60#define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */
61#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ 61#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
62#define MCFSIM_CSMR3 (MCF_MBAR + 0xaa) /* CS 3 Mask reg */ 62#define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */
63#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ 63#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
64#define MCFSIM_CSMR4 (MCF_MBAR + 0xb6) /* CS 4 Mask reg */ 64#define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */
65#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ 65#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
66#define MCFSIM_CSMR5 (MCF_MBAR + 0xc2) /* CS 5 Mask reg */ 66#define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */
67#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ 67#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
68#define MCFSIM_CSMR6 (MCF_MBAR + 0xce) /* CS 6 Mask reg */ 68#define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */
69#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ 69#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
70#define MCFSIM_CSMR7 (MCF_MBAR + 0xda) /* CS 7 Mask reg */ 70#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */
71#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ 71#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
72#else 72#else
73#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ 73#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
74#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ 74#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
75#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ 75#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
76#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ 76#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
77#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ 77#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
78#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ 78#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
79#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ 79#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
80#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ 80#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
81#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ 81#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
82#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */ 82#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
83#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */ 83#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
84#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ 84#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
85#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */ 85#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
86#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */ 86#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
87#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ 87#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
88#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */ 88#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
89#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */ 89#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
90#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ 90#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
91#endif /* CONFIG_OLDMASK */ 91#endif /* CONFIG_OLDMASK */
92 92
93#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 93#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
@@ -117,19 +117,19 @@
117 * UART module. 117 * UART module.
118 */ 118 */
119#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) 119#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
120#define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */ 120#define MCFUART_BASE1 0x200 /* Base address of UART1 */
121#define MCFUART_BASE1 (MCF_MBAR + 0x1c0) /* Base address UART1 */ 121#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
122#else 122#else
123#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ 123#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
124#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ 124#define MCFUART_BASE2 0x200 /* Base address of UART2 */
125#endif 125#endif
126 126
127/* 127/*
128 * Generic GPIO support 128 * Generic GPIO support
129 */ 129 */
130#define MCFGPIO_PIN_MAX 16 130#define MCFGPIO_PIN_MAX 16
131#define MCFGPIO_IRQ_MAX -1 131#define MCFGPIO_IRQ_MAX -1
132#define MCFGPIO_IRQ_VECBASE -1 132#define MCFGPIO_IRQ_VECBASE -1
133 133
134 134
135/* Definition offset address for CS2-7 -- old mask 5307 */ 135/* Definition offset address for CS2-7 -- old mask 5307 */
@@ -167,17 +167,15 @@
167/* 167/*
168 * Defines for the IRQPAR Register 168 * Defines for the IRQPAR Register
169 */ 169 */
170#define IRQ5_LEVEL4 0x80 170#define IRQ5_LEVEL4 0x80
171#define IRQ3_LEVEL6 0x40 171#define IRQ3_LEVEL6 0x40
172#define IRQ1_LEVEL2 0x20 172#define IRQ1_LEVEL2 0x20
173 173
174/* 174/*
175 * Define system peripheral IRQ usage. 175 * Define system peripheral IRQ usage.
176 */ 176 */
177#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 177#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
178#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 178#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
179#define MCF_IRQ_UART0 73 /* UART0 */
180#define MCF_IRQ_UART1 74 /* UART1 */
181 179
182/****************************************************************************/ 180/****************************************************************************/
183#endif /* m5307sim_h */ 181#endif /* m5307sim_h */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 8668e47ced0..ba4cc784f57 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -15,26 +15,17 @@
15 15
16#include <asm/m53xxacr.h> 16#include <asm/m53xxacr.h>
17 17
18#define MCF_REG32(x) (*(volatile unsigned long *)(x))
19#define MCF_REG16(x) (*(volatile unsigned short *)(x))
20#define MCF_REG08(x) (*(volatile unsigned char *)(x))
21
18#define MCFINT_VECBASE 64 22#define MCFINT_VECBASE 64
19#define MCFINT_UART0 26 /* Interrupt number for UART0 */ 23#define MCFINT_UART0 26 /* Interrupt number for UART0 */
20#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 24#define MCFINT_UART1 27 /* Interrupt number for UART1 */
21#define MCFINT_UART2 28 /* Interrupt number for UART2 */ 25#define MCFINT_UART2 28 /* Interrupt number for UART2 */
22#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 26#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
23#define MCFINT_FECRX0 36 /* Interrupt number for FEC */
24#define MCFINT_FECTX0 40 /* Interrupt number for FEC */
25#define MCFINT_FECENTC0 42 /* Interrupt number for FEC */
26
27#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
28#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
29#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
30
31#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
32#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
33#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
34 27
35#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 28#define MCF_WTM_WCR MCF_REG16(0xFC098000)
36
37#define MCF_WTM_WCR 0xFC098000
38 29
39/* 30/*
40 * Define the 532x SIM register set addresses. 31 * Define the 532x SIM register set addresses.
@@ -78,9 +69,6 @@
78#define MCFINTC1_SIMR 0xFC04C01C 69#define MCFINTC1_SIMR 0xFC04C01C
79#define MCFINTC1_CIMR 0xFC04C01D 70#define MCFINTC1_CIMR 0xFC04C01D
80#define MCFINTC1_ICR0 0xFC04C040 71#define MCFINTC1_ICR0 0xFC04C040
81#define MCFINTC2_SIMR (0)
82#define MCFINTC2_CIMR (0)
83#define MCFINTC2_ICR0 (0)
84 72
85#define MCFSIM_ICR_TIMER1 (0xFC048040+32) 73#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
86#define MCFSIM_ICR_TIMER2 (0xFC048040+33) 74#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
@@ -94,25 +82,9 @@
94/* 82/*
95 * UART module. 83 * UART module.
96 */ 84 */
97#define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */ 85#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
98#define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */ 86#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
99#define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */ 87#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */
100
101/*
102 * FEC module.
103 */
104#define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
105#define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */
106
107/*
108 * QSPI module.
109 */
110#define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */
111#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
112
113#define MCFQSPI_CS0 84
114#define MCFQSPI_CS1 85
115#define MCFQSPI_CS2 86
116 88
117/* 89/*
118 * Timer module. 90 * Timer module.
@@ -134,19 +106,41 @@
134#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 106#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
135#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 107#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
136 108
109/*********************************************************************
110 *
111 * Inter-IC (I2C) Module
112 *
113 *********************************************************************/
114
115/* Read/Write access macros for general use */
116#define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address
117#define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider
118#define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control
119#define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status
120#define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O
121
122/* Bit level definitions and macros */
123#define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
124
125#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F))
126
127#define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable
128#define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable
129#define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode
130#define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode
131#define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
132#define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start
133
134#define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit
135#define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
136#define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy
137#define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost
138#define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write
139#define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt
140#define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge
141
142#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053)
137 143
138/*
139 * Power Management
140 */
141#define MCFPM_WCR 0xfc040013
142#define MCFPM_PPMSR0 0xfc04002c
143#define MCFPM_PPMCR0 0xfc04002d
144#define MCFPM_PPMSR1 0xfc04002e
145#define MCFPM_PPMCR1 0xfc04002f
146#define MCFPM_PPMHR0 0xfc040030
147#define MCFPM_PPMLR0 0xfc040034
148#define MCFPM_PPMHR1 0xfc040038
149#define MCFPM_LPCR 0xec090007
150 144
151/* 145/*
152 * The M5329EVB board needs a help getting its devices initialized 146 * The M5329EVB board needs a help getting its devices initialized
@@ -177,13 +171,13 @@
177 *********************************************************************/ 171 *********************************************************************/
178 172
179/* Register read/write macros */ 173/* Register read/write macros */
180#define MCF_CCM_CCR 0xFC0A0004 174#define MCF_CCM_CCR MCF_REG16(0xFC0A0004)
181#define MCF_CCM_RCON 0xFC0A0008 175#define MCF_CCM_RCON MCF_REG16(0xFC0A0008)
182#define MCF_CCM_CIR 0xFC0A000A 176#define MCF_CCM_CIR MCF_REG16(0xFC0A000A)
183#define MCF_CCM_MISCCR 0xFC0A0010 177#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010)
184#define MCF_CCM_CDR 0xFC0A0012 178#define MCF_CCM_CDR MCF_REG16(0xFC0A0012)
185#define MCF_CCM_UHCSR 0xFC0A0014 179#define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014)
186#define MCF_CCM_UOCSR 0xFC0A0016 180#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016)
187 181
188/* Bit definitions and macros for MCF_CCM_CCR */ 182/* Bit definitions and macros for MCF_CCM_CCR */
189#define MCF_CCM_CCR_RESERVED (0x0001) 183#define MCF_CCM_CCR_RESERVED (0x0001)
@@ -247,29 +241,104 @@
247 241
248/********************************************************************* 242/*********************************************************************
249 * 243 *
244 * DMA Timers (DTIM)
245 *
246 *********************************************************************/
247
248/* Register read/write macros */
249#define MCF_DTIM0_DTMR MCF_REG16(0xFC070000)
250#define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002)
251#define MCF_DTIM0_DTER MCF_REG08(0xFC070003)
252#define MCF_DTIM0_DTRR MCF_REG32(0xFC070004)
253#define MCF_DTIM0_DTCR MCF_REG32(0xFC070008)
254#define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C)
255#define MCF_DTIM1_DTMR MCF_REG16(0xFC074000)
256#define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002)
257#define MCF_DTIM1_DTER MCF_REG08(0xFC074003)
258#define MCF_DTIM1_DTRR MCF_REG32(0xFC074004)
259#define MCF_DTIM1_DTCR MCF_REG32(0xFC074008)
260#define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C)
261#define MCF_DTIM2_DTMR MCF_REG16(0xFC078000)
262#define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002)
263#define MCF_DTIM2_DTER MCF_REG08(0xFC078003)
264#define MCF_DTIM2_DTRR MCF_REG32(0xFC078004)
265#define MCF_DTIM2_DTCR MCF_REG32(0xFC078008)
266#define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C)
267#define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000)
268#define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002)
269#define MCF_DTIM3_DTER MCF_REG08(0xFC07C003)
270#define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004)
271#define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008)
272#define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C)
273#define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000))
274#define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000))
275#define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000))
276#define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000))
277#define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000))
278#define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000))
279
280/* Bit definitions and macros for MCF_DTIM_DTMR */
281#define MCF_DTIM_DTMR_RST (0x0001)
282#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1)
283#define MCF_DTIM_DTMR_FRR (0x0008)
284#define MCF_DTIM_DTMR_ORRI (0x0010)
285#define MCF_DTIM_DTMR_OM (0x0020)
286#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6)
287#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8)
288#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
289#define MCF_DTIM_DTMR_CE_FALL (0x0080)
290#define MCF_DTIM_DTMR_CE_RISE (0x0040)
291#define MCF_DTIM_DTMR_CE_NONE (0x0000)
292#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
293#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
294#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
295#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
296
297/* Bit definitions and macros for MCF_DTIM_DTXMR */
298#define MCF_DTIM_DTXMR_MODE16 (0x01)
299#define MCF_DTIM_DTXMR_DMAEN (0x80)
300
301/* Bit definitions and macros for MCF_DTIM_DTER */
302#define MCF_DTIM_DTER_CAP (0x01)
303#define MCF_DTIM_DTER_REF (0x02)
304
305/* Bit definitions and macros for MCF_DTIM_DTRR */
306#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
307
308/* Bit definitions and macros for MCF_DTIM_DTCR */
309#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
310
311/* Bit definitions and macros for MCF_DTIM_DTCN */
312#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
313
314/*********************************************************************
315 *
250 * FlexBus Chip Selects (FBCS) 316 * FlexBus Chip Selects (FBCS)
251 * 317 *
252 *********************************************************************/ 318 *********************************************************************/
253 319
254/* Register read/write macros */ 320/* Register read/write macros */
255#define MCF_FBCS0_CSAR 0xFC008000 321#define MCF_FBCS0_CSAR MCF_REG32(0xFC008000)
256#define MCF_FBCS0_CSMR 0xFC008004 322#define MCF_FBCS0_CSMR MCF_REG32(0xFC008004)
257#define MCF_FBCS0_CSCR 0xFC008008 323#define MCF_FBCS0_CSCR MCF_REG32(0xFC008008)
258#define MCF_FBCS1_CSAR 0xFC00800C 324#define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C)
259#define MCF_FBCS1_CSMR 0xFC008010 325#define MCF_FBCS1_CSMR MCF_REG32(0xFC008010)
260#define MCF_FBCS1_CSCR 0xFC008014 326#define MCF_FBCS1_CSCR MCF_REG32(0xFC008014)
261#define MCF_FBCS2_CSAR 0xFC008018 327#define MCF_FBCS2_CSAR MCF_REG32(0xFC008018)
262#define MCF_FBCS2_CSMR 0xFC00801C 328#define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C)
263#define MCF_FBCS2_CSCR 0xFC008020 329#define MCF_FBCS2_CSCR MCF_REG32(0xFC008020)
264#define MCF_FBCS3_CSAR 0xFC008024 330#define MCF_FBCS3_CSAR MCF_REG32(0xFC008024)
265#define MCF_FBCS3_CSMR 0xFC008028 331#define MCF_FBCS3_CSMR MCF_REG32(0xFC008028)
266#define MCF_FBCS3_CSCR 0xFC00802C 332#define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C)
267#define MCF_FBCS4_CSAR 0xFC008030 333#define MCF_FBCS4_CSAR MCF_REG32(0xFC008030)
268#define MCF_FBCS4_CSMR 0xFC008034 334#define MCF_FBCS4_CSMR MCF_REG32(0xFC008034)
269#define MCF_FBCS4_CSCR 0xFC008038 335#define MCF_FBCS4_CSCR MCF_REG32(0xFC008038)
270#define MCF_FBCS5_CSAR 0xFC00803C 336#define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C)
271#define MCF_FBCS5_CSMR 0xFC008040 337#define MCF_FBCS5_CSMR MCF_REG32(0xFC008040)
272#define MCF_FBCS5_CSCR 0xFC008044 338#define MCF_FBCS5_CSCR MCF_REG32(0xFC008044)
339#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C))
340#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C))
341#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C))
273 342
274/* Bit definitions and macros for MCF_FBCS_CSAR */ 343/* Bit definitions and macros for MCF_FBCS_CSAR */
275#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) 344#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
@@ -386,32 +455,32 @@
386#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B) 455#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
387#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C) 456#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C)
388#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D) 457#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D)
389#define MCFGPIO_PAR_FEC (0xFC0A4050) 458#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050)
390#define MCFGPIO_PAR_PWM (0xFC0A4051) 459#define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051)
391#define MCFGPIO_PAR_BUSCTL (0xFC0A4052) 460#define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052)
392#define MCFGPIO_PAR_FECI2C (0xFC0A4053) 461#define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053)
393#define MCFGPIO_PAR_BE (0xFC0A4054) 462#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054)
394#define MCFGPIO_PAR_CS (0xFC0A4055) 463#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055)
395#define MCFGPIO_PAR_SSI (0xFC0A4056) 464#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056)
396#define MCFGPIO_PAR_UART (0xFC0A4058) 465#define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058)
397#define MCFGPIO_PAR_QSPI (0xFC0A405A) 466#define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A)
398#define MCFGPIO_PAR_TIMER (0xFC0A405C) 467#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C)
399#define MCFGPIO_PAR_LCDDATA (0xFC0A405D) 468#define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D)
400#define MCFGPIO_PAR_LCDCTL (0xFC0A405E) 469#define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E)
401#define MCFGPIO_PAR_IRQ (0xFC0A4060) 470#define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060)
402#define MCFGPIO_MSCR_FLEXBUS (0xFC0A4064) 471#define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064)
403#define MCFGPIO_MSCR_SDRAM (0xFC0A4065) 472#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065)
404#define MCFGPIO_DSCR_I2C (0xFC0A4068) 473#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068)
405#define MCFGPIO_DSCR_PWM (0xFC0A4069) 474#define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069)
406#define MCFGPIO_DSCR_FEC (0xFC0A406A) 475#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A)
407#define MCFGPIO_DSCR_UART (0xFC0A406B) 476#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B)
408#define MCFGPIO_DSCR_QSPI (0xFC0A406C) 477#define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C)
409#define MCFGPIO_DSCR_TIMER (0xFC0A406D) 478#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D)
410#define MCFGPIO_DSCR_SSI (0xFC0A406E) 479#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E)
411#define MCFGPIO_DSCR_LCD (0xFC0A406F) 480#define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F)
412#define MCFGPIO_DSCR_DEBUG (0xFC0A4070) 481#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070)
413#define MCFGPIO_DSCR_CLKRST (0xFC0A4071) 482#define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071)
414#define MCFGPIO_DSCR_IRQ (0xFC0A4072) 483#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072)
415 484
416/* Bit definitions and macros for MCF_GPIO_PODR_FECH */ 485/* Bit definitions and macros for MCF_GPIO_PODR_FECH */
417#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01) 486#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
@@ -1100,6 +1169,709 @@
1100#define MCFGPIO_IRQ_MAX 8 1169#define MCFGPIO_IRQ_MAX 8
1101#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 1170#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
1102 1171
1172
1173/*********************************************************************
1174 *
1175 * Interrupt Controller (INTC)
1176 *
1177 *********************************************************************/
1178
1179/* Register read/write macros */
1180#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
1181#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
1182#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
1183#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
1184#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
1185#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
1186#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
1187#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
1188#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
1189#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
1190#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
1191#define MCF_INTC0_ICR0 MCF_REG08(0xFC048040)
1192#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
1193#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
1194#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
1195#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
1196#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
1197#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
1198#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
1199#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
1200#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
1201#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
1202#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
1203#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
1204#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
1205#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
1206#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
1207#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
1208#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
1209#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
1210#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
1211#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
1212#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
1213#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
1214#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
1215#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
1216#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
1217#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
1218#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
1219#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
1220#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
1221#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
1222#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
1223#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
1224#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
1225#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
1226#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
1227#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
1228#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
1229#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
1230#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
1231#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
1232#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
1233#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
1234#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
1235#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
1236#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
1237#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
1238#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
1239#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
1240#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
1241#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
1242#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
1243#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
1244#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
1245#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
1246#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
1247#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
1248#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
1249#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
1250#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
1251#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
1252#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
1253#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
1254#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
1255#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001))
1256#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
1257#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
1258#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
1259#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
1260#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
1261#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
1262#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
1263#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
1264#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004))
1265#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
1266#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
1267#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
1268#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
1269#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
1270#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
1271#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
1272#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
1273#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
1274#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
1275#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
1276#define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040)
1277#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
1278#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
1279#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
1280#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
1281#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
1282#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
1283#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
1284#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
1285#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
1286#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
1287#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
1288#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
1289#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
1290#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
1291#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
1292#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
1293#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
1294#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
1295#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
1296#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
1297#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
1298#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
1299#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
1300#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
1301#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
1302#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
1303#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
1304#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
1305#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
1306#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
1307#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
1308#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
1309#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
1310#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
1311#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
1312#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
1313#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
1314#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
1315#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
1316#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
1317#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
1318#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
1319#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
1320#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
1321#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
1322#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
1323#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
1324#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
1325#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
1326#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
1327#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
1328#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
1329#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
1330#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
1331#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
1332#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
1333#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
1334#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
1335#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
1336#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
1337#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
1338#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
1339#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
1340#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001))
1341#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
1342#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
1343#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
1344#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
1345#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
1346#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
1347#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8)
1348#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
1349#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004))
1350#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
1351#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
1352#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
1353#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
1354#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
1355#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
1356#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
1357#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
1358#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
1359#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
1360#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
1361#define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000))
1362#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
1363#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
1364#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
1365#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
1366#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
1367#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
1368#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
1369#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
1370#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
1371#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
1372#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
1373#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
1374#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
1375#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
1376#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
1377#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
1378#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
1379#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
1380#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
1381#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
1382#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
1383#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
1384#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
1385#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
1386#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
1387#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
1388#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
1389#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
1390#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
1391#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
1392#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
1393#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
1394#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
1395#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
1396#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
1397#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
1398#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
1399#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
1400#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
1401#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
1402#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
1403#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
1404#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
1405#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
1406#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
1407#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
1408#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
1409#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
1410#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
1411#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
1412#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
1413#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
1414#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
1415#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
1416#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
1417#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
1418#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
1419#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
1420#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
1421#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
1422#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
1423#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
1424#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
1425#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
1426#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
1427#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
1428#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
1429#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
1430#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
1431#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
1432#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
1433
1434/* Bit definitions and macros for MCF_INTC_IPRH */
1435#define MCF_INTC_IPRH_INT32 (0x00000001)
1436#define MCF_INTC_IPRH_INT33 (0x00000002)
1437#define MCF_INTC_IPRH_INT34 (0x00000004)
1438#define MCF_INTC_IPRH_INT35 (0x00000008)
1439#define MCF_INTC_IPRH_INT36 (0x00000010)
1440#define MCF_INTC_IPRH_INT37 (0x00000020)
1441#define MCF_INTC_IPRH_INT38 (0x00000040)
1442#define MCF_INTC_IPRH_INT39 (0x00000080)
1443#define MCF_INTC_IPRH_INT40 (0x00000100)
1444#define MCF_INTC_IPRH_INT41 (0x00000200)
1445#define MCF_INTC_IPRH_INT42 (0x00000400)
1446#define MCF_INTC_IPRH_INT43 (0x00000800)
1447#define MCF_INTC_IPRH_INT44 (0x00001000)
1448#define MCF_INTC_IPRH_INT45 (0x00002000)
1449#define MCF_INTC_IPRH_INT46 (0x00004000)
1450#define MCF_INTC_IPRH_INT47 (0x00008000)
1451#define MCF_INTC_IPRH_INT48 (0x00010000)
1452#define MCF_INTC_IPRH_INT49 (0x00020000)
1453#define MCF_INTC_IPRH_INT50 (0x00040000)
1454#define MCF_INTC_IPRH_INT51 (0x00080000)
1455#define MCF_INTC_IPRH_INT52 (0x00100000)
1456#define MCF_INTC_IPRH_INT53 (0x00200000)
1457#define MCF_INTC_IPRH_INT54 (0x00400000)
1458#define MCF_INTC_IPRH_INT55 (0x00800000)
1459#define MCF_INTC_IPRH_INT56 (0x01000000)
1460#define MCF_INTC_IPRH_INT57 (0x02000000)
1461#define MCF_INTC_IPRH_INT58 (0x04000000)
1462#define MCF_INTC_IPRH_INT59 (0x08000000)
1463#define MCF_INTC_IPRH_INT60 (0x10000000)
1464#define MCF_INTC_IPRH_INT61 (0x20000000)
1465#define MCF_INTC_IPRH_INT62 (0x40000000)
1466#define MCF_INTC_IPRH_INT63 (0x80000000)
1467
1468/* Bit definitions and macros for MCF_INTC_IPRL */
1469#define MCF_INTC_IPRL_INT0 (0x00000001)
1470#define MCF_INTC_IPRL_INT1 (0x00000002)
1471#define MCF_INTC_IPRL_INT2 (0x00000004)
1472#define MCF_INTC_IPRL_INT3 (0x00000008)
1473#define MCF_INTC_IPRL_INT4 (0x00000010)
1474#define MCF_INTC_IPRL_INT5 (0x00000020)
1475#define MCF_INTC_IPRL_INT6 (0x00000040)
1476#define MCF_INTC_IPRL_INT7 (0x00000080)
1477#define MCF_INTC_IPRL_INT8 (0x00000100)
1478#define MCF_INTC_IPRL_INT9 (0x00000200)
1479#define MCF_INTC_IPRL_INT10 (0x00000400)
1480#define MCF_INTC_IPRL_INT11 (0x00000800)
1481#define MCF_INTC_IPRL_INT12 (0x00001000)
1482#define MCF_INTC_IPRL_INT13 (0x00002000)
1483#define MCF_INTC_IPRL_INT14 (0x00004000)
1484#define MCF_INTC_IPRL_INT15 (0x00008000)
1485#define MCF_INTC_IPRL_INT16 (0x00010000)
1486#define MCF_INTC_IPRL_INT17 (0x00020000)
1487#define MCF_INTC_IPRL_INT18 (0x00040000)
1488#define MCF_INTC_IPRL_INT19 (0x00080000)
1489#define MCF_INTC_IPRL_INT20 (0x00100000)
1490#define MCF_INTC_IPRL_INT21 (0x00200000)
1491#define MCF_INTC_IPRL_INT22 (0x00400000)
1492#define MCF_INTC_IPRL_INT23 (0x00800000)
1493#define MCF_INTC_IPRL_INT24 (0x01000000)
1494#define MCF_INTC_IPRL_INT25 (0x02000000)
1495#define MCF_INTC_IPRL_INT26 (0x04000000)
1496#define MCF_INTC_IPRL_INT27 (0x08000000)
1497#define MCF_INTC_IPRL_INT28 (0x10000000)
1498#define MCF_INTC_IPRL_INT29 (0x20000000)
1499#define MCF_INTC_IPRL_INT30 (0x40000000)
1500#define MCF_INTC_IPRL_INT31 (0x80000000)
1501
1502/* Bit definitions and macros for MCF_INTC_IMRH */
1503#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
1504#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
1505#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
1506#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
1507#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
1508#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
1509#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
1510#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
1511#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
1512#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
1513#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
1514#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
1515#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
1516#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
1517#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
1518#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
1519#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
1520#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
1521#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
1522#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
1523#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
1524#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
1525#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
1526#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
1527#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
1528#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
1529#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
1530#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
1531#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
1532#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
1533#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
1534#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
1535
1536/* Bit definitions and macros for MCF_INTC_IMRL */
1537#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
1538#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
1539#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
1540#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
1541#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
1542#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
1543#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
1544#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
1545#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
1546#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
1547#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
1548#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
1549#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
1550#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
1551#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
1552#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
1553#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
1554#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
1555#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
1556#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
1557#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
1558#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
1559#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
1560#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
1561#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
1562#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
1563#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
1564#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
1565#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
1566#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
1567#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
1568#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
1569
1570/* Bit definitions and macros for MCF_INTC_INTFRCH */
1571#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
1572#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
1573#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
1574#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
1575#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
1576#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
1577#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
1578#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
1579#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
1580#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
1581#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
1582#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
1583#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
1584#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
1585#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
1586#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
1587#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
1588#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
1589#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
1590#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
1591#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
1592#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
1593#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
1594#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
1595#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
1596#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
1597#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
1598#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
1599#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
1600#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
1601#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
1602#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
1603
1604/* Bit definitions and macros for MCF_INTC_INTFRCL */
1605#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
1606#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
1607#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
1608#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
1609#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
1610#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
1611#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
1612#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
1613#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
1614#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
1615#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
1616#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
1617#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
1618#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
1619#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
1620#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
1621#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
1622#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
1623#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
1624#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
1625#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
1626#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
1627#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
1628#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
1629#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
1630#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
1631#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
1632#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
1633#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
1634#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
1635#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
1636#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
1637
1638/* Bit definitions and macros for MCF_INTC_ICONFIG */
1639#define MCF_INTC_ICONFIG_EMASK (0x0020)
1640#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
1641#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
1642#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
1643#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
1644#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
1645#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
1646#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
1647
1648/* Bit definitions and macros for MCF_INTC_SIMR */
1649#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0)
1650
1651/* Bit definitions and macros for MCF_INTC_CIMR */
1652#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0)
1653
1654/* Bit definitions and macros for MCF_INTC_CLMASK */
1655#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0)
1656
1657/* Bit definitions and macros for MCF_INTC_SLMASK */
1658#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0)
1659
1660/* Bit definitions and macros for MCF_INTC_ICR */
1661#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0)
1662
1663/* Bit definitions and macros for MCF_INTC_SWIACK */
1664#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
1665
1666/* Bit definitions and macros for MCF_INTC_LIACK */
1667#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
1668
1669/********************************************************************/
1670/*********************************************************************
1671*
1672* LCD Controller (LCDC)
1673*
1674*********************************************************************/
1675
1676/* Register read/write macros */
1677#define MCF_LCDC_LSSAR MCF_REG32(0xFC0AC000)
1678#define MCF_LCDC_LSR MCF_REG32(0xFC0AC004)
1679#define MCF_LCDC_LVPWR MCF_REG32(0xFC0AC008)
1680#define MCF_LCDC_LCPR MCF_REG32(0xFC0AC00C)
1681#define MCF_LCDC_LCWHBR MCF_REG32(0xFC0AC010)
1682#define MCF_LCDC_LCCMR MCF_REG32(0xFC0AC014)
1683#define MCF_LCDC_LPCR MCF_REG32(0xFC0AC018)
1684#define MCF_LCDC_LHCR MCF_REG32(0xFC0AC01C)
1685#define MCF_LCDC_LVCR MCF_REG32(0xFC0AC020)
1686#define MCF_LCDC_LPOR MCF_REG32(0xFC0AC024)
1687#define MCF_LCDC_LSCR MCF_REG32(0xFC0AC028)
1688#define MCF_LCDC_LPCCR MCF_REG32(0xFC0AC02C)
1689#define MCF_LCDC_LDCR MCF_REG32(0xFC0AC030)
1690#define MCF_LCDC_LRMCR MCF_REG32(0xFC0AC034)
1691#define MCF_LCDC_LICR MCF_REG32(0xFC0AC038)
1692#define MCF_LCDC_LIER MCF_REG32(0xFC0AC03C)
1693#define MCF_LCDC_LISR MCF_REG32(0xFC0AC040)
1694#define MCF_LCDC_LGWSAR MCF_REG32(0xFC0AC050)
1695#define MCF_LCDC_LGWSR MCF_REG32(0xFC0AC054)
1696#define MCF_LCDC_LGWVPWR MCF_REG32(0xFC0AC058)
1697#define MCF_LCDC_LGWPOR MCF_REG32(0xFC0AC05C)
1698#define MCF_LCDC_LGWPR MCF_REG32(0xFC0AC060)
1699#define MCF_LCDC_LGWCR MCF_REG32(0xFC0AC064)
1700#define MCF_LCDC_LGWDCR MCF_REG32(0xFC0AC068)
1701#define MCF_LCDC_BPLUT_BASE MCF_REG32(0xFC0AC800)
1702#define MCF_LCDC_GWLUT_BASE MCF_REG32(0xFC0ACC00)
1703
1704/* Bit definitions and macros for MCF_LCDC_LSSAR */
1705#define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
1706
1707/* Bit definitions and macros for MCF_LCDC_LSR */
1708#define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
1709#define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
1710
1711/* Bit definitions and macros for MCF_LCDC_LVPWR */
1712#define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
1713
1714/* Bit definitions and macros for MCF_LCDC_LCPR */
1715#define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
1716#define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
1717#define MCF_LCDC_LCPR_OP (0x10000000)
1718#define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
1719#define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000)
1720#define MCF_LCDC_LCPR_CC_OR (0x40000000)
1721#define MCF_LCDC_LCPR_CC_XOR (0x80000000)
1722#define MCF_LCDC_LCPR_CC_AND (0xC0000000)
1723#define MCF_LCDC_LCPR_OP_ON (0x10000000)
1724#define MCF_LCDC_LCPR_OP_OFF (0x00000000)
1725
1726/* Bit definitions and macros for MCF_LCDC_LCWHBR */
1727#define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
1728#define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
1729#define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
1730#define MCF_LCDC_LCWHBR_BK_EN (0x80000000)
1731#define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000)
1732#define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000)
1733
1734/* Bit definitions and macros for MCF_LCDC_LCCMR */
1735#define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
1736#define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
1737#define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
1738
1739/* Bit definitions and macros for MCF_LCDC_LPCR */
1740#define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
1741#define MCF_LCDC_LPCR_SHARP (0x00000040)
1742#define MCF_LCDC_LPCR_SCLKSEL (0x00000080)
1743#define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
1744#define MCF_LCDC_LPCR_ACDSEL (0x00008000)
1745#define MCF_LCDC_LPCR_REV_VS (0x00010000)
1746#define MCF_LCDC_LPCR_SWAP_SEL (0x00020000)
1747#define MCF_LCDC_LPCR_ENDSEL (0x00040000)
1748#define MCF_LCDC_LPCR_SCLKIDLE (0x00080000)
1749#define MCF_LCDC_LPCR_OEPOL (0x00100000)
1750#define MCF_LCDC_LPCR_CLKPOL (0x00200000)
1751#define MCF_LCDC_LPCR_LPPOL (0x00400000)
1752#define MCF_LCDC_LPCR_FLM (0x00800000)
1753#define MCF_LCDC_LPCR_PIXPOL (0x01000000)
1754#define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
1755#define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
1756#define MCF_LCDC_LPCR_COLOR (0x40000000)
1757#define MCF_LCDC_LPCR_TFT (0x80000000)
1758#define MCF_LCDC_LPCR_MODE_MONOCGROME (0x00000000)
1759#define MCF_LCDC_LPCR_MODE_CSTN (0x40000000)
1760#define MCF_LCDC_LPCR_MODE_TFT (0xC0000000)
1761#define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000)
1762#define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000)
1763#define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000)
1764#define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000)
1765#define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000)
1766#define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000)
1767#define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000)
1768#define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000)
1769#define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000)
1770#define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000)
1771#define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000)
1772
1773#define MCF_LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
1774
1775/* Bit definitions and macros for MCF_LCDC_LHCR */
1776#define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
1777#define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
1778#define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
1779
1780/* Bit definitions and macros for MCF_LCDC_LVCR */
1781#define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
1782#define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
1783#define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
1784
1785/* Bit definitions and macros for MCF_LCDC_LPOR */
1786#define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
1787
1788/* Bit definitions and macros for MCF_LCDC_LPCCR */
1789#define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
1790#define MCF_LCDC_LPCCR_CC_EN (0x00000100)
1791#define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
1792#define MCF_LCDC_LPCCR_LDMSK (0x00008000)
1793#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
1794#define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
1795#define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
1796#define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
1797
1798/* Bit definitions and macros for MCF_LCDC_LDCR */
1799#define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
1800#define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
1801#define MCF_LCDC_LDCR_BURST (0x80000000)
1802
1803/* Bit definitions and macros for MCF_LCDC_LRMCR */
1804#define MCF_LCDC_LRMCR_SEL_REF (0x00000001)
1805
1806/* Bit definitions and macros for MCF_LCDC_LICR */
1807#define MCF_LCDC_LICR_INTCON (0x00000001)
1808#define MCF_LCDC_LICR_INTSYN (0x00000004)
1809#define MCF_LCDC_LICR_GW_INT_CON (0x00000010)
1810
1811/* Bit definitions and macros for MCF_LCDC_LIER */
1812#define MCF_LCDC_LIER_BOF_EN (0x00000001)
1813#define MCF_LCDC_LIER_EOF_EN (0x00000002)
1814#define MCF_LCDC_LIER_ERR_RES_EN (0x00000004)
1815#define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008)
1816#define MCF_LCDC_LIER_GW_BOF_EN (0x00000010)
1817#define MCF_LCDC_LIER_GW_EOF_EN (0x00000020)
1818#define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040)
1819#define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
1820
1821/* Bit definitions and macros for MCF_LCDC_LISR */
1822#define MCF_LCDC_LISR_BOF (0x00000001)
1823#define MCF_LCDC_LISR_EOF (0x00000002)
1824#define MCF_LCDC_LISR_ERR_RES (0x00000004)
1825#define MCF_LCDC_LISR_UDR_ERR (0x00000008)
1826#define MCF_LCDC_LISR_GW_BOF (0x00000010)
1827#define MCF_LCDC_LISR_GW_EOF (0x00000020)
1828#define MCF_LCDC_LISR_GW_ERR_RES (0x00000040)
1829#define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080)
1830
1831/* Bit definitions and macros for MCF_LCDC_LGWSAR */
1832#define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
1833
1834/* Bit definitions and macros for MCF_LCDC_LGWSR */
1835#define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
1836#define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
1837
1838/* Bit definitions and macros for MCF_LCDC_LGWVPWR */
1839#define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
1840
1841/* Bit definitions and macros for MCF_LCDC_LGWPOR */
1842#define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
1843
1844/* Bit definitions and macros for MCF_LCDC_LGWPR */
1845#define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
1846#define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
1847
1848/* Bit definitions and macros for MCF_LCDC_LGWCR */
1849#define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
1850#define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
1851#define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
1852#define MCF_LCDC_LGWCR_GW_RVS (0x00200000)
1853#define MCF_LCDC_LGWCR_GWE (0x00400000)
1854#define MCF_LCDC_LGWCR_GWCKE (0x00800000)
1855#define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
1856
1857/* Bit definitions and macros for MCF_LCDC_LGWDCR */
1858#define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
1859#define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
1860#define MCF_LCDC_LGWDCR_GWBT (0x80000000)
1861
1862/* Bit definitions and macros for MCF_LCDC_LSCR */
1863#define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26)
1864#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16)
1865#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
1866#define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4)
1867#define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0)
1868
1869/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
1870#define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
1871
1872/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
1873#define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
1874
1103/********************************************************************* 1875/*********************************************************************
1104 * 1876 *
1105 * Phase Locked Loop (PLL) 1877 * Phase Locked Loop (PLL)
@@ -1107,10 +1879,10 @@
1107 *********************************************************************/ 1879 *********************************************************************/
1108 1880
1109/* Register read/write macros */ 1881/* Register read/write macros */
1110#define MCF_PLL_PODR 0xFC0C0000 1882#define MCF_PLL_PODR MCF_REG08(0xFC0C0000)
1111#define MCF_PLL_PLLCR 0xFC0C0004 1883#define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004)
1112#define MCF_PLL_PMDR 0xFC0C0008 1884#define MCF_PLL_PMDR MCF_REG08(0xFC0C0008)
1113#define MCF_PLL_PFDR 0xFC0C000C 1885#define MCF_PLL_PFDR MCF_REG08(0xFC0C000C)
1114 1886
1115/* Bit definitions and macros for MCF_PLL_PODR */ 1887/* Bit definitions and macros for MCF_PLL_PODR */
1116#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0) 1888#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
@@ -1133,15 +1905,15 @@
1133 *********************************************************************/ 1905 *********************************************************************/
1134 1906
1135/* Register read/write macros */ 1907/* Register read/write macros */
1136#define MCF_SCM_MPR 0xFC000000 1908#define MCF_SCM_MPR MCF_REG32(0xFC000000)
1137#define MCF_SCM_PACRA 0xFC000020 1909#define MCF_SCM_PACRA MCF_REG32(0xFC000020)
1138#define MCF_SCM_PACRB 0xFC000024 1910#define MCF_SCM_PACRB MCF_REG32(0xFC000024)
1139#define MCF_SCM_PACRC 0xFC000028 1911#define MCF_SCM_PACRC MCF_REG32(0xFC000028)
1140#define MCF_SCM_PACRD 0xFC00002C 1912#define MCF_SCM_PACRD MCF_REG32(0xFC00002C)
1141#define MCF_SCM_PACRE 0xFC000040 1913#define MCF_SCM_PACRE MCF_REG32(0xFC000040)
1142#define MCF_SCM_PACRF 0xFC000044 1914#define MCF_SCM_PACRF MCF_REG32(0xFC000044)
1143 1915
1144#define MCF_SCM_BCR 0xFC040024 1916#define MCF_SCM_BCR MCF_REG32(0xFC040024)
1145 1917
1146/********************************************************************* 1918/*********************************************************************
1147 * 1919 *
@@ -1150,16 +1922,17 @@
1150 *********************************************************************/ 1922 *********************************************************************/
1151 1923
1152/* Register read/write macros */ 1924/* Register read/write macros */
1153#define MCF_SDRAMC_SDMR 0xFC0B8000 1925#define MCF_SDRAMC_SDMR MCF_REG32(0xFC0B8000)
1154#define MCF_SDRAMC_SDCR 0xFC0B8004 1926#define MCF_SDRAMC_SDCR MCF_REG32(0xFC0B8004)
1155#define MCF_SDRAMC_SDCFG1 0xFC0B8008 1927#define MCF_SDRAMC_SDCFG1 MCF_REG32(0xFC0B8008)
1156#define MCF_SDRAMC_SDCFG2 0xFC0B800C 1928#define MCF_SDRAMC_SDCFG2 MCF_REG32(0xFC0B800C)
1157#define MCF_SDRAMC_LIMP_FIX 0xFC0B8080 1929#define MCF_SDRAMC_LIMP_FIX MCF_REG32(0xFC0B8080)
1158#define MCF_SDRAMC_SDDS 0xFC0B8100 1930#define MCF_SDRAMC_SDDS MCF_REG32(0xFC0B8100)
1159#define MCF_SDRAMC_SDCS0 0xFC0B8110 1931#define MCF_SDRAMC_SDCS0 MCF_REG32(0xFC0B8110)
1160#define MCF_SDRAMC_SDCS1 0xFC0B8114 1932#define MCF_SDRAMC_SDCS1 MCF_REG32(0xFC0B8114)
1161#define MCF_SDRAMC_SDCS2 0xFC0B8118 1933#define MCF_SDRAMC_SDCS2 MCF_REG32(0xFC0B8118)
1162#define MCF_SDRAMC_SDCS3 0xFC0B811C 1934#define MCF_SDRAMC_SDCS3 MCF_REG32(0xFC0B811C)
1935#define MCF_SDRAMC_SDCS(x) MCF_REG32(0xFC0B8110+((x)*0x004))
1163 1936
1164/* Bit definitions and macros for MCF_SDRAMC_SDMR */ 1937/* Bit definitions and macros for MCF_SDRAMC_SDMR */
1165#define MCF_SDRAMC_SDMR_CMD (0x00010000) 1938#define MCF_SDRAMC_SDMR_CMD (0x00010000)
@@ -1227,9 +2000,143 @@
1227#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) 2000#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
1228#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) 2001#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
1229 2002
2003/*********************************************************************
2004 *
2005 * FlexCAN module registers
2006 *
2007 *********************************************************************/
2008#define MCF_FLEXCAN_BASEADDR(x) (0xFC020000+(x)*0x0800)
2009#define MCF_FLEXCAN_CANMCR(x) MCF_REG32(0xFC020000+(x)*0x0800+0x00)
2010#define MCF_FLEXCAN_CANCTRL(x) MCF_REG32(0xFC020000+(x)*0x0800+0x04)
2011#define MCF_FLEXCAN_TIMER(x) MCF_REG32(0xFC020000+(x)*0x0800+0x08)
2012#define MCF_FLEXCAN_RXGMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x10)
2013#define MCF_FLEXCAN_RX14MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x14)
2014#define MCF_FLEXCAN_RX15MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x18)
2015#define MCF_FLEXCAN_ERRCNT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
2016#define MCF_FLEXCAN_ERRSTAT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x20)
2017#define MCF_FLEXCAN_IMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x28)
2018#define MCF_FLEXCAN_IFLAG(x) MCF_REG32(0xFC020000+(x)*0x0800+0x30)
2019
2020#define MCF_FLEXCAN_MB_CNT(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
2021#define MCF_FLEXCAN_MB_ID(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
2022#define MCF_FLEXCAN_MB_DB(x,y,z) MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
2023
1230/* 2024/*
1231 * Edge Port Module (EPORT) 2025 * FlexCAN Module Configuration Register
2026 */
2027#define CANMCR_MDIS (0x80000000)
2028#define CANMCR_FRZ (0x40000000)
2029#define CANMCR_HALT (0x10000000)
2030#define CANMCR_SOFTRST (0x02000000)
2031#define CANMCR_FRZACK (0x01000000)
2032#define CANMCR_SUPV (0x00800000)
2033#define CANMCR_MAXMB(x) ((x)&0x0F)
2034
2035/*
2036 * FlexCAN Control Register
2037 */
2038#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
2039#define CANCTRL_RJW(x) (((x)&0x03)<<22)
2040#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
2041#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
2042#define CANCTRL_BOFFMSK (0x00008000)
2043#define CANCTRL_ERRMSK (0x00004000)
2044#define CANCTRL_CLKSRC (0x00002000)
2045#define CANCTRL_LPB (0x00001000)
2046#define CANCTRL_SAMP (0x00000080)
2047#define CANCTRL_BOFFREC (0x00000040)
2048#define CANCTRL_TSYNC (0x00000020)
2049#define CANCTRL_LBUF (0x00000010)
2050#define CANCTRL_LOM (0x00000008)
2051#define CANCTRL_PROPSEG(x) ((x)&0x07)
2052
2053/*
2054 * FlexCAN Error Counter Register
2055 */
2056#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
2057#define ERRCNT_TXECTR(x) ((x)&0xFF)
2058
2059/*
2060 * FlexCAN Error and Status Register
2061 */
2062#define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
2063#define ERRSTAT_ACKERR (0x00002000)
2064#define ERRSTAT_CRCERR (0x00001000)
2065#define ERRSTAT_FRMERR (0x00000800)
2066#define ERRSTAT_STFERR (0x00000400)
2067#define ERRSTAT_TXWRN (0x00000200)
2068#define ERRSTAT_RXWRN (0x00000100)
2069#define ERRSTAT_IDLE (0x00000080)
2070#define ERRSTAT_TXRX (0x00000040)
2071#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
2072#define ERRSTAT_BOFFINT (0x00000004)
2073#define ERRSTAT_ERRINT (0x00000002)
2074
2075/*
2076 * Interrupt Mask Register
2077 */
2078#define IMASK_BUF15M (0x8000)
2079#define IMASK_BUF14M (0x4000)
2080#define IMASK_BUF13M (0x2000)
2081#define IMASK_BUF12M (0x1000)
2082#define IMASK_BUF11M (0x0800)
2083#define IMASK_BUF10M (0x0400)
2084#define IMASK_BUF9M (0x0200)
2085#define IMASK_BUF8M (0x0100)
2086#define IMASK_BUF7M (0x0080)
2087#define IMASK_BUF6M (0x0040)
2088#define IMASK_BUF5M (0x0020)
2089#define IMASK_BUF4M (0x0010)
2090#define IMASK_BUF3M (0x0008)
2091#define IMASK_BUF2M (0x0004)
2092#define IMASK_BUF1M (0x0002)
2093#define IMASK_BUF0M (0x0001)
2094#define IMASK_BUFnM(x) (0x1<<(x))
2095#define IMASK_BUFF_ENABLE_ALL (0x1111)
2096#define IMASK_BUFF_DISABLE_ALL (0x0000)
2097
2098/*
2099 * Interrupt Flag Register
2100 */
2101#define IFLAG_BUF15M (0x8000)
2102#define IFLAG_BUF14M (0x4000)
2103#define IFLAG_BUF13M (0x2000)
2104#define IFLAG_BUF12M (0x1000)
2105#define IFLAG_BUF11M (0x0800)
2106#define IFLAG_BUF10M (0x0400)
2107#define IFLAG_BUF9M (0x0200)
2108#define IFLAG_BUF8M (0x0100)
2109#define IFLAG_BUF7M (0x0080)
2110#define IFLAG_BUF6M (0x0040)
2111#define IFLAG_BUF5M (0x0020)
2112#define IFLAG_BUF4M (0x0010)
2113#define IFLAG_BUF3M (0x0008)
2114#define IFLAG_BUF2M (0x0004)
2115#define IFLAG_BUF1M (0x0002)
2116#define IFLAG_BUF0M (0x0001)
2117#define IFLAG_BUFF_SET_ALL (0xFFFF)
2118#define IFLAG_BUFF_CLEAR_ALL (0x0000)
2119#define IFLAG_BUFnM(x) (0x1<<(x))
2120
2121/*
2122 * Message Buffers
1232 */ 2123 */
2124#define MB_CNT_CODE(x) (((x)&0x0F)<<24)
2125#define MB_CNT_SRR (0x00400000)
2126#define MB_CNT_IDE (0x00200000)
2127#define MB_CNT_RTR (0x00100000)
2128#define MB_CNT_LENGTH(x) (((x)&0x0F)<<16)
2129#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF)
2130#define MB_ID_STD(x) (((x)&0x07FF)<<18)
2131#define MB_ID_EXT(x) ((x)&0x3FFFF)
2132
2133/*********************************************************************
2134 *
2135 * Edge Port Module (EPORT)
2136 *
2137 *********************************************************************/
2138
2139/* Register read/write macros */
1233#define MCFEPORT_EPPAR (0xFC094000) 2140#define MCFEPORT_EPPAR (0xFC094000)
1234#define MCFEPORT_EPDDR (0xFC094002) 2141#define MCFEPORT_EPDDR (0xFC094002)
1235#define MCFEPORT_EPIER (0xFC094003) 2142#define MCFEPORT_EPIER (0xFC094003)
@@ -1237,5 +2144,91 @@
1237#define MCFEPORT_EPPDR (0xFC094005) 2144#define MCFEPORT_EPPDR (0xFC094005)
1238#define MCFEPORT_EPFR (0xFC094006) 2145#define MCFEPORT_EPFR (0xFC094006)
1239 2146
2147/* Bit definitions and macros for MCF_EPORT_EPPAR */
2148#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
2149#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
2150#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
2151#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
2152#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
2153#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
2154#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
2155#define MCF_EPORT_EPPAR_LEVEL (0)
2156#define MCF_EPORT_EPPAR_RISING (1)
2157#define MCF_EPORT_EPPAR_FALLING (2)
2158#define MCF_EPORT_EPPAR_BOTH (3)
2159#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
2160#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
2161#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
2162#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
2163#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
2164#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
2165#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
2166#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
2167#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
2168#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
2169#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
2170#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
2171#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
2172#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
2173#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
2174#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
2175#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
2176#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
2177#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
2178#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
2179#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
2180#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
2181#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
2182#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
2183#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
2184#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
2185#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
2186#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
2187
2188/* Bit definitions and macros for MCF_EPORT_EPDDR */
2189#define MCF_EPORT_EPDDR_EPDD1 (0x02)
2190#define MCF_EPORT_EPDDR_EPDD2 (0x04)
2191#define MCF_EPORT_EPDDR_EPDD3 (0x08)
2192#define MCF_EPORT_EPDDR_EPDD4 (0x10)
2193#define MCF_EPORT_EPDDR_EPDD5 (0x20)
2194#define MCF_EPORT_EPDDR_EPDD6 (0x40)
2195#define MCF_EPORT_EPDDR_EPDD7 (0x80)
2196
2197/* Bit definitions and macros for MCF_EPORT_EPIER */
2198#define MCF_EPORT_EPIER_EPIE1 (0x02)
2199#define MCF_EPORT_EPIER_EPIE2 (0x04)
2200#define MCF_EPORT_EPIER_EPIE3 (0x08)
2201#define MCF_EPORT_EPIER_EPIE4 (0x10)
2202#define MCF_EPORT_EPIER_EPIE5 (0x20)
2203#define MCF_EPORT_EPIER_EPIE6 (0x40)
2204#define MCF_EPORT_EPIER_EPIE7 (0x80)
2205
2206/* Bit definitions and macros for MCF_EPORT_EPDR */
2207#define MCF_EPORT_EPDR_EPD1 (0x02)
2208#define MCF_EPORT_EPDR_EPD2 (0x04)
2209#define MCF_EPORT_EPDR_EPD3 (0x08)
2210#define MCF_EPORT_EPDR_EPD4 (0x10)
2211#define MCF_EPORT_EPDR_EPD5 (0x20)
2212#define MCF_EPORT_EPDR_EPD6 (0x40)
2213#define MCF_EPORT_EPDR_EPD7 (0x80)
2214
2215/* Bit definitions and macros for MCF_EPORT_EPPDR */
2216#define MCF_EPORT_EPPDR_EPPD1 (0x02)
2217#define MCF_EPORT_EPPDR_EPPD2 (0x04)
2218#define MCF_EPORT_EPPDR_EPPD3 (0x08)
2219#define MCF_EPORT_EPPDR_EPPD4 (0x10)
2220#define MCF_EPORT_EPPDR_EPPD5 (0x20)
2221#define MCF_EPORT_EPPDR_EPPD6 (0x40)
2222#define MCF_EPORT_EPPDR_EPPD7 (0x80)
2223
2224/* Bit definitions and macros for MCF_EPORT_EPFR */
2225#define MCF_EPORT_EPFR_EPF1 (0x02)
2226#define MCF_EPORT_EPFR_EPF2 (0x04)
2227#define MCF_EPORT_EPFR_EPF3 (0x08)
2228#define MCF_EPORT_EPFR_EPF4 (0x10)
2229#define MCF_EPORT_EPFR_EPF5 (0x20)
2230#define MCF_EPORT_EPFR_EPF6 (0x40)
2231#define MCF_EPORT_EPFR_EPF7 (0x80)
2232
1240/********************************************************************/ 2233/********************************************************************/
1241#endif /* m532xsim_h */ 2234#endif /* m532xsim_h */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index a7550bc5cd1..51e00b00b8a 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -23,55 +23,55 @@
23/* 23/*
24 * Define the 5407 SIM register set addresses. 24 * Define the 5407 SIM register set addresses.
25 */ 25 */
26#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ 26#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
27#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ 27#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
28#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ 28#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
29#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/ 29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
30#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */ 30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
31#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */ 31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
32#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */ 32#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
33#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ 33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
34#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ 34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
35#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ 35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
36#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */ 36#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
37#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ 37#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
38#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ 38#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
39#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ 39#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
40#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ 40#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
41#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ 41#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
42#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ 42#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
43#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ 43#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
44#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ 44#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
45#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ 45#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
46#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ 46#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
47#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ 47#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
48#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ 48#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
49 49
50#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ 50#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
51#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ 51#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
52#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ 52#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
53#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ 53#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
54#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ 54#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
55#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ 55#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
56 56
57#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ 57#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
58#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ 58#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
59#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ 59#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
60#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ 60#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
61#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ 61#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
62#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ 62#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
63#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ 63#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
64#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ 64#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
65#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ 65#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
66#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */ 66#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
67#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */ 67#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
68#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ 68#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
69#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */ 69#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
70#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */ 70#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
71#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ 71#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
72#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */ 72#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
73#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */ 73#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
74#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ 74#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
75 75
76#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 76#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
77#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ 77#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
@@ -85,8 +85,8 @@
85#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ 85#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
86#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ 86#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
87 87
88#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ 88#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
89#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ 89#define MCFUART_BASE2 0x200 /* Base address of UART2 */
90 90
91#define MCFSIM_PADDR (MCF_MBAR + 0x244) 91#define MCFSIM_PADDR (MCF_MBAR + 0x244)
92#define MCFSIM_PADAT (MCF_MBAR + 0x248) 92#define MCFSIM_PADAT (MCF_MBAR + 0x248)
@@ -102,9 +102,9 @@
102/* 102/*
103 * Generic GPIO support 103 * Generic GPIO support
104 */ 104 */
105#define MCFGPIO_PIN_MAX 16 105#define MCFGPIO_PIN_MAX 16
106#define MCFGPIO_IRQ_MAX -1 106#define MCFGPIO_IRQ_MAX -1
107#define MCFGPIO_IRQ_VECBASE -1 107#define MCFGPIO_IRQ_VECBASE -1
108 108
109/* 109/*
110 * Some symbol defines for the above... 110 * Some symbol defines for the above...
@@ -130,17 +130,15 @@
130/* 130/*
131 * Defines for the IRQPAR Register 131 * Defines for the IRQPAR Register
132 */ 132 */
133#define IRQ5_LEVEL4 0x80 133#define IRQ5_LEVEL4 0x80
134#define IRQ3_LEVEL6 0x40 134#define IRQ3_LEVEL6 0x40
135#define IRQ1_LEVEL2 0x20 135#define IRQ1_LEVEL2 0x20
136 136
137/* 137/*
138 * Define system peripheral IRQ usage. 138 * Define system peripheral IRQ usage.
139 */ 139 */
140#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 140#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
141#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 141#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
142#define MCF_IRQ_UART0 73 /* UART0 */
143#define MCF_IRQ_UART1 74 /* UART1 */
144 142
145/****************************************************************************/ 143/****************************************************************************/
146#endif /* m5407sim_h */ 144#endif /* m5407sim_h */
diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h
deleted file mode 100644
index cc798ab9524..00000000000
--- a/arch/m68k/include/asm/m5441xsim.h
+++ /dev/null
@@ -1,276 +0,0 @@
1/*
2 * m5441xsim.h -- Coldfire 5441x register definitions
3 *
4 * (C) Copyright 2012, Steven King <sfking@fdwdc.com>
5*/
6
7#ifndef m5441xsim_h
8#define m5441xsim_h
9
10#define CPU_NAME "COLDFIRE(m5441x)"
11#define CPU_INSTR_PER_JIFFY 2
12#define MCF_BUSCLK (MCF_CLK / 2)
13
14#include <asm/m54xxacr.h>
15
16/*
17 * Reset Controller Module.
18 */
19
20#define MCF_RCR 0xec090000
21#define MCF_RSR 0xec090001
22
23#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
24#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
25
26/*
27 * Interrupt Controller Modules.
28 */
29/* the 5441x have 3 interrupt controllers, each control 64 interrupts */
30#define MCFINT_VECBASE 64
31#define MCFINT0_VECBASE MCFINT_VECBASE
32#define MCFINT1_VECBASE (MCFINT0_VECBASE + 64)
33#define MCFINT2_VECBASE (MCFINT1_VECBASE + 64)
34
35/* interrupt controller 0 */
36#define MCFINTC0_SIMR 0xfc04801c
37#define MCFINTC0_CIMR 0xfc04801d
38#define MCFINTC0_ICR0 0xfc048040
39/* interrupt controller 1 */
40#define MCFINTC1_SIMR 0xfc04c01c
41#define MCFINTC1_CIMR 0xfc04c01d
42#define MCFINTC1_ICR0 0xfc04c040
43/* interrupt controller 2 */
44#define MCFINTC2_SIMR 0xfc05001c
45#define MCFINTC2_CIMR 0xfc05001d
46#define MCFINTC2_ICR0 0xfc050040
47
48/* on interrupt controller 0 */
49#define MCFINT0_EPORT0 1
50#define MCFINT0_UART0 26
51#define MCFINT0_UART1 27
52#define MCFINT0_UART2 28
53#define MCFINT0_UART3 29
54#define MCFINT0_I2C0 30
55#define MCFINT0_DSPI0 31
56
57#define MCFINT0_TIMER0 32
58#define MCFINT0_TIMER1 33
59#define MCFINT0_TIMER2 34
60#define MCFINT0_TIMER3 35
61
62#define MCFINT0_FECRX0 36
63#define MCFINT0_FECTX0 40
64#define MCFINT0_FECENTC0 42
65
66#define MCFINT0_FECRX1 49
67#define MCFINT0_FECTX1 53
68#define MCFINT0_FECENTC1 55
69
70/* on interrupt controller 1 */
71#define MCFINT1_UART4 48
72#define MCFINT1_UART5 49
73#define MCFINT1_UART6 50
74#define MCFINT1_UART7 51
75#define MCFINT1_UART8 52
76#define MCFINT1_UART9 53
77#define MCFINT1_DSPI1 54
78#define MCFINT1_DSPI2 55
79#define MCFINT1_DSPI3 56
80#define MCFINT1_I2C1 57
81#define MCFINT1_I2C2 58
82#define MCFINT1_I2C3 59
83#define MCFINT1_I2C4 60
84#define MCFINT1_I2C5 61
85
86/* on interrupt controller 2 */
87#define MCFINT2_PIT0 13
88#define MCFINT2_PIT1 14
89#define MCFINT2_PIT2 15
90#define MCFINT2_PIT3 16
91#define MCFINT2_RTC 26
92
93/*
94 * PIT timer module.
95 */
96#define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */
97#define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */
98#define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */
99#define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */
100
101
102#define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1)
103
104/*
105 * Power Management
106 */
107#define MCFPM_WCR 0xfc040013
108#define MCFPM_PPMSR0 0xfc04002c
109#define MCFPM_PPMCR0 0xfc04002d
110#define MCFPM_PPMSR1 0xfc04002e
111#define MCFPM_PPMCR1 0xfc04002f
112#define MCFPM_PPMHR0 0xfc040030
113#define MCFPM_PPMLR0 0xfc040034
114#define MCFPM_PPMHR1 0xfc040038
115#define MCFPM_PPMLR1 0xfc04003c
116#define MCFPM_LPCR 0xec090007
117/*
118 * UART module.
119 */
120#define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */
121#define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */
122#define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */
123#define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */
124#define MCFUART_BASE4 0xec060000 /* Base address of UART4 */
125#define MCFUART_BASE5 0xec064000 /* Base address of UART5 */
126#define MCFUART_BASE6 0xec068000 /* Base address of UART6 */
127#define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */
128#define MCFUART_BASE8 0xec070000 /* Base address of UART8 */
129#define MCFUART_BASE9 0xec074000 /* Base address of UART9 */
130
131#define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0)
132#define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1)
133#define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2)
134#define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3)
135#define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4)
136#define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5)
137#define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6)
138#define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7)
139#define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8)
140#define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9)
141/*
142 * FEC modules.
143 */
144#define MCFFEC_BASE0 0xfc0d4000
145#define MCFFEC_SIZE0 0x800
146#define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0)
147#define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0)
148#define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0)
149
150#define MCFFEC_BASE1 0xfc0d8000
151#define MCFFEC_SIZE1 0x800
152#define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1)
153#define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1)
154#define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1)
155/*
156 * I2C modules.
157 */
158#define MCFI2C_BASE0 0xfc058000
159#define MCFI2C_SIZE0 0x20
160#define MCFI2C_BASE1 0xfc038000
161#define MCFI2C_SIZE1 0x20
162#define MCFI2C_BASE2 0xec010000
163#define MCFI2C_SIZE2 0x20
164#define MCFI2C_BASE3 0xec014000
165#define MCFI2C_SIZE3 0x20
166#define MCFI2C_BASE4 0xec018000
167#define MCFI2C_SIZE4 0x20
168#define MCFI2C_BASE5 0xec01c000
169#define MCFI2C_SIZE5 0x20
170
171#define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0)
172#define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1)
173#define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2)
174#define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3)
175#define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4)
176#define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5)
177/*
178 * EPORT Module.
179 */
180#define MCFEPORT_EPPAR 0xfc090000
181#define MCFEPORT_EPIER 0xfc090003
182#define MCFEPORT_EPFR 0xfc090006
183/*
184 * RTC Module.
185 */
186#define MCFRTC_BASE 0xfc0a8000
187#define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000)
188#define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC)
189
190/*
191 * GPIO Module.
192 */
193#define MCFGPIO_PODR_A 0xec094000
194#define MCFGPIO_PODR_B 0xec094001
195#define MCFGPIO_PODR_C 0xec094002
196#define MCFGPIO_PODR_D 0xec094003
197#define MCFGPIO_PODR_E 0xec094004
198#define MCFGPIO_PODR_F 0xec094005
199#define MCFGPIO_PODR_G 0xec094006
200#define MCFGPIO_PODR_H 0xec094007
201#define MCFGPIO_PODR_I 0xec094008
202#define MCFGPIO_PODR_J 0xec094009
203#define MCFGPIO_PODR_K 0xec09400a
204
205#define MCFGPIO_PDDR_A 0xec09400c
206#define MCFGPIO_PDDR_B 0xec09400d
207#define MCFGPIO_PDDR_C 0xec09400e
208#define MCFGPIO_PDDR_D 0xec09400f
209#define MCFGPIO_PDDR_E 0xec094010
210#define MCFGPIO_PDDR_F 0xec094011
211#define MCFGPIO_PDDR_G 0xec094012
212#define MCFGPIO_PDDR_H 0xec094013
213#define MCFGPIO_PDDR_I 0xec094014
214#define MCFGPIO_PDDR_J 0xec094015
215#define MCFGPIO_PDDR_K 0xec094016
216
217#define MCFGPIO_PPDSDR_A 0xec094018
218#define MCFGPIO_PPDSDR_B 0xec094019
219#define MCFGPIO_PPDSDR_C 0xec09401a
220#define MCFGPIO_PPDSDR_D 0xec09401b
221#define MCFGPIO_PPDSDR_E 0xec09401c
222#define MCFGPIO_PPDSDR_F 0xec09401d
223#define MCFGPIO_PPDSDR_G 0xec09401e
224#define MCFGPIO_PPDSDR_H 0xec09401f
225#define MCFGPIO_PPDSDR_I 0xec094020
226#define MCFGPIO_PPDSDR_J 0xec094021
227#define MCFGPIO_PPDSDR_K 0xec094022
228
229#define MCFGPIO_PCLRR_A 0xec094024
230#define MCFGPIO_PCLRR_B 0xec094025
231#define MCFGPIO_PCLRR_C 0xec094026
232#define MCFGPIO_PCLRR_D 0xec094027
233#define MCFGPIO_PCLRR_E 0xec094028
234#define MCFGPIO_PCLRR_F 0xec094029
235#define MCFGPIO_PCLRR_G 0xec09402a
236#define MCFGPIO_PCLRR_H 0xec09402b
237#define MCFGPIO_PCLRR_I 0xec09402c
238#define MCFGPIO_PCLRR_J 0xec09402d
239#define MCFGPIO_PCLRR_K 0xec09402e
240
241#define MCFGPIO_PAR_FBCTL 0xec094048
242#define MCFGPIO_PAR_BE 0xec094049
243#define MCFGPIO_PAR_CS 0xec09404a
244#define MCFGPIO_PAR_CANI2C 0xec09404b
245#define MCFGPIO_PAR_IRQ0H 0xec09404c
246#define MCFGPIO_PAR_IRQ0L 0xec09404d
247#define MCFGPIO_PAR_DSPIOWH 0xec09404e
248#define MCFGPIO_PAR_DSPIOWL 0xec09404f
249#define MCFGPIO_PAR_TIMER 0xec094050
250#define MCFGPIO_PAR_UART2 0xec094051
251#define MCFGPIO_PAR_UART1 0xec094052
252#define MCFGPIO_PAR_UART0 0xec094053
253#define MCFGPIO_PAR_SDHCH 0xec094054
254#define MCFGPIO_PAR_SDHCL 0xec094055
255#define MCFGPIO_PAR_SIMP0H 0xec094056
256#define MCFGPIO_PAR_SIMP0L 0xec094057
257#define MCFGPIO_PAR_SSI0H 0xec094058
258#define MCFGPIO_PAR_SSI0L 0xec094059
259#define MCFGPIO_PAR_DEBUGH1 0xec09405a
260#define MCFGPIO_PAR_DEBUGH0 0xec09405b
261#define MCFGPIO_PAR_DEBUGl 0xec09405c
262#define MCFGPIO_PAR_FEC 0xec09405e
263
264/* generalization for generic gpio support */
265#define MCFGPIO_PODR MCFGPIO_PODR_A
266#define MCFGPIO_PDDR MCFGPIO_PDDR_A
267#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A
268#define MCFGPIO_SETR MCFGPIO_PPDSDR_A
269#define MCFGPIO_CLRR MCFGPIO_PCLRR_A
270
271#define MCFGPIO_IRQ_MIN 17
272#define MCFGPIO_IRQ_MAX 24
273#define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
274#define MCFGPIO_PIN_MAX 87
275
276#endif /* m5441xsim_h */
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 192bbfeabf7..16a1835f9b2 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -39,12 +39,8 @@
39#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ 39#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */
40#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ 40#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */
41#define ACR_CM 0x00000060 /* Cache mode mask */ 41#define ACR_CM 0x00000060 /* Cache mode mask */
42#define ACR_SP 0x00000008 /* Supervisor protect */
43#define ACR_WPROTECT 0x00000004 /* Write protect */ 42#define ACR_WPROTECT 0x00000004 /* Write protect */
44 43
45#define ACR_BA(x) ((x) & 0xff000000)
46#define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
47
48#if defined(CONFIG_M5407) 44#if defined(CONFIG_M5407)
49 45
50#define ICACHE_SIZE 0x4000 /* instruction - 16k */ 46#define ICACHE_SIZE 0x4000 /* instruction - 16k */
@@ -55,20 +51,11 @@
55#define ICACHE_SIZE 0x8000 /* instruction - 32k */ 51#define ICACHE_SIZE 0x8000 /* instruction - 32k */
56#define DCACHE_SIZE 0x8000 /* data - 32k */ 52#define DCACHE_SIZE 0x8000 /* data - 32k */
57 53
58#elif defined(CONFIG_M5441x)
59
60#define ICACHE_SIZE 0x2000 /* instruction - 8k */
61#define DCACHE_SIZE 0x2000 /* data - 8k */
62#endif 54#endif
63 55
64#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ 56#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
65#define CACHE_WAYS 4 /* 4 ways */ 57#define CACHE_WAYS 4 /* 4 ways */
66 58
67#define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS)
68#define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS)
69#define ICACHE_MAX_ADDR ICACHE_SET_MASK
70#define DCACHE_MAX_ADDR DCACHE_SET_MASK
71
72/* 59/*
73 * Version 4 cores have a true harvard style separate instruction 60 * Version 4 cores have a true harvard style separate instruction
74 * and data cache. Enable data and instruction caches, also enable write 61 * and data cache. Enable data and instruction caches, also enable write
@@ -86,27 +73,6 @@
86#else 73#else
87#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) 74#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
88#endif 75#endif
89#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
90
91#if defined(CONFIG_MMU)
92/*
93 * If running with the MMU enabled then we need to map the internal
94 * register region as non-cacheable. And then we map all our RAM as
95 * cacheable and supervisor access only.
96 */
97#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
98 ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
99#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
100 ACR_ENABLE+ACR_SUPER+ACR_SP)
101#define ACR2_MODE 0
102#define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
103 ACR_ENABLE+ACR_SUPER+ACR_SP)
104
105#else
106
107/*
108 * For the non-MMU enabled case we map all of RAM as cacheable.
109 */
110#if defined(CONFIG_CACHE_COPYBACK) 76#if defined(CONFIG_CACHE_COPYBACK)
111#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP) 77#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP)
112#else 78#else
@@ -114,6 +80,7 @@
114#endif 80#endif
115#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) 81#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
116 82
83#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
117#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) 84#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
118#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) 85#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA)
119#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) 86#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA)
@@ -127,5 +94,4 @@
127#define CACHE_PUSH 94#define CACHE_PUSH
128#endif 95#endif
129 96
130#endif /* CONFIG_MMU */
131#endif /* m54xxacr_h */ 97#endif /* m54xxacr_h */
diff --git a/arch/m68k/include/asm/m54xxgpt.h b/arch/m68k/include/asm/m54xxgpt.h
index 0b69cd1ed0e..df75dd87ae7 100644
--- a/arch/m68k/include/asm/m54xxgpt.h
+++ b/arch/m68k/include/asm/m54xxgpt.h
@@ -16,26 +16,26 @@
16*********************************************************************/ 16*********************************************************************/
17 17
18/* Register read/write macros */ 18/* Register read/write macros */
19#define MCF_GPT_GMS0 (MCF_MBAR + 0x000800) 19#define MCF_GPT_GMS0 0x000800
20#define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804) 20#define MCF_GPT_GCIR0 0x000804
21#define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808) 21#define MCF_GPT_GPWM0 0x000808
22#define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C) 22#define MCF_GPT_GSR0 0x00080C
23#define MCF_GPT_GMS1 (MCF_MBAR + 0x000810) 23#define MCF_GPT_GMS1 0x000810
24#define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814) 24#define MCF_GPT_GCIR1 0x000814
25#define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818) 25#define MCF_GPT_GPWM1 0x000818
26#define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C) 26#define MCF_GPT_GSR1 0x00081C
27#define MCF_GPT_GMS2 (MCF_MBAR + 0x000820) 27#define MCF_GPT_GMS2 0x000820
28#define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824) 28#define MCF_GPT_GCIR2 0x000824
29#define MCF_GPT_GPWM2 (MCF_MBAR + 0x000828) 29#define MCF_GPT_GPWM2 0x000828
30#define MCF_GPT_GSR2 (MCF_MBAR + 0x00082C) 30#define MCF_GPT_GSR2 0x00082C
31#define MCF_GPT_GMS3 (MCF_MBAR + 0x000830) 31#define MCF_GPT_GMS3 0x000830
32#define MCF_GPT_GCIR3 (MCF_MBAR + 0x000834) 32#define MCF_GPT_GCIR3 0x000834
33#define MCF_GPT_GPWM3 (MCF_MBAR + 0x000838) 33#define MCF_GPT_GPWM3 0x000838
34#define MCF_GPT_GSR3 (MCF_MBAR + 0x00083C) 34#define MCF_GPT_GSR3 0x00083C
35#define MCF_GPT_GMS(x) (MCF_MBAR + 0x000800 + ((x) * 0x010)) 35#define MCF_GPT_GMS(x) (0x000800+((x)*0x010))
36#define MCF_GPT_GCIR(x) (MCF_MBAR + 0x000804 + ((x) * 0x010)) 36#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010))
37#define MCF_GPT_GPWM(x) (MCF_MBAR + 0x000808 + ((x) * 0x010)) 37#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010))
38#define MCF_GPT_GSR(x) (MCF_MBAR + 0x00080C + ((x) * 0x010)) 38#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010))
39 39
40/* Bit definitions and macros for MCF_GPT_GMS */ 40/* Bit definitions and macros for MCF_GPT_GMS */
41#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) 41#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
diff --git a/arch/m68k/include/asm/m54xxpci.h b/arch/m68k/include/asm/m54xxpci.h
deleted file mode 100644
index 6fbf54f72f2..00000000000
--- a/arch/m68k/include/asm/m54xxpci.h
+++ /dev/null
@@ -1,138 +0,0 @@
1/****************************************************************************/
2
3/*
4 * m54xxpci.h -- ColdFire 547x and 548x PCI bus support
5 *
6 * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12
13/****************************************************************************/
14#ifndef M54XXPCI_H
15#define M54XXPCI_H
16/****************************************************************************/
17
18/*
19 * The core set of PCI support registers are mapped into the MBAR region.
20 */
21#define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
22#define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */
23#define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */
24#define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
25#define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
26#define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
27#define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
28#define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
29#define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
30#define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
31#define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */
32
33#define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */
34#define PCITBATR0 (CONFIG_MBAR + 0xb64) /* Target base translation 0 */
35#define PCITBATR1 (CONFIG_MBAR + 0xb68) /* Target base translation 1 */
36#define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */
37#define PCIIW0BTAR (CONFIG_MBAR + 0xb70) /* Initiator window 0 */
38#define PCIIW1BTAR (CONFIG_MBAR + 0xb74) /* Initiator window 1 */
39#define PCIIW2BTAR (CONFIG_MBAR + 0xb78) /* Initiator window 2 */
40#define PCIIWCR (CONFIG_MBAR + 0xb80) /* Initiator window config */
41#define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */
42#define PCIISR (CONFIG_MBAR + 0xb88) /* Initiator status */
43#define PCICAR (CONFIG_MBAR + 0xbf8) /* Configuration address */
44
45#define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
46#define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */
47#define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
48#define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */
49#define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */
50#define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */
51#define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */
52#define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */
53#define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
54#define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */
55#define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */
56#define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */
57#define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */
58#define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */
59
60#define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */
61#define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */
62#define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */
63#define PCIRER (CONFIG_MBAR + 0x848c) /* RX enables */
64#define PCIRNAR (CONFIG_MBAR + 0x8490) /* RX next address */
65#define PCIRDCR (CONFIG_MBAR + 0x8498) /* RX done counts */
66#define PCIRSR (CONFIG_MBAR + 0x849c) /* RX status */
67#define PCIRFDR (CONFIG_MBAR + 0x84c0) /* RX FIFO data */
68#define PCIRFSR (CONFIG_MBAR + 0x84c4) /* RX FIFO status */
69#define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */
70#define PCIRFAR (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */
71#define PCIRFRPR (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */
72#define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */
73
74#define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
75#define PASR (COFNIG_MBAR + 0xc04) /* PCI arbiter status */
76
77/*
78 * Definitions for the Global status and control register.
79 */
80#define PCIGSCR_PE 0x20000000 /* Parity error detected */
81#define PCIGSCR_SE 0x10000000 /* System error detected */
82#define PCIGSCR_XCLKBIN 0x07000000 /* XLB2CLKIN mask */
83#define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */
84#define PCIGSCR_SEE 0x00001000 /* System error intr enable */
85#define PCIGSCR_RESET 0x00000001 /* Reset bit */
86
87/*
88 * Bit definitions for the PCICAR configuration address register.
89 */
90#define PCICAR_E 0x80000000 /* Enable config space */
91#define PCICAR_BUSN 16 /* Move bus bits */
92#define PCICAR_DEVFNN 8 /* Move devfn bits */
93#define PCICAR_DWORDN 0 /* Move dword bits */
94
95/*
96 * The initiator windows hold the memory and IO mapping information.
97 * This macro creates the register values from the desired addresses.
98 */
99#define WXBTAR(hostaddr, pciaddr, size) \
100 (((hostaddr) & 0xff000000) | \
101 ((((size) - 1) & 0xff000000) >> 8) | \
102 (((pciaddr) & 0xff000000) >> 16))
103
104#define PCIIWCR_W0_MEM 0x00000000 /* Window 0 is memory */
105#define PCIIWCR_W0_IO 0x08000000 /* Window 0 is IO */
106#define PCIIWCR_W0_MRD 0x00000000 /* Window 0 memory read */
107#define PCIIWCR_W0_MRDL 0x02000000 /* Window 0 memory read line */
108#define PCIIWCR_W0_MRDM 0x04000000 /* Window 0 memory read mult */
109#define PCIIWCR_W0_E 0x01000000 /* Window 0 enable */
110
111#define PCIIWCR_W1_MEM 0x00000000 /* Window 0 is memory */
112#define PCIIWCR_W1_IO 0x00080000 /* Window 0 is IO */
113#define PCIIWCR_W1_MRD 0x00000000 /* Window 0 memory read */
114#define PCIIWCR_W1_MRDL 0x00020000 /* Window 0 memory read line */
115#define PCIIWCR_W1_MRDM 0x00040000 /* Window 0 memory read mult */
116#define PCIIWCR_W1_E 0x00010000 /* Window 0 enable */
117
118/*
119 * Bit definitions for the PCIBATR registers.
120 */
121#define PCITBATR0_E 0x00000001 /* Enable window 0 */
122#define PCITBATR1_E 0x00000001 /* Enable window 1 */
123
124/*
125 * PCI arbiter support definitions and macros.
126 */
127#define PACR_INTMPRI 0x00000001
128#define PACR_EXTMPRI(x) (((x) & 0x1f) << 1)
129#define PACR_INTMINTE 0x00010000
130#define PACR_EXTMINTE(x) (((x) & 0x1f) << 17)
131#define PACR_PKMD 0x40000000
132#define PACR_DS 0x80000000
133
134#define PCICR1_CL(x) ((x) & 0xf) /* Cacheline size field */
135#define PCICR1_LT(x) (((x) & 0xff) << 8) /* Latency timer field */
136
137/****************************************************************************/
138#endif /* M54XXPCI_H */
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index d3bd8388742..1ed8bfb0277 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -31,26 +31,16 @@
31/* 31/*
32 * UART module. 32 * UART module.
33 */ 33 */
34#define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */ 34#define MCFUART_BASE1 0x8600 /* Base address of UART1 */
35#define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */ 35#define MCFUART_BASE2 0x8700 /* Base address of UART2 */
36#define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */ 36#define MCFUART_BASE3 0x8800 /* Base address of UART3 */
37#define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */ 37#define MCFUART_BASE4 0x8900 /* Base address of UART4 */
38 38
39/* 39/*
40 * Define system peripheral IRQ usage. 40 * Define system peripheral IRQ usage.
41 */ 41 */
42#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */ 42#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
43#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */ 43#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */
44#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
45#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
46#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
47#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
48
49/*
50 * Slice Timer support.
51 */
52#define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */
53#define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
54 44
55/* 45/*
56 * Generic GPIO support 46 * Generic GPIO support
@@ -70,25 +60,15 @@
70#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ 60#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
71 61
72/* 62/*
73 * Pin Assignment register definitions 63 * Some PSC related definitions
74 */ 64 */
75#define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40) 65#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
76#define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)
77#define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)
78#define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44)
79#define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */
80#define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */
81#define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)
82#define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)
83#define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D)
84#define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C)
85#define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50)
86#define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52)
87
88#define MCF_PAR_SDA (0x0008) 66#define MCF_PAR_SDA (0x0008)
89#define MCF_PAR_SCL (0x0004) 67#define MCF_PAR_SCL (0x0004)
90#define MCF_PAR_PSC_TXD (0x04) 68#define MCF_PAR_PSC_TXD (0x04)
91#define MCF_PAR_PSC_RXD (0x08) 69#define MCF_PAR_PSC_RXD (0x08)
70#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
71#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
92#define MCF_PAR_PSC_CTS_GPIO (0x00) 72#define MCF_PAR_PSC_CTS_GPIO (0x00)
93#define MCF_PAR_PSC_CTS_BCLK (0x80) 73#define MCF_PAR_PSC_CTS_BCLK (0x80)
94#define MCF_PAR_PSC_CTS_CTS (0xC0) 74#define MCF_PAR_PSC_CTS_CTS (0xC0)
diff --git a/arch/m68k/include/asm/m68360.h b/arch/m68k/include/asm/m68360.h
index 4664180a3ab..eb7d39ef285 100644
--- a/arch/m68k/include/asm/m68360.h
+++ b/arch/m68k/include/asm/m68360.h
@@ -1,7 +1,7 @@
1#include <asm/m68360_regs.h> 1#include "m68360_regs.h"
2#include <asm/m68360_pram.h> 2#include "m68360_pram.h"
3#include <asm/m68360_quicc.h> 3#include "m68360_quicc.h"
4#include <asm/m68360_enet.h> 4#include "m68360_enet.h"
5 5
6#ifdef CONFIG_M68360 6#ifdef CONFIG_M68360
7 7
diff --git a/arch/m68k/include/asm/m68360_enet.h b/arch/m68k/include/asm/m68360_enet.h
index 4d04037c78a..c36f4d05920 100644
--- a/arch/m68k/include/asm/m68360_enet.h
+++ b/arch/m68k/include/asm/m68360_enet.h
@@ -10,7 +10,7 @@
10#ifndef __ETHER_H 10#ifndef __ETHER_H
11#define __ETHER_H 11#define __ETHER_H
12 12
13#include <asm/quicc_simple.h> 13#include "quicc_simple.h"
14 14
15/* 15/*
16 * transmit BD's 16 * transmit BD's
diff --git a/arch/m68k/include/asm/mac_baboon.h b/arch/m68k/include/asm/mac_baboon.h
index a2d32f6589f..c2a042b8c34 100644
--- a/arch/m68k/include/asm/mac_baboon.h
+++ b/arch/m68k/include/asm/mac_baboon.h
@@ -29,10 +29,4 @@ struct baboon {
29 */ 29 */
30}; 30};
31 31
32extern int baboon_present;
33
34extern void baboon_register_interrupts(void);
35extern void baboon_irq_enable(int);
36extern void baboon_irq_disable(int);
37
38#endif /* __ASSEMBLY **/ 32#endif /* __ASSEMBLY **/
diff --git a/arch/m68k/include/asm/mac_iop.h b/arch/m68k/include/asm/mac_iop.h
index fde874a01e2..a2c7e6fcca3 100644
--- a/arch/m68k/include/asm/mac_iop.h
+++ b/arch/m68k/include/asm/mac_iop.h
@@ -159,6 +159,4 @@ extern void iop_upload_code(uint, __u8 *, uint, __u16);
159extern void iop_download_code(uint, __u8 *, uint, __u16); 159extern void iop_download_code(uint, __u8 *, uint, __u16);
160extern __u8 *iop_compare_code(uint, __u8 *, uint, __u16); 160extern __u8 *iop_compare_code(uint, __u8 *, uint, __u16);
161 161
162extern void iop_register_interrupts(void);
163
164#endif /* __ASSEMBLY__ */ 162#endif /* __ASSEMBLY__ */
diff --git a/arch/m68k/include/asm/mac_oss.h b/arch/m68k/include/asm/mac_oss.h
index 425fbff4f4d..3cf2b6ed685 100644
--- a/arch/m68k/include/asm/mac_oss.h
+++ b/arch/m68k/include/asm/mac_oss.h
@@ -58,6 +58,25 @@
58 58
59#define OSS_POWEROFF 0x80 59#define OSS_POWEROFF 0x80
60 60
61/*
62 * OSS Interrupt levels for various sub-systems
63 *
64 * This mapping is laid out with two things in mind: first, we try to keep
65 * things on their own levels to avoid having to do double-dispatches. Second,
66 * the levels match as closely as possible the alternate IRQ mapping mode (aka
67 * "A/UX mode") available on some VIA machines.
68 */
69
70#define OSS_IRQLEV_DISABLED 0
71#define OSS_IRQLEV_IOPISM 1 /* ADB? */
72#define OSS_IRQLEV_SCSI IRQ_AUTO_2
73#define OSS_IRQLEV_NUBUS IRQ_AUTO_3 /* keep this on its own level */
74#define OSS_IRQLEV_IOPSCC IRQ_AUTO_4 /* matches VIA alternate mapping */
75#define OSS_IRQLEV_SOUND IRQ_AUTO_5 /* matches VIA alternate mapping */
76#define OSS_IRQLEV_60HZ 6 /* matches VIA alternate mapping */
77#define OSS_IRQLEV_VIA1 IRQ_AUTO_6 /* matches VIA alternate mapping */
78#define OSS_IRQLEV_PARITY 7 /* matches VIA alternate mapping */
79
61#ifndef __ASSEMBLY__ 80#ifndef __ASSEMBLY__
62 81
63struct mac_oss { 82struct mac_oss {
@@ -72,8 +91,4 @@ struct mac_oss {
72extern volatile struct mac_oss *oss; 91extern volatile struct mac_oss *oss;
73extern int oss_present; 92extern int oss_present;
74 93
75extern void oss_register_interrupts(void);
76extern void oss_irq_enable(int);
77extern void oss_irq_disable(int);
78
79#endif /* __ASSEMBLY__ */ 94#endif /* __ASSEMBLY__ */
diff --git a/arch/m68k/include/asm/mac_psc.h b/arch/m68k/include/asm/mac_psc.h
index e5c0d71d154..7808bb0b232 100644
--- a/arch/m68k/include/asm/mac_psc.h
+++ b/arch/m68k/include/asm/mac_psc.h
@@ -211,10 +211,6 @@
211extern volatile __u8 *psc; 211extern volatile __u8 *psc;
212extern int psc_present; 212extern int psc_present;
213 213
214extern void psc_register_interrupts(void);
215extern void psc_irq_enable(int);
216extern void psc_irq_disable(int);
217
218/* 214/*
219 * Access functions 215 * Access functions
220 */ 216 */
diff --git a/arch/m68k/include/asm/mac_via.h b/arch/m68k/include/asm/mac_via.h
index aeeedf8b2d2..a59665e1d41 100644
--- a/arch/m68k/include/asm/mac_via.h
+++ b/arch/m68k/include/asm/mac_via.h
@@ -254,15 +254,6 @@
254extern volatile __u8 *via1,*via2; 254extern volatile __u8 *via1,*via2;
255extern int rbv_present,via_alt_mapping; 255extern int rbv_present,via_alt_mapping;
256 256
257extern void via_register_interrupts(void);
258extern void via_irq_enable(int);
259extern void via_irq_disable(int);
260extern void via_nubus_irq_startup(int irq);
261extern void via_nubus_irq_shutdown(int irq);
262extern void via1_irq(unsigned int irq, struct irq_desc *desc);
263extern void via1_set_head(int);
264extern int via2_scsi_drq_pending(void);
265
266static inline int rbv_set_video_bpp(int bpp) 257static inline int rbv_set_video_bpp(int bpp)
267{ 258{
268 char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1; 259 char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1;
diff --git a/arch/m68k/include/asm/machdep.h b/arch/m68k/include/asm/machdep.h
index 825c1c81319..789f3b2de0e 100644
--- a/arch/m68k/include/asm/machdep.h
+++ b/arch/m68k/include/asm/machdep.h
@@ -22,6 +22,8 @@ extern unsigned int (*mach_get_ss)(void);
22extern int (*mach_get_rtc_pll)(struct rtc_pll_info *); 22extern int (*mach_get_rtc_pll)(struct rtc_pll_info *);
23extern int (*mach_set_rtc_pll)(struct rtc_pll_info *); 23extern int (*mach_set_rtc_pll)(struct rtc_pll_info *);
24extern int (*mach_set_clock_mmss)(unsigned long); 24extern int (*mach_set_clock_mmss)(unsigned long);
25extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour,
26 int *min, int *sec);
25extern void (*mach_reset)( void ); 27extern void (*mach_reset)( void );
26extern void (*mach_halt)( void ); 28extern void (*mach_halt)( void );
27extern void (*mach_power_off)( void ); 29extern void (*mach_power_off)( void );
@@ -33,8 +35,9 @@ extern void (*mach_l2_flush) (int);
33extern void (*mach_beep) (unsigned int, unsigned int); 35extern void (*mach_beep) (unsigned int, unsigned int);
34 36
35/* Hardware clock functions */ 37/* Hardware clock functions */
36extern void hw_timer_init(irq_handler_t handler); 38extern void hw_timer_init(void);
37extern unsigned long hw_timer_offset(void); 39extern unsigned long hw_timer_offset(void);
40extern irqreturn_t arch_timer_interrupt(int irq, void *dummy);
38 41
39extern void config_BSP(char *command, int len); 42extern void config_BSP(char *command, int len);
40 43
diff --git a/arch/m68k/include/asm/macintosh.h b/arch/m68k/include/asm/macintosh.h
index 682a1a2ff55..c2a1c5eac1a 100644
--- a/arch/m68k/include/asm/macintosh.h
+++ b/arch/m68k/include/asm/macintosh.h
@@ -11,9 +11,13 @@
11extern void mac_reset(void); 11extern void mac_reset(void);
12extern void mac_poweroff(void); 12extern void mac_poweroff(void);
13extern void mac_init_IRQ(void); 13extern void mac_init_IRQ(void);
14extern int mac_irq_pending(unsigned int);
14 15
15extern void mac_irq_enable(struct irq_data *data); 16/*
16extern void mac_irq_disable(struct irq_data *data); 17 * Floppy driver magic hook - probably shouldn't be here
18 */
19
20extern void via1_set_head(int);
17 21
18/* 22/*
19 * Macintosh Table 23 * Macintosh Table
@@ -42,7 +46,7 @@ struct mac_model
42#define MAC_ADB_IOP 6 46#define MAC_ADB_IOP 6
43 47
44#define MAC_VIA_II 1 48#define MAC_VIA_II 1
45#define MAC_VIA_IICI 2 49#define MAC_VIA_IIci 2
46#define MAC_VIA_QUADRA 3 50#define MAC_VIA_QUADRA 3
47 51
48#define MAC_SCSI_NONE 0 52#define MAC_SCSI_NONE 0
diff --git a/arch/m68k/include/asm/macints.h b/arch/m68k/include/asm/macints.h
index 92aa8a4c2d0..ebe1b70fe90 100644
--- a/arch/m68k/include/asm/macints.h
+++ b/arch/m68k/include/asm/macints.h
@@ -104,9 +104,6 @@
104#define IRQ_PSC4_3 (35) 104#define IRQ_PSC4_3 (35)
105#define IRQ_MAC_MACE_DMA IRQ_PSC4_3 105#define IRQ_MAC_MACE_DMA IRQ_PSC4_3
106 106
107/* OSS Level 4 interrupts */
108#define IRQ_MAC_SCC (33)
109
110/* Level 5 (PSC, AV Macs only) interrupts */ 107/* Level 5 (PSC, AV Macs only) interrupts */
111#define IRQ_PSC5_0 (40) 108#define IRQ_PSC5_0 (40)
112#define IRQ_PSC5_1 (41) 109#define IRQ_PSC5_1 (41)
@@ -134,6 +131,9 @@
134#define IRQ_BABOON_2 (66) 131#define IRQ_BABOON_2 (66)
135#define IRQ_BABOON_3 (67) 132#define IRQ_BABOON_3 (67)
136 133
134/* On non-PSC machines, the serial ports share an IRQ */
135#define IRQ_MAC_SCC IRQ_AUTO_4
136
137#define SLOT2IRQ(x) (x + 47) 137#define SLOT2IRQ(x) (x + 47)
138#define IRQ2SLOT(x) (x - 47) 138#define IRQ2SLOT(x) (x - 47)
139 139
diff --git a/arch/m68k/include/asm/mcf8390.h b/arch/m68k/include/asm/mcf8390.h
deleted file mode 100644
index a72a20819a5..00000000000
--- a/arch/m68k/include/asm/mcf8390.h
+++ /dev/null
@@ -1,131 +0,0 @@
1/****************************************************************************/
2
3/*
4 * mcf8390.h -- NS8390 support for ColdFire eval boards.
5 *
6 * (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo (www.lineo.com)
8 * (C) Copyright 2001, SnapGear (www.snapgear.com)
9 *
10 * 19990409 David W. Miller Converted from m5206ne.h for 5307 eval board
11 *
12 * Hacked support for m5206e Cadre III evaluation board
13 * Fred Stevens (fred.stevens@pemstar.com) 13 April 1999
14 */
15
16/****************************************************************************/
17#ifndef mcf8390_h
18#define mcf8390_h
19/****************************************************************************/
20
21
22/*
23 * Support for NE2000 clones devices in ColdFire based boards.
24 * Not all boards address these parts the same way, some use a
25 * direct addressing method, others use a side-band address space
26 * to access odd address registers, some require byte swapping
27 * others do not.
28 */
29#define BSWAP(w) (((w) << 8) | ((w) >> 8))
30#define RSWAP(w) (w)
31
32
33/*
34 * Define the basic hardware resources of NE2000 boards.
35 */
36
37#if defined(CONFIG_ARN5206)
38#define NE2000_ADDR 0x40000300
39#define NE2000_ODDOFFSET 0x00010000
40#define NE2000_ADDRSIZE 0x00020000
41#define NE2000_IRQ_VECTOR 0xf0
42#define NE2000_IRQ_PRIORITY 2
43#define NE2000_IRQ_LEVEL 4
44#define NE2000_BYTE volatile unsigned short
45#endif
46
47#if defined(CONFIG_M5206eC3)
48#define NE2000_ADDR 0x40000300
49#define NE2000_ODDOFFSET 0x00010000
50#define NE2000_ADDRSIZE 0x00020000
51#define NE2000_IRQ_VECTOR 0x1c
52#define NE2000_IRQ_PRIORITY 2
53#define NE2000_IRQ_LEVEL 4
54#define NE2000_BYTE volatile unsigned short
55#endif
56
57#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel)
58#define NE2000_ADDR 0x30000300
59#define NE2000_ADDRSIZE 0x00001000
60#define NE2000_IRQ_VECTOR 25
61#define NE2000_IRQ_PRIORITY 1
62#define NE2000_IRQ_LEVEL 3
63#define NE2000_BYTE volatile unsigned char
64#endif
65
66#if defined(CONFIG_M5307C3)
67#define NE2000_ADDR 0x40000300
68#define NE2000_ODDOFFSET 0x00010000
69#define NE2000_ADDRSIZE 0x00020000
70#define NE2000_IRQ_VECTOR 0x1b
71#define NE2000_BYTE volatile unsigned short
72#endif
73
74#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
75#define NE2000_ADDR 0x30600300
76#define NE2000_ODDOFFSET 0x00008000
77#define NE2000_ADDRSIZE 0x00010000
78#define NE2000_IRQ_VECTOR 67
79#undef BSWAP
80#define BSWAP(w) (w)
81#define NE2000_BYTE volatile unsigned short
82#undef RSWAP
83#define RSWAP(w) (((w) << 8) | ((w) >> 8))
84#endif
85
86#if defined(CONFIG_M5307) && defined(CONFIG_NETtel)
87#define NE2000_ADDR0 0x30600300
88#define NE2000_ADDR1 0x30800300
89#define NE2000_ODDOFFSET 0x00008000
90#define NE2000_ADDRSIZE 0x00010000
91#define NE2000_IRQ_VECTOR0 27
92#define NE2000_IRQ_VECTOR1 29
93#undef BSWAP
94#define BSWAP(w) (w)
95#define NE2000_BYTE volatile unsigned short
96#undef RSWAP
97#define RSWAP(w) (((w) << 8) | ((w) >> 8))
98#endif
99
100#if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3)
101#define NE2000_ADDR 0x30600300
102#define NE2000_ODDOFFSET 0x00008000
103#define NE2000_ADDRSIZE 0x00010000
104#define NE2000_IRQ_VECTOR 27
105#undef BSWAP
106#define BSWAP(w) (w)
107#define NE2000_BYTE volatile unsigned short
108#undef RSWAP
109#define RSWAP(w) (((w) << 8) | ((w) >> 8))
110#endif
111
112#if defined(CONFIG_ARN5307)
113#define NE2000_ADDR 0xfe600300
114#define NE2000_ODDOFFSET 0x00010000
115#define NE2000_ADDRSIZE 0x00020000
116#define NE2000_IRQ_VECTOR 0x1b
117#define NE2000_IRQ_PRIORITY 2
118#define NE2000_IRQ_LEVEL 3
119#define NE2000_BYTE volatile unsigned short
120#endif
121
122#if defined(CONFIG_M5407C3)
123#define NE2000_ADDR 0x40000300
124#define NE2000_ODDOFFSET 0x00010000
125#define NE2000_ADDRSIZE 0x00020000
126#define NE2000_IRQ_VECTOR 0x1b
127#define NE2000_BYTE volatile unsigned short
128#endif
129
130/****************************************************************************/
131#endif /* mcf8390_h */
diff --git a/arch/m68k/include/asm/mcf_pgalloc.h b/arch/m68k/include/asm/mcf_pgalloc.h
deleted file mode 100644
index 313f3dd23cd..00000000000
--- a/arch/m68k/include/asm/mcf_pgalloc.h
+++ /dev/null
@@ -1,102 +0,0 @@
1#ifndef M68K_MCF_PGALLOC_H
2#define M68K_MCF_PGALLOC_H
3
4#include <asm/tlb.h>
5#include <asm/tlbflush.h>
6
7extern inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
8{
9 free_page((unsigned long) pte);
10}
11
12extern const char bad_pmd_string[];
13
14extern inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
15 unsigned long address)
16{
17 unsigned long page = __get_free_page(GFP_DMA|__GFP_REPEAT);
18
19 if (!page)
20 return NULL;
21
22 memset((void *)page, 0, PAGE_SIZE);
23 return (pte_t *) (page);
24}
25
26extern inline pmd_t *pmd_alloc_kernel(pgd_t *pgd, unsigned long address)
27{
28 return (pmd_t *) pgd;
29}
30
31#define pmd_alloc_one_fast(mm, address) ({ BUG(); ((pmd_t *)1); })
32#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); })
33
34#define pte_alloc_one_fast(mm, addr) pte_alloc_one(mm, addr)
35
36#define pmd_populate(mm, pmd, page) (pmd_val(*pmd) = \
37 (unsigned long)(page_address(page)))
38
39#define pmd_populate_kernel(mm, pmd, pte) (pmd_val(*pmd) = (unsigned long)(pte))
40
41#define pmd_pgtable(pmd) pmd_page(pmd)
42
43static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t page,
44 unsigned long address)
45{
46 __free_page(page);
47}
48
49#define __pmd_free_tlb(tlb, pmd, address) do { } while (0)
50
51static inline struct page *pte_alloc_one(struct mm_struct *mm,
52 unsigned long address)
53{
54 struct page *page = alloc_pages(GFP_DMA|__GFP_REPEAT, 0);
55 pte_t *pte;
56
57 if (!page)
58 return NULL;
59
60 pte = kmap(page);
61 if (pte) {
62 clear_page(pte);
63 __flush_page_to_ram(pte);
64 flush_tlb_kernel_page(pte);
65 nocache_page(pte);
66 }
67 kunmap(page);
68
69 return page;
70}
71
72extern inline void pte_free(struct mm_struct *mm, struct page *page)
73{
74 __free_page(page);
75}
76
77/*
78 * In our implementation, each pgd entry contains 1 pmd that is never allocated
79 * or freed. pgd_present is always 1, so this should never be called. -NL
80 */
81#define pmd_free(mm, pmd) BUG()
82
83static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
84{
85 free_page((unsigned long) pgd);
86}
87
88static inline pgd_t *pgd_alloc(struct mm_struct *mm)
89{
90 pgd_t *new_pgd;
91
92 new_pgd = (pgd_t *)__get_free_page(GFP_DMA | __GFP_NOWARN);
93 if (!new_pgd)
94 return NULL;
95 memcpy(new_pgd, swapper_pg_dir, PAGE_SIZE);
96 memset(new_pgd, 0, PAGE_OFFSET >> PGDIR_SHIFT);
97 return new_pgd;
98}
99
100#define pgd_populate(mm, pmd, pte) BUG()
101
102#endif /* M68K_MCF_PGALLOC_H */
diff --git a/arch/m68k/include/asm/mcf_pgtable.h b/arch/m68k/include/asm/mcf_pgtable.h
deleted file mode 100644
index 3c793682e5d..00000000000
--- a/arch/m68k/include/asm/mcf_pgtable.h
+++ /dev/null
@@ -1,426 +0,0 @@
1#ifndef _MCF_PGTABLE_H
2#define _MCF_PGTABLE_H
3
4#include <asm/mcfmmu.h>
5#include <asm/page.h>
6
7/*
8 * MMUDR bits, in proper place. We write these directly into the MMUDR
9 * after masking from the pte.
10 */
11#define CF_PAGE_LOCKED MMUDR_LK /* 0x00000002 */
12#define CF_PAGE_EXEC MMUDR_X /* 0x00000004 */
13#define CF_PAGE_WRITABLE MMUDR_W /* 0x00000008 */
14#define CF_PAGE_READABLE MMUDR_R /* 0x00000010 */
15#define CF_PAGE_SYSTEM MMUDR_SP /* 0x00000020 */
16#define CF_PAGE_COPYBACK MMUDR_CM_CCB /* 0x00000040 */
17#define CF_PAGE_NOCACHE MMUDR_CM_NCP /* 0x00000080 */
18
19#define CF_CACHEMASK (~MMUDR_CM_CCB)
20#define CF_PAGE_MMUDR_MASK 0x000000fe
21
22#define _PAGE_NOCACHE030 CF_PAGE_NOCACHE
23
24/*
25 * MMUTR bits, need shifting down.
26 */
27#define CF_PAGE_MMUTR_MASK 0x00000c00
28#define CF_PAGE_MMUTR_SHIFT 10
29
30#define CF_PAGE_VALID (MMUTR_V << CF_PAGE_MMUTR_SHIFT)
31#define CF_PAGE_SHARED (MMUTR_SG << CF_PAGE_MMUTR_SHIFT)
32
33/*
34 * Fake bits, not implemented in CF, will get masked out before
35 * hitting hardware.
36 */
37#define CF_PAGE_DIRTY 0x00000001
38#define CF_PAGE_FILE 0x00000200
39#define CF_PAGE_ACCESSED 0x00001000
40
41#define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */
42#define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */
43#define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */
44#define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */
45#define _DESCTYPE_MASK 0x003
46#define _CACHEMASK040 (~0x060)
47#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */
48
49/*
50 * Externally used page protection values.
51 */
52#define _PAGE_PRESENT (CF_PAGE_VALID)
53#define _PAGE_ACCESSED (CF_PAGE_ACCESSED)
54#define _PAGE_DIRTY (CF_PAGE_DIRTY)
55#define _PAGE_READWRITE (CF_PAGE_READABLE \
56 | CF_PAGE_WRITABLE \
57 | CF_PAGE_SYSTEM \
58 | CF_PAGE_SHARED)
59
60/*
61 * Compound page protection values.
62 */
63#define PAGE_NONE __pgprot(CF_PAGE_VALID \
64 | CF_PAGE_ACCESSED)
65
66#define PAGE_SHARED __pgprot(CF_PAGE_VALID \
67 | CF_PAGE_ACCESSED \
68 | CF_PAGE_SHARED)
69
70#define PAGE_INIT __pgprot(CF_PAGE_VALID \
71 | CF_PAGE_READABLE \
72 | CF_PAGE_WRITABLE \
73 | CF_PAGE_EXEC \
74 | CF_PAGE_SYSTEM)
75
76#define PAGE_KERNEL __pgprot(CF_PAGE_VALID \
77 | CF_PAGE_ACCESSED \
78 | CF_PAGE_READABLE \
79 | CF_PAGE_WRITABLE \
80 | CF_PAGE_EXEC \
81 | CF_PAGE_SYSTEM \
82 | CF_PAGE_SHARED)
83
84#define PAGE_COPY __pgprot(CF_PAGE_VALID \
85 | CF_PAGE_ACCESSED \
86 | CF_PAGE_READABLE \
87 | CF_PAGE_DIRTY)
88
89/*
90 * Page protections for initialising protection_map. See mm/mmap.c
91 * for use. In general, the bit positions are xwr, and P-items are
92 * private, the S-items are shared.
93 */
94#define __P000 PAGE_NONE
95#define __P001 __pgprot(CF_PAGE_VALID \
96 | CF_PAGE_ACCESSED \
97 | CF_PAGE_READABLE)
98#define __P010 __pgprot(CF_PAGE_VALID \
99 | CF_PAGE_ACCESSED \
100 | CF_PAGE_WRITABLE)
101#define __P011 __pgprot(CF_PAGE_VALID \
102 | CF_PAGE_ACCESSED \
103 | CF_PAGE_READABLE \
104 | CF_PAGE_WRITABLE)
105#define __P100 __pgprot(CF_PAGE_VALID \
106 | CF_PAGE_ACCESSED \
107 | CF_PAGE_EXEC)
108#define __P101 __pgprot(CF_PAGE_VALID \
109 | CF_PAGE_ACCESSED \
110 | CF_PAGE_READABLE \
111 | CF_PAGE_EXEC)
112#define __P110 __pgprot(CF_PAGE_VALID \
113 | CF_PAGE_ACCESSED \
114 | CF_PAGE_WRITABLE \
115 | CF_PAGE_EXEC)
116#define __P111 __pgprot(CF_PAGE_VALID \
117 | CF_PAGE_ACCESSED \
118 | CF_PAGE_READABLE \
119 | CF_PAGE_WRITABLE \
120 | CF_PAGE_EXEC)
121
122#define __S000 PAGE_NONE
123#define __S001 __pgprot(CF_PAGE_VALID \
124 | CF_PAGE_ACCESSED \
125 | CF_PAGE_READABLE)
126#define __S010 PAGE_SHARED
127#define __S011 __pgprot(CF_PAGE_VALID \
128 | CF_PAGE_ACCESSED \
129 | CF_PAGE_SHARED \
130 | CF_PAGE_READABLE)
131#define __S100 __pgprot(CF_PAGE_VALID \
132 | CF_PAGE_ACCESSED \
133 | CF_PAGE_EXEC)
134#define __S101 __pgprot(CF_PAGE_VALID \
135 | CF_PAGE_ACCESSED \
136 | CF_PAGE_READABLE \
137 | CF_PAGE_EXEC)
138#define __S110 __pgprot(CF_PAGE_VALID \
139 | CF_PAGE_ACCESSED \
140 | CF_PAGE_SHARED \
141 | CF_PAGE_EXEC)
142#define __S111 __pgprot(CF_PAGE_VALID \
143 | CF_PAGE_ACCESSED \
144 | CF_PAGE_SHARED \
145 | CF_PAGE_READABLE \
146 | CF_PAGE_EXEC)
147
148#define PTE_MASK PAGE_MASK
149#define CF_PAGE_CHG_MASK (PTE_MASK | CF_PAGE_ACCESSED | CF_PAGE_DIRTY)
150
151#ifndef __ASSEMBLY__
152
153/*
154 * Conversion functions: convert a page and protection to a page entry,
155 * and a page entry and page directory to the page they refer to.
156 */
157#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
158
159static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
160{
161 pte_val(pte) = (pte_val(pte) & CF_PAGE_CHG_MASK) | pgprot_val(newprot);
162 return pte;
163}
164
165#define pmd_set(pmdp, ptep) do {} while (0)
166
167static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp)
168{
169 pgd_val(*pgdp) = virt_to_phys(pmdp);
170}
171
172#define __pte_page(pte) ((unsigned long) (pte_val(pte) & PAGE_MASK))
173#define __pmd_page(pmd) ((unsigned long) (pmd_val(pmd)))
174
175static inline int pte_none(pte_t pte)
176{
177 return !pte_val(pte);
178}
179
180static inline int pte_present(pte_t pte)
181{
182 return pte_val(pte) & CF_PAGE_VALID;
183}
184
185static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
186 pte_t *ptep)
187{
188 pte_val(*ptep) = 0;
189}
190
191#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
192#define pte_page(pte) virt_to_page(__pte_page(pte))
193
194static inline int pmd_none2(pmd_t *pmd) { return !pmd_val(*pmd); }
195#define pmd_none(pmd) pmd_none2(&(pmd))
196static inline int pmd_bad2(pmd_t *pmd) { return 0; }
197#define pmd_bad(pmd) pmd_bad2(&(pmd))
198#define pmd_present(pmd) (!pmd_none2(&(pmd)))
199static inline void pmd_clear(pmd_t *pmdp) { pmd_val(*pmdp) = 0; }
200
201static inline int pgd_none(pgd_t pgd) { return 0; }
202static inline int pgd_bad(pgd_t pgd) { return 0; }
203static inline int pgd_present(pgd_t pgd) { return 1; }
204static inline void pgd_clear(pgd_t *pgdp) {}
205
206#define pte_ERROR(e) \
207 printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \
208 __FILE__, __LINE__, pte_val(e))
209#define pmd_ERROR(e) \
210 printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \
211 __FILE__, __LINE__, pmd_val(e))
212#define pgd_ERROR(e) \
213 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
214 __FILE__, __LINE__, pgd_val(e))
215
216/*
217 * The following only work if pte_present() is true.
218 * Undefined behaviour if not...
219 * [we have the full set here even if they don't change from m68k]
220 */
221static inline int pte_read(pte_t pte)
222{
223 return pte_val(pte) & CF_PAGE_READABLE;
224}
225
226static inline int pte_write(pte_t pte)
227{
228 return pte_val(pte) & CF_PAGE_WRITABLE;
229}
230
231static inline int pte_exec(pte_t pte)
232{
233 return pte_val(pte) & CF_PAGE_EXEC;
234}
235
236static inline int pte_dirty(pte_t pte)
237{
238 return pte_val(pte) & CF_PAGE_DIRTY;
239}
240
241static inline int pte_young(pte_t pte)
242{
243 return pte_val(pte) & CF_PAGE_ACCESSED;
244}
245
246static inline int pte_file(pte_t pte)
247{
248 return pte_val(pte) & CF_PAGE_FILE;
249}
250
251static inline int pte_special(pte_t pte)
252{
253 return 0;
254}
255
256static inline pte_t pte_wrprotect(pte_t pte)
257{
258 pte_val(pte) &= ~CF_PAGE_WRITABLE;
259 return pte;
260}
261
262static inline pte_t pte_rdprotect(pte_t pte)
263{
264 pte_val(pte) &= ~CF_PAGE_READABLE;
265 return pte;
266}
267
268static inline pte_t pte_exprotect(pte_t pte)
269{
270 pte_val(pte) &= ~CF_PAGE_EXEC;
271 return pte;
272}
273
274static inline pte_t pte_mkclean(pte_t pte)
275{
276 pte_val(pte) &= ~CF_PAGE_DIRTY;
277 return pte;
278}
279
280static inline pte_t pte_mkold(pte_t pte)
281{
282 pte_val(pte) &= ~CF_PAGE_ACCESSED;
283 return pte;
284}
285
286static inline pte_t pte_mkwrite(pte_t pte)
287{
288 pte_val(pte) |= CF_PAGE_WRITABLE;
289 return pte;
290}
291
292static inline pte_t pte_mkread(pte_t pte)
293{
294 pte_val(pte) |= CF_PAGE_READABLE;
295 return pte;
296}
297
298static inline pte_t pte_mkexec(pte_t pte)
299{
300 pte_val(pte) |= CF_PAGE_EXEC;
301 return pte;
302}
303
304static inline pte_t pte_mkdirty(pte_t pte)
305{
306 pte_val(pte) |= CF_PAGE_DIRTY;
307 return pte;
308}
309
310static inline pte_t pte_mkyoung(pte_t pte)
311{
312 pte_val(pte) |= CF_PAGE_ACCESSED;
313 return pte;
314}
315
316static inline pte_t pte_mknocache(pte_t pte)
317{
318 pte_val(pte) |= 0x80 | (pte_val(pte) & ~0x40);
319 return pte;
320}
321
322static inline pte_t pte_mkcache(pte_t pte)
323{
324 pte_val(pte) &= ~CF_PAGE_NOCACHE;
325 return pte;
326}
327
328static inline pte_t pte_mkspecial(pte_t pte)
329{
330 return pte;
331}
332
333#define swapper_pg_dir kernel_pg_dir
334extern pgd_t kernel_pg_dir[PTRS_PER_PGD];
335
336/*
337 * Find an entry in a pagetable directory.
338 */
339#define pgd_index(address) ((address) >> PGDIR_SHIFT)
340#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
341
342/*
343 * Find an entry in a kernel pagetable directory.
344 */
345#define pgd_offset_k(address) pgd_offset(&init_mm, address)
346
347/*
348 * Find an entry in the second-level pagetable.
349 */
350static inline pmd_t *pmd_offset(pgd_t *pgd, unsigned long address)
351{
352 return (pmd_t *) pgd;
353}
354
355/*
356 * Find an entry in the third-level pagetable.
357 */
358#define __pte_offset(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
359#define pte_offset_kernel(dir, address) \
360 ((pte_t *) __pmd_page(*(dir)) + __pte_offset(address))
361
362/*
363 * Disable caching for page at given kernel virtual address.
364 */
365static inline void nocache_page(void *vaddr)
366{
367 pgd_t *dir;
368 pmd_t *pmdp;
369 pte_t *ptep;
370 unsigned long addr = (unsigned long) vaddr;
371
372 dir = pgd_offset_k(addr);
373 pmdp = pmd_offset(dir, addr);
374 ptep = pte_offset_kernel(pmdp, addr);
375 *ptep = pte_mknocache(*ptep);
376}
377
378/*
379 * Enable caching for page at given kernel virtual address.
380 */
381static inline void cache_page(void *vaddr)
382{
383 pgd_t *dir;
384 pmd_t *pmdp;
385 pte_t *ptep;
386 unsigned long addr = (unsigned long) vaddr;
387
388 dir = pgd_offset_k(addr);
389 pmdp = pmd_offset(dir, addr);
390 ptep = pte_offset_kernel(pmdp, addr);
391 *ptep = pte_mkcache(*ptep);
392}
393
394#define PTE_FILE_MAX_BITS 21
395#define PTE_FILE_SHIFT 11
396
397static inline unsigned long pte_to_pgoff(pte_t pte)
398{
399 return pte_val(pte) >> PTE_FILE_SHIFT;
400}
401
402static inline pte_t pgoff_to_pte(unsigned pgoff)
403{
404 return __pte((pgoff << PTE_FILE_SHIFT) + CF_PAGE_FILE);
405}
406
407/*
408 * Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e))
409 */
410#define __swp_type(x) ((x).val & 0xFF)
411#define __swp_offset(x) ((x).val >> PTE_FILE_SHIFT)
412#define __swp_entry(typ, off) ((swp_entry_t) { (typ) | \
413 (off << PTE_FILE_SHIFT) })
414#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
415#define __swp_entry_to_pte(x) (__pte((x).val))
416
417#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
418
419#define pte_offset_map(pmdp, addr) ((pte_t *)__pmd_page(*pmdp) + \
420 __pte_offset(addr))
421#define pte_unmap(pte) ((void) 0)
422#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
423#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
424
425#endif /* !__ASSEMBLY__ */
426#endif /* _MCF_PGTABLE_H */
diff --git a/arch/m68k/include/asm/mcfclk.h b/arch/m68k/include/asm/mcfclk.h
deleted file mode 100644
index ea4791e3a55..00000000000
--- a/arch/m68k/include/asm/mcfclk.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * mcfclk.h -- coldfire specific clock structure
3 */
4
5
6#ifndef mcfclk_h
7#define mcfclk_h
8
9struct clk;
10
11struct clk_ops {
12 void (*enable)(struct clk *);
13 void (*disable)(struct clk *);
14};
15
16struct clk {
17 const char *name;
18 struct clk_ops *clk_ops;
19 unsigned long rate;
20 unsigned long enabled;
21 u8 slot;
22};
23
24extern struct clk *mcf_clks[];
25
26#ifdef MCFPM_PPMCR0
27extern struct clk_ops clk_ops0;
28#ifdef MCFPM_PPMCR1
29extern struct clk_ops clk_ops1;
30#endif /* MCFPM_PPMCR1 */
31
32#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
33static struct clk __clk_##clk_bank##_##clk_slot = { \
34 .name = clk_name, \
35 .clk_ops = &clk_ops##clk_bank, \
36 .rate = clk_rate, \
37 .slot = clk_slot, \
38}
39
40void __clk_init_enabled(struct clk *);
41void __clk_init_disabled(struct clk *);
42#else
43#define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
44 static struct clk clk_##clk_ref = { \
45 .name = clk_name, \
46 .rate = clk_rate, \
47 }
48#endif /* MCFPM_PPMCR0 */
49
50#endif /* mcfclk_h */
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
index fa1059f50df..ee5e4ccce89 100644
--- a/arch/m68k/include/asm/mcfgpio.h
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -16,289 +16,25 @@
16#ifndef mcfgpio_h 16#ifndef mcfgpio_h
17#define mcfgpio_h 17#define mcfgpio_h
18 18
19#ifdef CONFIG_GPIOLIB 19#include <linux/io.h>
20#include <asm-generic/gpio.h> 20#include <asm-generic/gpio.h>
21#else
22 21
23int __mcfgpio_get_value(unsigned gpio); 22struct mcf_gpio_chip {
24void __mcfgpio_set_value(unsigned gpio, int value); 23 struct gpio_chip gpio_chip;
25int __mcfgpio_direction_input(unsigned gpio); 24 void __iomem *pddr;
26int __mcfgpio_direction_output(unsigned gpio, int value); 25 void __iomem *podr;
27int __mcfgpio_request(unsigned gpio); 26 void __iomem *ppdr;
28void __mcfgpio_free(unsigned gpio); 27 void __iomem *setr;
29 28 void __iomem *clrr;
30/* our alternate 'gpiolib' functions */ 29 const u8 *gpio_to_pinmux;
31static inline int __gpio_get_value(unsigned gpio) 30};
32{ 31
33 if (gpio < MCFGPIO_PIN_MAX) 32int mcf_gpio_direction_input(struct gpio_chip *, unsigned);
34 return __mcfgpio_get_value(gpio); 33int mcf_gpio_get_value(struct gpio_chip *, unsigned);
35 else 34int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);
36 return -EINVAL; 35void mcf_gpio_set_value(struct gpio_chip *, unsigned, int);
37} 36void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);
38 37int mcf_gpio_request(struct gpio_chip *, unsigned);
39static inline void __gpio_set_value(unsigned gpio, int value) 38void mcf_gpio_free(struct gpio_chip *, unsigned);
40{
41 if (gpio < MCFGPIO_PIN_MAX)
42 __mcfgpio_set_value(gpio, value);
43}
44
45static inline int __gpio_cansleep(unsigned gpio)
46{
47 if (gpio < MCFGPIO_PIN_MAX)
48 return 0;
49 else
50 return -EINVAL;
51}
52
53static inline int __gpio_to_irq(unsigned gpio)
54{
55 return -EINVAL;
56}
57
58static inline int gpio_direction_input(unsigned gpio)
59{
60 if (gpio < MCFGPIO_PIN_MAX)
61 return __mcfgpio_direction_input(gpio);
62 else
63 return -EINVAL;
64}
65
66static inline int gpio_direction_output(unsigned gpio, int value)
67{
68 if (gpio < MCFGPIO_PIN_MAX)
69 return __mcfgpio_direction_output(gpio, value);
70 else
71 return -EINVAL;
72}
73
74static inline int gpio_request(unsigned gpio, const char *label)
75{
76 if (gpio < MCFGPIO_PIN_MAX)
77 return __mcfgpio_request(gpio);
78 else
79 return -EINVAL;
80}
81
82static inline void gpio_free(unsigned gpio)
83{
84 if (gpio < MCFGPIO_PIN_MAX)
85 __mcfgpio_free(gpio);
86}
87
88#endif /* CONFIG_GPIOLIB */
89
90
91/*
92 * The Freescale Coldfire family is quite varied in how they implement GPIO.
93 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
94 * only one port, others have multiple ports; some have a single data latch
95 * for both input and output, others have a separate pin data register to read
96 * input; some require a read-modify-write access to change an output, others
97 * have set and clear registers for some of the outputs; Some have all the
98 * GPIOs in a single control area, others have some GPIOs implemented in
99 * different modules.
100 *
101 * This implementation attempts accommodate the differences while presenting
102 * a generic interface that will optimize to as few instructions as possible.
103 */
104#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
105 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
106 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
107 defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \
108 defined(CONFIG_M5441x)
109
110/* These parts have GPIO organized by 8 bit ports */
111
112#define MCFGPIO_PORTTYPE u8
113#define MCFGPIO_PORTSIZE 8
114#define mcfgpio_read(port) __raw_readb(port)
115#define mcfgpio_write(data, port) __raw_writeb(data, port)
116
117#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
118
119/* These parts have GPIO organized by 16 bit ports */
120
121#define MCFGPIO_PORTTYPE u16
122#define MCFGPIO_PORTSIZE 16
123#define mcfgpio_read(port) __raw_readw(port)
124#define mcfgpio_write(data, port) __raw_writew(data, port)
125
126#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
127
128/* These parts have GPIO organized by 32 bit ports */
129
130#define MCFGPIO_PORTTYPE u32
131#define MCFGPIO_PORTSIZE 32
132#define mcfgpio_read(port) __raw_readl(port)
133#define mcfgpio_write(data, port) __raw_writel(data, port)
134 39
135#endif 40#endif
136
137#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
138#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
139
140#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
141 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
142 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
143/*
144 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
145 * read-modify-write to change an output and a GPIO module which has separate
146 * set/clr registers to directly change outputs with a single write access.
147 */
148#if defined(CONFIG_M528x)
149/*
150 * The 528x also has GPIOs in other modules (GPT, QADC) which use
151 * read-modify-write as well as those controlled by the EPORT and GPIO modules.
152 */
153#define MCFGPIO_SCR_START 40
154#elif defined(CONFIGM5441x)
155/* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
156#define MCFGPIO_SCR_START 0
157#else
158#define MCFGPIO_SCR_START 8
159#endif
160
161#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
162 mcfgpio_port(gpio - MCFGPIO_SCR_START))
163
164#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
165 mcfgpio_port(gpio - MCFGPIO_SCR_START))
166#else
167
168#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
169/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
170#define MCFGPIO_SETR_PORT(gpio) 0
171#define MCFGPIO_CLRR_PORT(gpio) 0
172
173#endif
174/*
175 * Coldfire specific helper functions
176 */
177
178/* return the port pin data register for a gpio */
179static inline u32 __mcfgpio_ppdr(unsigned gpio)
180{
181#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
182 defined(CONFIG_M5307) || defined(CONFIG_M5407)
183 return MCFSIM_PADAT;
184#elif defined(CONFIG_M5272)
185 if (gpio < 16)
186 return MCFSIM_PADAT;
187 else if (gpio < 32)
188 return MCFSIM_PBDAT;
189 else
190 return MCFSIM_PCDAT;
191#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
192 if (gpio < 32)
193 return MCFSIM2_GPIOREAD;
194 else
195 return MCFSIM2_GPIO1READ;
196#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
197 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
198 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
199#if !defined(CONFIG_M5441x)
200 if (gpio < 8)
201 return MCFEPORT_EPPDR;
202#if defined(CONFIG_M528x)
203 else if (gpio < 16)
204 return MCFGPTA_GPTPORT;
205 else if (gpio < 24)
206 return MCFGPTB_GPTPORT;
207 else if (gpio < 32)
208 return MCFQADC_PORTQA;
209 else if (gpio < 40)
210 return MCFQADC_PORTQB;
211#endif /* defined(CONFIG_M528x) */
212 else
213#endif /* !defined(CONFIG_M5441x) */
214 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
215#else
216 return 0;
217#endif
218}
219
220/* return the port output data register for a gpio */
221static inline u32 __mcfgpio_podr(unsigned gpio)
222{
223#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
224 defined(CONFIG_M5307) || defined(CONFIG_M5407)
225 return MCFSIM_PADAT;
226#elif defined(CONFIG_M5272)
227 if (gpio < 16)
228 return MCFSIM_PADAT;
229 else if (gpio < 32)
230 return MCFSIM_PBDAT;
231 else
232 return MCFSIM_PCDAT;
233#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
234 if (gpio < 32)
235 return MCFSIM2_GPIOWRITE;
236 else
237 return MCFSIM2_GPIO1WRITE;
238#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
239 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
240 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
241#if !defined(CONFIG_M5441x)
242 if (gpio < 8)
243 return MCFEPORT_EPDR;
244#if defined(CONFIG_M528x)
245 else if (gpio < 16)
246 return MCFGPTA_GPTPORT;
247 else if (gpio < 24)
248 return MCFGPTB_GPTPORT;
249 else if (gpio < 32)
250 return MCFQADC_PORTQA;
251 else if (gpio < 40)
252 return MCFQADC_PORTQB;
253#endif /* defined(CONFIG_M528x) */
254 else
255#endif /* !defined(CONFIG_M5441x) */
256 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
257#else
258 return 0;
259#endif
260}
261
262/* return the port direction data register for a gpio */
263static inline u32 __mcfgpio_pddr(unsigned gpio)
264{
265#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
266 defined(CONFIG_M5307) || defined(CONFIG_M5407)
267 return MCFSIM_PADDR;
268#elif defined(CONFIG_M5272)
269 if (gpio < 16)
270 return MCFSIM_PADDR;
271 else if (gpio < 32)
272 return MCFSIM_PBDDR;
273 else
274 return MCFSIM_PCDDR;
275#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
276 if (gpio < 32)
277 return MCFSIM2_GPIOENABLE;
278 else
279 return MCFSIM2_GPIO1ENABLE;
280#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
281 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
282 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
283#if !defined(CONFIG_M5441x)
284 if (gpio < 8)
285 return MCFEPORT_EPDDR;
286#if defined(CONFIG_M528x)
287 else if (gpio < 16)
288 return MCFGPTA_GPTDDR;
289 else if (gpio < 24)
290 return MCFGPTB_GPTDDR;
291 else if (gpio < 32)
292 return MCFQADC_DDRQA;
293 else if (gpio < 40)
294 return MCFQADC_DDRQB;
295#endif /* defined(CONFIG_M528x) */
296 else
297#endif /* !defined(CONFIG_M5441x) */
298 return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
299#else
300 return 0;
301#endif
302}
303
304#endif /* mcfgpio_h */
diff --git a/arch/m68k/include/asm/mcfmmu.h b/arch/m68k/include/asm/mcfmmu.h
deleted file mode 100644
index 26cc3d5a63f..00000000000
--- a/arch/m68k/include/asm/mcfmmu.h
+++ /dev/null
@@ -1,112 +0,0 @@
1/*
2 * mcfmmu.h -- definitions for the ColdFire v4e MMU
3 *
4 * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef MCFMMU_H
12#define MCFMMU_H
13
14/*
15 * The MMU support registers are mapped into the address space using
16 * the processor MMUBASE register. We used a fixed address for mapping,
17 * there doesn't seem any need to make this configurable yet.
18 */
19#define MMUBASE 0xfe000000
20
21/*
22 * The support registers of the MMU. Names are the sames as those
23 * used in the Freescale v4e documentation.
24 */
25#define MMUCR (MMUBASE + 0x00) /* Control register */
26#define MMUOR (MMUBASE + 0x04) /* Operation register */
27#define MMUSR (MMUBASE + 0x08) /* Status register */
28#define MMUAR (MMUBASE + 0x10) /* TLB Address register */
29#define MMUTR (MMUBASE + 0x14) /* TLB Tag register */
30#define MMUDR (MMUBASE + 0x18) /* TLB Data register */
31
32/*
33 * MMU Control register bit flags
34 */
35#define MMUCR_EN 0x00000001 /* Virtual mode enable */
36#define MMUCR_ASM 0x00000002 /* Address space mode */
37
38/*
39 * MMU Operation register.
40 */
41#define MMUOR_UAA 0x00000001 /* Update allocatiom address */
42#define MMUOR_ACC 0x00000002 /* TLB access */
43#define MMUOR_RD 0x00000004 /* TLB access read */
44#define MMUOR_WR 0x00000000 /* TLB access write */
45#define MMUOR_ADR 0x00000008 /* TLB address select */
46#define MMUOR_ITLB 0x00000010 /* ITLB operation */
47#define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */
48#define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */
49#define MMUOR_CA 0x00000080 /* Clear all TLBs */
50#define MMUOR_STLB 0x00000100 /* Search TLBs */
51#define MMUOR_AAN 16 /* TLB allocation address */
52#define MMUOR_AAMASK 0xffff0000 /* AA mask */
53
54/*
55 * MMU Status register.
56 */
57#define MMUSR_HIT 0x00000002 /* Search TLB hit */
58#define MMUSR_WF 0x00000008 /* Write access fault */
59#define MMUSR_RF 0x00000010 /* Read access fault */
60#define MMUSR_SPF 0x00000020 /* Supervisor protect fault */
61
62/*
63 * MMU Read/Write Tag register.
64 */
65#define MMUTR_V 0x00000001 /* Valid */
66#define MMUTR_SG 0x00000002 /* Shared global */
67#define MMUTR_IDN 2 /* Address Space ID */
68#define MMUTR_IDMASK 0x000003fc /* ASID mask */
69#define MMUTR_VAN 10 /* Virtual Address */
70#define MMUTR_VAMASK 0xfffffc00 /* VA mask */
71
72/*
73 * MMU Read/Write Data register.
74 */
75#define MMUDR_LK 0x00000002 /* Lock entry */
76#define MMUDR_X 0x00000004 /* Execute access enable */
77#define MMUDR_W 0x00000008 /* Write access enable */
78#define MMUDR_R 0x00000010 /* Read access enable */
79#define MMUDR_SP 0x00000020 /* Supervisor access enable */
80#define MMUDR_CM_CWT 0x00000000 /* Cachable write thru */
81#define MMUDR_CM_CCB 0x00000040 /* Cachable copy back */
82#define MMUDR_CM_NCP 0x00000080 /* Non-cachable precise */
83#define MMUDR_CM_NCI 0x000000c0 /* Non-cachable imprecise */
84#define MMUDR_SZ_1MB 0x00000000 /* 1MB page size */
85#define MMUDR_SZ_4KB 0x00000100 /* 4kB page size */
86#define MMUDR_SZ_8KB 0x00000200 /* 8kB page size */
87#define MMUDR_SZ_1KB 0x00000300 /* 1kB page size */
88#define MMUDR_PAN 10 /* Physical address */
89#define MMUDR_PAMASK 0xfffffc00 /* PA mask */
90
91#ifndef __ASSEMBLY__
92
93/*
94 * Simple access functions for the MMU registers. Nothing fancy
95 * currently required, just simple 32bit access.
96 */
97static inline u32 mmu_read(u32 a)
98{
99 return *((volatile u32 *) a);
100}
101
102static inline void mmu_write(u32 a, u32 v)
103{
104 *((volatile u32 *) a) = v;
105 __asm__ __volatile__ ("nop");
106}
107
108int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word);
109
110#endif
111
112#endif /* MCFMMU_H */
diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h
index 7b51416ccae..39d90d51111 100644
--- a/arch/m68k/include/asm/mcfqspi.h
+++ b/arch/m68k/include/asm/mcfqspi.h
@@ -21,6 +21,15 @@
21#ifndef mcfqspi_h 21#ifndef mcfqspi_h
22#define mcfqspi_h 22#define mcfqspi_h
23 23
24#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
25#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
26#elif defined(CONFIG_M5249)
27#define MCFQSPI_IOBASE (MCF_MBAR + 0x300)
28#elif defined(CONFIG_M520x) || defined(CONFIG_M532x)
29#define MCFQSPI_IOBASE 0xFC058000
30#endif
31#define MCFQSPI_IOSIZE 0x40
32
24/** 33/**
25 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver 34 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
26 * @setup: setup the control; allocate gpio's, etc. May be NULL. 35 * @setup: setup the control; allocate gpio's, etc. May be NULL.
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index a04fd9b2714..ebd0304054a 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -24,8 +24,8 @@
24#elif defined(CONFIG_M523x) 24#elif defined(CONFIG_M523x)
25#include <asm/m523xsim.h> 25#include <asm/m523xsim.h>
26#include <asm/mcfintc.h> 26#include <asm/mcfintc.h>
27#elif defined(CONFIG_M5249) || defined(CONFIG_M525x) 27#elif defined(CONFIG_M5249)
28#include <asm/m525xsim.h> 28#include <asm/m5249sim.h>
29#include <asm/mcfintc.h> 29#include <asm/mcfintc.h>
30#elif defined(CONFIG_M527x) 30#elif defined(CONFIG_M527x)
31#include <asm/m527xsim.h> 31#include <asm/m527xsim.h>
@@ -43,8 +43,6 @@
43#include <asm/mcfintc.h> 43#include <asm/mcfintc.h>
44#elif defined(CONFIG_M54xx) 44#elif defined(CONFIG_M54xx)
45#include <asm/m54xxsim.h> 45#include <asm/m54xxsim.h>
46#elif defined(CONFIG_M5441x)
47#include <asm/m5441xsim.h>
48#endif 46#endif
49 47
50/****************************************************************************/ 48/****************************************************************************/
diff --git a/arch/m68k/include/asm/mcfslt.h b/arch/m68k/include/asm/mcfslt.h
index c2314b6f8ca..d0d0ecba533 100644
--- a/arch/m68k/include/asm/mcfslt.h
+++ b/arch/m68k/include/asm/mcfslt.h
@@ -13,6 +13,13 @@
13/****************************************************************************/ 13/****************************************************************************/
14 14
15/* 15/*
16 * Get address specific defines for the 547x.
17 */
18#define MCFSLT_TIMER0 0x900 /* Base address of TIMER0 */
19#define MCFSLT_TIMER1 0x910 /* Base address of TIMER1 */
20
21
22/*
16 * Define the SLT timer register set addresses. 23 * Define the SLT timer register set addresses.
17 */ 24 */
18#define MCFSLT_STCNT 0x00 /* Terminal count */ 25#define MCFSLT_STCNT 0x00 /* Terminal count */
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index da2fa43c2e4..351c2723787 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -19,7 +19,7 @@
19#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ 19#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
20#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ 20#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
21#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ 21#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
22#if defined(CONFIG_M532x) || defined(CONFIG_M5441x) 22#if defined(CONFIG_M532x)
23#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ 23#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
24#else 24#else
25#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ 25#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index b40c20f6664..2abedff0a69 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -41,10 +41,7 @@ struct mcf_platform_uart {
41#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ 41#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
42#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ 42#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
43#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ 43#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
44#endif 44#else
45#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
46 defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
47 defined(CONFIG_M5307) || defined(CONFIG_M5407)
48#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ 45#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
49#endif 46#endif
50#define MCFUART_UIPR 0x34 /* Input Port (r) */ 47#define MCFUART_UIPR 0x34 /* Input Port (r) */
diff --git a/arch/m68k/include/asm/mmu_context.h b/arch/m68k/include/asm/mmu_context.h
index dc3be991d63..7d4341e55a9 100644
--- a/arch/m68k/include/asm/mmu_context.h
+++ b/arch/m68k/include/asm/mmu_context.h
@@ -8,206 +8,7 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
8} 8}
9 9
10#ifdef CONFIG_MMU 10#ifdef CONFIG_MMU
11 11#ifndef CONFIG_SUN3
12#if defined(CONFIG_COLDFIRE)
13
14#include <asm/atomic.h>
15#include <asm/bitops.h>
16#include <asm/mcfmmu.h>
17#include <asm/mmu.h>
18
19#define NO_CONTEXT 256
20#define LAST_CONTEXT 255
21#define FIRST_CONTEXT 1
22
23extern unsigned long context_map[];
24extern mm_context_t next_mmu_context;
25
26extern atomic_t nr_free_contexts;
27extern struct mm_struct *context_mm[LAST_CONTEXT+1];
28extern void steal_context(void);
29
30static inline void get_mmu_context(struct mm_struct *mm)
31{
32 mm_context_t ctx;
33
34 if (mm->context != NO_CONTEXT)
35 return;
36 while (atomic_dec_and_test_lt(&nr_free_contexts)) {
37 atomic_inc(&nr_free_contexts);
38 steal_context();
39 }
40 ctx = next_mmu_context;
41 while (test_and_set_bit(ctx, context_map)) {
42 ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
43 if (ctx > LAST_CONTEXT)
44 ctx = 0;
45 }
46 next_mmu_context = (ctx + 1) & LAST_CONTEXT;
47 mm->context = ctx;
48 context_mm[ctx] = mm;
49}
50
51/*
52 * Set up the context for a new address space.
53 */
54#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0)
55
56/*
57 * We're finished using the context for an address space.
58 */
59static inline void destroy_context(struct mm_struct *mm)
60{
61 if (mm->context != NO_CONTEXT) {
62 clear_bit(mm->context, context_map);
63 mm->context = NO_CONTEXT;
64 atomic_inc(&nr_free_contexts);
65 }
66}
67
68static inline void set_context(mm_context_t context, pgd_t *pgd)
69{
70 __asm__ __volatile__ ("movec %0,%%asid" : : "d" (context));
71}
72
73static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
74 struct task_struct *tsk)
75{
76 get_mmu_context(tsk->mm);
77 set_context(tsk->mm->context, next->pgd);
78}
79
80/*
81 * After we have set current->mm to a new value, this activates
82 * the context for the new mm so we see the new mappings.
83 */
84static inline void activate_mm(struct mm_struct *active_mm,
85 struct mm_struct *mm)
86{
87 get_mmu_context(mm);
88 set_context(mm->context, mm->pgd);
89}
90
91#define deactivate_mm(tsk, mm) do { } while (0)
92
93extern void mmu_context_init(void);
94#define prepare_arch_switch(next) load_ksp_mmu(next)
95
96static inline void load_ksp_mmu(struct task_struct *task)
97{
98 unsigned long flags;
99 struct mm_struct *mm;
100 int asid;
101 pgd_t *pgd;
102 pmd_t *pmd;
103 pte_t *pte;
104 unsigned long mmuar;
105
106 local_irq_save(flags);
107 mmuar = task->thread.ksp;
108
109 /* Search for a valid TLB entry, if one is found, don't remap */
110 mmu_write(MMUAR, mmuar);
111 mmu_write(MMUOR, MMUOR_STLB | MMUOR_ADR);
112 if (mmu_read(MMUSR) & MMUSR_HIT)
113 goto end;
114
115 if (mmuar >= PAGE_OFFSET) {
116 mm = &init_mm;
117 } else {
118 pr_info("load_ksp_mmu: non-kernel mm found: 0x%p\n", task->mm);
119 mm = task->mm;
120 }
121
122 if (!mm)
123 goto bug;
124
125 pgd = pgd_offset(mm, mmuar);
126 if (pgd_none(*pgd))
127 goto bug;
128
129 pmd = pmd_offset(pgd, mmuar);
130 if (pmd_none(*pmd))
131 goto bug;
132
133 pte = (mmuar >= PAGE_OFFSET) ? pte_offset_kernel(pmd, mmuar)
134 : pte_offset_map(pmd, mmuar);
135 if (pte_none(*pte) || !pte_present(*pte))
136 goto bug;
137
138 set_pte(pte, pte_mkyoung(*pte));
139 asid = mm->context & 0xff;
140 if (!pte_dirty(*pte) && mmuar <= PAGE_OFFSET)
141 set_pte(pte, pte_wrprotect(*pte));
142
143 mmu_write(MMUTR, (mmuar & PAGE_MASK) | (asid << MMUTR_IDN) |
144 (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK)
145 >> CF_PAGE_MMUTR_SHIFT) | MMUTR_V);
146
147 mmu_write(MMUDR, (pte_val(*pte) & PAGE_MASK) |
148 ((pte->pte) & CF_PAGE_MMUDR_MASK) | MMUDR_SZ_8KB | MMUDR_X);
149
150 mmu_write(MMUOR, MMUOR_ACC | MMUOR_UAA);
151
152 goto end;
153
154bug:
155 pr_info("ksp load failed: mm=0x%p ksp=0x08%lx\n", mm, mmuar);
156end:
157 local_irq_restore(flags);
158}
159
160#elif defined(CONFIG_SUN3)
161#include <asm/sun3mmu.h>
162#include <linux/sched.h>
163
164extern unsigned long get_free_context(struct mm_struct *mm);
165extern void clear_context(unsigned long context);
166
167/* set the context for a new task to unmapped */
168static inline int init_new_context(struct task_struct *tsk,
169 struct mm_struct *mm)
170{
171 mm->context = SUN3_INVALID_CONTEXT;
172 return 0;
173}
174
175/* find the context given to this process, and if it hasn't already
176 got one, go get one for it. */
177static inline void get_mmu_context(struct mm_struct *mm)
178{
179 if (mm->context == SUN3_INVALID_CONTEXT)
180 mm->context = get_free_context(mm);
181}
182
183/* flush context if allocated... */
184static inline void destroy_context(struct mm_struct *mm)
185{
186 if (mm->context != SUN3_INVALID_CONTEXT)
187 clear_context(mm->context);
188}
189
190static inline void activate_context(struct mm_struct *mm)
191{
192 get_mmu_context(mm);
193 sun3_put_context(mm->context);
194}
195
196static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
197 struct task_struct *tsk)
198{
199 activate_context(tsk->mm);
200}
201
202#define deactivate_mm(tsk, mm) do { } while (0)
203
204static inline void activate_mm(struct mm_struct *prev_mm,
205 struct mm_struct *next_mm)
206{
207 activate_context(next_mm);
208}
209
210#else
211 12
212#include <asm/setup.h> 13#include <asm/setup.h>
213#include <asm/page.h> 14#include <asm/page.h>
@@ -302,8 +103,55 @@ static inline void activate_mm(struct mm_struct *prev_mm,
302 switch_mm_0460(next_mm); 103 switch_mm_0460(next_mm);
303} 104}
304 105
305#endif 106#else /* CONFIG_SUN3 */
107#include <asm/sun3mmu.h>
108#include <linux/sched.h>
109
110extern unsigned long get_free_context(struct mm_struct *mm);
111extern void clear_context(unsigned long context);
112
113/* set the context for a new task to unmapped */
114static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
115{
116 mm->context = SUN3_INVALID_CONTEXT;
117 return 0;
118}
119
120/* find the context given to this process, and if it hasn't already
121 got one, go get one for it. */
122static inline void get_mmu_context(struct mm_struct *mm)
123{
124 if(mm->context == SUN3_INVALID_CONTEXT)
125 mm->context = get_free_context(mm);
126}
127
128/* flush context if allocated... */
129static inline void destroy_context(struct mm_struct *mm)
130{
131 if(mm->context != SUN3_INVALID_CONTEXT)
132 clear_context(mm->context);
133}
134
135static inline void activate_context(struct mm_struct *mm)
136{
137 get_mmu_context(mm);
138 sun3_put_context(mm->context);
139}
306 140
141static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)
142{
143 activate_context(tsk->mm);
144}
145
146#define deactivate_mm(tsk,mm) do { } while (0)
147
148static inline void activate_mm(struct mm_struct *prev_mm,
149 struct mm_struct *next_mm)
150{
151 activate_context(next_mm);
152}
153
154#endif
307#else /* !CONFIG_MMU */ 155#else /* !CONFIG_MMU */
308 156
309static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) 157static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
diff --git a/arch/m68k/include/asm/module.h b/arch/m68k/include/asm/module.h
index 8b58fce843d..edffe66b7f4 100644
--- a/arch/m68k/include/asm/module.h
+++ b/arch/m68k/include/asm/module.h
@@ -1,8 +1,6 @@
1#ifndef _ASM_M68K_MODULE_H 1#ifndef _ASM_M68K_MODULE_H
2#define _ASM_M68K_MODULE_H 2#define _ASM_M68K_MODULE_H
3 3
4#include <asm-generic/module.h>
5
6enum m68k_fixup_type { 4enum m68k_fixup_type {
7 m68k_fixup_memoffset, 5 m68k_fixup_memoffset,
8 m68k_fixup_vnode_shift, 6 m68k_fixup_vnode_shift,
@@ -38,4 +36,8 @@ struct module;
38extern void module_fixup(struct module *mod, struct m68k_fixup_info *start, 36extern void module_fixup(struct module *mod, struct m68k_fixup_info *start,
39 struct m68k_fixup_info *end); 37 struct m68k_fixup_info *end);
40 38
39#define Elf_Shdr Elf32_Shdr
40#define Elf_Sym Elf32_Sym
41#define Elf_Ehdr Elf32_Ehdr
42
41#endif /* _ASM_M68K_MODULE_H */ 43#endif /* _ASM_M68K_MODULE_H */
diff --git a/arch/m68k/include/asm/motorola_pgtable.h b/arch/m68k/include/asm/motorola_pgtable.h
index e0fdd4d0807..45bd3f589bf 100644
--- a/arch/m68k/include/asm/motorola_pgtable.h
+++ b/arch/m68k/include/asm/motorola_pgtable.h
@@ -8,7 +8,6 @@
8#define _PAGE_PRESENT 0x001 8#define _PAGE_PRESENT 0x001
9#define _PAGE_SHORT 0x002 9#define _PAGE_SHORT 0x002
10#define _PAGE_RONLY 0x004 10#define _PAGE_RONLY 0x004
11#define _PAGE_READWRITE 0x000
12#define _PAGE_ACCESSED 0x008 11#define _PAGE_ACCESSED 0x008
13#define _PAGE_DIRTY 0x010 12#define _PAGE_DIRTY 0x010
14#define _PAGE_SUPER 0x080 /* 68040 supervisor only */ 13#define _PAGE_SUPER 0x080 /* 68040 supervisor only */
diff --git a/arch/m68k/include/asm/nettel.h b/arch/m68k/include/asm/nettel.h
index 2a7a7667d80..4dec2d9fb99 100644
--- a/arch/m68k/include/asm/nettel.h
+++ b/arch/m68k/include/asm/nettel.h
@@ -21,7 +21,6 @@
21#ifdef CONFIG_COLDFIRE 21#ifdef CONFIG_COLDFIRE
22#include <asm/coldfire.h> 22#include <asm/coldfire.h>
23#include <asm/mcfsim.h> 23#include <asm/mcfsim.h>
24#include <asm/io.h>
25#endif 24#endif
26 25
27/*---------------------------------------------------------------------------*/ 26/*---------------------------------------------------------------------------*/
@@ -87,12 +86,16 @@ static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
87 */ 86 */
88static __inline__ unsigned int mcf_getppdata(void) 87static __inline__ unsigned int mcf_getppdata(void)
89{ 88{
90 return readw(MCFSIM_PBDAT); 89 volatile unsigned short *pp;
90 pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
91 return((unsigned int) *pp);
91} 92}
92 93
93static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) 94static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
94{ 95{
95 write((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT); 96 volatile unsigned short *pp;
97 pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
98 *pp = (*pp & ~mask) | bits;
96} 99}
97#endif 100#endif
98 101
diff --git a/arch/m68k/include/asm/page.h b/arch/m68k/include/asm/page.h
index 7c360dac00b..dfebb7c1e37 100644
--- a/arch/m68k/include/asm/page.h
+++ b/arch/m68k/include/asm/page.h
@@ -6,10 +6,10 @@
6#include <asm/page_offset.h> 6#include <asm/page_offset.h>
7 7
8/* PAGE_SHIFT determines the page size */ 8/* PAGE_SHIFT determines the page size */
9#if defined(CONFIG_SUN3) || defined(CONFIG_COLDFIRE) 9#ifndef CONFIG_SUN3
10#define PAGE_SHIFT 13 10#define PAGE_SHIFT (12)
11#else 11#else
12#define PAGE_SHIFT 12 12#define PAGE_SHIFT (13)
13#endif 13#endif
14#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) 14#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
15#define PAGE_MASK (~(PAGE_SIZE-1)) 15#define PAGE_MASK (~(PAGE_SIZE-1))
@@ -36,16 +36,12 @@ typedef struct page *pgtable_t;
36#define __pgd(x) ((pgd_t) { (x) } ) 36#define __pgd(x) ((pgd_t) { (x) } )
37#define __pgprot(x) ((pgprot_t) { (x) } ) 37#define __pgprot(x) ((pgprot_t) { (x) } )
38 38
39extern unsigned long _rambase;
40extern unsigned long _ramstart;
41extern unsigned long _ramend;
42
43#endif /* !__ASSEMBLY__ */ 39#endif /* !__ASSEMBLY__ */
44 40
45#ifdef CONFIG_MMU 41#ifdef CONFIG_MMU
46#include <asm/page_mm.h> 42#include "page_mm.h"
47#else 43#else
48#include <asm/page_no.h> 44#include "page_no.h"
49#endif 45#endif
50 46
51#include <asm-generic/getorder.h> 47#include <asm-generic/getorder.h>
diff --git a/arch/m68k/include/asm/page_no.h b/arch/m68k/include/asm/page_no.h
index ef209169579..90595721185 100644
--- a/arch/m68k/include/asm/page_no.h
+++ b/arch/m68k/include/asm/page_no.h
@@ -26,7 +26,7 @@ extern unsigned long memory_end;
26#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT) 26#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
27 27
28#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) 28#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
29#define page_to_virt(page) __va(((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)) 29#define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
30 30
31#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn)) 31#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn))
32#define page_to_pfn(page) virt_to_pfn(page_to_virt(page)) 32#define page_to_pfn(page) virt_to_pfn(page_to_virt(page))
diff --git a/arch/m68k/include/asm/page_offset.h b/arch/m68k/include/asm/page_offset.h
index 82626a8f1d0..1780152d81d 100644
--- a/arch/m68k/include/asm/page_offset.h
+++ b/arch/m68k/include/asm/page_offset.h
@@ -1,9 +1,11 @@
1/* This handles the memory map.. */ 1/* This handles the memory map.. */
2 2
3#if defined(CONFIG_RAMBASE) 3#ifdef CONFIG_MMU
4#define PAGE_OFFSET_RAW CONFIG_RAMBASE 4#ifndef CONFIG_SUN3
5#elif defined(CONFIG_SUN3) 5#define PAGE_OFFSET_RAW 0x00000000
6#else
6#define PAGE_OFFSET_RAW 0x0E000000 7#define PAGE_OFFSET_RAW 0x0E000000
8#endif
7#else 9#else
8#define PAGE_OFFSET_RAW 0x00000000 10#define PAGE_OFFSET_RAW CONFIG_RAMBASE
9#endif 11#endif
diff --git a/arch/m68k/include/asm/parport.h b/arch/m68k/include/asm/parport.h
index 5ea75e6a739..646b1872f73 100644
--- a/arch/m68k/include/asm/parport.h
+++ b/arch/m68k/include/asm/parport.h
@@ -15,8 +15,8 @@
15#define outsl(port,buf,len) isa_outsb(port,buf,(len)<<2) 15#define outsl(port,buf,len) isa_outsb(port,buf,(len)<<2)
16 16
17/* no dma, or IRQ autoprobing */ 17/* no dma, or IRQ autoprobing */
18static int parport_pc_find_isa_ports (int autoirq, int autodma); 18static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
19static int parport_pc_find_nonpci_ports (int autoirq, int autodma) 19static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
20{ 20{
21 if (! (MACH_IS_Q40)) 21 if (! (MACH_IS_Q40))
22 return 0; /* count=0 */ 22 return 0; /* count=0 */
diff --git a/arch/m68k/include/asm/pci.h b/arch/m68k/include/asm/pci.h
index 848c3dfaad5..4ad0aea48ab 100644
--- a/arch/m68k/include/asm/pci.h
+++ b/arch/m68k/include/asm/pci.h
@@ -2,7 +2,6 @@
2#define _ASM_M68K_PCI_H 2#define _ASM_M68K_PCI_H
3 3
4#include <asm-generic/pci-dma-compat.h> 4#include <asm-generic/pci-dma-compat.h>
5#include <asm-generic/pci.h>
6 5
7/* The PCI address space does equal the physical memory 6/* The PCI address space does equal the physical memory
8 * address space. The networking and block device layers use 7 * address space. The networking and block device layers use
@@ -10,9 +9,4 @@
10 */ 9 */
11#define PCI_DMA_BUS_IS_PHYS (1) 10#define PCI_DMA_BUS_IS_PHYS (1)
12 11
13#define pcibios_assign_all_busses() 1
14
15#define PCIBIOS_MIN_IO 0x00000100
16#define PCIBIOS_MIN_MEM 0x02000000
17
18#endif /* _ASM_M68K_PCI_H */ 12#endif /* _ASM_M68K_PCI_H */
diff --git a/arch/m68k/include/asm/pgalloc.h b/arch/m68k/include/asm/pgalloc.h
index 37bee7e3223..c294aad8a90 100644
--- a/arch/m68k/include/asm/pgalloc.h
+++ b/arch/m68k/include/asm/pgalloc.h
@@ -7,9 +7,7 @@
7 7
8#ifdef CONFIG_MMU 8#ifdef CONFIG_MMU
9#include <asm/virtconvert.h> 9#include <asm/virtconvert.h>
10#if defined(CONFIG_COLDFIRE) 10#ifdef CONFIG_SUN3
11#include <asm/mcf_pgalloc.h>
12#elif defined(CONFIG_SUN3)
13#include <asm/sun3_pgalloc.h> 11#include <asm/sun3_pgalloc.h>
14#else 12#else
15#include <asm/motorola_pgalloc.h> 13#include <asm/motorola_pgalloc.h>
diff --git a/arch/m68k/include/asm/pgtable.h b/arch/m68k/include/asm/pgtable.h
index a3d733b524d..ee6759eb445 100644
--- a/arch/m68k/include/asm/pgtable.h
+++ b/arch/m68k/include/asm/pgtable.h
@@ -1,5 +1,5 @@
1#ifdef __uClinux__ 1#ifdef __uClinux__
2#include <asm/pgtable_no.h> 2#include "pgtable_no.h"
3#else 3#else
4#include <asm/pgtable_mm.h> 4#include "pgtable_mm.h"
5#endif 5#endif
diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h
index dc35e0e106e..87174c904d2 100644
--- a/arch/m68k/include/asm/pgtable_mm.h
+++ b/arch/m68k/include/asm/pgtable_mm.h
@@ -40,8 +40,6 @@
40/* PGDIR_SHIFT determines what a third-level page table entry can map */ 40/* PGDIR_SHIFT determines what a third-level page table entry can map */
41#ifdef CONFIG_SUN3 41#ifdef CONFIG_SUN3
42#define PGDIR_SHIFT 17 42#define PGDIR_SHIFT 17
43#elif defined(CONFIG_COLDFIRE)
44#define PGDIR_SHIFT 22
45#else 43#else
46#define PGDIR_SHIFT 25 44#define PGDIR_SHIFT 25
47#endif 45#endif
@@ -56,10 +54,6 @@
56#define PTRS_PER_PTE 16 54#define PTRS_PER_PTE 16
57#define PTRS_PER_PMD 1 55#define PTRS_PER_PMD 1
58#define PTRS_PER_PGD 2048 56#define PTRS_PER_PGD 2048
59#elif defined(CONFIG_COLDFIRE)
60#define PTRS_PER_PTE 512
61#define PTRS_PER_PMD 1
62#define PTRS_PER_PGD 1024
63#else 57#else
64#define PTRS_PER_PTE 1024 58#define PTRS_PER_PTE 1024
65#define PTRS_PER_PMD 8 59#define PTRS_PER_PMD 8
@@ -72,22 +66,12 @@
72#ifdef CONFIG_SUN3 66#ifdef CONFIG_SUN3
73#define KMAP_START 0x0DC00000 67#define KMAP_START 0x0DC00000
74#define KMAP_END 0x0E000000 68#define KMAP_END 0x0E000000
75#elif defined(CONFIG_COLDFIRE)
76#define KMAP_START 0xe0000000
77#define KMAP_END 0xf0000000
78#else 69#else
79#define KMAP_START 0xd0000000 70#define KMAP_START 0xd0000000
80#define KMAP_END 0xf0000000 71#define KMAP_END 0xf0000000
81#endif 72#endif
82 73
83#ifdef CONFIG_SUN3 74#ifndef CONFIG_SUN3
84extern unsigned long m68k_vmalloc_end;
85#define VMALLOC_START 0x0f800000
86#define VMALLOC_END m68k_vmalloc_end
87#elif defined(CONFIG_COLDFIRE)
88#define VMALLOC_START 0xd0000000
89#define VMALLOC_END 0xe0000000
90#else
91/* Just any arbitrary offset to the start of the vmalloc VM area: the 75/* Just any arbitrary offset to the start of the vmalloc VM area: the
92 * current 8MB value just means that there will be a 8MB "hole" after the 76 * current 8MB value just means that there will be a 8MB "hole" after the
93 * physical memory until the kernel virtual memory starts. That means that 77 * physical memory until the kernel virtual memory starts. That means that
@@ -98,7 +82,11 @@ extern unsigned long m68k_vmalloc_end;
98#define VMALLOC_OFFSET (8*1024*1024) 82#define VMALLOC_OFFSET (8*1024*1024)
99#define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) 83#define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
100#define VMALLOC_END KMAP_START 84#define VMALLOC_END KMAP_START
101#endif 85#else
86extern unsigned long m68k_vmalloc_end;
87#define VMALLOC_START 0x0f800000
88#define VMALLOC_END m68k_vmalloc_end
89#endif /* CONFIG_SUN3 */
102 90
103/* zero page used for uninitialized stuff */ 91/* zero page used for uninitialized stuff */
104extern void *empty_zero_page; 92extern void *empty_zero_page;
@@ -142,8 +130,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
142 130
143#ifdef CONFIG_SUN3 131#ifdef CONFIG_SUN3
144#include <asm/sun3_pgtable.h> 132#include <asm/sun3_pgtable.h>
145#elif defined(CONFIG_COLDFIRE)
146#include <asm/mcf_pgtable.h>
147#else 133#else
148#include <asm/motorola_pgtable.h> 134#include <asm/motorola_pgtable.h>
149#endif 135#endif
@@ -152,9 +138,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
152/* 138/*
153 * Macro to mark a page protection value as "uncacheable". 139 * Macro to mark a page protection value as "uncacheable".
154 */ 140 */
155#ifdef CONFIG_COLDFIRE
156# define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | CF_PAGE_NOCACHE))
157#else
158#ifdef SUN3_PAGE_NOCACHE 141#ifdef SUN3_PAGE_NOCACHE
159# define __SUN3_PAGE_NOCACHE SUN3_PAGE_NOCACHE 142# define __SUN3_PAGE_NOCACHE SUN3_PAGE_NOCACHE
160#else 143#else
@@ -169,7 +152,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
169 ? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \ 152 ? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \
170 : (prot))) 153 : (prot)))
171 154
172#endif /* CONFIG_COLDFIRE */
173#include <asm-generic/pgtable.h> 155#include <asm-generic/pgtable.h>
174#endif /* !__ASSEMBLY__ */ 156#endif /* !__ASSEMBLY__ */
175 157
diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h
index ae700f49e51..d8ef53ac03f 100644
--- a/arch/m68k/include/asm/processor.h
+++ b/arch/m68k/include/asm/processor.h
@@ -48,12 +48,10 @@ static inline void wrusp(unsigned long usp)
48 * so don't change it unless you know what you are doing. 48 * so don't change it unless you know what you are doing.
49 */ 49 */
50#ifdef CONFIG_MMU 50#ifdef CONFIG_MMU
51#if defined(CONFIG_COLDFIRE) 51#ifndef CONFIG_SUN3
52#define TASK_SIZE (0xC0000000UL)
53#elif defined(CONFIG_SUN3)
54#define TASK_SIZE (0x0E000000UL)
55#else
56#define TASK_SIZE (0xF0000000UL) 52#define TASK_SIZE (0xF0000000UL)
53#else
54#define TASK_SIZE (0x0E000000UL)
57#endif 55#endif
58#else 56#else
59#define TASK_SIZE (0xFFFFFFFFUL) 57#define TASK_SIZE (0xFFFFFFFFUL)
@@ -68,12 +66,10 @@ static inline void wrusp(unsigned long usp)
68 * space during mmap's. 66 * space during mmap's.
69 */ 67 */
70#ifdef CONFIG_MMU 68#ifdef CONFIG_MMU
71#if defined(CONFIG_COLDFIRE) 69#ifndef CONFIG_SUN3
72#define TASK_UNMAPPED_BASE 0x60000000UL
73#elif defined(CONFIG_SUN3)
74#define TASK_UNMAPPED_BASE 0x0A000000UL
75#else
76#define TASK_UNMAPPED_BASE 0xC0000000UL 70#define TASK_UNMAPPED_BASE 0xC0000000UL
71#else
72#define TASK_UNMAPPED_BASE 0x0A000000UL
77#endif 73#endif
78#define TASK_UNMAPPED_ALIGN(addr, off) PAGE_ALIGN(addr) 74#define TASK_UNMAPPED_ALIGN(addr, off) PAGE_ALIGN(addr)
79#else 75#else
@@ -92,24 +88,16 @@ struct thread_struct {
92 unsigned long fp[8*3]; 88 unsigned long fp[8*3];
93 unsigned long fpcntl[3]; /* fp control regs */ 89 unsigned long fpcntl[3]; /* fp control regs */
94 unsigned char fpstate[FPSTATESIZE]; /* floating point state */ 90 unsigned char fpstate[FPSTATESIZE]; /* floating point state */
91 struct thread_info info;
95}; 92};
96 93
97#define INIT_THREAD { \ 94#define INIT_THREAD { \
98 .ksp = sizeof(init_stack) + (unsigned long) init_stack, \ 95 .ksp = sizeof(init_stack) + (unsigned long) init_stack, \
99 .sr = PS_S, \ 96 .sr = PS_S, \
100 .fs = __KERNEL_DS, \ 97 .fs = __KERNEL_DS, \
98 .info = INIT_THREAD_INFO(init_task), \
101} 99}
102 100
103/*
104 * ColdFire stack format sbould be 0x4 for an aligned usp (will always be
105 * true on thread creation). We need to set this explicitly.
106 */
107#ifdef CONFIG_COLDFIRE
108#define setframeformat(_regs) do { (_regs)->format = 0x4; } while(0)
109#else
110#define setframeformat(_regs) do { } while (0)
111#endif
112
113#ifdef CONFIG_MMU 101#ifdef CONFIG_MMU
114/* 102/*
115 * Do necessary setup to start up a newly executed thread. 103 * Do necessary setup to start up a newly executed thread.
@@ -119,7 +107,6 @@ static inline void start_thread(struct pt_regs * regs, unsigned long pc,
119{ 107{
120 regs->pc = pc; 108 regs->pc = pc;
121 regs->sr &= ~0x2000; 109 regs->sr &= ~0x2000;
122 setframeformat(regs);
123 wrusp(usp); 110 wrusp(usp);
124} 111}
125 112
@@ -127,23 +114,27 @@ extern int handle_kernel_fault(struct pt_regs *regs);
127 114
128#else 115#else
129 116
117/*
118 * Coldfire stacks need to be re-aligned on trap exit, conventional
119 * 68k can handle this case cleanly.
120 */
121#ifdef CONFIG_COLDFIRE
122#define reformat(_regs) do { (_regs)->format = 0x4; } while(0)
123#else
124#define reformat(_regs) do { } while (0)
125#endif
126
130#define start_thread(_regs, _pc, _usp) \ 127#define start_thread(_regs, _pc, _usp) \
131do { \ 128do { \
132 (_regs)->pc = (_pc); \ 129 (_regs)->pc = (_pc); \
133 ((struct switch_stack *)(_regs))[-1].a6 = 0; \ 130 ((struct switch_stack *)(_regs))[-1].a6 = 0; \
134 setframeformat(_regs); \ 131 reformat(_regs); \
135 if (current->mm) \ 132 if (current->mm) \
136 (_regs)->d5 = current->mm->start_data; \ 133 (_regs)->d5 = current->mm->start_data; \
137 (_regs)->sr &= ~0x2000; \ 134 (_regs)->sr &= ~0x2000; \
138 wrusp(_usp); \ 135 wrusp(_usp); \
139} while(0) 136} while(0)
140 137
141static inline int handle_kernel_fault(struct pt_regs *regs)
142{
143 /* Any fault in kernel is fatal on non-mmu */
144 return 0;
145}
146
147#endif 138#endif
148 139
149/* Forward declaration, a strange C thing */ 140/* Forward declaration, a strange C thing */
@@ -154,6 +145,11 @@ static inline void release_thread(struct task_struct *dead_task)
154{ 145{
155} 146}
156 147
148/* Prepare to copy thread state - unlazy all lazy status */
149#define prepare_to_copy(tsk) do { } while (0)
150
151extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
152
157/* 153/*
158 * Free current thread data structures etc.. 154 * Free current thread data structures etc..
159 */ 155 */
diff --git a/arch/m68k/include/asm/ptrace.h b/arch/m68k/include/asm/ptrace.h
index a45cb6894ad..65322b17b6c 100644
--- a/arch/m68k/include/asm/ptrace.h
+++ b/arch/m68k/include/asm/ptrace.h
@@ -1,10 +1,82 @@
1#ifndef _M68K_PTRACE_H 1#ifndef _M68K_PTRACE_H
2#define _M68K_PTRACE_H 2#define _M68K_PTRACE_H
3 3
4#include <uapi/asm/ptrace.h> 4#define PT_D1 0
5#define PT_D2 1
6#define PT_D3 2
7#define PT_D4 3
8#define PT_D5 4
9#define PT_D6 5
10#define PT_D7 6
11#define PT_A0 7
12#define PT_A1 8
13#define PT_A2 9
14#define PT_A3 10
15#define PT_A4 11
16#define PT_A5 12
17#define PT_A6 13
18#define PT_D0 14
19#define PT_USP 15
20#define PT_ORIG_D0 16
21#define PT_SR 17
22#define PT_PC 18
5 23
6#ifndef __ASSEMBLY__ 24#ifndef __ASSEMBLY__
7 25
26/* this struct defines the way the registers are stored on the
27 stack during a system call. */
28
29struct pt_regs {
30 long d1;
31 long d2;
32 long d3;
33 long d4;
34 long d5;
35 long a0;
36 long a1;
37 long a2;
38 long d0;
39 long orig_d0;
40 long stkadj;
41#ifdef CONFIG_COLDFIRE
42 unsigned format : 4; /* frame format specifier */
43 unsigned vector : 12; /* vector offset */
44 unsigned short sr;
45 unsigned long pc;
46#else
47 unsigned short sr;
48 unsigned long pc;
49 unsigned format : 4; /* frame format specifier */
50 unsigned vector : 12; /* vector offset */
51#endif
52};
53
54/*
55 * This is the extended stack used by signal handlers and the context
56 * switcher: it's pushed after the normal "struct pt_regs".
57 */
58struct switch_stack {
59 unsigned long d6;
60 unsigned long d7;
61 unsigned long a3;
62 unsigned long a4;
63 unsigned long a5;
64 unsigned long a6;
65 unsigned long retpc;
66};
67
68/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
69#define PTRACE_GETREGS 12
70#define PTRACE_SETREGS 13
71#define PTRACE_GETFPREGS 14
72#define PTRACE_SETFPREGS 15
73
74#define PTRACE_GET_THREAD_AREA 25
75
76#define PTRACE_SINGLEBLOCK 33 /* resume execution until next branch */
77
78#ifdef __KERNEL__
79
8#ifndef PS_S 80#ifndef PS_S
9#define PS_S (0x2000) 81#define PS_S (0x2000)
10#define PS_M (0x1000) 82#define PS_M (0x1000)
@@ -13,9 +85,6 @@
13#define user_mode(regs) (!((regs)->sr & PS_S)) 85#define user_mode(regs) (!((regs)->sr & PS_S))
14#define instruction_pointer(regs) ((regs)->pc) 86#define instruction_pointer(regs) ((regs)->pc)
15#define profile_pc(regs) instruction_pointer(regs) 87#define profile_pc(regs) instruction_pointer(regs)
16#define current_pt_regs() \
17 (struct pt_regs *)((char *)current_thread_info() + THREAD_SIZE) - 1
18#define current_user_stack_pointer() rdusp()
19 88
20#define arch_has_single_step() (1) 89#define arch_has_single_step() (1)
21 90
@@ -23,5 +92,6 @@
23#define arch_has_block_step() (1) 92#define arch_has_block_step() (1)
24#endif 93#endif
25 94
95#endif /* __KERNEL__ */
26#endif /* __ASSEMBLY__ */ 96#endif /* __ASSEMBLY__ */
27#endif /* _M68K_PTRACE_H */ 97#endif /* _M68K_PTRACE_H */
diff --git a/arch/m68k/include/asm/q40_master.h b/arch/m68k/include/asm/q40_master.h
index fc5b36278d0..3907a09d4fc 100644
--- a/arch/m68k/include/asm/q40_master.h
+++ b/arch/m68k/include/asm/q40_master.h
@@ -60,7 +60,7 @@
60#define Q40_RTC_WRITE 128 60#define Q40_RTC_WRITE 128
61 61
62/* define some Q40 specific ints */ 62/* define some Q40 specific ints */
63#include <asm/q40ints.h> 63#include "q40ints.h"
64 64
65/* misc defs */ 65/* misc defs */
66#define DAC_LEFT ((unsigned char *)0xff008000) 66#define DAC_LEFT ((unsigned char *)0xff008000)
diff --git a/arch/m68k/include/asm/q40ints.h b/arch/m68k/include/asm/q40ints.h
index 22f12c9eb91..3d970afb708 100644
--- a/arch/m68k/include/asm/q40ints.h
+++ b/arch/m68k/include/asm/q40ints.h
@@ -24,3 +24,6 @@
24#define Q40_IRQ10_MASK (1<<5) 24#define Q40_IRQ10_MASK (1<<5)
25#define Q40_IRQ14_MASK (1<<6) 25#define Q40_IRQ14_MASK (1<<6)
26#define Q40_IRQ15_MASK (1<<7) 26#define Q40_IRQ15_MASK (1<<7)
27
28extern unsigned long q40_probe_irq_on (void);
29extern int q40_probe_irq_off (unsigned long irqs);
diff --git a/arch/m68k/include/asm/segment.h b/arch/m68k/include/asm/segment.h
index 0fa80e97ed2..ee959219fdf 100644
--- a/arch/m68k/include/asm/segment.h
+++ b/arch/m68k/include/asm/segment.h
@@ -22,26 +22,23 @@ typedef struct {
22} mm_segment_t; 22} mm_segment_t;
23 23
24#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) 24#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
25#define USER_DS MAKE_MM_SEG(__USER_DS)
26#define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS)
25 27
26#ifdef CONFIG_CPU_HAS_ADDRESS_SPACES
27/* 28/*
28 * Get/set the SFC/DFC registers for MOVES instructions 29 * Get/set the SFC/DFC registers for MOVES instructions
29 */ 30 */
30#define USER_DS MAKE_MM_SEG(__USER_DS)
31#define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS)
32 31
33static inline mm_segment_t get_fs(void) 32static inline mm_segment_t get_fs(void)
34{ 33{
34#ifdef CONFIG_MMU
35 mm_segment_t _v; 35 mm_segment_t _v;
36 __asm__ ("movec %/dfc,%0":"=r" (_v.seg):); 36 __asm__ ("movec %/dfc,%0":"=r" (_v.seg):);
37 return _v;
38}
39 37
40static inline void set_fs(mm_segment_t val) 38 return _v;
41{ 39#else
42 __asm__ __volatile__ ("movec %0,%/sfc\n\t" 40 return USER_DS;
43 "movec %0,%/dfc\n\t" 41#endif
44 : /* no outputs */ : "r" (val.seg) : "memory");
45} 42}
46 43
47static inline mm_segment_t get_ds(void) 44static inline mm_segment_t get_ds(void)
@@ -50,13 +47,14 @@ static inline mm_segment_t get_ds(void)
50 return KERNEL_DS; 47 return KERNEL_DS;
51} 48}
52 49
53#else 50static inline void set_fs(mm_segment_t val)
54#define USER_DS MAKE_MM_SEG(TASK_SIZE) 51{
55#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF) 52#ifdef CONFIG_MMU
56#define get_ds() (KERNEL_DS) 53 __asm__ __volatile__ ("movec %0,%/sfc\n\t"
57#define get_fs() (current_thread_info()->addr_limit) 54 "movec %0,%/dfc\n\t"
58#define set_fs(x) (current_thread_info()->addr_limit = (x)) 55 : /* no outputs */ : "r" (val.seg) : "memory");
59#endif 56#endif
57}
60 58
61#define segment_eq(a,b) ((a).seg == (b).seg) 59#define segment_eq(a,b) ((a).seg == (b).seg)
62 60
diff --git a/arch/m68k/include/asm/serial.h b/arch/m68k/include/asm/serial.h
index 7267536adbc..2b90d6e6907 100644
--- a/arch/m68k/include/asm/serial.h
+++ b/arch/m68k/include/asm/serial.h
@@ -25,11 +25,9 @@
25#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 25#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
26#endif 26#endif
27 27
28#ifdef CONFIG_ISA
29#define SERIAL_PORT_DFNS \ 28#define SERIAL_PORT_DFNS \
30 /* UART CLK PORT IRQ FLAGS */ \ 29 /* UART CLK PORT IRQ FLAGS */ \
31 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 30 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
32 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 31 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
33 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 32 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
34 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 33 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
35#endif
diff --git a/arch/m68k/include/asm/setup.h b/arch/m68k/include/asm/setup.h
index 65e78a2dad6..4dfb3952b37 100644
--- a/arch/m68k/include/asm/setup.h
+++ b/arch/m68k/include/asm/setup.h
@@ -19,12 +19,32 @@
19** Redesign of the boot information structure; moved boot information 19** Redesign of the boot information structure; moved boot information
20** structure to bootinfo.h 20** structure to bootinfo.h
21*/ 21*/
22
22#ifndef _M68K_SETUP_H 23#ifndef _M68K_SETUP_H
23#define _M68K_SETUP_H 24#define _M68K_SETUP_H
24 25
25#include <uapi/asm/setup.h>
26 26
27 27
28 /*
29 * Linux/m68k Architectures
30 */
31
32#define MACH_AMIGA 1
33#define MACH_ATARI 2
34#define MACH_MAC 3
35#define MACH_APOLLO 4
36#define MACH_SUN3 5
37#define MACH_MVME147 6
38#define MACH_MVME16x 7
39#define MACH_BVME6000 8
40#define MACH_HP300 9
41#define MACH_Q40 10
42#define MACH_SUN3X 11
43
44#define COMMAND_LINE_SIZE 256
45
46#ifdef __KERNEL__
47
28#define CL_SIZE COMMAND_LINE_SIZE 48#define CL_SIZE COMMAND_LINE_SIZE
29 49
30#ifndef __ASSEMBLY__ 50#ifndef __ASSEMBLY__
@@ -173,6 +193,57 @@ extern unsigned long m68k_machtype;
173# define MACH_TYPE (m68k_machtype) 193# define MACH_TYPE (m68k_machtype)
174#endif 194#endif
175 195
196#endif /* __KERNEL__ */
197
198
199 /*
200 * CPU, FPU and MMU types
201 *
202 * Note: we may rely on the following equalities:
203 *
204 * CPU_68020 == MMU_68851
205 * CPU_68030 == MMU_68030
206 * CPU_68040 == FPU_68040 == MMU_68040
207 * CPU_68060 == FPU_68060 == MMU_68060
208 */
209
210#define CPUB_68020 0
211#define CPUB_68030 1
212#define CPUB_68040 2
213#define CPUB_68060 3
214
215#define CPU_68020 (1<<CPUB_68020)
216#define CPU_68030 (1<<CPUB_68030)
217#define CPU_68040 (1<<CPUB_68040)
218#define CPU_68060 (1<<CPUB_68060)
219
220#define FPUB_68881 0
221#define FPUB_68882 1
222#define FPUB_68040 2 /* Internal FPU */
223#define FPUB_68060 3 /* Internal FPU */
224#define FPUB_SUNFPA 4 /* Sun-3 FPA */
225
226#define FPU_68881 (1<<FPUB_68881)
227#define FPU_68882 (1<<FPUB_68882)
228#define FPU_68040 (1<<FPUB_68040)
229#define FPU_68060 (1<<FPUB_68060)
230#define FPU_SUNFPA (1<<FPUB_SUNFPA)
231
232#define MMUB_68851 0
233#define MMUB_68030 1 /* Internal MMU */
234#define MMUB_68040 2 /* Internal MMU */
235#define MMUB_68060 3 /* Internal MMU */
236#define MMUB_APOLLO 4 /* Custom Apollo */
237#define MMUB_SUN3 5 /* Custom Sun-3 */
238
239#define MMU_68851 (1<<MMUB_68851)
240#define MMU_68030 (1<<MMUB_68030)
241#define MMU_68040 (1<<MMUB_68040)
242#define MMU_68060 (1<<MMUB_68060)
243#define MMU_SUN3 (1<<MMUB_SUN3)
244#define MMU_APOLLO (1<<MMUB_APOLLO)
245
246#ifdef __KERNEL__
176 247
177#ifndef __ASSEMBLY__ 248#ifndef __ASSEMBLY__
178extern unsigned long m68k_cputype; 249extern unsigned long m68k_cputype;
@@ -270,13 +341,6 @@ extern int m68k_is040or060;
270# endif 341# endif
271#endif 342#endif
272 343
273#if !defined(CONFIG_COLDFIRE)
274# define CPU_IS_COLDFIRE (0)
275#else
276# define CPU_IS_COLDFIRE (1)
277# define MMU_IS_COLDFIRE (1)
278#endif
279
280#define CPU_TYPE (m68k_cputype) 344#define CPU_TYPE (m68k_cputype)
281 345
282#ifdef CONFIG_M68KFPU_EMU 346#ifdef CONFIG_M68KFPU_EMU
@@ -307,4 +371,6 @@ extern int m68k_realnum_memory; /* real # of memory blocks found */
307extern struct mem_info m68k_memory[NUM_MEMINFO];/* memory description */ 371extern struct mem_info m68k_memory[NUM_MEMINFO];/* memory description */
308#endif 372#endif
309 373
374#endif /* __KERNEL__ */
375
310#endif /* _M68K_SETUP_H */ 376#endif /* _M68K_SETUP_H */
diff --git a/arch/m68k/include/asm/signal.h b/arch/m68k/include/asm/signal.h
index 9c8c46b06b0..60e88660169 100644
--- a/arch/m68k/include/asm/signal.h
+++ b/arch/m68k/include/asm/signal.h
@@ -1,8 +1,12 @@
1#ifndef _M68K_SIGNAL_H 1#ifndef _M68K_SIGNAL_H
2#define _M68K_SIGNAL_H 2#define _M68K_SIGNAL_H
3 3
4#include <uapi/asm/signal.h> 4#include <linux/types.h>
5 5
6/* Avoid too many header ordering problems. */
7struct siginfo;
8
9#ifdef __KERNEL__
6/* Most things should be clean enough to redefine this at will, if care 10/* Most things should be clean enough to redefine this at will, if care
7 is taken to make libc match. */ 11 is taken to make libc match. */
8 12
@@ -16,6 +20,92 @@ typedef struct {
16 unsigned long sig[_NSIG_WORDS]; 20 unsigned long sig[_NSIG_WORDS];
17} sigset_t; 21} sigset_t;
18 22
23#else
24/* Here we must cater to libcs that poke about in kernel headers. */
25
26#define NSIG 32
27typedef unsigned long sigset_t;
28
29#endif /* __KERNEL__ */
30
31#define SIGHUP 1
32#define SIGINT 2
33#define SIGQUIT 3
34#define SIGILL 4
35#define SIGTRAP 5
36#define SIGABRT 6
37#define SIGIOT 6
38#define SIGBUS 7
39#define SIGFPE 8
40#define SIGKILL 9
41#define SIGUSR1 10
42#define SIGSEGV 11
43#define SIGUSR2 12
44#define SIGPIPE 13
45#define SIGALRM 14
46#define SIGTERM 15
47#define SIGSTKFLT 16
48#define SIGCHLD 17
49#define SIGCONT 18
50#define SIGSTOP 19
51#define SIGTSTP 20
52#define SIGTTIN 21
53#define SIGTTOU 22
54#define SIGURG 23
55#define SIGXCPU 24
56#define SIGXFSZ 25
57#define SIGVTALRM 26
58#define SIGPROF 27
59#define SIGWINCH 28
60#define SIGIO 29
61#define SIGPOLL SIGIO
62/*
63#define SIGLOST 29
64*/
65#define SIGPWR 30
66#define SIGSYS 31
67#define SIGUNUSED 31
68
69/* These should not be considered constants from userland. */
70#define SIGRTMIN 32
71#define SIGRTMAX _NSIG
72
73/*
74 * SA_FLAGS values:
75 *
76 * SA_ONSTACK indicates that a registered stack_t will be used.
77 * SA_RESTART flag to get restarting signals (which were the default long ago)
78 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
79 * SA_RESETHAND clears the handler when the signal is delivered.
80 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
81 * SA_NODEFER prevents the current signal from being masked in the handler.
82 *
83 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
84 * Unix names RESETHAND and NODEFER respectively.
85 */
86#define SA_NOCLDSTOP 0x00000001
87#define SA_NOCLDWAIT 0x00000002
88#define SA_SIGINFO 0x00000004
89#define SA_ONSTACK 0x08000000
90#define SA_RESTART 0x10000000
91#define SA_NODEFER 0x40000000
92#define SA_RESETHAND 0x80000000
93
94#define SA_NOMASK SA_NODEFER
95#define SA_ONESHOT SA_RESETHAND
96
97/*
98 * sigaltstack controls
99 */
100#define SS_ONSTACK 1
101#define SS_DISABLE 2
102
103#define MINSIGSTKSZ 2048
104#define SIGSTKSZ 8192
105
106#include <asm-generic/signal-defs.h>
107
108#ifdef __KERNEL__
19struct old_sigaction { 109struct old_sigaction {
20 __sighandler_t sa_handler; 110 __sighandler_t sa_handler;
21 old_sigset_t sa_mask; 111 old_sigset_t sa_mask;
@@ -33,6 +123,31 @@ struct sigaction {
33struct k_sigaction { 123struct k_sigaction {
34 struct sigaction sa; 124 struct sigaction sa;
35}; 125};
126#else
127/* Here we must cater to libcs that poke about in kernel headers. */
128
129struct sigaction {
130 union {
131 __sighandler_t _sa_handler;
132 void (*_sa_sigaction)(int, struct siginfo *, void *);
133 } _u;
134 sigset_t sa_mask;
135 unsigned long sa_flags;
136 void (*sa_restorer)(void);
137};
138
139#define sa_handler _u._sa_handler
140#define sa_sigaction _u._sa_sigaction
141
142#endif /* __KERNEL__ */
143
144typedef struct sigaltstack {
145 void __user *ss_sp;
146 int ss_flags;
147 size_t ss_size;
148} stack_t;
149
150#ifdef __KERNEL__
36#include <asm/sigcontext.h> 151#include <asm/sigcontext.h>
37 152
38#ifndef CONFIG_CPU_HAS_NO_BITFIELDS 153#ifndef CONFIG_CPU_HAS_NO_BITFIELDS
@@ -41,7 +156,7 @@ struct k_sigaction {
41static inline void sigaddset(sigset_t *set, int _sig) 156static inline void sigaddset(sigset_t *set, int _sig)
42{ 157{
43 asm ("bfset %0{%1,#1}" 158 asm ("bfset %0{%1,#1}"
44 : "+o" (*set) 159 : "+od" (*set)
45 : "id" ((_sig - 1) ^ 31) 160 : "id" ((_sig - 1) ^ 31)
46 : "cc"); 161 : "cc");
47} 162}
@@ -49,7 +164,7 @@ static inline void sigaddset(sigset_t *set, int _sig)
49static inline void sigdelset(sigset_t *set, int _sig) 164static inline void sigdelset(sigset_t *set, int _sig)
50{ 165{
51 asm ("bfclr %0{%1,#1}" 166 asm ("bfclr %0{%1,#1}"
52 : "+o" (*set) 167 : "+od" (*set)
53 : "id" ((_sig - 1) ^ 31) 168 : "id" ((_sig - 1) ^ 31)
54 : "cc"); 169 : "cc");
55} 170}
@@ -65,7 +180,7 @@ static inline int __gen_sigismember(sigset_t *set, int _sig)
65 int ret; 180 int ret;
66 asm ("bfextu %1{%2,#1},%0" 181 asm ("bfextu %1{%2,#1},%0"
67 : "=d" (ret) 182 : "=d" (ret)
68 : "o" (*set), "id" ((_sig-1) ^ 31) 183 : "od" (*set), "id" ((_sig-1) ^ 31)
69 : "cc"); 184 : "cc");
70 return ret; 185 return ret;
71} 186}
@@ -86,9 +201,12 @@ static inline int sigfindinword(unsigned long word)
86 201
87#endif /* !CONFIG_CPU_HAS_NO_BITFIELDS */ 202#endif /* !CONFIG_CPU_HAS_NO_BITFIELDS */
88 203
89#ifndef __uClinux__ 204#ifdef __uClinux__
90extern void ptrace_signal_deliver(void); 205#define ptrace_signal_deliver(regs, cookie) do { } while (0)
91#define ptrace_signal_deliver ptrace_signal_deliver 206#else
207struct pt_regs;
208extern void ptrace_signal_deliver(struct pt_regs *regs, void *cookie);
92#endif /* __uClinux__ */ 209#endif /* __uClinux__ */
93 210
211#endif /* __KERNEL__ */
94#endif /* _M68K_SIGNAL_H */ 212#endif /* _M68K_SIGNAL_H */
diff --git a/arch/m68k/include/asm/sun3xflop.h b/arch/m68k/include/asm/sun3xflop.h
index 95231e2f9d6..32c45f84ac6 100644
--- a/arch/m68k/include/asm/sun3xflop.h
+++ b/arch/m68k/include/asm/sun3xflop.h
@@ -11,6 +11,7 @@
11 11
12#include <asm/page.h> 12#include <asm/page.h>
13#include <asm/pgtable.h> 13#include <asm/pgtable.h>
14#include <asm/system.h>
14#include <asm/irq.h> 15#include <asm/irq.h>
15#include <asm/sun3x.h> 16#include <asm/sun3x.h>
16 17
diff --git a/arch/m68k/include/asm/switch_to.h b/arch/m68k/include/asm/switch_to.h
deleted file mode 100644
index 16fd6b63498..00000000000
--- a/arch/m68k/include/asm/switch_to.h
+++ /dev/null
@@ -1,41 +0,0 @@
1#ifndef _M68K_SWITCH_TO_H
2#define _M68K_SWITCH_TO_H
3
4/*
5 * switch_to(n) should switch tasks to task ptr, first checking that
6 * ptr isn't the current task, in which case it does nothing. This
7 * also clears the TS-flag if the task we switched to has used the
8 * math co-processor latest.
9 */
10/*
11 * switch_to() saves the extra registers, that are not saved
12 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
13 * a0-a1. Some of these are used by schedule() and its predecessors
14 * and so we might get see unexpected behaviors when a task returns
15 * with unexpected register values.
16 *
17 * syscall stores these registers itself and none of them are used
18 * by syscall after the function in the syscall has been called.
19 *
20 * Beware that resume now expects *next to be in d1 and the offset of
21 * tss to be in a1. This saves a few instructions as we no longer have
22 * to push them onto the stack and read them back right after.
23 *
24 * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
25 *
26 * Changed 96/09/19 by Andreas Schwab
27 * pass prev in a0, next in a1
28 */
29asmlinkage void resume(void);
30#define switch_to(prev,next,last) do { \
31 register void *_prev __asm__ ("a0") = (prev); \
32 register void *_next __asm__ ("a1") = (next); \
33 register void *_last __asm__ ("d1"); \
34 __asm__ __volatile__("jbsr resume" \
35 : "=a" (_prev), "=a" (_next), "=d" (_last) \
36 : "0" (_prev), "1" (_next) \
37 : "d0", "d2", "d3", "d4", "d5"); \
38 (last) = _last; \
39} while (0)
40
41#endif /* _M68K_SWITCH_TO_H */
diff --git a/arch/m68k/include/asm/thread_info.h b/arch/m68k/include/asm/thread_info.h
index 126131f94a2..790988967ba 100644
--- a/arch/m68k/include/asm/thread_info.h
+++ b/arch/m68k/include/asm/thread_info.h
@@ -3,7 +3,6 @@
3 3
4#include <asm/types.h> 4#include <asm/types.h>
5#include <asm/page.h> 5#include <asm/page.h>
6#include <asm/segment.h>
7 6
8/* 7/*
9 * On machines with 4k pages we default to an 8k thread size, though we 8 * On machines with 4k pages we default to an 8k thread size, though we
@@ -27,7 +26,6 @@ struct thread_info {
27 struct task_struct *task; /* main task structure */ 26 struct task_struct *task; /* main task structure */
28 unsigned long flags; 27 unsigned long flags;
29 struct exec_domain *exec_domain; /* execution domain */ 28 struct exec_domain *exec_domain; /* execution domain */
30 mm_segment_t addr_limit; /* thread address space */
31 int preempt_count; /* 0 => preemptable, <0 => BUG */ 29 int preempt_count; /* 0 => preemptable, <0 => BUG */
32 __u32 cpu; /* should always be 0 on m68k */ 30 __u32 cpu; /* should always be 0 on m68k */
33 unsigned long tp_value; /* thread pointer */ 31 unsigned long tp_value; /* thread pointer */
@@ -41,7 +39,6 @@ struct thread_info {
41{ \ 39{ \
42 .task = &tsk, \ 40 .task = &tsk, \
43 .exec_domain = &default_exec_domain, \ 41 .exec_domain = &default_exec_domain, \
44 .addr_limit = KERNEL_DS, \
45 .preempt_count = INIT_PREEMPT_COUNT, \ 42 .preempt_count = INIT_PREEMPT_COUNT, \
46 .restart_block = { \ 43 .restart_block = { \
47 .fn = do_no_restart_syscall, \ 44 .fn = do_no_restart_syscall, \
@@ -50,6 +47,34 @@ struct thread_info {
50 47
51#define init_stack (init_thread_union.stack) 48#define init_stack (init_thread_union.stack)
52 49
50#ifdef CONFIG_MMU
51
52#ifndef __ASSEMBLY__
53#include <asm/current.h>
54#endif
55
56#ifdef ASM_OFFSETS_C
57#define task_thread_info(tsk) ((struct thread_info *) NULL)
58#else
59#include <asm/asm-offsets.h>
60#define task_thread_info(tsk) ((struct thread_info *)((char *)tsk+TASK_TINFO))
61#endif
62
63#define init_thread_info (init_task.thread.info)
64#define task_stack_page(tsk) ((tsk)->stack)
65#define current_thread_info() task_thread_info(current)
66
67#define __HAVE_THREAD_FUNCTIONS
68
69#define setup_thread_stack(p, org) ({ \
70 *(struct task_struct **)(p)->stack = (p); \
71 task_thread_info(p)->task = (p); \
72})
73
74#define end_of_stack(p) ((unsigned long *)(p)->stack + 1)
75
76#else /* !CONFIG_MMU */
77
53#ifndef __ASSEMBLY__ 78#ifndef __ASSEMBLY__
54/* how to get the thread information struct from C */ 79/* how to get the thread information struct from C */
55static inline struct thread_info *current_thread_info(void) 80static inline struct thread_info *current_thread_info(void)
@@ -67,16 +92,18 @@ static inline struct thread_info *current_thread_info(void)
67 92
68#define init_thread_info (init_thread_union.thread_info) 93#define init_thread_info (init_thread_union.thread_info)
69 94
95#endif /* CONFIG_MMU */
96
70/* entry.S relies on these definitions! 97/* entry.S relies on these definitions!
71 * bits 0-7 are tested at every exception exit 98 * bits 0-7 are tested at every exception exit
72 * bits 8-15 are also tested at syscall exit 99 * bits 8-15 are also tested at syscall exit
73 */ 100 */
74#define TIF_NOTIFY_RESUME 5 /* callback before returning to user */
75#define TIF_SIGPENDING 6 /* signal pending */ 101#define TIF_SIGPENDING 6 /* signal pending */
76#define TIF_NEED_RESCHED 7 /* rescheduling necessary */ 102#define TIF_NEED_RESCHED 7 /* rescheduling necessary */
77#define TIF_DELAYED_TRACE 14 /* single step a syscall */ 103#define TIF_DELAYED_TRACE 14 /* single step a syscall */
78#define TIF_SYSCALL_TRACE 15 /* syscall trace active */ 104#define TIF_SYSCALL_TRACE 15 /* syscall trace active */
79#define TIF_MEMDIE 16 /* is terminating due to OOM killer */ 105#define TIF_MEMDIE 16 /* is terminating due to OOM killer */
106#define TIF_FREEZE 17 /* thread is freezing for suspend */
80#define TIF_RESTORE_SIGMASK 18 /* restore signal mask in do_signal */ 107#define TIF_RESTORE_SIGMASK 18 /* restore signal mask in do_signal */
81 108
82#endif /* _ASM_M68K_THREAD_INFO_H */ 109#endif /* _ASM_M68K_THREAD_INFO_H */
diff --git a/arch/m68k/include/asm/tlbflush.h b/arch/m68k/include/asm/tlbflush.h
index 965ea35c9a4..a6b4ed4fc90 100644
--- a/arch/m68k/include/asm/tlbflush.h
+++ b/arch/m68k/include/asm/tlbflush.h
@@ -5,13 +5,10 @@
5#ifndef CONFIG_SUN3 5#ifndef CONFIG_SUN3
6 6
7#include <asm/current.h> 7#include <asm/current.h>
8#include <asm/mcfmmu.h>
9 8
10static inline void flush_tlb_kernel_page(void *addr) 9static inline void flush_tlb_kernel_page(void *addr)
11{ 10{
12 if (CPU_IS_COLDFIRE) { 11 if (CPU_IS_040_OR_060) {
13 mmu_write(MMUOR, MMUOR_CNL);
14 } else if (CPU_IS_040_OR_060) {
15 mm_segment_t old_fs = get_fs(); 12 mm_segment_t old_fs = get_fs();
16 set_fs(KERNEL_DS); 13 set_fs(KERNEL_DS);
17 __asm__ __volatile__(".chip 68040\n\t" 14 __asm__ __volatile__(".chip 68040\n\t"
@@ -28,15 +25,12 @@ static inline void flush_tlb_kernel_page(void *addr)
28 */ 25 */
29static inline void __flush_tlb(void) 26static inline void __flush_tlb(void)
30{ 27{
31 if (CPU_IS_COLDFIRE) { 28 if (CPU_IS_040_OR_060)
32 mmu_write(MMUOR, MMUOR_CNL);
33 } else if (CPU_IS_040_OR_060) {
34 __asm__ __volatile__(".chip 68040\n\t" 29 __asm__ __volatile__(".chip 68040\n\t"
35 "pflushan\n\t" 30 "pflushan\n\t"
36 ".chip 68k"); 31 ".chip 68k");
37 } else if (CPU_IS_020_OR_030) { 32 else if (CPU_IS_020_OR_030)
38 __asm__ __volatile__("pflush #0,#4"); 33 __asm__ __volatile__("pflush #0,#4");
39 }
40} 34}
41 35
42static inline void __flush_tlb040_one(unsigned long addr) 36static inline void __flush_tlb040_one(unsigned long addr)
@@ -49,9 +43,7 @@ static inline void __flush_tlb040_one(unsigned long addr)
49 43
50static inline void __flush_tlb_one(unsigned long addr) 44static inline void __flush_tlb_one(unsigned long addr)
51{ 45{
52 if (CPU_IS_COLDFIRE) 46 if (CPU_IS_040_OR_060)
53 mmu_write(MMUOR, MMUOR_CNL);
54 else if (CPU_IS_040_OR_060)
55 __flush_tlb040_one(addr); 47 __flush_tlb040_one(addr);
56 else if (CPU_IS_020_OR_030) 48 else if (CPU_IS_020_OR_030)
57 __asm__ __volatile__("pflush #0,#4,(%0)" : : "a" (addr)); 49 __asm__ __volatile__("pflush #0,#4,(%0)" : : "a" (addr));
@@ -64,15 +56,12 @@ static inline void __flush_tlb_one(unsigned long addr)
64 */ 56 */
65static inline void flush_tlb_all(void) 57static inline void flush_tlb_all(void)
66{ 58{
67 if (CPU_IS_COLDFIRE) { 59 if (CPU_IS_040_OR_060)
68 mmu_write(MMUOR, MMUOR_CNL);
69 } else if (CPU_IS_040_OR_060) {
70 __asm__ __volatile__(".chip 68040\n\t" 60 __asm__ __volatile__(".chip 68040\n\t"
71 "pflusha\n\t" 61 "pflusha\n\t"
72 ".chip 68k"); 62 ".chip 68k");
73 } else if (CPU_IS_020_OR_030) { 63 else if (CPU_IS_020_OR_030)
74 __asm__ __volatile__("pflusha"); 64 __asm__ __volatile__("pflusha");
75 }
76} 65}
77 66
78static inline void flush_tlb_mm(struct mm_struct *mm) 67static inline void flush_tlb_mm(struct mm_struct *mm)
diff --git a/arch/m68k/include/asm/traps.h b/arch/m68k/include/asm/traps.h
index 4aff3358fba..151068f64f4 100644
--- a/arch/m68k/include/asm/traps.h
+++ b/arch/m68k/include/asm/traps.h
@@ -18,7 +18,6 @@
18 18
19typedef void (*e_vector)(void); 19typedef void (*e_vector)(void);
20extern e_vector vectors[]; 20extern e_vector vectors[];
21extern e_vector *_ramvec;
22 21
23asmlinkage void auto_inthandler(void); 22asmlinkage void auto_inthandler(void);
24asmlinkage void user_inthandler(void); 23asmlinkage void user_inthandler(void);
diff --git a/arch/m68k/include/asm/uaccess.h b/arch/m68k/include/asm/uaccess.h
index 639c731568b..38f92dbb9a4 100644
--- a/arch/m68k/include/asm/uaccess.h
+++ b/arch/m68k/include/asm/uaccess.h
@@ -1,5 +1,5 @@
1#ifdef __uClinux__ 1#ifdef __uClinux__
2#include <asm/uaccess_no.h> 2#include "uaccess_no.h"
3#else 3#else
4#include <asm/uaccess_mm.h> 4#include "uaccess_mm.h"
5#endif 5#endif
diff --git a/arch/m68k/include/asm/uaccess_mm.h b/arch/m68k/include/asm/uaccess_mm.h
index 472c891a4ae..7107f3fbdbb 100644
--- a/arch/m68k/include/asm/uaccess_mm.h
+++ b/arch/m68k/include/asm/uaccess_mm.h
@@ -21,22 +21,6 @@ static inline int access_ok(int type, const void __user *addr,
21} 21}
22 22
23/* 23/*
24 * Not all varients of the 68k family support the notion of address spaces.
25 * The traditional 680x0 parts do, and they use the sfc/dfc registers and
26 * the "moves" instruction to access user space from kernel space. Other
27 * family members like ColdFire don't support this, and only have a single
28 * address space, and use the usual "move" instruction for user space access.
29 *
30 * Outside of this difference the user space access functions are the same.
31 * So lets keep the code simple and just define in what we need to use.
32 */
33#ifdef CONFIG_CPU_HAS_ADDRESS_SPACES
34#define MOVES "moves"
35#else
36#define MOVES "move"
37#endif
38
39/*
40 * The exception table consists of pairs of addresses: the first is the 24 * The exception table consists of pairs of addresses: the first is the
41 * address of an instruction that is allowed to fault, and the second is 25 * address of an instruction that is allowed to fault, and the second is
42 * the address at which the program should continue. No registers are 26 * the address at which the program should continue. No registers are
@@ -59,7 +43,7 @@ extern int __get_user_bad(void);
59 43
60#define __put_user_asm(res, x, ptr, bwl, reg, err) \ 44#define __put_user_asm(res, x, ptr, bwl, reg, err) \
61asm volatile ("\n" \ 45asm volatile ("\n" \
62 "1: "MOVES"."#bwl" %2,%1\n" \ 46 "1: moves."#bwl" %2,%1\n" \
63 "2:\n" \ 47 "2:\n" \
64 " .section .fixup,\"ax\"\n" \ 48 " .section .fixup,\"ax\"\n" \
65 " .even\n" \ 49 " .even\n" \
@@ -99,8 +83,8 @@ asm volatile ("\n" \
99 { \ 83 { \
100 const void __user *__pu_ptr = (ptr); \ 84 const void __user *__pu_ptr = (ptr); \
101 asm volatile ("\n" \ 85 asm volatile ("\n" \
102 "1: "MOVES".l %2,(%1)+\n" \ 86 "1: moves.l %2,(%1)+\n" \
103 "2: "MOVES".l %R2,(%1)\n" \ 87 "2: moves.l %R2,(%1)\n" \
104 "3:\n" \ 88 "3:\n" \
105 " .section .fixup,\"ax\"\n" \ 89 " .section .fixup,\"ax\"\n" \
106 " .even\n" \ 90 " .even\n" \
@@ -131,12 +115,12 @@ asm volatile ("\n" \
131#define __get_user_asm(res, x, ptr, type, bwl, reg, err) ({ \ 115#define __get_user_asm(res, x, ptr, type, bwl, reg, err) ({ \
132 type __gu_val; \ 116 type __gu_val; \
133 asm volatile ("\n" \ 117 asm volatile ("\n" \
134 "1: "MOVES"."#bwl" %2,%1\n" \ 118 "1: moves."#bwl" %2,%1\n" \
135 "2:\n" \ 119 "2:\n" \
136 " .section .fixup,\"ax\"\n" \ 120 " .section .fixup,\"ax\"\n" \
137 " .even\n" \ 121 " .even\n" \
138 "10: move.l %3,%0\n" \ 122 "10: move.l %3,%0\n" \
139 " sub.l %1,%1\n" \ 123 " sub."#bwl" %1,%1\n" \
140 " jra 2b\n" \ 124 " jra 2b\n" \
141 " .previous\n" \ 125 " .previous\n" \
142 "\n" \ 126 "\n" \
@@ -168,8 +152,8 @@ asm volatile ("\n" \
168 const void *__gu_ptr = (ptr); \ 152 const void *__gu_ptr = (ptr); \
169 u64 __gu_val; \ 153 u64 __gu_val; \
170 asm volatile ("\n" \ 154 asm volatile ("\n" \
171 "1: "MOVES".l (%2)+,%1\n" \ 155 "1: moves.l (%2)+,%1\n" \
172 "2: "MOVES".l (%2),%R1\n" \ 156 "2: moves.l (%2),%R1\n" \
173 "3:\n" \ 157 "3:\n" \
174 " .section .fixup,\"ax\"\n" \ 158 " .section .fixup,\"ax\"\n" \
175 " .even\n" \ 159 " .even\n" \
@@ -204,12 +188,12 @@ unsigned long __generic_copy_to_user(void __user *to, const void *from, unsigned
204 188
205#define __constant_copy_from_user_asm(res, to, from, tmp, n, s1, s2, s3)\ 189#define __constant_copy_from_user_asm(res, to, from, tmp, n, s1, s2, s3)\
206 asm volatile ("\n" \ 190 asm volatile ("\n" \
207 "1: "MOVES"."#s1" (%2)+,%3\n" \ 191 "1: moves."#s1" (%2)+,%3\n" \
208 " move."#s1" %3,(%1)+\n" \ 192 " move."#s1" %3,(%1)+\n" \
209 "2: "MOVES"."#s2" (%2)+,%3\n" \ 193 "2: moves."#s2" (%2)+,%3\n" \
210 " move."#s2" %3,(%1)+\n" \ 194 " move."#s2" %3,(%1)+\n" \
211 " .ifnc \""#s3"\",\"\"\n" \ 195 " .ifnc \""#s3"\",\"\"\n" \
212 "3: "MOVES"."#s3" (%2)+,%3\n" \ 196 "3: moves."#s3" (%2)+,%3\n" \
213 " move."#s3" %3,(%1)+\n" \ 197 " move."#s3" %3,(%1)+\n" \
214 " .endif\n" \ 198 " .endif\n" \
215 "4:\n" \ 199 "4:\n" \
@@ -285,13 +269,13 @@ __constant_copy_from_user(void *to, const void __user *from, unsigned long n)
285#define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \ 269#define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \
286 asm volatile ("\n" \ 270 asm volatile ("\n" \
287 " move."#s1" (%2)+,%3\n" \ 271 " move."#s1" (%2)+,%3\n" \
288 "11: "MOVES"."#s1" %3,(%1)+\n" \ 272 "11: moves."#s1" %3,(%1)+\n" \
289 "12: move."#s2" (%2)+,%3\n" \ 273 "12: move."#s2" (%2)+,%3\n" \
290 "21: "MOVES"."#s2" %3,(%1)+\n" \ 274 "21: moves."#s2" %3,(%1)+\n" \
291 "22:\n" \ 275 "22:\n" \
292 " .ifnc \""#s3"\",\"\"\n" \ 276 " .ifnc \""#s3"\",\"\"\n" \
293 " move."#s3" (%2)+,%3\n" \ 277 " move."#s3" (%2)+,%3\n" \
294 "31: "MOVES"."#s3" %3,(%1)+\n" \ 278 "31: moves."#s3" %3,(%1)+\n" \
295 "32:\n" \ 279 "32:\n" \
296 " .endif\n" \ 280 " .endif\n" \
297 "4:\n" \ 281 "4:\n" \
@@ -379,15 +363,12 @@ __constant_copy_to_user(void __user *to, const void *from, unsigned long n)
379#define copy_from_user(to, from, n) __copy_from_user(to, from, n) 363#define copy_from_user(to, from, n) __copy_from_user(to, from, n)
380#define copy_to_user(to, from, n) __copy_to_user(to, from, n) 364#define copy_to_user(to, from, n) __copy_to_user(to, from, n)
381 365
382#define user_addr_max() \ 366long strncpy_from_user(char *dst, const char __user *src, long count);
383 (segment_eq(get_fs(), USER_DS) ? TASK_SIZE : ~0UL) 367long strnlen_user(const char __user *src, long n);
384
385extern long strncpy_from_user(char *dst, const char __user *src, long count);
386extern __must_check long strlen_user(const char __user *str);
387extern __must_check long strnlen_user(const char __user *str, long n);
388
389unsigned long __clear_user(void __user *to, unsigned long n); 368unsigned long __clear_user(void __user *to, unsigned long n);
390 369
391#define clear_user __clear_user 370#define clear_user __clear_user
392 371
372#define strlen_user(str) strnlen_user(str, 32767)
373
393#endif /* _M68K_UACCESS_H */ 374#endif /* _M68K_UACCESS_H */
diff --git a/arch/m68k/include/asm/ucontext.h b/arch/m68k/include/asm/ucontext.h
index e4e22669edc..00dcc5176c5 100644
--- a/arch/m68k/include/asm/ucontext.h
+++ b/arch/m68k/include/asm/ucontext.h
@@ -7,7 +7,11 @@ typedef greg_t gregset_t[NGREG];
7 7
8typedef struct fpregset { 8typedef struct fpregset {
9 int f_fpcntl[3]; 9 int f_fpcntl[3];
10#ifdef __mcoldfire__
11 int f_fpregs[8][2];
12#else
10 int f_fpregs[8*3]; 13 int f_fpregs[8*3];
14#endif
11} fpregset_t; 15} fpregset_t;
12 16
13struct mcontext { 17struct mcontext {
diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h
index 2b3ca0bf7a0..019caa740c2 100644
--- a/arch/m68k/include/asm/unaligned.h
+++ b/arch/m68k/include/asm/unaligned.h
@@ -2,7 +2,7 @@
2#define _ASM_M68K_UNALIGNED_H 2#define _ASM_M68K_UNALIGNED_H
3 3
4 4
5#ifdef CONFIG_CPU_HAS_NO_UNALIGNED 5#ifdef CONFIG_COLDFIRE
6#include <linux/unaligned/be_struct.h> 6#include <linux/unaligned/be_struct.h>
7#include <linux/unaligned/le_byteshift.h> 7#include <linux/unaligned/le_byteshift.h>
8#include <linux/unaligned/generic.h> 8#include <linux/unaligned/generic.h>
@@ -12,7 +12,7 @@
12 12
13#else 13#else
14/* 14/*
15 * The m68k can do unaligned accesses itself. 15 * The m68k can do unaligned accesses itself.
16 */ 16 */
17#include <linux/unaligned/access_ok.h> 17#include <linux/unaligned/access_ok.h>
18#include <linux/unaligned/generic.h> 18#include <linux/unaligned/generic.h>
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index 847994ce680..43f984e9397 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -1,11 +1,361 @@
1#ifndef _ASM_M68K_UNISTD_H_ 1#ifndef _ASM_M68K_UNISTD_H_
2#define _ASM_M68K_UNISTD_H_ 2#define _ASM_M68K_UNISTD_H_
3 3
4#include <uapi/asm/unistd.h> 4/*
5 * This file contains the system call numbers.
6 */
7
8#define __NR_restart_syscall 0
9#define __NR_exit 1
10#define __NR_fork 2
11#define __NR_read 3
12#define __NR_write 4
13#define __NR_open 5
14#define __NR_close 6
15#define __NR_waitpid 7
16#define __NR_creat 8
17#define __NR_link 9
18#define __NR_unlink 10
19#define __NR_execve 11
20#define __NR_chdir 12
21#define __NR_time 13
22#define __NR_mknod 14
23#define __NR_chmod 15
24#define __NR_chown 16
25/*#define __NR_break 17*/
26#define __NR_oldstat 18
27#define __NR_lseek 19
28#define __NR_getpid 20
29#define __NR_mount 21
30#define __NR_umount 22
31#define __NR_setuid 23
32#define __NR_getuid 24
33#define __NR_stime 25
34#define __NR_ptrace 26
35#define __NR_alarm 27
36#define __NR_oldfstat 28
37#define __NR_pause 29
38#define __NR_utime 30
39/*#define __NR_stty 31*/
40/*#define __NR_gtty 32*/
41#define __NR_access 33
42#define __NR_nice 34
43/*#define __NR_ftime 35*/
44#define __NR_sync 36
45#define __NR_kill 37
46#define __NR_rename 38
47#define __NR_mkdir 39
48#define __NR_rmdir 40
49#define __NR_dup 41
50#define __NR_pipe 42
51#define __NR_times 43
52/*#define __NR_prof 44*/
53#define __NR_brk 45
54#define __NR_setgid 46
55#define __NR_getgid 47
56#define __NR_signal 48
57#define __NR_geteuid 49
58#define __NR_getegid 50
59#define __NR_acct 51
60#define __NR_umount2 52
61/*#define __NR_lock 53*/
62#define __NR_ioctl 54
63#define __NR_fcntl 55
64/*#define __NR_mpx 56*/
65#define __NR_setpgid 57
66/*#define __NR_ulimit 58*/
67/*#define __NR_oldolduname 59*/
68#define __NR_umask 60
69#define __NR_chroot 61
70#define __NR_ustat 62
71#define __NR_dup2 63
72#define __NR_getppid 64
73#define __NR_getpgrp 65
74#define __NR_setsid 66
75#define __NR_sigaction 67
76#define __NR_sgetmask 68
77#define __NR_ssetmask 69
78#define __NR_setreuid 70
79#define __NR_setregid 71
80#define __NR_sigsuspend 72
81#define __NR_sigpending 73
82#define __NR_sethostname 74
83#define __NR_setrlimit 75
84#define __NR_getrlimit 76
85#define __NR_getrusage 77
86#define __NR_gettimeofday 78
87#define __NR_settimeofday 79
88#define __NR_getgroups 80
89#define __NR_setgroups 81
90#define __NR_select 82
91#define __NR_symlink 83
92#define __NR_oldlstat 84
93#define __NR_readlink 85
94#define __NR_uselib 86
95#define __NR_swapon 87
96#define __NR_reboot 88
97#define __NR_readdir 89
98#define __NR_mmap 90
99#define __NR_munmap 91
100#define __NR_truncate 92
101#define __NR_ftruncate 93
102#define __NR_fchmod 94
103#define __NR_fchown 95
104#define __NR_getpriority 96
105#define __NR_setpriority 97
106/*#define __NR_profil 98*/
107#define __NR_statfs 99
108#define __NR_fstatfs 100
109/*#define __NR_ioperm 101*/
110#define __NR_socketcall 102
111#define __NR_syslog 103
112#define __NR_setitimer 104
113#define __NR_getitimer 105
114#define __NR_stat 106
115#define __NR_lstat 107
116#define __NR_fstat 108
117/*#define __NR_olduname 109*/
118/*#define __NR_iopl 110*/ /* not supported */
119#define __NR_vhangup 111
120/*#define __NR_idle 112*/ /* Obsolete */
121/*#define __NR_vm86 113*/ /* not supported */
122#define __NR_wait4 114
123#define __NR_swapoff 115
124#define __NR_sysinfo 116
125#define __NR_ipc 117
126#define __NR_fsync 118
127#define __NR_sigreturn 119
128#define __NR_clone 120
129#define __NR_setdomainname 121
130#define __NR_uname 122
131#define __NR_cacheflush 123
132#define __NR_adjtimex 124
133#define __NR_mprotect 125
134#define __NR_sigprocmask 126
135/*#define __NR_create_module 127*/
136#define __NR_init_module 128
137#define __NR_delete_module 129
138/*#define __NR_get_kernel_syms 130*/
139#define __NR_quotactl 131
140#define __NR_getpgid 132
141#define __NR_fchdir 133
142#define __NR_bdflush 134
143#define __NR_sysfs 135
144#define __NR_personality 136
145/*#define __NR_afs_syscall 137*/ /* Syscall for Andrew File System */
146#define __NR_setfsuid 138
147#define __NR_setfsgid 139
148#define __NR__llseek 140
149#define __NR_getdents 141
150#define __NR__newselect 142
151#define __NR_flock 143
152#define __NR_msync 144
153#define __NR_readv 145
154#define __NR_writev 146
155#define __NR_getsid 147
156#define __NR_fdatasync 148
157#define __NR__sysctl 149
158#define __NR_mlock 150
159#define __NR_munlock 151
160#define __NR_mlockall 152
161#define __NR_munlockall 153
162#define __NR_sched_setparam 154
163#define __NR_sched_getparam 155
164#define __NR_sched_setscheduler 156
165#define __NR_sched_getscheduler 157
166#define __NR_sched_yield 158
167#define __NR_sched_get_priority_max 159
168#define __NR_sched_get_priority_min 160
169#define __NR_sched_rr_get_interval 161
170#define __NR_nanosleep 162
171#define __NR_mremap 163
172#define __NR_setresuid 164
173#define __NR_getresuid 165
174#define __NR_getpagesize 166
175/*#define __NR_query_module 167*/
176#define __NR_poll 168
177#define __NR_nfsservctl 169
178#define __NR_setresgid 170
179#define __NR_getresgid 171
180#define __NR_prctl 172
181#define __NR_rt_sigreturn 173
182#define __NR_rt_sigaction 174
183#define __NR_rt_sigprocmask 175
184#define __NR_rt_sigpending 176
185#define __NR_rt_sigtimedwait 177
186#define __NR_rt_sigqueueinfo 178
187#define __NR_rt_sigsuspend 179
188#define __NR_pread64 180
189#define __NR_pwrite64 181
190#define __NR_lchown 182
191#define __NR_getcwd 183
192#define __NR_capget 184
193#define __NR_capset 185
194#define __NR_sigaltstack 186
195#define __NR_sendfile 187
196/*#define __NR_getpmsg 188*/ /* some people actually want streams */
197/*#define __NR_putpmsg 189*/ /* some people actually want streams */
198#define __NR_vfork 190
199#define __NR_ugetrlimit 191
200#define __NR_mmap2 192
201#define __NR_truncate64 193
202#define __NR_ftruncate64 194
203#define __NR_stat64 195
204#define __NR_lstat64 196
205#define __NR_fstat64 197
206#define __NR_chown32 198
207#define __NR_getuid32 199
208#define __NR_getgid32 200
209#define __NR_geteuid32 201
210#define __NR_getegid32 202
211#define __NR_setreuid32 203
212#define __NR_setregid32 204
213#define __NR_getgroups32 205
214#define __NR_setgroups32 206
215#define __NR_fchown32 207
216#define __NR_setresuid32 208
217#define __NR_getresuid32 209
218#define __NR_setresgid32 210
219#define __NR_getresgid32 211
220#define __NR_lchown32 212
221#define __NR_setuid32 213
222#define __NR_setgid32 214
223#define __NR_setfsuid32 215
224#define __NR_setfsgid32 216
225#define __NR_pivot_root 217
226/* 218*/
227/* 219*/
228#define __NR_getdents64 220
229#define __NR_gettid 221
230#define __NR_tkill 222
231#define __NR_setxattr 223
232#define __NR_lsetxattr 224
233#define __NR_fsetxattr 225
234#define __NR_getxattr 226
235#define __NR_lgetxattr 227
236#define __NR_fgetxattr 228
237#define __NR_listxattr 229
238#define __NR_llistxattr 230
239#define __NR_flistxattr 231
240#define __NR_removexattr 232
241#define __NR_lremovexattr 233
242#define __NR_fremovexattr 234
243#define __NR_futex 235
244#define __NR_sendfile64 236
245#define __NR_mincore 237
246#define __NR_madvise 238
247#define __NR_fcntl64 239
248#define __NR_readahead 240
249#define __NR_io_setup 241
250#define __NR_io_destroy 242
251#define __NR_io_getevents 243
252#define __NR_io_submit 244
253#define __NR_io_cancel 245
254#define __NR_fadvise64 246
255#define __NR_exit_group 247
256#define __NR_lookup_dcookie 248
257#define __NR_epoll_create 249
258#define __NR_epoll_ctl 250
259#define __NR_epoll_wait 251
260#define __NR_remap_file_pages 252
261#define __NR_set_tid_address 253
262#define __NR_timer_create 254
263#define __NR_timer_settime 255
264#define __NR_timer_gettime 256
265#define __NR_timer_getoverrun 257
266#define __NR_timer_delete 258
267#define __NR_clock_settime 259
268#define __NR_clock_gettime 260
269#define __NR_clock_getres 261
270#define __NR_clock_nanosleep 262
271#define __NR_statfs64 263
272#define __NR_fstatfs64 264
273#define __NR_tgkill 265
274#define __NR_utimes 266
275#define __NR_fadvise64_64 267
276#define __NR_mbind 268
277#define __NR_get_mempolicy 269
278#define __NR_set_mempolicy 270
279#define __NR_mq_open 271
280#define __NR_mq_unlink 272
281#define __NR_mq_timedsend 273
282#define __NR_mq_timedreceive 274
283#define __NR_mq_notify 275
284#define __NR_mq_getsetattr 276
285#define __NR_waitid 277
286/*#define __NR_vserver 278*/
287#define __NR_add_key 279
288#define __NR_request_key 280
289#define __NR_keyctl 281
290#define __NR_ioprio_set 282
291#define __NR_ioprio_get 283
292#define __NR_inotify_init 284
293#define __NR_inotify_add_watch 285
294#define __NR_inotify_rm_watch 286
295#define __NR_migrate_pages 287
296#define __NR_openat 288
297#define __NR_mkdirat 289
298#define __NR_mknodat 290
299#define __NR_fchownat 291
300#define __NR_futimesat 292
301#define __NR_fstatat64 293
302#define __NR_unlinkat 294
303#define __NR_renameat 295
304#define __NR_linkat 296
305#define __NR_symlinkat 297
306#define __NR_readlinkat 298
307#define __NR_fchmodat 299
308#define __NR_faccessat 300
309#define __NR_pselect6 301
310#define __NR_ppoll 302
311#define __NR_unshare 303
312#define __NR_set_robust_list 304
313#define __NR_get_robust_list 305
314#define __NR_splice 306
315#define __NR_sync_file_range 307
316#define __NR_tee 308
317#define __NR_vmsplice 309
318#define __NR_move_pages 310
319#define __NR_sched_setaffinity 311
320#define __NR_sched_getaffinity 312
321#define __NR_kexec_load 313
322#define __NR_getcpu 314
323#define __NR_epoll_pwait 315
324#define __NR_utimensat 316
325#define __NR_signalfd 317
326#define __NR_timerfd_create 318
327#define __NR_eventfd 319
328#define __NR_fallocate 320
329#define __NR_timerfd_settime 321
330#define __NR_timerfd_gettime 322
331#define __NR_signalfd4 323
332#define __NR_eventfd2 324
333#define __NR_epoll_create1 325
334#define __NR_dup3 326
335#define __NR_pipe2 327
336#define __NR_inotify_init1 328
337#define __NR_preadv 329
338#define __NR_pwritev 330
339#define __NR_rt_tgsigqueueinfo 331
340#define __NR_perf_event_open 332
341#define __NR_get_thread_area 333
342#define __NR_set_thread_area 334
343#define __NR_atomic_cmpxchg_32 335
344#define __NR_atomic_barrier 336
345#define __NR_fanotify_init 337
346#define __NR_fanotify_mark 338
347#define __NR_prlimit64 339
348#define __NR_name_to_handle_at 340
349#define __NR_open_by_handle_at 341
350#define __NR_clock_adjtime 342
351#define __NR_syncfs 343
352#define __NR_setns 344
5 353
354#ifdef __KERNEL__
6 355
7#define NR_syscalls 348 356#define NR_syscalls 345
8 357
358#define __ARCH_WANT_IPC_PARSE_VERSION
9#define __ARCH_WANT_OLD_READDIR 359#define __ARCH_WANT_OLD_READDIR
10#define __ARCH_WANT_OLD_STAT 360#define __ARCH_WANT_OLD_STAT
11#define __ARCH_WANT_STAT64 361#define __ARCH_WANT_STAT64
@@ -31,8 +381,6 @@
31#define __ARCH_WANT_SYS_SIGPROCMASK 381#define __ARCH_WANT_SYS_SIGPROCMASK
32#define __ARCH_WANT_SYS_RT_SIGACTION 382#define __ARCH_WANT_SYS_RT_SIGACTION
33#define __ARCH_WANT_SYS_RT_SIGSUSPEND 383#define __ARCH_WANT_SYS_RT_SIGSUSPEND
34#define __ARCH_WANT_SYS_FORK
35#define __ARCH_WANT_SYS_VFORK
36 384
37/* 385/*
38 * "Conditional" syscalls 386 * "Conditional" syscalls
@@ -42,4 +390,5 @@
42 */ 390 */
43#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") 391#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
44 392
393#endif /* __KERNEL__ */
45#endif /* _ASM_M68K_UNISTD_H_ */ 394#endif /* _ASM_M68K_UNISTD_H_ */
diff --git a/arch/m68k/include/asm/vga.h b/arch/m68k/include/asm/vga.h
deleted file mode 100644
index d3aa1401e7a..00000000000
--- a/arch/m68k/include/asm/vga.h
+++ /dev/null
@@ -1,27 +0,0 @@
1#ifndef _ASM_M68K_VGA_H
2#define _ASM_M68K_VGA_H
3
4#include <asm/raw_io.h>
5
6/*
7 * FIXME
8 * Ugh, we don't have PCI space, so map readb() and friends to use raw I/O
9 * accessors, which are identical to the z_*() Zorro bus accessors.
10 * This should make cirrusfb work again on Amiga
11 */
12#undef inb_p
13#undef inw_p
14#undef outb_p
15#undef outw
16#undef readb
17#undef writeb
18#undef writew
19#define inb_p(port) 0
20#define inw_p(port) 0
21#define outb_p(port, val) do { } while (0)
22#define outw(port, val) do { } while (0)
23#define readb raw_inb
24#define writeb raw_outb
25#define writew raw_outw
26
27#endif /* _ASM_M68K_VGA_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-30 16:14:02 -0400