[IA64] Workaround for RSE issue

Problem: An application violating the architectural rules regarding
operation dependencies and having specific Register Stack Engine (RSE)
state at the time of the violation, may result in an illegal operation
fault and invalid RSE state.  Such faults may initiate a cascade of
repeated illegal operation faults within OS interruption handlers.
The specific behavior is OS dependent.

Implication: An application causing an illegal operation fault with
specific RSE state may result in a series of illegal operation faults
and an eventual OS stack overflow condition.

Workaround: OS interruption handlers that switch to kernel backing
store implement a check for invalid RSE state to avoid the series
of illegal operation faults.

The core of the workaround is the RSE_WORKAROUND code sequence
inserted into each invocation of the SAVE_MIN_WITH_COVER and
SAVE_MIN_WITH_COVER_R19 macros.  This sequence includes hard-coded
constants that depend on the number of stacked physical registers
being 96.  The rest of this patch consists of code to disable this
workaround should this not be the case (with the presumption that
if a future Itanium processor increases the number of registers, it
would also remove the need for this patch).

Move the start of the RBS up to a mod32 boundary to avoid some
corner cases.

The dispatch_illegal_op_fault code outgrew the spot it was
squatting in when built with this patch and CONFIG_VIRT_CPU_ACCOUNTING=y
Move it out to the end of the ivt.

Signed-off-by: Tony Luck <tony.luck@intel.com>

1 files changed, 42 insertions, 42 deletions

diff --git a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S
index 6678c49daba..80b44ea052d 100644
--- a/arch/ia64/kernel/ivt.S
+++ b/arch/ia64/kernel/ivt.S
@@ -1076,48 +1076,6 @@ END(ia64_syscall_setup)
         DBG_FAULT(15)
         FAULT(15)
 
-        /*
-         * Squatting in this space ...
-         *
-         * This special case dispatcher for illegal operation faults allows preserved
-         * registers to be modified through a callback function (asm only) that is handed
-         * back from the fault handler in r8. Up to three arguments can be passed to the
-         * callback function by returning an aggregate with the callback as its first
-         * element, followed by the arguments.
-         */
-ENTRY(dispatch_illegal_op_fault)
-        .prologue
-        .body
-        SAVE_MIN_WITH_COVER
-        ssm psr.ic | PSR_DEFAULT_BITS
-        ;;
-        srlz.i          // guarantee that interruption collection is on
-        ;;
-(p15)   ssm psr.i       // restore psr.i
-        adds r3=8,r2    // set up second base pointer for SAVE_REST
-        ;;
-        alloc r14=ar.pfs,0,0,1,0        // must be first in insn group
-        mov out0=ar.ec
-        ;;
-        SAVE_REST
-        PT_REGS_UNWIND_INFO(0)
-        ;;
-        br.call.sptk.many rp=ia64_illegal_op_fault
-.ret0:  ;;
-        alloc r14=ar.pfs,0,0,3,0        // must be first in insn group
-        mov out0=r9
-        mov out1=r10
-        mov out2=r11
-        movl r15=ia64_leave_kernel
-        ;;
-        mov rp=r15
-        mov b6=r8
-        ;;
-        cmp.ne p6,p0=0,r8
-(p6)    br.call.dpnt.many b6=b6         // call returns to ia64_leave_kernel
-        br.sptk.many ia64_leave_kernel
-END(dispatch_illegal_op_fault)
-
         .org ia64_ivt+0x4000
 /////////////////////////////////////////////////////////////////////////////////////////
 // 0x4000 Entry 16 (size 64 bundles) Reserved
@@ -1715,6 +1673,48 @@ END(ia32_interrupt)
         DBG_FAULT(67)
         FAULT(67)
 
+        /*
+         * Squatting in this space ...
+         *
+         * This special case dispatcher for illegal operation faults allows preserved
+         * registers to be modified through a callback function (asm only) that is handed
+         * back from the fault handler in r8. Up to three arguments can be passed to the
+         * callback function by returning an aggregate with the callback as its first
+         * element, followed by the arguments.
+         */
+ENTRY(dispatch_illegal_op_fault)
+        .prologue
+        .body
+        SAVE_MIN_WITH_COVER
+        ssm psr.ic | PSR_DEFAULT_BITS
+        ;;
+        srlz.i          // guarantee that interruption collection is on
+        ;;
+(p15)   ssm psr.i       // restore psr.i
+        adds r3=8,r2    // set up second base pointer for SAVE_REST
+        ;;
+        alloc r14=ar.pfs,0,0,1,0        // must be first in insn group
+        mov out0=ar.ec
+        ;;
+        SAVE_REST
+        PT_REGS_UNWIND_INFO(0)
+        ;;
+        br.call.sptk.many rp=ia64_illegal_op_fault
+.ret0:  ;;
+        alloc r14=ar.pfs,0,0,3,0        // must be first in insn group
+        mov out0=r9
+        mov out1=r10
+        mov out2=r11
+        movl r15=ia64_leave_kernel
+        ;;
+        mov rp=r15
+        mov b6=r8
+        ;;
+        cmp.ne p6,p0=0,r8
+(p6)    br.call.dpnt.many b6=b6         // call returns to ia64_leave_kernel
+        br.sptk.many ia64_leave_kernel
+END(dispatch_illegal_op_fault)
+
 #ifdef CONFIG_IA32_SUPPORT
 
         /*