i386: Add L3 cache support to AMD CPUID4 emulation

With that an L3 cache is correctly reported in the cache information in /sys

With fixes from Andreas Herrmann and Dean Gaudet and Joachim Deguara

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

1 files changed, 6 insertions, 2 deletions

diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c
index 6f47eeeb93e..815a5f0aa47 100644
--- a/arch/i386/kernel/cpu/amd.c
+++ b/arch/i386/kernel/cpu/amd.c
@@ -272,8 +272,12 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
         }
 #endif
 
-        if (cpuid_eax(0x80000000) >= 0x80000006)
-                num_cache_leaves = 3;
+        if (cpuid_eax(0x80000000) >= 0x80000006) {
+                if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
+                        num_cache_leaves = 4;
+                else
+                        num_cache_leaves = 3;
+        }
 
         if (amd_apic_timer_broken())
                 set_bit(X86_FEATURE_LAPIC_TIMER_BROKEN, c->x86_capability);