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authorLinus Torvalds <torvalds@linux-foundation.org>2011-05-25 18:34:14 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-05-25 18:34:14 -0400
commited0795aa12129df9f3d2cc81ee579a9e54e12885 (patch)
tree28187d937a3c3e8f5f50cd3b3aeca14585a14048 /arch/blackfin
parent4e8a780ed6e1fdb8af203f61718212d5739bc4a0 (diff)
parentd6cb2e3a8dc44b52f6564e8249e54aab3c308026 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (37 commits) Blackfin: use new common PERCPU_INPUT define MAINTAINERS: Fix Analog Devices mailinglist address Blackfin: boards: update ASoC resources after machine driver overhaul Blackfin: work around anomaly 05000480 Blackfin: fix addr type with bfin_write_{or,and} helpers Blackfin: convert /proc/sram to seq_file Blackfin: switch /proc/gpio to seq_file Blackfin: fix indentation with bfin_read() helper Blackfin: convert old cpumask API to new one Blackfin: don't touch task->cpus_allowed directly Blackfin: don't touch cpu_possible_map and cpu_present_map directly Blackfin: bf548-ezkit/bf561-ezkit: update nor flash layout Blackfin: initial perf_event support Blackfin: update anomaly lists to latest public info Blackfin: use on-chip reset func with newer parts Blackfin: bf533-stamp/bf537-stamp: drop ad1980 from defconfigs Blackfin: optimize MMR reads during startup a bit Blackfin: bf537: demux port H mask A and emac rx ints Blackfin: bf537: fix excessive gpio int demuxing Blackfin: bf54x: drop unused pm gpio handling ...
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/Kconfig2
-rw-r--r--arch/blackfin/Kconfig.debug2
-rw-r--r--arch/blackfin/configs/BF527-EZKIT-V2_defconfig12
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig14
-rw-r--r--arch/blackfin/configs/BF533-STAMP_defconfig2
-rw-r--r--arch/blackfin/configs/BF537-STAMP_defconfig2
-rw-r--r--arch/blackfin/include/asm/bfin-global.h10
-rw-r--r--arch/blackfin/include/asm/bfin_pfmon.h44
-rw-r--r--arch/blackfin/include/asm/bfin_sport.h4
-rw-r--r--arch/blackfin/include/asm/cacheflush.h23
-rw-r--r--arch/blackfin/include/asm/cpu.h3
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h12
-rw-r--r--arch/blackfin/include/asm/irq_handler.h25
-rw-r--r--arch/blackfin/include/asm/kgdb.h6
-rw-r--r--arch/blackfin/include/asm/perf_event.h1
-rw-r--r--arch/blackfin/include/asm/ptrace.h2
-rw-r--r--arch/blackfin/include/mach-common/irq.h57
-rw-r--r--arch/blackfin/kernel/Makefile3
-rw-r--r--arch/blackfin/kernel/bfin_dma_5xx.c5
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c34
-rw-r--r--arch/blackfin/kernel/bfin_ksyms.c1
-rw-r--r--arch/blackfin/kernel/debug-mmrs.c1860
-rw-r--r--arch/blackfin/kernel/ipipe.c1
-rw-r--r--arch/blackfin/kernel/irqchip.c1
-rw-r--r--arch/blackfin/kernel/nmi.c8
-rw-r--r--arch/blackfin/kernel/perf_event.c498
-rw-r--r--arch/blackfin/kernel/process.c6
-rw-r--r--arch/blackfin/kernel/reboot.c65
-rw-r--r--arch/blackfin/kernel/setup.c54
-rw-r--r--arch/blackfin/kernel/vmlinux.lds.S8
-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h4
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF512.h16
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF512.h8
-rw-r--r--arch/blackfin/mach-bf518/include/mach/irq.h262
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c74
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h8
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF522.h16
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF522.h8
-rw-r--r--arch/blackfin/mach-bf527/include/mach/irq.h266
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h11
-rw-r--r--arch/blackfin/mach-bf533/include/mach/irq.h168
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c106
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h10
-rw-r--r--arch/blackfin/mach-bf537/include/mach/irq.h365
-rw-r--r--arch/blackfin/mach-bf537/ints-priority.c163
-rw-r--r--arch/blackfin/mach-bf538/include/mach/anomaly.h9
-rw-r--r--arch/blackfin/mach-bf538/include/mach/irq.h89
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c116
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h8
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h89
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c10
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h15
-rw-r--r--arch/blackfin/mach-bf561/include/mach/irq.h505
-rw-r--r--arch/blackfin/mach-bf561/smp.c17
-rw-r--r--arch/blackfin/mach-common/dpmc.c7
-rw-r--r--arch/blackfin/mach-common/ints-priority.c476
-rw-r--r--arch/blackfin/mach-common/smp.c28
-rw-r--r--arch/blackfin/mm/sram-alloc.c43
58 files changed, 4001 insertions, 1661 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 8addb1220b4..a18180f2d00 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -24,11 +24,13 @@ config BLACKFIN
24 select HAVE_FUNCTION_TRACER 24 select HAVE_FUNCTION_TRACER
25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST 25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
26 select HAVE_IDE 26 select HAVE_IDE
27 select HAVE_IRQ_WORK
27 select HAVE_KERNEL_GZIP if RAMKERNEL 28 select HAVE_KERNEL_GZIP if RAMKERNEL
28 select HAVE_KERNEL_BZIP2 if RAMKERNEL 29 select HAVE_KERNEL_BZIP2 if RAMKERNEL
29 select HAVE_KERNEL_LZMA if RAMKERNEL 30 select HAVE_KERNEL_LZMA if RAMKERNEL
30 select HAVE_KERNEL_LZO if RAMKERNEL 31 select HAVE_KERNEL_LZO if RAMKERNEL
31 select HAVE_OPROFILE 32 select HAVE_OPROFILE
33 select HAVE_PERF_EVENTS
32 select ARCH_WANT_OPTIONAL_GPIOLIB 34 select ARCH_WANT_OPTIONAL_GPIOLIB
33 select HAVE_GENERIC_HARDIRQS 35 select HAVE_GENERIC_HARDIRQS
34 select GENERIC_ATOMIC64 36 select GENERIC_ATOMIC64
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index 19ccfb3b67d..e2a3d4c8ab9 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -23,7 +23,7 @@ config DEBUG_VERBOSE
23 Most people should say N here. 23 Most people should say N here.
24 24
25config DEBUG_MMRS 25config DEBUG_MMRS
26 bool "Generate Blackfin MMR tree" 26 tristate "Generate Blackfin MMR tree"
27 select DEBUG_FS 27 select DEBUG_FS
28 help 28 help
29 Create a tree of Blackfin MMRs via the debugfs tree. If 29 Create a tree of Blackfin MMRs via the debugfs tree. If
diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
index 95cf2ba9de1..8465b3e6b86 100644
--- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
@@ -121,13 +121,11 @@ CONFIG_LOGO=y
121# CONFIG_LOGO_LINUX_VGA16 is not set 121# CONFIG_LOGO_LINUX_VGA16 is not set
122# CONFIG_LOGO_LINUX_CLUT224 is not set 122# CONFIG_LOGO_LINUX_CLUT224 is not set
123# CONFIG_LOGO_BLACKFIN_VGA16 is not set 123# CONFIG_LOGO_BLACKFIN_VGA16 is not set
124CONFIG_SOUND=m 124CONFIG_SOUND=y
125CONFIG_SND=m 125CONFIG_SND=y
126CONFIG_SND_SOC=m 126CONFIG_SND_SOC=y
127CONFIG_SND_BF5XX_I2S=m 127CONFIG_SND_BF5XX_I2S=y
128CONFIG_SND_BF5XX_SOC_SSM2602=m 128CONFIG_SND_BF5XX_SOC_SSM2602=y
129CONFIG_SND_BF5XX_AC97=m
130CONFIG_SND_BF5XX_SOC_AD1980=m
131CONFIG_HID_A4TECH=y 129CONFIG_HID_A4TECH=y
132CONFIG_HID_APPLE=y 130CONFIG_HID_APPLE=y
133CONFIG_HID_BELKIN=y 131CONFIG_HID_BELKIN=y
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 8be8e33fac5..5e7321b2604 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -96,7 +96,7 @@ CONFIG_SERIAL_BFIN_UART1=y
96# CONFIG_HW_RANDOM is not set 96# CONFIG_HW_RANDOM is not set
97CONFIG_I2C=y 97CONFIG_I2C=y
98CONFIG_I2C_CHARDEV=m 98CONFIG_I2C_CHARDEV=m
99CONFIG_I2C_BLACKFIN_TWI=m 99CONFIG_I2C_BLACKFIN_TWI=y
100CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 100CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
101CONFIG_SPI=y 101CONFIG_SPI=y
102CONFIG_SPI_BFIN=y 102CONFIG_SPI_BFIN=y
@@ -115,13 +115,11 @@ CONFIG_LOGO=y
115# CONFIG_LOGO_LINUX_VGA16 is not set 115# CONFIG_LOGO_LINUX_VGA16 is not set
116# CONFIG_LOGO_LINUX_CLUT224 is not set 116# CONFIG_LOGO_LINUX_CLUT224 is not set
117# CONFIG_LOGO_BLACKFIN_VGA16 is not set 117# CONFIG_LOGO_BLACKFIN_VGA16 is not set
118CONFIG_SOUND=m 118CONFIG_SOUND=y
119CONFIG_SND=m 119CONFIG_SND=y
120CONFIG_SND_SOC=m 120CONFIG_SND_SOC=y
121CONFIG_SND_BF5XX_I2S=m 121CONFIG_SND_BF5XX_I2S=y
122CONFIG_SND_BF5XX_SOC_SSM2602=m 122CONFIG_SND_BF5XX_SOC_SSM2602=y
123CONFIG_SND_BF5XX_AC97=m
124CONFIG_SND_BF5XX_SOC_AD1980=m
125CONFIG_HID_A4TECH=y 123CONFIG_HID_A4TECH=y
126CONFIG_HID_APPLE=y 124CONFIG_HID_APPLE=y
127CONFIG_HID_BELKIN=y 125CONFIG_HID_BELKIN=y
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index 0aafde6c8c2..b90d3792ed5 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -99,8 +99,6 @@ CONFIG_SND_PCM_OSS=m
99CONFIG_SND_SOC=m 99CONFIG_SND_SOC=m
100CONFIG_SND_BF5XX_I2S=m 100CONFIG_SND_BF5XX_I2S=m
101CONFIG_SND_BF5XX_SOC_AD73311=m 101CONFIG_SND_BF5XX_SOC_AD73311=m
102CONFIG_SND_BF5XX_AC97=m
103CONFIG_SND_BF5XX_SOC_AD1980=m
104# CONFIG_USB_SUPPORT is not set 102# CONFIG_USB_SUPPORT is not set
105CONFIG_RTC_CLASS=y 103CONFIG_RTC_CLASS=y
106CONFIG_RTC_DRV_BFIN=y 104CONFIG_RTC_DRV_BFIN=y
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index c9077fb5813..005362537a7 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -110,8 +110,6 @@ CONFIG_SND_PCM_OSS=m
110CONFIG_SND_SOC=m 110CONFIG_SND_SOC=m
111CONFIG_SND_BF5XX_I2S=m 111CONFIG_SND_BF5XX_I2S=m
112CONFIG_SND_BF5XX_SOC_AD73311=m 112CONFIG_SND_BF5XX_SOC_AD73311=m
113CONFIG_SND_BF5XX_AC97=m
114CONFIG_SND_BF5XX_SOC_AD1980=m
115# CONFIG_USB_SUPPORT is not set 113# CONFIG_USB_SUPPORT is not set
116CONFIG_RTC_CLASS=y 114CONFIG_RTC_CLASS=y
117CONFIG_RTC_DRV_BFIN=y 115CONFIG_RTC_DRV_BFIN=y
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 121cc04d877..17bcbf60bca 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -49,16 +49,6 @@ extern void dump_bfin_trace_buffer(void);
49#define dump_bfin_trace_buffer() 49#define dump_bfin_trace_buffer()
50#endif 50#endif
51 51
52/* init functions only */
53extern int init_arch_irq(void);
54extern void init_exception_vectors(void);
55extern void program_IAR(void);
56
57extern asmlinkage void lower_to_irq14(void);
58extern asmlinkage void bfin_return_from_exception(void);
59extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
60extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
61
62extern void *l1_data_A_sram_alloc(size_t); 52extern void *l1_data_A_sram_alloc(size_t);
63extern void *l1_data_B_sram_alloc(size_t); 53extern void *l1_data_B_sram_alloc(size_t);
64extern void *l1_inst_sram_alloc(size_t); 54extern void *l1_inst_sram_alloc(size_t);
diff --git a/arch/blackfin/include/asm/bfin_pfmon.h b/arch/blackfin/include/asm/bfin_pfmon.h
new file mode 100644
index 00000000000..accd47e2db4
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_pfmon.h
@@ -0,0 +1,44 @@
1/*
2 * Blackfin Performance Monitor definitions
3 *
4 * Copyright 2005-2011 Analog Devices Inc.
5 *
6 * Licensed under the ADI BSD license or GPL-2 (or later).
7 */
8
9#ifndef __ASM_BFIN_PFMON_H__
10#define __ASM_BFIN_PFMON_H__
11
12/* PFCTL Masks */
13#define PFMON_MASK 0xff
14#define PFCEN_MASK 0x3
15#define PFCEN_DISABLE 0x0
16#define PFCEN_ENABLE_USER 0x1
17#define PFCEN_ENABLE_SUPV 0x2
18#define PFCEN_ENABLE_ALL (PFCEN_ENABLE_USER | PFCEN_ENABLE_SUPV)
19
20#define PFPWR_P 0
21#define PEMUSW0_P 2
22#define PFCEN0_P 3
23#define PFMON0_P 5
24#define PEMUSW1_P 13
25#define PFCEN1_P 14
26#define PFMON1_P 16
27#define PFCNT0_P 24
28#define PFCNT1_P 25
29
30#define PFPWR (1 << PFPWR_P)
31#define PEMUSW(n, x) ((x) << ((n) ? PEMUSW1_P : PEMUSW0_P))
32#define PEMUSW0 PEMUSW(0, 1)
33#define PEMUSW1 PEMUSW(1, 1)
34#define PFCEN(n, x) ((x) << ((n) ? PFCEN1_P : PFCEN0_P))
35#define PFCEN0 PFCEN(0, PFCEN_MASK)
36#define PFCEN1 PFCEN(1, PFCEN_MASK)
37#define PFCNT(n, x) ((x) << ((n) ? PFCNT1_P : PFCNT0_P))
38#define PFCNT0 PFCNT(0, 1)
39#define PFCNT1 PFCNT(1, 1)
40#define PFMON(n, x) ((x) << ((n) ? PFMON1_P : PFMON0_P))
41#define PFMON0 PFMON(0, PFMON_MASK)
42#define PFMON1 PFMON(1, PFMON_MASK)
43
44#endif
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index d27600c262c..f8568a31d0a 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -100,6 +100,10 @@ struct sport_register {
100}; 100};
101#undef __BFP 101#undef __BFP
102 102
103struct bfin_snd_platform_data {
104 const unsigned short *pin_req;
105};
106
103#define bfin_read_sport_rx32(base) \ 107#define bfin_read_sport_rx32(base) \
104({ \ 108({ \
105 struct sport_register *__mmrs = (void *)base; \ 109 struct sport_register *__mmrs = (void *)base; \
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 77135b62818..9a5b2c572eb 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -39,8 +39,13 @@ extern void blackfin_invalidate_entire_icache(void);
39 39
40static inline void flush_icache_range(unsigned start, unsigned end) 40static inline void flush_icache_range(unsigned start, unsigned end)
41{ 41{
42#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) 42#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
43 blackfin_dcache_flush_range(start, end); 43 if (end <= physical_mem_end)
44 blackfin_dcache_flush_range(start, end);
45#endif
46#if defined(CONFIG_BFIN_L2_WRITEBACK)
47 if (start >= L2_START && end <= L2_START + L2_LENGTH)
48 blackfin_dcache_flush_range(start, end);
44#endif 49#endif
45 50
46 /* Make sure all write buffers in the data side of the core 51 /* Make sure all write buffers in the data side of the core
@@ -52,9 +57,17 @@ static inline void flush_icache_range(unsigned start, unsigned end)
52 * the pipeline. 57 * the pipeline.
53 */ 58 */
54 SSYNC(); 59 SSYNC();
55#if defined(CONFIG_BFIN_ICACHE) 60#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
56 blackfin_icache_flush_range(start, end); 61 if (end <= physical_mem_end) {
57 flush_icache_range_others(start, end); 62 blackfin_icache_flush_range(start, end);
63 flush_icache_range_others(start, end);
64 }
65#endif
66#if defined(CONFIG_BFIN_L2_ICACHEABLE)
67 if (start >= L2_START && end <= L2_START + L2_LENGTH) {
68 blackfin_icache_flush_range(start, end);
69 flush_icache_range_others(start, end);
70 }
58#endif 71#endif
59} 72}
60 73
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
index 16883e582e3..05043786da2 100644
--- a/arch/blackfin/include/asm/cpu.h
+++ b/arch/blackfin/include/asm/cpu.h
@@ -10,11 +10,8 @@
10 10
11#include <linux/percpu.h> 11#include <linux/percpu.h>
12 12
13struct task_struct;
14
15struct blackfin_cpudata { 13struct blackfin_cpudata {
16 struct cpu cpu; 14 struct cpu cpu;
17 struct task_struct *idle;
18 unsigned int imemctl; 15 unsigned int imemctl;
19 unsigned int dmemctl; 16 unsigned int dmemctl;
20}; 17};
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index 7600fe0696a..82367901145 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -52,10 +52,10 @@
52 52
53#define bfin_read(addr) \ 53#define bfin_read(addr) \
54({ \ 54({ \
55 sizeof(*(addr)) == 1 ? bfin_read8(addr) : \ 55 sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
56 sizeof(*(addr)) == 2 ? bfin_read16(addr) : \ 56 sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
57 sizeof(*(addr)) == 4 ? bfin_read32(addr) : \ 57 sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
58 ({ BUG(); 0; }); \ 58 ({ BUG(); 0; }); \
59}) 59})
60#define bfin_write(addr, val) \ 60#define bfin_write(addr, val) \
61do { \ 61do { \
@@ -69,13 +69,13 @@ do { \
69 69
70#define bfin_write_or(addr, bits) \ 70#define bfin_write_or(addr, bits) \
71do { \ 71do { \
72 void *__addr = (void *)(addr); \ 72 typeof(addr) __addr = (addr); \
73 bfin_write(__addr, bfin_read(__addr) | (bits)); \ 73 bfin_write(__addr, bfin_read(__addr) | (bits)); \
74} while (0) 74} while (0)
75 75
76#define bfin_write_and(addr, bits) \ 76#define bfin_write_and(addr, bits) \
77do { \ 77do { \
78 void *__addr = (void *)(addr); \ 78 typeof(addr) __addr = (addr); \
79 bfin_write(__addr, bfin_read(__addr) & (bits)); \ 79 bfin_write(__addr, bfin_read(__addr) & (bits)); \
80} while (0) 80} while (0)
81 81
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h
index 7fbe42307b9..ee73f79aef1 100644
--- a/arch/blackfin/include/asm/irq_handler.h
+++ b/arch/blackfin/include/asm/irq_handler.h
@@ -10,6 +10,16 @@
10#include <linux/types.h> 10#include <linux/types.h>
11#include <linux/linkage.h> 11#include <linux/linkage.h>
12 12
13/* init functions only */
14extern int __init init_arch_irq(void);
15extern void init_exception_vectors(void);
16extern void __init program_IAR(void);
17#ifdef init_mach_irq
18extern void __init init_mach_irq(void);
19#else
20# define init_mach_irq()
21#endif
22
13/* BASE LEVEL interrupt handler routines */ 23/* BASE LEVEL interrupt handler routines */
14asmlinkage void evt_exception(void); 24asmlinkage void evt_exception(void);
15asmlinkage void trap(void); 25asmlinkage void trap(void);
@@ -37,4 +47,19 @@ extern void return_from_exception(void);
37extern int bfin_request_exception(unsigned int exception, void (*handler)(void)); 47extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
38extern int bfin_free_exception(unsigned int exception, void (*handler)(void)); 48extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
39 49
50extern asmlinkage void lower_to_irq14(void);
51extern asmlinkage void bfin_return_from_exception(void);
52extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
53extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
54
55struct irq_data;
56extern void bfin_handle_irq(unsigned irq);
57extern void bfin_ack_noop(struct irq_data *);
58extern void bfin_internal_mask_irq(unsigned int irq);
59extern void bfin_internal_unmask_irq(unsigned int irq);
60
61struct irq_desc;
62extern void bfin_demux_mac_status_irq(unsigned int, struct irq_desc *);
63extern void bfin_demux_gpio_irq(unsigned int, struct irq_desc *);
64
40#endif 65#endif
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
index 8651afe1299..3ac0c72e9fe 100644
--- a/arch/blackfin/include/asm/kgdb.h
+++ b/arch/blackfin/include/asm/kgdb.h
@@ -103,7 +103,11 @@ static inline void arch_kgdb_breakpoint(void)
103 asm("EXCPT 2;"); 103 asm("EXCPT 2;");
104} 104}
105#define BREAK_INSTR_SIZE 2 105#define BREAK_INSTR_SIZE 2
106#define CACHE_FLUSH_IS_SAFE 1 106#ifdef CONFIG_SMP
107# define CACHE_FLUSH_IS_SAFE 0
108#else
109# define CACHE_FLUSH_IS_SAFE 1
110#endif
107#define HW_INST_WATCHPOINT_NUM 6 111#define HW_INST_WATCHPOINT_NUM 6
108#define HW_WATCHPOINT_NUM 8 112#define HW_WATCHPOINT_NUM 8
109#define TYPE_INST_WATCHPOINT 0 113#define TYPE_INST_WATCHPOINT 0
diff --git a/arch/blackfin/include/asm/perf_event.h b/arch/blackfin/include/asm/perf_event.h
new file mode 100644
index 00000000000..3d2b1716322
--- /dev/null
+++ b/arch/blackfin/include/asm/perf_event.h
@@ -0,0 +1 @@
#define MAX_HWEVENTS 2
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
index 832d7c009a2..1066d63e62b 100644
--- a/arch/blackfin/include/asm/ptrace.h
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -108,8 +108,6 @@ struct pt_regs {
108extern void show_regs(struct pt_regs *); 108extern void show_regs(struct pt_regs *);
109 109
110#define arch_has_single_step() (1) 110#define arch_has_single_step() (1)
111extern void user_enable_single_step(struct task_struct *child);
112extern void user_disable_single_step(struct task_struct *child);
113/* common code demands this function */ 111/* common code demands this function */
114#define ptrace_disable(child) user_disable_single_step(child) 112#define ptrace_disable(child) user_disable_single_step(child)
115 113
diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h
new file mode 100644
index 00000000000..cab14e911dc
--- /dev/null
+++ b/arch/blackfin/include/mach-common/irq.h
@@ -0,0 +1,57 @@
1/*
2 * Common Blackfin IRQ definitions (i.e. the CEC)
3 *
4 * Copyright 2005-2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later
7 */
8
9#ifndef _MACH_COMMON_IRQ_H_
10#define _MACH_COMMON_IRQ_H_
11
12/*
13 * Core events interrupt source definitions
14 *
15 * Event Source Event Name
16 * Emulation EMU 0 (highest priority)
17 * Reset RST 1
18 * NMI NMI 2
19 * Exception EVX 3
20 * Reserved -- 4
21 * Hardware Error IVHW 5
22 * Core Timer IVTMR 6
23 * Peripherals IVG7 7
24 * Peripherals IVG8 8
25 * Peripherals IVG9 9
26 * Peripherals IVG10 10
27 * Peripherals IVG11 11
28 * Peripherals IVG12 12
29 * Peripherals IVG13 13
30 * Softirq IVG14 14
31 * System Call IVG15 15 (lowest priority)
32 */
33
34/* The ABSTRACT IRQ definitions */
35#define IRQ_EMU 0 /* Emulation */
36#define IRQ_RST 1 /* reset */
37#define IRQ_NMI 2 /* Non Maskable */
38#define IRQ_EVX 3 /* Exception */
39#define IRQ_UNUSED 4 /* - unused interrupt */
40#define IRQ_HWERR 5 /* Hardware Error */
41#define IRQ_CORETMR 6 /* Core timer */
42
43#define BFIN_IRQ(x) ((x) + 7)
44
45#define IVG7 7
46#define IVG8 8
47#define IVG9 9
48#define IVG10 10
49#define IVG11 11
50#define IVG12 12
51#define IVG13 13
52#define IVG14 14
53#define IVG15 15
54
55#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
56
57#endif
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index ca5ccc77777..d550b24d9e9 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -33,7 +33,10 @@ obj-$(CONFIG_EARLY_PRINTK) += shadow_console.o
33obj-$(CONFIG_STACKTRACE) += stacktrace.o 33obj-$(CONFIG_STACKTRACE) += stacktrace.o
34obj-$(CONFIG_DEBUG_VERBOSE) += trace.o 34obj-$(CONFIG_DEBUG_VERBOSE) += trace.o
35obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o 35obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o
36obj-$(CONFIG_PERF_EVENTS) += perf_event.o
36 37
37# the kgdb test puts code into L2 and without linker 38# the kgdb test puts code into L2 and without linker
38# relaxation, we need to force long calls to/from it 39# relaxation, we need to force long calls to/from it
39CFLAGS_kgdb_test.o := -mlong-calls -O0 40CFLAGS_kgdb_test.o := -mlong-calls -O0
41
42obj-$(CONFIG_DEBUG_MMRS) += debug-mmrs.o
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 6ce8dce753c..71dbaa4a48a 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -36,6 +36,11 @@ static int __init blackfin_dma_init(void)
36 36
37 printk(KERN_INFO "Blackfin DMA Controller\n"); 37 printk(KERN_INFO "Blackfin DMA Controller\n");
38 38
39
40#if ANOMALY_05000480
41 bfin_write_DMAC_TC_PER(0x0111);
42#endif
43
39 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 44 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
40 atomic_set(&dma_ch[i].chan_status, 0); 45 atomic_set(&dma_ch[i].chan_status, 0);
41 dma_ch[i].regs = dma_io_base_addr[i]; 46 dma_ch[i].regs = dma_io_base_addr[i];
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 170cf90735b..bcf8cf6fe41 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -10,10 +10,12 @@
10#include <linux/module.h> 10#include <linux/module.h>
11#include <linux/err.h> 11#include <linux/err.h>
12#include <linux/proc_fs.h> 12#include <linux/proc_fs.h>
13#include <linux/seq_file.h>
13#include <asm/blackfin.h> 14#include <asm/blackfin.h>
14#include <asm/gpio.h> 15#include <asm/gpio.h>
15#include <asm/portmux.h> 16#include <asm/portmux.h>
16#include <linux/irq.h> 17#include <linux/irq.h>
18#include <asm/irq_handler.h>
17 19
18#if ANOMALY_05000311 || ANOMALY_05000323 20#if ANOMALY_05000311 || ANOMALY_05000323
19enum { 21enum {
@@ -534,7 +536,7 @@ static const unsigned int sic_iwr_irqs[] = {
534#if defined(BF533_FAMILY) 536#if defined(BF533_FAMILY)
535 IRQ_PROG_INTB 537 IRQ_PROG_INTB
536#elif defined(BF537_FAMILY) 538#elif defined(BF537_FAMILY)
537 IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX 539 IRQ_PF_INTB_WATCH, IRQ_PORTG_INTB, IRQ_PH_INTB_MAC_TX
538#elif defined(BF538_FAMILY) 540#elif defined(BF538_FAMILY)
539 IRQ_PORTF_INTB 541 IRQ_PORTF_INTB
540#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) 542#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
@@ -1203,35 +1205,43 @@ void bfin_reset_boot_spi_cs(unsigned short pin)
1203} 1205}
1204 1206
1205#if defined(CONFIG_PROC_FS) 1207#if defined(CONFIG_PROC_FS)
1206static int gpio_proc_read(char *buf, char **start, off_t offset, 1208static int gpio_proc_show(struct seq_file *m, void *v)
1207 int len, int *unused_i, void *unused_v)
1208{ 1209{
1209 int c, irq, gpio, outlen = 0; 1210 int c, irq, gpio;
1210 1211
1211 for (c = 0; c < MAX_RESOURCES; c++) { 1212 for (c = 0; c < MAX_RESOURCES; c++) {
1212 irq = is_reserved(gpio_irq, c, 1); 1213 irq = is_reserved(gpio_irq, c, 1);
1213 gpio = is_reserved(gpio, c, 1); 1214 gpio = is_reserved(gpio, c, 1);
1214 if (!check_gpio(c) && (gpio || irq)) 1215 if (!check_gpio(c) && (gpio || irq))
1215 len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c, 1216 seq_printf(m, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
1216 get_label(c), (gpio && irq) ? " *" : "", 1217 get_label(c), (gpio && irq) ? " *" : "",
1217 get_gpio_dir(c) ? "OUTPUT" : "INPUT"); 1218 get_gpio_dir(c) ? "OUTPUT" : "INPUT");
1218 else if (is_reserved(peri, c, 1)) 1219 else if (is_reserved(peri, c, 1))
1219 len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c)); 1220 seq_printf(m, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
1220 else 1221 else
1221 continue; 1222 continue;
1222 buf += len;
1223 outlen += len;
1224 } 1223 }
1225 return outlen; 1224
1225 return 0;
1226} 1226}
1227 1227
1228static int gpio_proc_open(struct inode *inode, struct file *file)
1229{
1230 return single_open(file, gpio_proc_show, NULL);
1231}
1232
1233static const struct file_operations gpio_proc_ops = {
1234 .open = gpio_proc_open,
1235 .read = seq_read,
1236 .llseek = seq_lseek,
1237 .release = single_release,
1238};
1239
1228static __init int gpio_register_proc(void) 1240static __init int gpio_register_proc(void)
1229{ 1241{
1230 struct proc_dir_entry *proc_gpio; 1242 struct proc_dir_entry *proc_gpio;
1231 1243
1232 proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL); 1244 proc_gpio = proc_create("gpio", S_IRUGO, NULL, &gpio_proc_ops);
1233 if (proc_gpio)
1234 proc_gpio->read_proc = gpio_proc_read;
1235 return proc_gpio != NULL; 1245 return proc_gpio != NULL;
1236} 1246}
1237__initcall(gpio_register_proc); 1247__initcall(gpio_register_proc);
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
index 2c264b51566..c446591b961 100644
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -11,6 +11,7 @@
11 11
12#include <asm/cacheflush.h> 12#include <asm/cacheflush.h>
13#include <asm/io.h> 13#include <asm/io.h>
14#include <asm/irq_handler.h>
14 15
15/* Allow people to have their own Blackfin exception handler in a module */ 16/* Allow people to have their own Blackfin exception handler in a module */
16EXPORT_SYMBOL(bfin_return_from_exception); 17EXPORT_SYMBOL(bfin_return_from_exception);
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
new file mode 100644
index 00000000000..94b1d8a0256
--- /dev/null
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -0,0 +1,1860 @@
1/*
2 * debugfs interface to core/system MMRs
3 *
4 * Copyright 2007-2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later
7 */
8
9#include <linux/debugfs.h>
10#include <linux/fs.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13
14#include <asm/blackfin.h>
15#include <asm/gpio.h>
16#include <asm/bfin_can.h>
17#include <asm/bfin_dma.h>
18#include <asm/bfin_ppi.h>
19#include <asm/bfin_serial.h>
20#include <asm/bfin5xx_spi.h>
21#include <asm/bfin_twi.h>
22
23/* Common code defines PORT_MUX on us, so redirect the MMR back locally */
24#ifdef BFIN_PORT_MUX
25#undef PORT_MUX
26#define PORT_MUX BFIN_PORT_MUX
27#endif
28
29#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)addr)
30#define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
31#define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
32#define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
33
34#define D_RO(name, bits) d_RO(#name, bits, name)
35#define D_WO(name, bits) d_WO(#name, bits, name)
36#define D32(name) d(#name, 32, name)
37#define D16(name) d(#name, 16, name)
38
39#define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
40#define __REGS(peri, sname, rname) \
41 do { \
42 struct bfin_##peri##_regs r; \
43 void *addr = (void *)(base + REGS_OFF(peri, rname)); \
44 strcpy(_buf, sname); \
45 if (sizeof(r.rname) == 2) \
46 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
47 else \
48 debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
49 } while (0)
50#define REGS_STR_PFX(buf, pfx, num) \
51 ({ \
52 buf + (num >= 0 ? \
53 sprintf(buf, #pfx "%i_", num) : \
54 sprintf(buf, #pfx "_")); \
55 })
56#define REGS_STR_PFX_C(buf, pfx, num) \
57 ({ \
58 buf + (num >= 0 ? \
59 sprintf(buf, #pfx "%c_", 'A' + num) : \
60 sprintf(buf, #pfx "_")); \
61 })
62
63/*
64 * Core registers (not memory mapped)
65 */
66extern u32 last_seqstat;
67
68static int debug_cclk_get(void *data, u64 *val)
69{
70 *val = get_cclk();
71 return 0;
72}
73DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
74
75static int debug_sclk_get(void *data, u64 *val)
76{
77 *val = get_sclk();
78 return 0;
79}
80DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
81
82#define DEFINE_SYSREG(sr, pre, post) \
83static int sysreg_##sr##_get(void *data, u64 *val) \
84{ \
85 unsigned long tmp; \
86 pre; \
87 __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
88 *val = tmp; \
89 return 0; \
90} \
91static int sysreg_##sr##_set(void *data, u64 val) \
92{ \
93 unsigned long tmp = val; \
94 __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
95 post; \
96 return 0; \
97} \
98DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
99
100DEFINE_SYSREG(cycles, , );
101DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
102DEFINE_SYSREG(emudat, , );
103DEFINE_SYSREG(seqstat, , );
104DEFINE_SYSREG(syscfg, , CSYNC());
105#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
106
107/*
108 * CAN
109 */
110#define CAN_OFF(mmr) REGS_OFF(can, mmr)
111#define __CAN(uname, lname) __REGS(can, #uname, lname)
112static void __init __maybe_unused
113bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
114{
115 static struct dentry *am, *mb;
116 int i, j;
117 char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
118
119 if (!am) {
120 am = debugfs_create_dir("am", parent);
121 mb = debugfs_create_dir("mb", parent);
122 }
123
124 __CAN(MC1, mc1);
125 __CAN(MD1, md1);
126 __CAN(TRS1, trs1);
127 __CAN(TRR1, trr1);
128 __CAN(TA1, ta1);
129 __CAN(AA1, aa1);
130 __CAN(RMP1, rmp1);
131 __CAN(RML1, rml1);
132 __CAN(MBTIF1, mbtif1);
133 __CAN(MBRIF1, mbrif1);
134 __CAN(MBIM1, mbim1);
135 __CAN(RFH1, rfh1);
136 __CAN(OPSS1, opss1);
137
138 __CAN(MC2, mc2);
139 __CAN(MD2, md2);
140 __CAN(TRS2, trs2);
141 __CAN(TRR2, trr2);
142 __CAN(TA2, ta2);
143 __CAN(AA2, aa2);
144 __CAN(RMP2, rmp2);
145 __CAN(RML2, rml2);
146 __CAN(MBTIF2, mbtif2);
147 __CAN(MBRIF2, mbrif2);
148 __CAN(MBIM2, mbim2);
149 __CAN(RFH2, rfh2);
150 __CAN(OPSS2, opss2);
151
152 __CAN(CLOCK, clock);
153 __CAN(TIMING, timing);
154 __CAN(DEBUG, debug);
155 __CAN(STATUS, status);
156 __CAN(CEC, cec);
157 __CAN(GIS, gis);
158 __CAN(GIM, gim);
159 __CAN(GIF, gif);
160 __CAN(CONTROL, control);
161 __CAN(INTR, intr);
162 __CAN(VERSION, version);
163 __CAN(MBTD, mbtd);
164 __CAN(EWR, ewr);
165 __CAN(ESR, esr);
166 /*__CAN(UCREG, ucreg); no longer exists */
167 __CAN(UCCNT, uccnt);
168 __CAN(UCRC, ucrc);
169 __CAN(UCCNF, uccnf);
170 __CAN(VERSION2, version2);
171
172 for (i = 0; i < 32; ++i) {
173 sprintf(_buf, "AM%02iL", i);
174 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
175 (u16 *)(base + CAN_OFF(msk[i].aml)));
176 sprintf(_buf, "AM%02iH", i);
177 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
178 (u16 *)(base + CAN_OFF(msk[i].amh)));
179
180 for (j = 0; j < 3; ++j) {
181 sprintf(_buf, "MB%02i_DATA%i", i, j);
182 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
183 (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
184 }
185 sprintf(_buf, "MB%02i_LENGTH", i);
186 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
187 (u16 *)(base + CAN_OFF(chl[i].dlc)));
188 sprintf(_buf, "MB%02i_TIMESTAMP", i);
189 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
190 (u16 *)(base + CAN_OFF(chl[i].tsv)));
191 sprintf(_buf, "MB%02i_ID0", i);
192 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
193 (u16 *)(base + CAN_OFF(chl[i].id0)));
194 sprintf(_buf, "MB%02i_ID1", i);
195 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
196 (u16 *)(base + CAN_OFF(chl[i].id1)));
197 }
198}
199#define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
200
201/*
202 * DMA
203 */
204#define __DMA(uname, lname) __REGS(dma, #uname, lname)
205static void __init __maybe_unused
206bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
207{
208 char buf[32], *_buf;
209
210 if (mdma)
211 _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
212 else
213 _buf = buf + sprintf(buf, "%s%i_", pfx, num);
214
215 __DMA(NEXT_DESC_PTR, next_desc_ptr);
216 __DMA(START_ADDR, start_addr);
217 __DMA(CONFIG, config);
218 __DMA(X_COUNT, x_count);
219 __DMA(X_MODIFY, x_modify);
220 __DMA(Y_COUNT, y_count);
221 __DMA(Y_MODIFY, y_modify);
222 __DMA(CURR_DESC_PTR, curr_desc_ptr);
223 __DMA(CURR_ADDR, curr_addr);
224 __DMA(IRQ_STATUS, irq_status);
225 __DMA(PERIPHERAL_MAP, peripheral_map);
226 __DMA(CURR_X_COUNT, curr_x_count);
227 __DMA(CURR_Y_COUNT, curr_y_count);
228}
229#define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
230#define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
231#define _MDMA(num, x) \
232 do { \
233 _DMA(num, x##DMA_D##num##_CONFIG, 'D', #x); \
234 _DMA(num, x##DMA_S##num##_CONFIG, 'S', #x); \
235 } while (0)
236#define MDMA(num) _MDMA(num, M)
237#define IMDMA(num) _MDMA(num, IM)
238
239/*
240 * EPPI
241 */
242#define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
243static void __init __maybe_unused
244bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
245{
246 char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
247 __EPPI(STATUS, status);
248 __EPPI(HCOUNT, hcount);
249 __EPPI(HDELAY, hdelay);
250 __EPPI(VCOUNT, vcount);
251 __EPPI(VDELAY, vdelay);
252 __EPPI(FRAME, frame);
253 __EPPI(LINE, line);
254 __EPPI(CLKDIV, clkdiv);
255 __EPPI(CONTROL, control);
256 __EPPI(FS1W_HBL, fs1w_hbl);
257 __EPPI(FS1P_AVPL, fs1p_avpl);
258 __EPPI(FS2W_LVB, fs2w_lvb);
259 __EPPI(FS2P_LAVF, fs2p_lavf);
260 __EPPI(CLIP, clip);
261}
262#define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
263
264/*
265 * General Purpose Timers
266 */
267#define GPTIMER_OFF(mmr) (TIMER0_##mmr - TIMER0_CONFIG)
268#define __GPTIMER(name) \
269 do { \
270 strcpy(_buf, #name); \
271 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, (u16 *)(base + GPTIMER_OFF(name))); \
272 } while (0)
273static void __init __maybe_unused
274bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
275{
276 char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
277 __GPTIMER(CONFIG);
278 __GPTIMER(COUNTER);
279 __GPTIMER(PERIOD);
280 __GPTIMER(WIDTH);
281}
282#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
283
284/*
285 * Handshake MDMA
286 */
287#define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
288static void __init __maybe_unused
289bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
290{
291 char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
292 __HMDMA(CONTROL, control);
293 __HMDMA(ECINIT, ecinit);
294 __HMDMA(BCINIT, bcinit);
295 __HMDMA(ECURGENT, ecurgent);
296 __HMDMA(ECOVERFLOW, ecoverflow);
297 __HMDMA(ECOUNT, ecount);
298 __HMDMA(BCOUNT, bcount);
299}
300#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
301
302/*
303 * Port/GPIO
304 */
305#define bfin_gpio_regs gpio_port_t
306#define __PORT(uname, lname) __REGS(gpio, #uname, lname)
307static void __init __maybe_unused
308bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
309{
310 char buf[32], *_buf;
311#ifdef __ADSPBF54x__
312 _buf = REGS_STR_PFX_C(buf, PORT, num);
313 __PORT(FER, port_fer);
314 __PORT(SET, data_set);
315 __PORT(CLEAR, data_clear);
316 __PORT(DIR_SET, dir_set);
317 __PORT(DIR_CLEAR, dir_clear);
318 __PORT(INEN, inen);
319 __PORT(MUX, port_mux);
320#else
321 _buf = buf + sprintf(buf, "PORT%cIO_", num);
322 __PORT(CLEAR, data_clear);
323 __PORT(SET, data_set);
324 __PORT(TOGGLE, toggle);
325 __PORT(MASKA, maska);
326 __PORT(MASKA_CLEAR, maska_clear);
327 __PORT(MASKA_SET, maska_set);
328 __PORT(MASKA_TOGGLE, maska_toggle);
329 __PORT(MASKB, maskb);
330 __PORT(MASKB_CLEAR, maskb_clear);
331 __PORT(MASKB_SET, maskb_set);
332 __PORT(MASKB_TOGGLE, maskb_toggle);
333 __PORT(DIR, dir);
334 __PORT(POLAR, polar);
335 __PORT(EDGE, edge);
336 __PORT(BOTH, both);
337 __PORT(INEN, inen);
338#endif
339 _buf[-1] = '\0';
340 d(buf, 16, base + REGS_OFF(gpio, data));
341}
342#define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
343
344/*
345 * PPI
346 */
347#define __PPI(uname, lname) __REGS(ppi, #uname, lname)
348static void __init __maybe_unused
349bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
350{
351 char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
352 __PPI(CONTROL, control);
353 __PPI(STATUS, status);
354 __PPI(COUNT, count);
355 __PPI(DELAY, delay);
356 __PPI(FRAME, frame);
357}
358#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_STATUS, num)
359
360/*
361 * SPI
362 */
363#define __SPI(uname, lname) __REGS(spi, #uname, lname)
364static void __init __maybe_unused
365bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
366{
367 char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
368 __SPI(CTL, ctl);
369 __SPI(FLG, flg);
370 __SPI(STAT, stat);
371 __SPI(TDBR, tdbr);
372 __SPI(RDBR, rdbr);
373 __SPI(BAUD, baud);
374 __SPI(SHADOW, shadow);
375}
376#define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
377
378/*
379 * SPORT
380 */
381static inline int sport_width(void *mmr)
382{
383 unsigned long lmmr = (unsigned long)mmr;
384 if ((lmmr & 0xff) == 0x10)
385 /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
386 lmmr -= 0xc;
387 else
388 /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
389 lmmr += 0xc;
390 /* extract SLEN field from control register 2 and add 1 */
391 return (bfin_read16(lmmr) & 0x1f) + 1;
392}
393static int sport_set(void *mmr, u64 val)
394{
395 unsigned long flags;
396 local_irq_save(flags);
397 if (sport_width(mmr) <= 16)
398 bfin_write16(mmr, val);
399 else
400 bfin_write32(mmr, val);
401 local_irq_restore(flags);
402 return 0;
403}
404static int sport_get(void *mmr, u64 *val)
405{
406 unsigned long flags;
407 local_irq_save(flags);
408 if (sport_width(mmr) <= 16)
409 *val = bfin_read16(mmr);
410 else
411 *val = bfin_read32(mmr);
412 local_irq_restore(flags);
413 return 0;
414}
415DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
416/*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
417DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
418#define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
419#define _D_SPORT(name, perms, fops) \
420 do { \
421 strcpy(_buf, #name); \
422 debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
423 } while (0)
424#define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
425#define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
426#define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
427#define __SPORT(name, bits) \
428 do { \
429 strcpy(_buf, #name); \
430 debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
431 } while (0)
432static void __init __maybe_unused
433bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
434{
435 char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
436 __SPORT(CHNL, 16);
437 __SPORT(MCMC1, 16);
438 __SPORT(MCMC2, 16);
439 __SPORT(MRCS0, 32);
440 __SPORT(MRCS1, 32);
441 __SPORT(MRCS2, 32);
442 __SPORT(MRCS3, 32);
443 __SPORT(MTCS0, 32);
444 __SPORT(MTCS1, 32);
445 __SPORT(MTCS2, 32);
446 __SPORT(MTCS3, 32);
447 __SPORT(RCLKDIV, 16);
448 __SPORT(RCR1, 16);
449 __SPORT(RCR2, 16);
450 __SPORT(RFSDIV, 16);
451 __SPORT_RW(RX);
452 __SPORT(STAT, 16);
453 __SPORT(TCLKDIV, 16);
454 __SPORT(TCR1, 16);
455 __SPORT(TCR2, 16);
456 __SPORT(TFSDIV, 16);
457 __SPORT_WO(TX);
458}
459#define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
460
461/*
462 * TWI
463 */
464#define __TWI(uname, lname) __REGS(twi, #uname, lname)
465static void __init __maybe_unused
466bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
467{
468 char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
469 __TWI(CLKDIV, clkdiv);
470 __TWI(CONTROL, control);
471 __TWI(SLAVE_CTL, slave_ctl);
472 __TWI(SLAVE_STAT, slave_stat);
473 __TWI(SLAVE_ADDR, slave_addr);
474 __TWI(MASTER_CTL, master_ctl);
475 __TWI(MASTER_STAT, master_stat);
476 __TWI(MASTER_ADDR, master_addr);
477 __TWI(INT_STAT, int_stat);
478 __TWI(INT_MASK, int_mask);
479 __TWI(FIFO_CTL, fifo_ctl);
480 __TWI(FIFO_STAT, fifo_stat);
481 __TWI(XMT_DATA8, xmt_data8);
482 __TWI(XMT_DATA16, xmt_data16);
483 __TWI(RCV_DATA8, rcv_data8);
484 __TWI(RCV_DATA16, rcv_data16);
485}
486#define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
487
488/*
489 * UART
490 */
491#define __UART(uname, lname) __REGS(uart, #uname, lname)
492static void __init __maybe_unused
493bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
494{
495 char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
496#ifdef BFIN_UART_BF54X_STYLE
497 __UART(DLL, dll);
498 __UART(DLH, dlh);
499 __UART(GCTL, gctl);
500 __UART(LCR, lcr);
501 __UART(MCR, mcr);
502 __UART(LSR, lsr);
503 __UART(MSR, msr);
504 __UART(SCR, scr);
505 __UART(IER_SET, ier_set);
506 __UART(IER_CLEAR, ier_clear);
507 __UART(THR, thr);
508 __UART(RBR, rbr);
509#else
510 __UART(DLL, dll);
511 __UART(THR, thr);
512 __UART(RBR, rbr);
513 __UART(DLH, dlh);
514 __UART(IER, ier);
515 __UART(IIR, iir);
516 __UART(LCR, lcr);
517 __UART(MCR, mcr);
518 __UART(LSR, lsr);
519 __UART(MSR, msr);
520 __UART(SCR, scr);
521 __UART(GCTL, gctl);
522#endif
523}
524#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
525
526/*
527 * The actual debugfs generation
528 */
529static struct dentry *debug_mmrs_dentry;
530
531static int __init bfin_debug_mmrs_init(void)
532{
533 struct dentry *top, *parent;
534
535 pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
536
537 top = debugfs_create_dir("blackfin", NULL);
538 if (top == NULL)
539 return -1;
540
541 parent = debugfs_create_dir("core_regs", top);
542 debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
543 debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
544 debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
545 D_SYSREG(cycles);
546 D_SYSREG(cycles2);
547 D_SYSREG(emudat);
548 D_SYSREG(seqstat);
549 D_SYSREG(syscfg);
550
551 /* Core MMRs */
552 parent = debugfs_create_dir("ctimer", top);
553 D32(TCNTL);
554 D32(TCOUNT);
555 D32(TPERIOD);
556 D32(TSCALE);
557
558 parent = debugfs_create_dir("cec", top);
559 D32(EVT0);
560 D32(EVT1);
561 D32(EVT2);
562 D32(EVT3);
563 D32(EVT4);
564 D32(EVT5);
565 D32(EVT6);
566 D32(EVT7);
567 D32(EVT8);
568 D32(EVT9);
569 D32(EVT10);
570 D32(EVT11);
571 D32(EVT12);
572 D32(EVT13);
573 D32(EVT14);
574 D32(EVT15);
575 D32(EVT_OVERRIDE);
576 D32(IMASK);
577 D32(IPEND);
578 D32(ILAT);
579 D32(IPRIO);
580
581 parent = debugfs_create_dir("debug", top);
582 D32(DBGSTAT);
583 D32(DSPID);
584
585 parent = debugfs_create_dir("mmu", top);
586 D32(SRAM_BASE_ADDRESS);
587 D32(DCPLB_ADDR0);
588 D32(DCPLB_ADDR10);
589 D32(DCPLB_ADDR11);
590 D32(DCPLB_ADDR12);
591 D32(DCPLB_ADDR13);
592 D32(DCPLB_ADDR14);
593 D32(DCPLB_ADDR15);
594 D32(DCPLB_ADDR1);
595 D32(DCPLB_ADDR2);
596 D32(DCPLB_ADDR3);
597 D32(DCPLB_ADDR4);
598 D32(DCPLB_ADDR5);
599 D32(DCPLB_ADDR6);
600 D32(DCPLB_ADDR7);
601 D32(DCPLB_ADDR8);
602 D32(DCPLB_ADDR9);
603 D32(DCPLB_DATA0);
604 D32(DCPLB_DATA10);
605 D32(DCPLB_DATA11);
606 D32(DCPLB_DATA12);
607 D32(DCPLB_DATA13);
608 D32(DCPLB_DATA14);
609 D32(DCPLB_DATA15);
610 D32(DCPLB_DATA1);
611 D32(DCPLB_DATA2);
612 D32(DCPLB_DATA3);
613 D32(DCPLB_DATA4);
614 D32(DCPLB_DATA5);
615 D32(DCPLB_DATA6);
616 D32(DCPLB_DATA7);
617 D32(DCPLB_DATA8);
618 D32(DCPLB_DATA9);
619 D32(DCPLB_FAULT_ADDR);
620 D32(DCPLB_STATUS);
621 D32(DMEM_CONTROL);
622 D32(DTEST_COMMAND);
623 D32(DTEST_DATA0);
624 D32(DTEST_DATA1);
625
626 D32(ICPLB_ADDR0);
627 D32(ICPLB_ADDR1);
628 D32(ICPLB_ADDR2);
629 D32(ICPLB_ADDR3);
630 D32(ICPLB_ADDR4);
631 D32(ICPLB_ADDR5);
632 D32(ICPLB_ADDR6);
633 D32(ICPLB_ADDR7);
634 D32(ICPLB_ADDR8);
635 D32(ICPLB_ADDR9);
636 D32(ICPLB_ADDR10);
637 D32(ICPLB_ADDR11);
638 D32(ICPLB_ADDR12);
639 D32(ICPLB_ADDR13);
640 D32(ICPLB_ADDR14);
641 D32(ICPLB_ADDR15);
642 D32(ICPLB_DATA0);
643 D32(ICPLB_DATA1);
644 D32(ICPLB_DATA2);
645 D32(ICPLB_DATA3);
646 D32(ICPLB_DATA4);
647 D32(ICPLB_DATA5);
648 D32(ICPLB_DATA6);
649 D32(ICPLB_DATA7);
650 D32(ICPLB_DATA8);
651 D32(ICPLB_DATA9);
652 D32(ICPLB_DATA10);
653 D32(ICPLB_DATA11);
654 D32(ICPLB_DATA12);
655 D32(ICPLB_DATA13);
656 D32(ICPLB_DATA14);
657 D32(ICPLB_DATA15);
658 D32(ICPLB_FAULT_ADDR);
659 D32(ICPLB_STATUS);
660 D32(IMEM_CONTROL);
661 if (!ANOMALY_05000481) {
662 D32(ITEST_COMMAND);
663 D32(ITEST_DATA0);
664 D32(ITEST_DATA1);
665 }
666
667 parent = debugfs_create_dir("perf", top);
668 D32(PFCNTR0);
669 D32(PFCNTR1);
670 D32(PFCTL);
671
672 parent = debugfs_create_dir("trace", top);
673 D32(TBUF);
674 D32(TBUFCTL);
675 D32(TBUFSTAT);
676
677 parent = debugfs_create_dir("watchpoint", top);
678 D32(WPIACTL);
679 D32(WPIA0);
680 D32(WPIA1);
681 D32(WPIA2);
682 D32(WPIA3);
683 D32(WPIA4);
684 D32(WPIA5);
685 D32(WPIACNT0);
686 D32(WPIACNT1);
687 D32(WPIACNT2);
688 D32(WPIACNT3);
689 D32(WPIACNT4);
690 D32(WPIACNT5);
691 D32(WPDACTL);
692 D32(WPDA0);
693 D32(WPDA1);
694 D32(WPDACNT0);
695 D32(WPDACNT1);
696 D32(WPSTAT);
697
698 /* System MMRs */
699#ifdef ATAPI_CONTROL
700 parent = debugfs_create_dir("atapi", top);
701 D16(ATAPI_CONTROL);
702 D16(ATAPI_DEV_ADDR);
703 D16(ATAPI_DEV_RXBUF);
704 D16(ATAPI_DEV_TXBUF);
705 D16(ATAPI_DMA_TFRCNT);
706 D16(ATAPI_INT_MASK);
707 D16(ATAPI_INT_STATUS);
708 D16(ATAPI_LINE_STATUS);
709 D16(ATAPI_MULTI_TIM_0);
710 D16(ATAPI_MULTI_TIM_1);
711 D16(ATAPI_MULTI_TIM_2);
712 D16(ATAPI_PIO_TFRCNT);
713 D16(ATAPI_PIO_TIM_0);
714 D16(ATAPI_PIO_TIM_1);
715 D16(ATAPI_REG_TIM_0);
716 D16(ATAPI_SM_STATE);
717 D16(ATAPI_STATUS);
718 D16(ATAPI_TERMINATE);
719 D16(ATAPI_UDMAOUT_TFRCNT);
720 D16(ATAPI_ULTRA_TIM_0);
721 D16(ATAPI_ULTRA_TIM_1);
722 D16(ATAPI_ULTRA_TIM_2);
723 D16(ATAPI_ULTRA_TIM_3);
724 D16(ATAPI_UMAIN_TFRCNT);
725 D16(ATAPI_XFER_LEN);
726#endif
727
728#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
729 parent = debugfs_create_dir("can", top);
730# ifdef CAN_MC1
731 bfin_debug_mmrs_can(parent, CAN_MC1, -1);
732# endif
733# ifdef CAN0_MC1
734 CAN(0);
735# endif
736# ifdef CAN1_MC1
737 CAN(1);
738# endif
739#endif
740
741#ifdef CNT_COMMAND
742 parent = debugfs_create_dir("counter", top);
743 D16(CNT_COMMAND);
744 D16(CNT_CONFIG);
745 D32(CNT_COUNTER);
746 D16(CNT_DEBOUNCE);
747 D16(CNT_IMASK);
748 D32(CNT_MAX);
749 D32(CNT_MIN);
750 D16(CNT_STATUS);
751#endif
752
753 parent = debugfs_create_dir("dmac", top);
754#ifdef DMA_TC_CNT
755 D16(DMAC_TC_CNT);
756 D16(DMAC_TC_PER);
757#endif
758#ifdef DMAC0_TC_CNT
759 D16(DMAC0_TC_CNT);
760 D16(DMAC0_TC_PER);
761#endif
762#ifdef DMAC1_TC_CNT
763 D16(DMAC1_TC_CNT);
764 D16(DMAC1_TC_PER);
765#endif
766#ifdef DMAC1_PERIMUX
767 D16(DMAC1_PERIMUX);
768#endif
769
770#ifdef __ADSPBF561__
771 /* XXX: should rewrite the MMR map */
772# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
773# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
774# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
775# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
776# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
777# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
778# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
779# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
780# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
781# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
782# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
783# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
784# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
785# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
786# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
787# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
788# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
789# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
790# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
791# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
792# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
793# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
794# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
795# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
796#endif
797 parent = debugfs_create_dir("dma", top);
798 DMA(0);
799 DMA(1);
800 DMA(1);
801 DMA(2);
802 DMA(3);
803 DMA(4);
804 DMA(5);
805 DMA(6);
806 DMA(7);
807#ifdef DMA8_NEXT_DESC_PTR
808 DMA(8);
809 DMA(9);
810 DMA(10);
811 DMA(11);
812#endif
813#ifdef DMA12_NEXT_DESC_PTR
814 DMA(12);
815 DMA(13);
816 DMA(14);
817 DMA(15);
818 DMA(16);
819 DMA(17);
820 DMA(18);
821 DMA(19);
822#endif
823#ifdef DMA20_NEXT_DESC_PTR
824 DMA(20);
825 DMA(21);
826 DMA(22);
827 DMA(23);
828#endif
829
830 parent = debugfs_create_dir("ebiu_amc", top);
831 D32(EBIU_AMBCTL0);
832 D32(EBIU_AMBCTL1);
833 D16(EBIU_AMGCTL);
834#ifdef EBIU_MBSCTL
835 D16(EBIU_MBSCTL);
836 D32(EBIU_ARBSTAT);
837 D32(EBIU_MODE);
838 D16(EBIU_FCTL);
839#endif
840
841#ifdef EBIU_SDGCTL
842 parent = debugfs_create_dir("ebiu_sdram", top);
843# ifdef __ADSPBF561__
844 D32(EBIU_SDBCTL);
845# else
846 D16(EBIU_SDBCTL);
847# endif
848 D32(EBIU_SDGCTL);
849 D16(EBIU_SDRRC);
850 D16(EBIU_SDSTAT);
851#endif
852
853#ifdef EBIU_DDRACCT
854 parent = debugfs_create_dir("ebiu_ddr", top);
855 D32(EBIU_DDRACCT);
856 D32(EBIU_DDRARCT);
857 D32(EBIU_DDRBRC0);
858 D32(EBIU_DDRBRC1);
859 D32(EBIU_DDRBRC2);
860 D32(EBIU_DDRBRC3);
861 D32(EBIU_DDRBRC4);
862 D32(EBIU_DDRBRC5);
863 D32(EBIU_DDRBRC6);
864 D32(EBIU_DDRBRC7);
865 D32(EBIU_DDRBWC0);
866 D32(EBIU_DDRBWC1);
867 D32(EBIU_DDRBWC2);
868 D32(EBIU_DDRBWC3);
869 D32(EBIU_DDRBWC4);
870 D32(EBIU_DDRBWC5);
871 D32(EBIU_DDRBWC6);
872 D32(EBIU_DDRBWC7);
873 D32(EBIU_DDRCTL0);
874 D32(EBIU_DDRCTL1);
875 D32(EBIU_DDRCTL2);
876 D32(EBIU_DDRCTL3);
877 D32(EBIU_DDRGC0);
878 D32(EBIU_DDRGC1);
879 D32(EBIU_DDRGC2);
880 D32(EBIU_DDRGC3);
881 D32(EBIU_DDRMCCL);
882 D32(EBIU_DDRMCEN);
883 D32(EBIU_DDRQUE);
884 D32(EBIU_DDRTACT);
885 D32(EBIU_ERRADD);
886 D16(EBIU_ERRMST);
887 D16(EBIU_RSTCTL);
888#endif
889
890#ifdef EMAC_ADDRHI
891 parent = debugfs_create_dir("emac", top);
892 D32(EMAC_ADDRHI);
893 D32(EMAC_ADDRLO);
894 D32(EMAC_FLC);
895 D32(EMAC_HASHHI);
896 D32(EMAC_HASHLO);
897 D32(EMAC_MMC_CTL);
898 D32(EMAC_MMC_RIRQE);
899 D32(EMAC_MMC_RIRQS);
900 D32(EMAC_MMC_TIRQE);
901 D32(EMAC_MMC_TIRQS);
902 D32(EMAC_OPMODE);
903 D32(EMAC_RXC_ALIGN);
904 D32(EMAC_RXC_ALLFRM);
905 D32(EMAC_RXC_ALLOCT);
906 D32(EMAC_RXC_BROAD);
907 D32(EMAC_RXC_DMAOVF);
908 D32(EMAC_RXC_EQ64);
909 D32(EMAC_RXC_FCS);
910 D32(EMAC_RXC_GE1024);
911 D32(EMAC_RXC_LNERRI);
912 D32(EMAC_RXC_LNERRO);
913 D32(EMAC_RXC_LONG);
914 D32(EMAC_RXC_LT1024);
915 D32(EMAC_RXC_LT128);
916 D32(EMAC_RXC_LT256);
917 D32(EMAC_RXC_LT512);
918 D32(EMAC_RXC_MACCTL);
919 D32(EMAC_RXC_MULTI);
920 D32(EMAC_RXC_OCTET);
921 D32(EMAC_RXC_OK);
922 D32(EMAC_RXC_OPCODE);
923 D32(EMAC_RXC_PAUSE);
924 D32(EMAC_RXC_SHORT);
925 D32(EMAC_RXC_TYPED);
926 D32(EMAC_RXC_UNICST);
927 D32(EMAC_RX_IRQE);
928 D32(EMAC_RX_STAT);
929 D32(EMAC_RX_STKY);
930 D32(EMAC_STAADD);
931 D32(EMAC_STADAT);
932 D32(EMAC_SYSCTL);
933 D32(EMAC_SYSTAT);
934 D32(EMAC_TXC_1COL);
935 D32(EMAC_TXC_ABORT);
936 D32(EMAC_TXC_ALLFRM);
937 D32(EMAC_TXC_ALLOCT);
938 D32(EMAC_TXC_BROAD);
939 D32(EMAC_TXC_CRSERR);
940 D32(EMAC_TXC_DEFER);
941 D32(EMAC_TXC_DMAUND);
942 D32(EMAC_TXC_EQ64);
943 D32(EMAC_TXC_GE1024);
944 D32(EMAC_TXC_GT1COL);
945 D32(EMAC_TXC_LATECL);
946 D32(EMAC_TXC_LT1024);
947 D32(EMAC_TXC_LT128);
948 D32(EMAC_TXC_LT256);
949 D32(EMAC_TXC_LT512);
950 D32(EMAC_TXC_MACCTL);
951 D32(EMAC_TXC_MULTI);
952 D32(EMAC_TXC_OCTET);
953 D32(EMAC_TXC_OK);
954 D32(EMAC_TXC_UNICST);
955 D32(EMAC_TXC_XS_COL);
956 D32(EMAC_TXC_XS_DFR);
957 D32(EMAC_TX_IRQE);
958 D32(EMAC_TX_STAT);
959 D32(EMAC_TX_STKY);
960 D32(EMAC_VLAN1);
961 D32(EMAC_VLAN2);
962 D32(EMAC_WKUP_CTL);
963 D32(EMAC_WKUP_FFCMD);
964 D32(EMAC_WKUP_FFCRC0);
965 D32(EMAC_WKUP_FFCRC1);
966 D32(EMAC_WKUP_FFMSK0);
967 D32(EMAC_WKUP_FFMSK1);
968 D32(EMAC_WKUP_FFMSK2);
969 D32(EMAC_WKUP_FFMSK3);
970 D32(EMAC_WKUP_FFOFF);
971# ifdef EMAC_PTP_ACCR
972 D32(EMAC_PTP_ACCR);
973 D32(EMAC_PTP_ADDEND);
974 D32(EMAC_PTP_ALARMHI);
975 D32(EMAC_PTP_ALARMLO);
976 D16(EMAC_PTP_CTL);
977 D32(EMAC_PTP_FOFF);
978 D32(EMAC_PTP_FV1);
979 D32(EMAC_PTP_FV2);
980 D32(EMAC_PTP_FV3);
981 D16(EMAC_PTP_ID_OFF);
982 D32(EMAC_PTP_ID_SNAP);
983 D16(EMAC_PTP_IE);
984 D16(EMAC_PTP_ISTAT);
985 D32(EMAC_PTP_OFFSET);
986 D32(EMAC_PTP_PPS_PERIOD);
987 D32(EMAC_PTP_PPS_STARTHI);
988 D32(EMAC_PTP_PPS_STARTLO);
989 D32(EMAC_PTP_RXSNAPHI);
990 D32(EMAC_PTP_RXSNAPLO);
991 D32(EMAC_PTP_TIMEHI);
992 D32(EMAC_PTP_TIMELO);
993 D32(EMAC_PTP_TXSNAPHI);
994 D32(EMAC_PTP_TXSNAPLO);
995# endif
996#endif
997
998#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
999 parent = debugfs_create_dir("eppi", top);
1000# ifdef EPPI0_STATUS
1001 EPPI(0);
1002# endif
1003# ifdef EPPI1_STATUS
1004 EPPI(1);
1005# endif
1006# ifdef EPPI2_STATUS
1007 EPPI(2);
1008# endif
1009#endif
1010
1011 parent = debugfs_create_dir("gptimer", top);
1012#ifdef TIMER_DISABLE
1013 D16(TIMER_DISABLE);
1014 D16(TIMER_ENABLE);
1015 D32(TIMER_STATUS);
1016#endif
1017#ifdef TIMER_DISABLE0
1018 D16(TIMER_DISABLE0);
1019 D16(TIMER_ENABLE0);
1020 D32(TIMER_STATUS0);
1021#endif
1022#ifdef TIMER_DISABLE1
1023 D16(TIMER_DISABLE1);
1024 D16(TIMER_ENABLE1);
1025 D32(TIMER_STATUS1);
1026#endif
1027 /* XXX: Should convert BF561 MMR names */
1028#ifdef TMRS4_DISABLE
1029 D16(TMRS4_DISABLE);
1030 D16(TMRS4_ENABLE);
1031 D32(TMRS4_STATUS);
1032 D16(TMRS8_DISABLE);
1033 D16(TMRS8_ENABLE);
1034 D32(TMRS8_STATUS);
1035#endif
1036 GPTIMER(0);
1037 GPTIMER(1);
1038 GPTIMER(2);
1039#ifdef TIMER3_CONFIG
1040 GPTIMER(3);
1041 GPTIMER(4);
1042 GPTIMER(5);
1043 GPTIMER(6);
1044 GPTIMER(7);
1045#endif
1046#ifdef TIMER8_CONFIG
1047 GPTIMER(8);
1048 GPTIMER(9);
1049 GPTIMER(10);
1050#endif
1051#ifdef TIMER11_CONFIG
1052 GPTIMER(11);
1053#endif
1054
1055#ifdef HMDMA0_CONTROL
1056 parent = debugfs_create_dir("hmdma", top);
1057 HMDMA(0);
1058 HMDMA(1);
1059#endif
1060
1061#ifdef HOST_CONTROL
1062 parent = debugfs_create_dir("hostdp", top);
1063 D16(HOST_CONTROL);
1064 D16(HOST_STATUS);
1065 D16(HOST_TIMEOUT);
1066#endif
1067
1068#ifdef IMDMA_S0_CONFIG
1069 parent = debugfs_create_dir("imdma", top);
1070 IMDMA(0);
1071 IMDMA(1);
1072#endif
1073
1074#ifdef KPAD_CTL
1075 parent = debugfs_create_dir("keypad", top);
1076 D16(KPAD_CTL);
1077 D16(KPAD_PRESCALE);
1078 D16(KPAD_MSEL);
1079 D16(KPAD_ROWCOL);
1080 D16(KPAD_STAT);
1081 D16(KPAD_SOFTEVAL);
1082#endif
1083
1084 parent = debugfs_create_dir("mdma", top);
1085 MDMA(0);
1086 MDMA(1);
1087#ifdef MDMA_D2_CONFIG
1088 MDMA(2);
1089 MDMA(3);
1090#endif
1091
1092#ifdef MXVR_CONFIG
1093 parent = debugfs_create_dir("mxvr", top);
1094 D16(MXVR_CONFIG);
1095# ifdef MXVR_PLL_CTL_0
1096 D32(MXVR_PLL_CTL_0);
1097# endif
1098 D32(MXVR_STATE_0);
1099 D32(MXVR_STATE_1);
1100 D32(MXVR_INT_STAT_0);
1101 D32(MXVR_INT_STAT_1);
1102 D32(MXVR_INT_EN_0);
1103 D32(MXVR_INT_EN_1);
1104 D16(MXVR_POSITION);
1105 D16(MXVR_MAX_POSITION);
1106 D16(MXVR_DELAY);
1107 D16(MXVR_MAX_DELAY);
1108 D32(MXVR_LADDR);
1109 D16(MXVR_GADDR);
1110 D32(MXVR_AADDR);
1111 D32(MXVR_ALLOC_0);
1112 D32(MXVR_ALLOC_1);
1113 D32(MXVR_ALLOC_2);
1114 D32(MXVR_ALLOC_3);
1115 D32(MXVR_ALLOC_4);
1116 D32(MXVR_ALLOC_5);
1117 D32(MXVR_ALLOC_6);
1118 D32(MXVR_ALLOC_7);
1119 D32(MXVR_ALLOC_8);
1120 D32(MXVR_ALLOC_9);
1121 D32(MXVR_ALLOC_10);
1122 D32(MXVR_ALLOC_11);
1123 D32(MXVR_ALLOC_12);
1124 D32(MXVR_ALLOC_13);
1125 D32(MXVR_ALLOC_14);
1126 D32(MXVR_SYNC_LCHAN_0);
1127 D32(MXVR_SYNC_LCHAN_1);
1128 D32(MXVR_SYNC_LCHAN_2);
1129 D32(MXVR_SYNC_LCHAN_3);
1130 D32(MXVR_SYNC_LCHAN_4);
1131 D32(MXVR_SYNC_LCHAN_5);
1132 D32(MXVR_SYNC_LCHAN_6);
1133 D32(MXVR_SYNC_LCHAN_7);
1134 D32(MXVR_DMA0_CONFIG);
1135 D32(MXVR_DMA0_START_ADDR);
1136 D16(MXVR_DMA0_COUNT);
1137 D32(MXVR_DMA0_CURR_ADDR);
1138 D16(MXVR_DMA0_CURR_COUNT);
1139 D32(MXVR_DMA1_CONFIG);
1140 D32(MXVR_DMA1_START_ADDR);
1141 D16(MXVR_DMA1_COUNT);
1142 D32(MXVR_DMA1_CURR_ADDR);
1143 D16(MXVR_DMA1_CURR_COUNT);
1144 D32(MXVR_DMA2_CONFIG);
1145 D32(MXVR_DMA2_START_ADDR);
1146 D16(MXVR_DMA2_COUNT);
1147 D32(MXVR_DMA2_CURR_ADDR);
1148 D16(MXVR_DMA2_CURR_COUNT);
1149 D32(MXVR_DMA3_CONFIG);
1150 D32(MXVR_DMA3_START_ADDR);
1151 D16(MXVR_DMA3_COUNT);
1152 D32(MXVR_DMA3_CURR_ADDR);
1153 D16(MXVR_DMA3_CURR_COUNT);
1154 D32(MXVR_DMA4_CONFIG);
1155 D32(MXVR_DMA4_START_ADDR);
1156 D16(MXVR_DMA4_COUNT);
1157 D32(MXVR_DMA4_CURR_ADDR);
1158 D16(MXVR_DMA4_CURR_COUNT);
1159 D32(MXVR_DMA5_CONFIG);
1160 D32(MXVR_DMA5_START_ADDR);
1161 D16(MXVR_DMA5_COUNT);
1162 D32(MXVR_DMA5_CURR_ADDR);
1163 D16(MXVR_DMA5_CURR_COUNT);
1164 D32(MXVR_DMA6_CONFIG);
1165 D32(MXVR_DMA6_START_ADDR);
1166 D16(MXVR_DMA6_COUNT);
1167 D32(MXVR_DMA6_CURR_ADDR);
1168 D16(MXVR_DMA6_CURR_COUNT);
1169 D32(MXVR_DMA7_CONFIG);
1170 D32(MXVR_DMA7_START_ADDR);
1171 D16(MXVR_DMA7_COUNT);
1172 D32(MXVR_DMA7_CURR_ADDR);
1173 D16(MXVR_DMA7_CURR_COUNT);
1174 D16(MXVR_AP_CTL);
1175 D32(MXVR_APRB_START_ADDR);
1176 D32(MXVR_APRB_CURR_ADDR);
1177 D32(MXVR_APTB_START_ADDR);
1178 D32(MXVR_APTB_CURR_ADDR);
1179 D32(MXVR_CM_CTL);
1180 D32(MXVR_CMRB_START_ADDR);
1181 D32(MXVR_CMRB_CURR_ADDR);
1182 D32(MXVR_CMTB_START_ADDR);
1183 D32(MXVR_CMTB_CURR_ADDR);
1184 D32(MXVR_RRDB_START_ADDR);
1185 D32(MXVR_RRDB_CURR_ADDR);
1186 D32(MXVR_PAT_DATA_0);
1187 D32(MXVR_PAT_EN_0);
1188 D32(MXVR_PAT_DATA_1);
1189 D32(MXVR_PAT_EN_1);
1190 D16(MXVR_FRAME_CNT_0);
1191 D16(MXVR_FRAME_CNT_1);
1192 D32(MXVR_ROUTING_0);
1193 D32(MXVR_ROUTING_1);
1194 D32(MXVR_ROUTING_2);
1195 D32(MXVR_ROUTING_3);
1196 D32(MXVR_ROUTING_4);
1197 D32(MXVR_ROUTING_5);
1198 D32(MXVR_ROUTING_6);
1199 D32(MXVR_ROUTING_7);
1200 D32(MXVR_ROUTING_8);
1201 D32(MXVR_ROUTING_9);
1202 D32(MXVR_ROUTING_10);
1203 D32(MXVR_ROUTING_11);
1204 D32(MXVR_ROUTING_12);
1205 D32(MXVR_ROUTING_13);
1206 D32(MXVR_ROUTING_14);
1207# ifdef MXVR_PLL_CTL_1
1208 D32(MXVR_PLL_CTL_1);
1209# endif
1210 D16(MXVR_BLOCK_CNT);
1211# ifdef MXVR_CLK_CTL
1212 D32(MXVR_CLK_CTL);
1213# endif
1214# ifdef MXVR_CDRPLL_CTL
1215 D32(MXVR_CDRPLL_CTL);
1216# endif
1217# ifdef MXVR_FMPLL_CTL
1218 D32(MXVR_FMPLL_CTL);
1219# endif
1220# ifdef MXVR_PIN_CTL
1221 D16(MXVR_PIN_CTL);
1222# endif
1223# ifdef MXVR_SCLK_CNT
1224 D16(MXVR_SCLK_CNT);
1225# endif
1226#endif
1227
1228#ifdef NFC_ADDR
1229 parent = debugfs_create_dir("nfc", top);
1230 D_WO(NFC_ADDR, 16);
1231 D_WO(NFC_CMD, 16);
1232 D_RO(NFC_COUNT, 16);
1233 D16(NFC_CTL);
1234 D_WO(NFC_DATA_RD, 16);
1235 D_WO(NFC_DATA_WR, 16);
1236 D_RO(NFC_ECC0, 16);
1237 D_RO(NFC_ECC1, 16);
1238 D_RO(NFC_ECC2, 16);
1239 D_RO(NFC_ECC3, 16);
1240 D16(NFC_IRQMASK);
1241 D16(NFC_IRQSTAT);
1242 D_WO(NFC_PGCTL, 16);
1243 D_RO(NFC_READ, 16);
1244 D16(NFC_RST);
1245 D_RO(NFC_STAT, 16);
1246#endif
1247
1248#ifdef OTP_CONTROL
1249 parent = debugfs_create_dir("otp", top);
1250 D16(OTP_CONTROL);
1251 D16(OTP_BEN);
1252 D16(OTP_STATUS);
1253 D32(OTP_TIMING);
1254 D32(OTP_DATA0);
1255 D32(OTP_DATA1);
1256 D32(OTP_DATA2);
1257 D32(OTP_DATA3);
1258#endif
1259
1260#ifdef PIXC_CTL
1261 parent = debugfs_create_dir("pixc", top);
1262 D16(PIXC_CTL);
1263 D16(PIXC_PPL);
1264 D16(PIXC_LPF);
1265 D16(PIXC_AHSTART);
1266 D16(PIXC_AHEND);
1267 D16(PIXC_AVSTART);
1268 D16(PIXC_AVEND);
1269 D16(PIXC_ATRANSP);
1270 D16(PIXC_BHSTART);
1271 D16(PIXC_BHEND);
1272 D16(PIXC_BVSTART);
1273 D16(PIXC_BVEND);
1274 D16(PIXC_BTRANSP);
1275 D16(PIXC_INTRSTAT);
1276 D32(PIXC_RYCON);
1277 D32(PIXC_GUCON);
1278 D32(PIXC_BVCON);
1279 D32(PIXC_CCBIAS);
1280 D32(PIXC_TC);
1281#endif
1282
1283 parent = debugfs_create_dir("pll", top);
1284 D16(PLL_CTL);
1285 D16(PLL_DIV);
1286 D16(PLL_LOCKCNT);
1287 D16(PLL_STAT);
1288 D16(VR_CTL);
1289 D32(CHIPID); /* it's part of this hardware block */
1290
1291#if defined(PPI_STATUS) || defined(PPI0_STATUS) || defined(PPI1_STATUS)
1292 parent = debugfs_create_dir("ppi", top);
1293# ifdef PPI_STATUS
1294 bfin_debug_mmrs_ppi(parent, PPI_STATUS, -1);
1295# endif
1296# ifdef PPI0_STATUS
1297 PPI(0);
1298# endif
1299# ifdef PPI1_STATUS
1300 PPI(1);
1301# endif
1302#endif
1303
1304#ifdef PWM_CTRL
1305 parent = debugfs_create_dir("pwm", top);
1306 D16(PWM_CTRL);
1307 D16(PWM_STAT);
1308 D16(PWM_TM);
1309 D16(PWM_DT);
1310 D16(PWM_GATE);
1311 D16(PWM_CHA);
1312 D16(PWM_CHB);
1313 D16(PWM_CHC);
1314 D16(PWM_SEG);
1315 D16(PWM_SYNCWT);
1316 D16(PWM_CHAL);
1317 D16(PWM_CHBL);
1318 D16(PWM_CHCL);
1319 D16(PWM_LSI);
1320 D16(PWM_STAT2);
1321#endif
1322
1323#ifdef RSI_CONFIG
1324 parent = debugfs_create_dir("rsi", top);
1325 D32(RSI_ARGUMENT);
1326 D16(RSI_CEATA_CONTROL);
1327 D16(RSI_CLK_CONTROL);
1328 D16(RSI_COMMAND);
1329 D16(RSI_CONFIG);
1330 D16(RSI_DATA_CNT);
1331 D16(RSI_DATA_CONTROL);
1332 D16(RSI_DATA_LGTH);
1333 D32(RSI_DATA_TIMER);
1334 D16(RSI_EMASK);
1335 D16(RSI_ESTAT);
1336 D32(RSI_FIFO);
1337 D16(RSI_FIFO_CNT);
1338 D32(RSI_MASK0);
1339 D32(RSI_MASK1);
1340 D16(RSI_PID0);
1341 D16(RSI_PID1);
1342 D16(RSI_PID2);
1343 D16(RSI_PID3);
1344 D16(RSI_PWR_CONTROL);
1345 D16(RSI_RD_WAIT_EN);
1346 D32(RSI_RESPONSE0);
1347 D32(RSI_RESPONSE1);
1348 D32(RSI_RESPONSE2);
1349 D32(RSI_RESPONSE3);
1350 D16(RSI_RESP_CMD);
1351 D32(RSI_STATUS);
1352 D_WO(RSI_STATUSCL, 16);
1353#endif
1354
1355#ifdef RTC_ALARM
1356 parent = debugfs_create_dir("rtc", top);
1357 D32(RTC_ALARM);
1358 D16(RTC_ICTL);
1359 D16(RTC_ISTAT);
1360 D16(RTC_PREN);
1361 D32(RTC_STAT);
1362 D16(RTC_SWCNT);
1363#endif
1364
1365#ifdef SDH_CFG
1366 parent = debugfs_create_dir("sdh", top);
1367 D32(SDH_ARGUMENT);
1368 D16(SDH_CFG);
1369 D16(SDH_CLK_CTL);
1370 D16(SDH_COMMAND);
1371 D_RO(SDH_DATA_CNT, 16);
1372 D16(SDH_DATA_CTL);
1373 D16(SDH_DATA_LGTH);
1374 D32(SDH_DATA_TIMER);
1375 D16(SDH_E_MASK);
1376 D16(SDH_E_STATUS);
1377 D32(SDH_FIFO);
1378 D_RO(SDH_FIFO_CNT, 16);
1379 D32(SDH_MASK0);
1380 D32(SDH_MASK1);
1381 D_RO(SDH_PID0, 16);
1382 D_RO(SDH_PID1, 16);
1383 D_RO(SDH_PID2, 16);
1384 D_RO(SDH_PID3, 16);
1385 D_RO(SDH_PID4, 16);
1386 D_RO(SDH_PID5, 16);
1387 D_RO(SDH_PID6, 16);
1388 D_RO(SDH_PID7, 16);
1389 D16(SDH_PWR_CTL);
1390 D16(SDH_RD_WAIT_EN);
1391 D_RO(SDH_RESPONSE0, 32);
1392 D_RO(SDH_RESPONSE1, 32);
1393 D_RO(SDH_RESPONSE2, 32);
1394 D_RO(SDH_RESPONSE3, 32);
1395 D_RO(SDH_RESP_CMD, 16);
1396 D_RO(SDH_STATUS, 32);
1397 D_WO(SDH_STATUS_CLR, 16);
1398#endif
1399
1400#ifdef SECURE_CONTROL
1401 parent = debugfs_create_dir("security", top);
1402 D16(SECURE_CONTROL);
1403 D16(SECURE_STATUS);
1404 D32(SECURE_SYSSWT);
1405#endif
1406
1407 parent = debugfs_create_dir("sic", top);
1408 D16(SWRST);
1409 D16(SYSCR);
1410 D16(SIC_RVECT);
1411 D32(SIC_IAR0);
1412 D32(SIC_IAR1);
1413 D32(SIC_IAR2);
1414#ifdef SIC_IAR3
1415 D32(SIC_IAR3);
1416#endif
1417#ifdef SIC_IAR4
1418 D32(SIC_IAR4);
1419 D32(SIC_IAR5);
1420 D32(SIC_IAR6);
1421#endif
1422#ifdef SIC_IAR7
1423 D32(SIC_IAR7);
1424#endif
1425#ifdef SIC_IAR8
1426 D32(SIC_IAR8);
1427 D32(SIC_IAR9);
1428 D32(SIC_IAR10);
1429 D32(SIC_IAR11);
1430#endif
1431#ifdef SIC_IMASK
1432 D32(SIC_IMASK);
1433 D32(SIC_ISR);
1434 D32(SIC_IWR);
1435#endif
1436#ifdef SIC_IMASK0
1437 D32(SIC_IMASK0);
1438 D32(SIC_IMASK1);
1439 D32(SIC_ISR0);
1440 D32(SIC_ISR1);
1441 D32(SIC_IWR0);
1442 D32(SIC_IWR1);
1443#endif
1444#ifdef SIC_IMASK2
1445 D32(SIC_IMASK2);
1446 D32(SIC_ISR2);
1447 D32(SIC_IWR2);
1448#endif
1449#ifdef SICB_RVECT
1450 D16(SICB_SWRST);
1451 D16(SICB_SYSCR);
1452 D16(SICB_RVECT);
1453 D32(SICB_IAR0);
1454 D32(SICB_IAR1);
1455 D32(SICB_IAR2);
1456 D32(SICB_IAR3);
1457 D32(SICB_IAR4);
1458 D32(SICB_IAR5);
1459 D32(SICB_IAR6);
1460 D32(SICB_IAR7);
1461 D32(SICB_IMASK0);
1462 D32(SICB_IMASK1);
1463 D32(SICB_ISR0);
1464 D32(SICB_ISR1);
1465 D32(SICB_IWR0);
1466 D32(SICB_IWR1);
1467#endif
1468
1469 parent = debugfs_create_dir("spi", top);
1470#ifdef SPI0_REGBASE
1471 SPI(0);
1472#endif
1473#ifdef SPI1_REGBASE
1474 SPI(1);
1475#endif
1476#ifdef SPI2_REGBASE
1477 SPI(2);
1478#endif
1479
1480 parent = debugfs_create_dir("sport", top);
1481#ifdef SPORT0_STAT
1482 SPORT(0);
1483#endif
1484#ifdef SPORT1_STAT
1485 SPORT(1);
1486#endif
1487#ifdef SPORT2_STAT
1488 SPORT(2);
1489#endif
1490#ifdef SPORT3_STAT
1491 SPORT(3);
1492#endif
1493
1494#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
1495 parent = debugfs_create_dir("twi", top);
1496# ifdef TWI_CLKDIV
1497 bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
1498# endif
1499# ifdef TWI0_CLKDIV
1500 TWI(0);
1501# endif
1502# ifdef TWI1_CLKDIV
1503 TWI(1);
1504# endif
1505#endif
1506
1507 parent = debugfs_create_dir("uart", top);
1508#ifdef BFIN_UART_DLL
1509 bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
1510#endif
1511#ifdef UART0_DLL
1512 UART(0);
1513#endif
1514#ifdef UART1_DLL
1515 UART(1);
1516#endif
1517#ifdef UART2_DLL
1518 UART(2);
1519#endif
1520#ifdef UART3_DLL
1521 UART(3);
1522#endif
1523
1524#ifdef USB_FADDR
1525 parent = debugfs_create_dir("usb", top);
1526 D16(USB_FADDR);
1527 D16(USB_POWER);
1528 D16(USB_INTRTX);
1529 D16(USB_INTRRX);
1530 D16(USB_INTRTXE);
1531 D16(USB_INTRRXE);
1532 D16(USB_INTRUSB);
1533 D16(USB_INTRUSBE);
1534 D16(USB_FRAME);
1535 D16(USB_INDEX);
1536 D16(USB_TESTMODE);
1537 D16(USB_GLOBINTR);
1538 D16(USB_GLOBAL_CTL);
1539 D16(USB_TX_MAX_PACKET);
1540 D16(USB_CSR0);
1541 D16(USB_TXCSR);
1542 D16(USB_RX_MAX_PACKET);
1543 D16(USB_RXCSR);
1544 D16(USB_COUNT0);
1545 D16(USB_RXCOUNT);
1546 D16(USB_TXTYPE);
1547 D16(USB_NAKLIMIT0);
1548 D16(USB_TXINTERVAL);
1549 D16(USB_RXTYPE);
1550 D16(USB_RXINTERVAL);
1551 D16(USB_TXCOUNT);
1552 D16(USB_EP0_FIFO);
1553 D16(USB_EP1_FIFO);
1554 D16(USB_EP2_FIFO);
1555 D16(USB_EP3_FIFO);
1556 D16(USB_EP4_FIFO);
1557 D16(USB_EP5_FIFO);
1558 D16(USB_EP6_FIFO);
1559 D16(USB_EP7_FIFO);
1560 D16(USB_OTG_DEV_CTL);
1561 D16(USB_OTG_VBUS_IRQ);
1562 D16(USB_OTG_VBUS_MASK);
1563 D16(USB_LINKINFO);
1564 D16(USB_VPLEN);
1565 D16(USB_HS_EOF1);
1566 D16(USB_FS_EOF1);
1567 D16(USB_LS_EOF1);
1568 D16(USB_APHY_CNTRL);
1569 D16(USB_APHY_CALIB);
1570 D16(USB_APHY_CNTRL2);
1571 D16(USB_PHY_TEST);
1572 D16(USB_PLLOSC_CTRL);
1573 D16(USB_SRP_CLKDIV);
1574 D16(USB_EP_NI0_TXMAXP);
1575 D16(USB_EP_NI0_TXCSR);
1576 D16(USB_EP_NI0_RXMAXP);
1577 D16(USB_EP_NI0_RXCSR);
1578 D16(USB_EP_NI0_RXCOUNT);
1579 D16(USB_EP_NI0_TXTYPE);
1580 D16(USB_EP_NI0_TXINTERVAL);
1581 D16(USB_EP_NI0_RXTYPE);
1582 D16(USB_EP_NI0_RXINTERVAL);
1583 D16(USB_EP_NI0_TXCOUNT);
1584 D16(USB_EP_NI1_TXMAXP);
1585 D16(USB_EP_NI1_TXCSR);
1586 D16(USB_EP_NI1_RXMAXP);
1587 D16(USB_EP_NI1_RXCSR);
1588 D16(USB_EP_NI1_RXCOUNT);
1589 D16(USB_EP_NI1_TXTYPE);
1590 D16(USB_EP_NI1_TXINTERVAL);
1591 D16(USB_EP_NI1_RXTYPE);
1592 D16(USB_EP_NI1_RXINTERVAL);
1593 D16(USB_EP_NI1_TXCOUNT);
1594 D16(USB_EP_NI2_TXMAXP);
1595 D16(USB_EP_NI2_TXCSR);
1596 D16(USB_EP_NI2_RXMAXP);
1597 D16(USB_EP_NI2_RXCSR);
1598 D16(USB_EP_NI2_RXCOUNT);
1599 D16(USB_EP_NI2_TXTYPE);
1600 D16(USB_EP_NI2_TXINTERVAL);
1601 D16(USB_EP_NI2_RXTYPE);
1602 D16(USB_EP_NI2_RXINTERVAL);
1603 D16(USB_EP_NI2_TXCOUNT);
1604 D16(USB_EP_NI3_TXMAXP);
1605 D16(USB_EP_NI3_TXCSR);
1606 D16(USB_EP_NI3_RXMAXP);
1607 D16(USB_EP_NI3_RXCSR);
1608 D16(USB_EP_NI3_RXCOUNT);
1609 D16(USB_EP_NI3_TXTYPE);
1610 D16(USB_EP_NI3_TXINTERVAL);
1611 D16(USB_EP_NI3_RXTYPE);
1612 D16(USB_EP_NI3_RXINTERVAL);
1613 D16(USB_EP_NI3_TXCOUNT);
1614 D16(USB_EP_NI4_TXMAXP);
1615 D16(USB_EP_NI4_TXCSR);
1616 D16(USB_EP_NI4_RXMAXP);
1617 D16(USB_EP_NI4_RXCSR);
1618 D16(USB_EP_NI4_RXCOUNT);
1619 D16(USB_EP_NI4_TXTYPE);
1620 D16(USB_EP_NI4_TXINTERVAL);
1621 D16(USB_EP_NI4_RXTYPE);
1622 D16(USB_EP_NI4_RXINTERVAL);
1623 D16(USB_EP_NI4_TXCOUNT);
1624 D16(USB_EP_NI5_TXMAXP);
1625 D16(USB_EP_NI5_TXCSR);
1626 D16(USB_EP_NI5_RXMAXP);
1627 D16(USB_EP_NI5_RXCSR);
1628 D16(USB_EP_NI5_RXCOUNT);
1629 D16(USB_EP_NI5_TXTYPE);
1630 D16(USB_EP_NI5_TXINTERVAL);
1631 D16(USB_EP_NI5_RXTYPE);
1632 D16(USB_EP_NI5_RXINTERVAL);
1633 D16(USB_EP_NI5_TXCOUNT);
1634 D16(USB_EP_NI6_TXMAXP);
1635 D16(USB_EP_NI6_TXCSR);
1636 D16(USB_EP_NI6_RXMAXP);
1637 D16(USB_EP_NI6_RXCSR);
1638 D16(USB_EP_NI6_RXCOUNT);
1639 D16(USB_EP_NI6_TXTYPE);
1640 D16(USB_EP_NI6_TXINTERVAL);
1641 D16(USB_EP_NI6_RXTYPE);
1642 D16(USB_EP_NI6_RXINTERVAL);
1643 D16(USB_EP_NI6_TXCOUNT);
1644 D16(USB_EP_NI7_TXMAXP);
1645 D16(USB_EP_NI7_TXCSR);
1646 D16(USB_EP_NI7_RXMAXP);
1647 D16(USB_EP_NI7_RXCSR);
1648 D16(USB_EP_NI7_RXCOUNT);
1649 D16(USB_EP_NI7_TXTYPE);
1650 D16(USB_EP_NI7_TXINTERVAL);
1651 D16(USB_EP_NI7_RXTYPE);
1652 D16(USB_EP_NI7_RXINTERVAL);
1653 D16(USB_EP_NI7_TXCOUNT);
1654 D16(USB_DMA_INTERRUPT);
1655 D16(USB_DMA0CONTROL);
1656 D16(USB_DMA0ADDRLOW);
1657 D16(USB_DMA0ADDRHIGH);
1658 D16(USB_DMA0COUNTLOW);
1659 D16(USB_DMA0COUNTHIGH);
1660 D16(USB_DMA1CONTROL);
1661 D16(USB_DMA1ADDRLOW);
1662 D16(USB_DMA1ADDRHIGH);
1663 D16(USB_DMA1COUNTLOW);
1664 D16(USB_DMA1COUNTHIGH);
1665 D16(USB_DMA2CONTROL);
1666 D16(USB_DMA2ADDRLOW);
1667 D16(USB_DMA2ADDRHIGH);
1668 D16(USB_DMA2COUNTLOW);
1669 D16(USB_DMA2COUNTHIGH);
1670 D16(USB_DMA3CONTROL);
1671 D16(USB_DMA3ADDRLOW);
1672 D16(USB_DMA3ADDRHIGH);
1673 D16(USB_DMA3COUNTLOW);
1674 D16(USB_DMA3COUNTHIGH);
1675 D16(USB_DMA4CONTROL);
1676 D16(USB_DMA4ADDRLOW);
1677 D16(USB_DMA4ADDRHIGH);
1678 D16(USB_DMA4COUNTLOW);
1679 D16(USB_DMA4COUNTHIGH);
1680 D16(USB_DMA5CONTROL);
1681 D16(USB_DMA5ADDRLOW);
1682 D16(USB_DMA5ADDRHIGH);
1683 D16(USB_DMA5COUNTLOW);
1684 D16(USB_DMA5COUNTHIGH);
1685 D16(USB_DMA6CONTROL);
1686 D16(USB_DMA6ADDRLOW);
1687 D16(USB_DMA6ADDRHIGH);
1688 D16(USB_DMA6COUNTLOW);
1689 D16(USB_DMA6COUNTHIGH);
1690 D16(USB_DMA7CONTROL);
1691 D16(USB_DMA7ADDRLOW);
1692 D16(USB_DMA7ADDRHIGH);
1693 D16(USB_DMA7COUNTLOW);
1694 D16(USB_DMA7COUNTHIGH);
1695#endif
1696
1697#ifdef WDOG_CNT
1698 parent = debugfs_create_dir("watchdog", top);
1699 D32(WDOG_CNT);
1700 D16(WDOG_CTL);
1701 D32(WDOG_STAT);
1702#endif
1703#ifdef WDOGA_CNT
1704 parent = debugfs_create_dir("watchdog", top);
1705 D32(WDOGA_CNT);
1706 D16(WDOGA_CTL);
1707 D32(WDOGA_STAT);
1708 D32(WDOGB_CNT);
1709 D16(WDOGB_CTL);
1710 D32(WDOGB_STAT);
1711#endif
1712
1713 /* BF533 glue */
1714#ifdef FIO_FLAG_D
1715#define PORTFIO FIO_FLAG_D
1716#endif
1717 /* BF561 glue */
1718#ifdef FIO0_FLAG_D
1719#define PORTFIO FIO0_FLAG_D
1720#endif
1721#ifdef FIO1_FLAG_D
1722#define PORTGIO FIO1_FLAG_D
1723#endif
1724#ifdef FIO2_FLAG_D
1725#define PORTHIO FIO2_FLAG_D
1726#endif
1727 parent = debugfs_create_dir("port", top);
1728#ifdef PORTFIO
1729 PORT(PORTFIO, 'F');
1730#endif
1731#ifdef PORTGIO
1732 PORT(PORTGIO, 'G');
1733#endif
1734#ifdef PORTHIO
1735 PORT(PORTHIO, 'H');
1736#endif
1737
1738#ifdef __ADSPBF51x__
1739 D16(PORTF_FER);
1740 D16(PORTF_DRIVE);
1741 D16(PORTF_HYSTERESIS);
1742 D16(PORTF_MUX);
1743
1744 D16(PORTG_FER);
1745 D16(PORTG_DRIVE);
1746 D16(PORTG_HYSTERESIS);
1747 D16(PORTG_MUX);
1748
1749 D16(PORTH_FER);
1750 D16(PORTH_DRIVE);
1751 D16(PORTH_HYSTERESIS);
1752 D16(PORTH_MUX);
1753
1754 D16(MISCPORT_DRIVE);
1755 D16(MISCPORT_HYSTERESIS);
1756#endif /* BF51x */
1757
1758#ifdef __ADSPBF52x__
1759 D16(PORTF_FER);
1760 D16(PORTF_DRIVE);
1761 D16(PORTF_HYSTERESIS);
1762 D16(PORTF_MUX);
1763 D16(PORTF_SLEW);
1764
1765 D16(PORTG_FER);
1766 D16(PORTG_DRIVE);
1767 D16(PORTG_HYSTERESIS);
1768 D16(PORTG_MUX);
1769 D16(PORTG_SLEW);
1770
1771 D16(PORTH_FER);
1772 D16(PORTH_DRIVE);
1773 D16(PORTH_HYSTERESIS);
1774 D16(PORTH_MUX);
1775 D16(PORTH_SLEW);
1776
1777 D16(MISCPORT_DRIVE);
1778 D16(MISCPORT_HYSTERESIS);
1779 D16(MISCPORT_SLEW);
1780#endif /* BF52x */
1781
1782#ifdef BF537_FAMILY
1783 D16(PORTF_FER);
1784 D16(PORTG_FER);
1785 D16(PORTH_FER);
1786 D16(PORT_MUX);
1787#endif /* BF534 BF536 BF537 */
1788
1789#ifdef BF538_FAMILY
1790 D16(PORTCIO_FER);
1791 D16(PORTCIO);
1792 D16(PORTCIO_CLEAR);
1793 D16(PORTCIO_SET);
1794 D16(PORTCIO_TOGGLE);
1795 D16(PORTCIO_DIR);
1796 D16(PORTCIO_INEN);
1797
1798 D16(PORTDIO);
1799 D16(PORTDIO_CLEAR);
1800 D16(PORTDIO_DIR);
1801 D16(PORTDIO_FER);
1802 D16(PORTDIO_INEN);
1803 D16(PORTDIO_SET);
1804 D16(PORTDIO_TOGGLE);
1805
1806 D16(PORTEIO);
1807 D16(PORTEIO_CLEAR);
1808 D16(PORTEIO_DIR);
1809 D16(PORTEIO_FER);
1810 D16(PORTEIO_INEN);
1811 D16(PORTEIO_SET);
1812 D16(PORTEIO_TOGGLE);
1813#endif /* BF538 BF539 */
1814
1815#ifdef __ADSPBF54x__
1816 {
1817 int num;
1818 unsigned long base;
1819 char *_buf, buf[32];
1820
1821 base = PORTA_FER;
1822 for (num = 0; num < 10; ++num) {
1823 PORT(base, num);
1824 base += sizeof(struct bfin_gpio_regs);
1825 }
1826
1827#define __PINT(uname, lname) __REGS(pint, #uname, lname)
1828 parent = debugfs_create_dir("pint", top);
1829 base = PINT0_MASK_SET;
1830 for (num = 0; num < 4; ++num) {
1831 _buf = REGS_STR_PFX(buf, PINT, num);
1832 __PINT(MASK_SET, mask_set);
1833 __PINT(MASK_CLEAR, mask_clear);
1834 __PINT(IRQ, irq);
1835 __PINT(ASSIGN, assign);
1836 __PINT(EDGE_SET, edge_set);
1837 __PINT(EDGE_CLEAR, edge_clear);
1838 __PINT(INVERT_SET, invert_set);
1839 __PINT(INVERT_CLEAR, invert_clear);
1840 __PINT(PINSTATE, pinstate);
1841 __PINT(LATCH, latch);
1842 base += sizeof(struct bfin_pint_regs);
1843 }
1844
1845 }
1846#endif /* BF54x */
1847
1848 debug_mmrs_dentry = top;
1849
1850 return 0;
1851}
1852module_init(bfin_debug_mmrs_init);
1853
1854static void __exit bfin_debug_mmrs_exit(void)
1855{
1856 debugfs_remove_recursive(debug_mmrs_dentry);
1857}
1858module_exit(bfin_debug_mmrs_exit);
1859
1860MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index f37019c847c..486426f8a0d 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -33,6 +33,7 @@
33#include <linux/io.h> 33#include <linux/io.h>
34#include <asm/system.h> 34#include <asm/system.h>
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/irq_handler.h>
36 37
37DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs); 38DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
38 39
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 1696d34f51c..ff3d747154a 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -11,6 +11,7 @@
11#include <linux/kallsyms.h> 11#include <linux/kallsyms.h>
12#include <linux/interrupt.h> 12#include <linux/interrupt.h>
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <asm/irq_handler.h>
14#include <asm/trace.h> 15#include <asm/trace.h>
15#include <asm/pda.h> 16#include <asm/pda.h>
16 17
diff --git a/arch/blackfin/kernel/nmi.c b/arch/blackfin/kernel/nmi.c
index 401eb1d8e3b..679d0db3525 100644
--- a/arch/blackfin/kernel/nmi.c
+++ b/arch/blackfin/kernel/nmi.c
@@ -145,16 +145,16 @@ int check_nmi_wdt_touched(void)
145{ 145{
146 unsigned int this_cpu = smp_processor_id(); 146 unsigned int this_cpu = smp_processor_id();
147 unsigned int cpu; 147 unsigned int cpu;
148 cpumask_t mask;
148 149
149 cpumask_t mask = cpu_online_map; 150 cpumask_copy(&mask, cpu_online_mask);
150
151 if (!atomic_read(&nmi_touched[this_cpu])) 151 if (!atomic_read(&nmi_touched[this_cpu]))
152 return 0; 152 return 0;
153 153
154 atomic_set(&nmi_touched[this_cpu], 0); 154 atomic_set(&nmi_touched[this_cpu], 0);
155 155
156 cpu_clear(this_cpu, mask); 156 cpumask_clear_cpu(this_cpu, &mask);
157 for_each_cpu_mask(cpu, mask) { 157 for_each_cpu(cpu, &mask) {
158 invalidate_dcache_range((unsigned long)(&nmi_touched[cpu]), 158 invalidate_dcache_range((unsigned long)(&nmi_touched[cpu]),
159 (unsigned long)(&nmi_touched[cpu])); 159 (unsigned long)(&nmi_touched[cpu]));
160 if (!atomic_read(&nmi_touched[cpu])) 160 if (!atomic_read(&nmi_touched[cpu]))
diff --git a/arch/blackfin/kernel/perf_event.c b/arch/blackfin/kernel/perf_event.c
new file mode 100644
index 00000000000..04300f29c0e
--- /dev/null
+++ b/arch/blackfin/kernel/perf_event.c
@@ -0,0 +1,498 @@
1/*
2 * Blackfin performance counters
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Ripped from SuperH version:
7 *
8 * Copyright (C) 2009 Paul Mundt
9 *
10 * Heavily based on the x86 and PowerPC implementations.
11 *
12 * x86:
13 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
14 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
15 * Copyright (C) 2009 Jaswinder Singh Rajput
16 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
17 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
18 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
19 *
20 * ppc:
21 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
22 *
23 * Licensed under the GPL-2 or later.
24 */
25
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/perf_event.h>
29#include <asm/bfin_pfmon.h>
30
31/*
32 * We have two counters, and each counter can support an event type.
33 * The 'o' is PFCNTx=1 and 's' is PFCNTx=0
34 *
35 * 0x04 o pc invariant branches
36 * 0x06 o mispredicted branches
37 * 0x09 o predicted branches taken
38 * 0x0B o EXCPT insn
39 * 0x0C o CSYNC/SSYNC insn
40 * 0x0D o Insns committed
41 * 0x0E o Interrupts taken
42 * 0x0F o Misaligned address exceptions
43 * 0x80 o Code memory fetches stalled due to DMA
44 * 0x83 o 64bit insn fetches delivered
45 * 0x9A o data cache fills (bank a)
46 * 0x9B o data cache fills (bank b)
47 * 0x9C o data cache lines evicted (bank a)
48 * 0x9D o data cache lines evicted (bank b)
49 * 0x9E o data cache high priority fills
50 * 0x9F o data cache low priority fills
51 * 0x00 s loop 0 iterations
52 * 0x01 s loop 1 iterations
53 * 0x0A s CSYNC/SSYNC stalls
54 * 0x10 s DAG read/after write hazards
55 * 0x13 s RAW data hazards
56 * 0x81 s code TAG stalls
57 * 0x82 s code fill stalls
58 * 0x90 s processor to memory stalls
59 * 0x91 s data memory stalls not hidden by 0x90
60 * 0x92 s data store buffer full stalls
61 * 0x93 s data memory write buffer full stalls due to high->low priority
62 * 0x95 s data memory fill buffer stalls
63 * 0x96 s data TAG collision stalls
64 * 0x97 s data collision stalls
65 * 0x98 s data stalls
66 * 0x99 s data stalls sent to processor
67 */
68
69static const int event_map[] = {
70 /* use CYCLES cpu register */
71 [PERF_COUNT_HW_CPU_CYCLES] = -1,
72 [PERF_COUNT_HW_INSTRUCTIONS] = 0x0D,
73 [PERF_COUNT_HW_CACHE_REFERENCES] = -1,
74 [PERF_COUNT_HW_CACHE_MISSES] = 0x83,
75 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x09,
76 [PERF_COUNT_HW_BRANCH_MISSES] = 0x06,
77 [PERF_COUNT_HW_BUS_CYCLES] = -1,
78};
79
80#define C(x) PERF_COUNT_HW_CACHE_##x
81
82static const int cache_events[PERF_COUNT_HW_CACHE_MAX]
83 [PERF_COUNT_HW_CACHE_OP_MAX]
84 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
85{
86 [C(L1D)] = { /* Data bank A */
87 [C(OP_READ)] = {
88 [C(RESULT_ACCESS)] = 0,
89 [C(RESULT_MISS) ] = 0x9A,
90 },
91 [C(OP_WRITE)] = {
92 [C(RESULT_ACCESS)] = 0,
93 [C(RESULT_MISS) ] = 0,
94 },
95 [C(OP_PREFETCH)] = {
96 [C(RESULT_ACCESS)] = 0,
97 [C(RESULT_MISS) ] = 0,
98 },
99 },
100
101 [C(L1I)] = {
102 [C(OP_READ)] = {
103 [C(RESULT_ACCESS)] = 0,
104 [C(RESULT_MISS) ] = 0x83,
105 },
106 [C(OP_WRITE)] = {
107 [C(RESULT_ACCESS)] = -1,
108 [C(RESULT_MISS) ] = -1,
109 },
110 [C(OP_PREFETCH)] = {
111 [C(RESULT_ACCESS)] = 0,
112 [C(RESULT_MISS) ] = 0,
113 },
114 },
115
116 [C(LL)] = {
117 [C(OP_READ)] = {
118 [C(RESULT_ACCESS)] = -1,
119 [C(RESULT_MISS) ] = -1,
120 },
121 [C(OP_WRITE)] = {
122 [C(RESULT_ACCESS)] = -1,
123 [C(RESULT_MISS) ] = -1,
124 },
125 [C(OP_PREFETCH)] = {
126 [C(RESULT_ACCESS)] = -1,
127 [C(RESULT_MISS) ] = -1,
128 },
129 },
130
131 [C(DTLB)] = {
132 [C(OP_READ)] = {
133 [C(RESULT_ACCESS)] = -1,
134 [C(RESULT_MISS) ] = -1,
135 },
136 [C(OP_WRITE)] = {
137 [C(RESULT_ACCESS)] = -1,
138 [C(RESULT_MISS) ] = -1,
139 },
140 [C(OP_PREFETCH)] = {
141 [C(RESULT_ACCESS)] = -1,
142 [C(RESULT_MISS) ] = -1,
143 },
144 },
145
146 [C(ITLB)] = {
147 [C(OP_READ)] = {
148 [C(RESULT_ACCESS)] = -1,
149 [C(RESULT_MISS) ] = -1,
150 },
151 [C(OP_WRITE)] = {
152 [C(RESULT_ACCESS)] = -1,
153 [C(RESULT_MISS) ] = -1,
154 },
155 [C(OP_PREFETCH)] = {
156 [C(RESULT_ACCESS)] = -1,
157 [C(RESULT_MISS) ] = -1,
158 },
159 },
160
161 [C(BPU)] = {
162 [C(OP_READ)] = {
163 [C(RESULT_ACCESS)] = -1,
164 [C(RESULT_MISS) ] = -1,
165 },
166 [C(OP_WRITE)] = {
167 [C(RESULT_ACCESS)] = -1,
168 [C(RESULT_MISS) ] = -1,
169 },
170 [C(OP_PREFETCH)] = {
171 [C(RESULT_ACCESS)] = -1,
172 [C(RESULT_MISS) ] = -1,
173 },
174 },
175};
176
177const char *perf_pmu_name(void)
178{
179 return "bfin";
180}
181EXPORT_SYMBOL(perf_pmu_name);
182
183int perf_num_counters(void)
184{
185 return ARRAY_SIZE(event_map);
186}
187EXPORT_SYMBOL(perf_num_counters);
188
189static u64 bfin_pfmon_read(int idx)
190{
191 return bfin_read32(PFCNTR0 + (idx * 4));
192}
193
194static void bfin_pfmon_disable(struct hw_perf_event *hwc, int idx)
195{
196 bfin_write_PFCTL(bfin_read_PFCTL() & ~PFCEN(idx, PFCEN_MASK));
197}
198
199static void bfin_pfmon_enable(struct hw_perf_event *hwc, int idx)
200{
201 u32 val, mask;
202
203 val = PFPWR;
204 if (idx) {
205 mask = ~(PFCNT1 | PFMON1 | PFCEN1 | PEMUSW1);
206 /* The packed config is for event0, so shift it to event1 slots */
207 val |= (hwc->config << (PFMON1_P - PFMON0_P));
208 val |= (hwc->config & PFCNT0) << (PFCNT1_P - PFCNT0_P);
209 bfin_write_PFCNTR1(0);
210 } else {
211 mask = ~(PFCNT0 | PFMON0 | PFCEN0 | PEMUSW0);
212 val |= hwc->config;
213 bfin_write_PFCNTR0(0);
214 }
215
216 bfin_write_PFCTL((bfin_read_PFCTL() & mask) | val);
217}
218
219static void bfin_pfmon_disable_all(void)
220{
221 bfin_write_PFCTL(bfin_read_PFCTL() & ~PFPWR);
222}
223
224static void bfin_pfmon_enable_all(void)
225{
226 bfin_write_PFCTL(bfin_read_PFCTL() | PFPWR);
227}
228
229struct cpu_hw_events {
230 struct perf_event *events[MAX_HWEVENTS];
231 unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
232};
233DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
234
235static int hw_perf_cache_event(int config, int *evp)
236{
237 unsigned long type, op, result;
238 int ev;
239
240 /* unpack config */
241 type = config & 0xff;
242 op = (config >> 8) & 0xff;
243 result = (config >> 16) & 0xff;
244
245 if (type >= PERF_COUNT_HW_CACHE_MAX ||
246 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
247 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
248 return -EINVAL;
249
250 ev = cache_events[type][op][result];
251 if (ev == 0)
252 return -EOPNOTSUPP;
253 if (ev == -1)
254 return -EINVAL;
255 *evp = ev;
256 return 0;
257}
258
259static void bfin_perf_event_update(struct perf_event *event,
260 struct hw_perf_event *hwc, int idx)
261{
262 u64 prev_raw_count, new_raw_count;
263 s64 delta;
264 int shift = 0;
265
266 /*
267 * Depending on the counter configuration, they may or may not
268 * be chained, in which case the previous counter value can be
269 * updated underneath us if the lower-half overflows.
270 *
271 * Our tactic to handle this is to first atomically read and
272 * exchange a new raw count - then add that new-prev delta
273 * count to the generic counter atomically.
274 *
275 * As there is no interrupt associated with the overflow events,
276 * this is the simplest approach for maintaining consistency.
277 */
278again:
279 prev_raw_count = local64_read(&hwc->prev_count);
280 new_raw_count = bfin_pfmon_read(idx);
281
282 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
283 new_raw_count) != prev_raw_count)
284 goto again;
285
286 /*
287 * Now we have the new raw value and have updated the prev
288 * timestamp already. We can now calculate the elapsed delta
289 * (counter-)time and add that to the generic counter.
290 *
291 * Careful, not all hw sign-extends above the physical width
292 * of the count.
293 */
294 delta = (new_raw_count << shift) - (prev_raw_count << shift);
295 delta >>= shift;
296
297 local64_add(delta, &event->count);
298}
299
300static void bfin_pmu_stop(struct perf_event *event, int flags)
301{
302 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
303 struct hw_perf_event *hwc = &event->hw;
304 int idx = hwc->idx;
305
306 if (!(event->hw.state & PERF_HES_STOPPED)) {
307 bfin_pfmon_disable(hwc, idx);
308 cpuc->events[idx] = NULL;
309 event->hw.state |= PERF_HES_STOPPED;
310 }
311
312 if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
313 bfin_perf_event_update(event, &event->hw, idx);
314 event->hw.state |= PERF_HES_UPTODATE;
315 }
316}
317
318static void bfin_pmu_start(struct perf_event *event, int flags)
319{
320 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
321 struct hw_perf_event *hwc = &event->hw;
322 int idx = hwc->idx;
323
324 if (WARN_ON_ONCE(idx == -1))
325 return;
326
327 if (flags & PERF_EF_RELOAD)
328 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
329
330 cpuc->events[idx] = event;
331 event->hw.state = 0;
332 bfin_pfmon_enable(hwc, idx);
333}
334
335static void bfin_pmu_del(struct perf_event *event, int flags)
336{
337 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
338
339 bfin_pmu_stop(event, PERF_EF_UPDATE);
340 __clear_bit(event->hw.idx, cpuc->used_mask);
341
342 perf_event_update_userpage(event);
343}
344
345static int bfin_pmu_add(struct perf_event *event, int flags)
346{
347 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
348 struct hw_perf_event *hwc = &event->hw;
349 int idx = hwc->idx;
350 int ret = -EAGAIN;
351
352 perf_pmu_disable(event->pmu);
353
354 if (__test_and_set_bit(idx, cpuc->used_mask)) {
355 idx = find_first_zero_bit(cpuc->used_mask, MAX_HWEVENTS);
356 if (idx == MAX_HWEVENTS)
357 goto out;
358
359 __set_bit(idx, cpuc->used_mask);
360 hwc->idx = idx;
361 }
362
363 bfin_pfmon_disable(hwc, idx);
364
365 event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
366 if (flags & PERF_EF_START)
367 bfin_pmu_start(event, PERF_EF_RELOAD);
368
369 perf_event_update_userpage(event);
370 ret = 0;
371out:
372 perf_pmu_enable(event->pmu);
373 return ret;
374}
375
376static void bfin_pmu_read(struct perf_event *event)
377{
378 bfin_perf_event_update(event, &event->hw, event->hw.idx);
379}
380
381static int bfin_pmu_event_init(struct perf_event *event)
382{
383 struct perf_event_attr *attr = &event->attr;
384 struct hw_perf_event *hwc = &event->hw;
385 int config = -1;
386 int ret;
387
388 if (attr->exclude_hv || attr->exclude_idle)
389 return -EPERM;
390
391 /*
392 * All of the on-chip counters are "limited", in that they have
393 * no interrupts, and are therefore unable to do sampling without
394 * further work and timer assistance.
395 */
396 if (hwc->sample_period)
397 return -EINVAL;
398
399 ret = 0;
400 switch (attr->type) {
401 case PERF_TYPE_RAW:
402 config = PFMON(0, attr->config & PFMON_MASK) |
403 PFCNT(0, !(attr->config & 0x100));
404 break;
405 case PERF_TYPE_HW_CACHE:
406 ret = hw_perf_cache_event(attr->config, &config);
407 break;
408 case PERF_TYPE_HARDWARE:
409 if (attr->config >= ARRAY_SIZE(event_map))
410 return -EINVAL;
411
412 config = event_map[attr->config];
413 break;
414 }
415
416 if (config == -1)
417 return -EINVAL;
418
419 if (!attr->exclude_kernel)
420 config |= PFCEN(0, PFCEN_ENABLE_SUPV);
421 if (!attr->exclude_user)
422 config |= PFCEN(0, PFCEN_ENABLE_USER);
423
424 hwc->config |= config;
425
426 return ret;
427}
428
429static void bfin_pmu_enable(struct pmu *pmu)
430{
431 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
432 struct perf_event *event;
433 struct hw_perf_event *hwc;
434 int i;
435
436 for (i = 0; i < MAX_HWEVENTS; ++i) {
437 event = cpuc->events[i];
438 if (!event)
439 continue;
440 hwc = &event->hw;
441 bfin_pfmon_enable(hwc, hwc->idx);
442 }
443
444 bfin_pfmon_enable_all();
445}
446
447static void bfin_pmu_disable(struct pmu *pmu)
448{
449 bfin_pfmon_disable_all();
450}
451
452static struct pmu pmu = {
453 .pmu_enable = bfin_pmu_enable,
454 .pmu_disable = bfin_pmu_disable,
455 .event_init = bfin_pmu_event_init,
456 .add = bfin_pmu_add,
457 .del = bfin_pmu_del,
458 .start = bfin_pmu_start,
459 .stop = bfin_pmu_stop,
460 .read = bfin_pmu_read,
461};
462
463static void bfin_pmu_setup(int cpu)
464{
465 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
466
467 memset(cpuhw, 0, sizeof(struct cpu_hw_events));
468}
469
470static int __cpuinit
471bfin_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
472{
473 unsigned int cpu = (long)hcpu;
474
475 switch (action & ~CPU_TASKS_FROZEN) {
476 case CPU_UP_PREPARE:
477 bfin_write_PFCTL(0);
478 bfin_pmu_setup(cpu);
479 break;
480
481 default:
482 break;
483 }
484
485 return NOTIFY_OK;
486}
487
488static int __init bfin_pmu_init(void)
489{
490 int ret;
491
492 ret = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
493 if (!ret)
494 perf_cpu_notifier(bfin_pmu_notifier);
495
496 return ret;
497}
498early_initcall(bfin_pmu_init);
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index b407bc8ad91..6a660fa921b 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -171,10 +171,8 @@ asmlinkage int bfin_clone(struct pt_regs *regs)
171 unsigned long newsp; 171 unsigned long newsp;
172 172
173#ifdef __ARCH_SYNC_CORE_DCACHE 173#ifdef __ARCH_SYNC_CORE_DCACHE
174 if (current->rt.nr_cpus_allowed == num_possible_cpus()) { 174 if (current->rt.nr_cpus_allowed == num_possible_cpus())
175 current->cpus_allowed = cpumask_of_cpu(smp_processor_id()); 175 set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
176 current->rt.nr_cpus_allowed = 1;
177 }
178#endif 176#endif
179 177
180 /* syscall2 puts clone_flags in r0 and usp in r1 */ 178 /* syscall2 puts clone_flags in r0 and usp in r1 */
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 53d08dee853..488bdc51aaa 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -23,6 +23,9 @@
23__attribute__ ((__l1_text__, __noreturn__)) 23__attribute__ ((__l1_text__, __noreturn__))
24static void bfin_reset(void) 24static void bfin_reset(void)
25{ 25{
26 if (!ANOMALY_05000353 && !ANOMALY_05000386)
27 bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
28
26 /* Wait for completion of "system" events such as cache line 29 /* Wait for completion of "system" events such as cache line
27 * line fills so that we avoid infinite stalls later on as 30 * line fills so that we avoid infinite stalls later on as
28 * much as possible. This code is in L1, so it won't trigger 31 * much as possible. This code is in L1, so it won't trigger
@@ -30,46 +33,40 @@ static void bfin_reset(void)
30 */ 33 */
31 __builtin_bfin_ssync(); 34 __builtin_bfin_ssync();
32 35
33 /* The bootrom checks to see how it was reset and will 36 /* Initiate System software reset. */
34 * automatically perform a software reset for us when 37 bfin_write_SWRST(0x7);
35 * it starts executing after the core reset.
36 */
37 if (ANOMALY_05000353 || ANOMALY_05000386) {
38 /* Initiate System software reset. */
39 bfin_write_SWRST(0x7);
40 38
41 /* Due to the way reset is handled in the hardware, we need 39 /* Due to the way reset is handled in the hardware, we need
42 * to delay for 10 SCLKS. The only reliable way to do this is 40 * to delay for 10 SCLKS. The only reliable way to do this is
43 * to calculate the CCLK/SCLK ratio and multiply 10. For now, 41 * to calculate the CCLK/SCLK ratio and multiply 10. For now,
44 * we'll assume worse case which is a 1:15 ratio. 42 * we'll assume worse case which is a 1:15 ratio.
45 */ 43 */
46 asm( 44 asm(
47 "LSETUP (1f, 1f) LC0 = %0\n" 45 "LSETUP (1f, 1f) LC0 = %0\n"
48 "1: nop;" 46 "1: nop;"
49 : 47 :
50 : "a" (15 * 10) 48 : "a" (15 * 10)
51 : "LC0", "LB0", "LT0" 49 : "LC0", "LB0", "LT0"
52 ); 50 );
53 51
54 /* Clear System software reset */ 52 /* Clear System software reset */
55 bfin_write_SWRST(0); 53 bfin_write_SWRST(0);
56 54
57 /* The BF526 ROM will crash during reset */ 55 /* The BF526 ROM will crash during reset */
58#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) 56#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
59 bfin_read_SWRST(); 57 bfin_read_SWRST();
60#endif 58#endif
61 59
62 /* Wait for the SWRST write to complete. Cannot rely on SSYNC 60 /* Wait for the SWRST write to complete. Cannot rely on SSYNC
63 * though as the System state is all reset now. 61 * though as the System state is all reset now.
64 */ 62 */
65 asm( 63 asm(
66 "LSETUP (1f, 1f) LC1 = %0\n" 64 "LSETUP (1f, 1f) LC1 = %0\n"
67 "1: nop;" 65 "1: nop;"
68 : 66 :
69 : "a" (15 * 1) 67 : "a" (15 * 1)
70 : "LC1", "LB1", "LT1" 68 : "LC1", "LB1", "LT1"
71 ); 69 );
72 }
73 70
74 while (1) 71 while (1)
75 /* Issue core reset */ 72 /* Issue core reset */
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 805c6132c77..536bd9d7e0c 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -29,6 +29,7 @@
29#include <asm/cpu.h> 29#include <asm/cpu.h>
30#include <asm/fixed_code.h> 30#include <asm/fixed_code.h>
31#include <asm/early_printk.h> 31#include <asm/early_printk.h>
32#include <asm/irq_handler.h>
32 33
33u16 _bfin_swrst; 34u16 _bfin_swrst;
34EXPORT_SYMBOL(_bfin_swrst); 35EXPORT_SYMBOL(_bfin_swrst);
@@ -105,6 +106,8 @@ void __cpuinit bfin_setup_caches(unsigned int cpu)
105 bfin_dcache_init(dcplb_tbl[cpu]); 106 bfin_dcache_init(dcplb_tbl[cpu]);
106#endif 107#endif
107 108
109 bfin_setup_cpudata(cpu);
110
108 /* 111 /*
109 * In cache coherence emulation mode, we need to have the 112 * In cache coherence emulation mode, we need to have the
110 * D-cache enabled before running any atomic operation which 113 * D-cache enabled before running any atomic operation which
@@ -163,7 +166,6 @@ void __cpuinit bfin_setup_cpudata(unsigned int cpu)
163{ 166{
164 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu); 167 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
165 168
166 cpudata->idle = current;
167 cpudata->imemctl = bfin_read_IMEM_CONTROL(); 169 cpudata->imemctl = bfin_read_IMEM_CONTROL();
168 cpudata->dmemctl = bfin_read_DMEM_CONTROL(); 170 cpudata->dmemctl = bfin_read_DMEM_CONTROL();
169} 171}
@@ -851,6 +853,7 @@ void __init native_machine_early_platform_add_devices(void)
851 853
852void __init setup_arch(char **cmdline_p) 854void __init setup_arch(char **cmdline_p)
853{ 855{
856 u32 mmr;
854 unsigned long sclk, cclk; 857 unsigned long sclk, cclk;
855 858
856 native_machine_early_platform_add_devices(); 859 native_machine_early_platform_add_devices();
@@ -902,10 +905,10 @@ void __init setup_arch(char **cmdline_p)
902 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL); 905 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
903#endif 906#endif
904#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL 907#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
905 bfin_write_PORTF_HYSTERISIS(HYST_PORTF_0_15); 908 bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
906 bfin_write_PORTG_HYSTERISIS(HYST_PORTG_0_15); 909 bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
907 bfin_write_PORTH_HYSTERISIS(HYST_PORTH_0_15); 910 bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15);
908 bfin_write_MISCPORT_HYSTERISIS((bfin_read_MISCPORT_HYSTERISIS() & 911 bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() &
909 ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO); 912 ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
910#endif 913#endif
911 914
@@ -921,17 +924,14 @@ void __init setup_arch(char **cmdline_p)
921 bfin_read_IMDMA_D1_IRQ_STATUS(); 924 bfin_read_IMDMA_D1_IRQ_STATUS();
922 } 925 }
923#endif 926#endif
924 printk(KERN_INFO "Hardware Trace ");
925 if (bfin_read_TBUFCTL() & 0x1)
926 printk(KERN_CONT "Active ");
927 else
928 printk(KERN_CONT "Off ");
929 if (bfin_read_TBUFCTL() & 0x2)
930 printk(KERN_CONT "and Enabled\n");
931 else
932 printk(KERN_CONT "and Disabled\n");
933 927
934 printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF); 928 mmr = bfin_read_TBUFCTL();
929 printk(KERN_INFO "Hardware Trace %s and %sabled\n",
930 (mmr & 0x1) ? "active" : "off",
931 (mmr & 0x2) ? "en" : "dis");
932
933 mmr = bfin_read_SYSCR();
934 printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
935 935
936 /* Newer parts mirror SWRST bits in SYSCR */ 936 /* Newer parts mirror SWRST bits in SYSCR */
937#if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \ 937#if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
@@ -939,7 +939,7 @@ void __init setup_arch(char **cmdline_p)
939 _bfin_swrst = bfin_read_SWRST(); 939 _bfin_swrst = bfin_read_SWRST();
940#else 940#else
941 /* Clear boot mode field */ 941 /* Clear boot mode field */
942 _bfin_swrst = bfin_read_SYSCR() & ~0xf; 942 _bfin_swrst = mmr & ~0xf;
943#endif 943#endif
944 944
945#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT 945#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
@@ -1036,8 +1036,6 @@ void __init setup_arch(char **cmdline_p)
1036static int __init topology_init(void) 1036static int __init topology_init(void)
1037{ 1037{
1038 unsigned int cpu; 1038 unsigned int cpu;
1039 /* Record CPU-private information for the boot processor. */
1040 bfin_setup_cpudata(0);
1041 1039
1042 for_each_possible_cpu(cpu) { 1040 for_each_possible_cpu(cpu) {
1043 register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu); 1041 register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
@@ -1283,12 +1281,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1283 dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, 1281 dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
1284 BFIN_DLINES); 1282 BFIN_DLINES);
1285#ifdef __ARCH_SYNC_CORE_DCACHE 1283#ifdef __ARCH_SYNC_CORE_DCACHE
1286 seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", dcache_invld_count[cpu_num]); 1284 seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]);
1287#endif 1285#endif
1288#ifdef __ARCH_SYNC_CORE_ICACHE 1286#ifdef __ARCH_SYNC_CORE_ICACHE
1289 seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", icache_invld_count[cpu_num]); 1287 seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]);
1290#endif 1288#endif
1291 1289
1290 seq_printf(m, "\n");
1291
1292 if (cpu_num != num_possible_cpus() - 1) 1292 if (cpu_num != num_possible_cpus() - 1)
1293 return 0; 1293 return 0;
1294 1294
@@ -1312,13 +1312,11 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1312 " in data cache\n"); 1312 " in data cache\n");
1313 } 1313 }
1314 seq_printf(m, "board name\t: %s\n", bfin_board_name); 1314 seq_printf(m, "board name\t: %s\n", bfin_board_name);
1315 seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", 1315 seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
1316 physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); 1316 physical_mem_end >> 10, 0ul, physical_mem_end);
1317 seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n", 1317 seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
1318 ((int)memory_end - (int)_rambase) >> 10, 1318 ((int)memory_end - (int)_rambase) >> 10,
1319 (void *)_rambase, 1319 _rambase, memory_end);
1320 (void *)memory_end);
1321 seq_printf(m, "\n");
1322 1320
1323 return 0; 1321 return 0;
1324} 1322}
@@ -1326,7 +1324,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1326static void *c_start(struct seq_file *m, loff_t *pos) 1324static void *c_start(struct seq_file *m, loff_t *pos)
1327{ 1325{
1328 if (*pos == 0) 1326 if (*pos == 0)
1329 *pos = first_cpu(cpu_online_map); 1327 *pos = cpumask_first(cpu_online_mask);
1330 if (*pos >= num_online_cpus()) 1328 if (*pos >= num_online_cpus())
1331 return NULL; 1329 return NULL;
1332 1330
@@ -1335,7 +1333,7 @@ static void *c_start(struct seq_file *m, loff_t *pos)
1335 1333
1336static void *c_next(struct seq_file *m, void *v, loff_t *pos) 1334static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1337{ 1335{
1338 *pos = next_cpu(*pos, cpu_online_map); 1336 *pos = cpumask_next(*pos, cpu_online_mask);
1339 1337
1340 return c_start(m, pos); 1338 return c_start(m, pos);
1341} 1339}
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 8d85c8c6f85..3ac5b66d14a 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -155,14 +155,8 @@ SECTIONS
155 SECURITY_INITCALL 155 SECURITY_INITCALL
156 INIT_RAM_FS 156 INIT_RAM_FS
157 157
158 . = ALIGN(4);
159 ___per_cpu_load = .; 158 ___per_cpu_load = .;
160 ___per_cpu_start = .; 159 PERCPU_INPUT(32)
161 *(.data.percpu.first)
162 *(.data.percpu.page_aligned)
163 *(.data.percpu)
164 *(.data.percpu.shared_aligned)
165 ___per_cpu_end = .;
166 160
167 EXIT_DATA 161 EXIT_DATA
168 __einitdata = .; 162 __einitdata = .;
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index 24918c5f7ea..d2f076fbbc9 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -5,7 +5,7 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2010 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
@@ -141,6 +141,7 @@
141#define ANOMALY_05000364 (0) 141#define ANOMALY_05000364 (0)
142#define ANOMALY_05000371 (0) 142#define ANOMALY_05000371 (0)
143#define ANOMALY_05000380 (0) 143#define ANOMALY_05000380 (0)
144#define ANOMALY_05000383 (0)
144#define ANOMALY_05000386 (0) 145#define ANOMALY_05000386 (0)
145#define ANOMALY_05000389 (0) 146#define ANOMALY_05000389 (0)
146#define ANOMALY_05000400 (0) 147#define ANOMALY_05000400 (0)
@@ -155,6 +156,7 @@
155#define ANOMALY_05000467 (0) 156#define ANOMALY_05000467 (0)
156#define ANOMALY_05000474 (0) 157#define ANOMALY_05000474 (0)
157#define ANOMALY_05000475 (0) 158#define ANOMALY_05000475 (0)
159#define ANOMALY_05000480 (0)
158#define ANOMALY_05000485 (0) 160#define ANOMALY_05000485 (0)
159 161
160#endif 162#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
index b657d37a340..bb79627f092 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
@@ -990,18 +990,18 @@
990#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) 990#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
991#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) 991#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
992#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) 992#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
993#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) 993#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
994#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) 994#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
995#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) 995#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
996#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) 996#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
997#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) 997#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
998#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) 998#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
999#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) 999#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1000#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) 1000#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1001#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) 1001#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1002#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) 1002#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1003#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) 1003#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
1004#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) 1004#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
1005 1005
1006/* HOST Port Registers */ 1006/* HOST Port Registers */
1007 1007
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
index cb1172f5075..729704078cd 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h
@@ -561,12 +561,12 @@
561#define PORTF_SLEW 0xFFC03230 /* Port F slew control */ 561#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
562#define PORTG_SLEW 0xFFC03234 /* Port G slew control */ 562#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
563#define PORTH_SLEW 0xFFC03238 /* Port H slew control */ 563#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
564#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */ 564#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
565#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */ 565#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
566#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */ 566#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
567#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ 567#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
568#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ 568#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
569#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */ 569#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
570 570
571 571
572/*********************************************************************************** 572/***********************************************************************************
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
index 435e76e31aa..edf8efd457d 100644
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -7,38 +7,9 @@
7#ifndef _BF518_IRQ_H_ 7#ifndef _BF518_IRQ_H_
8#define _BF518_IRQ_H_ 8#define _BF518_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions 11
12 Event Source Core Event Name 12#define NR_PERI_INTS (2 * 32)
13 Core Emulation **
14 Events (highest priority) EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21
22 .....
23
24 Software Interrupt 1 IVG14 31
25 Software Interrupt 2 --
26 (lowest priority) IVG15 32 *
27*/
28
29#define NR_PERI_INTS (2 * 32)
30
31/* The ABSTRACT IRQ definitions */
32/** the first seven of the following are fixed, the rest you change if you need to **/
33#define IRQ_EMU 0 /* Emulation */
34#define IRQ_RST 1 /* reset */
35#define IRQ_NMI 2 /* Non Maskable */
36#define IRQ_EVX 3 /* Exception */
37#define IRQ_UNUSED 4 /* - unused interrupt */
38#define IRQ_HWERR 5 /* Hardware Error */
39#define IRQ_CORETMR 6 /* Core timer */
40
41#define BFIN_IRQ(x) ((x) + 7)
42 13
43#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
@@ -54,23 +25,23 @@
54#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ 25#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
55#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ 26#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
56#define IRQ_RTC BFIN_IRQ(14) /* RTC */ 27#define IRQ_RTC BFIN_IRQ(14) /* RTC */
57#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */ 28#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
58#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ 29#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
59#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ 30#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
60#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */ 31#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
61#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */ 32#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
62#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */ 33#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
63#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ 34#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
64#define IRQ_TWI BFIN_IRQ(20) /* TWI */ 35#define IRQ_TWI BFIN_IRQ(20) /* TWI */
65#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */ 36#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
66#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ 37#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
67#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ 38#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
68#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ 39#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
69#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ 40#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
70#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ 41#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
71#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ 42#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
72#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */ 43#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
73#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ 44#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
74#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */ 45#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
75#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ 46#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
76#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */ 47#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
@@ -96,101 +67,90 @@
96#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */ 67#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
97#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */ 68#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
98 69
99#define SYS_IRQS BFIN_IRQ(63) /* 70 */ 70#define SYS_IRQS BFIN_IRQ(63) /* 70 */
100 71
101#define IRQ_PF0 71 72#define IRQ_PF0 71
102#define IRQ_PF1 72 73#define IRQ_PF1 72
103#define IRQ_PF2 73 74#define IRQ_PF2 73
104#define IRQ_PF3 74 75#define IRQ_PF3 74
105#define IRQ_PF4 75 76#define IRQ_PF4 75
106#define IRQ_PF5 76 77#define IRQ_PF5 76
107#define IRQ_PF6 77 78#define IRQ_PF6 77
108#define IRQ_PF7 78 79#define IRQ_PF7 78
109#define IRQ_PF8 79 80#define IRQ_PF8 79
110#define IRQ_PF9 80 81#define IRQ_PF9 80
111#define IRQ_PF10 81 82#define IRQ_PF10 81
112#define IRQ_PF11 82 83#define IRQ_PF11 82
113#define IRQ_PF12 83 84#define IRQ_PF12 83
114#define IRQ_PF13 84 85#define IRQ_PF13 84
115#define IRQ_PF14 85 86#define IRQ_PF14 85
116#define IRQ_PF15 86 87#define IRQ_PF15 86
117 88
118#define IRQ_PG0 87 89#define IRQ_PG0 87
119#define IRQ_PG1 88 90#define IRQ_PG1 88
120#define IRQ_PG2 89 91#define IRQ_PG2 89
121#define IRQ_PG3 90 92#define IRQ_PG3 90
122#define IRQ_PG4 91 93#define IRQ_PG4 91
123#define IRQ_PG5 92 94#define IRQ_PG5 92
124#define IRQ_PG6 93 95#define IRQ_PG6 93
125#define IRQ_PG7 94 96#define IRQ_PG7 94
126#define IRQ_PG8 95 97#define IRQ_PG8 95
127#define IRQ_PG9 96 98#define IRQ_PG9 96
128#define IRQ_PG10 97 99#define IRQ_PG10 97
129#define IRQ_PG11 98 100#define IRQ_PG11 98
130#define IRQ_PG12 99 101#define IRQ_PG12 99
131#define IRQ_PG13 100 102#define IRQ_PG13 100
132#define IRQ_PG14 101 103#define IRQ_PG14 101
133#define IRQ_PG15 102 104#define IRQ_PG15 102
134 105
135#define IRQ_PH0 103 106#define IRQ_PH0 103
136#define IRQ_PH1 104 107#define IRQ_PH1 104
137#define IRQ_PH2 105 108#define IRQ_PH2 105
138#define IRQ_PH3 106 109#define IRQ_PH3 106
139#define IRQ_PH4 107 110#define IRQ_PH4 107
140#define IRQ_PH5 108 111#define IRQ_PH5 108
141#define IRQ_PH6 109 112#define IRQ_PH6 109
142#define IRQ_PH7 110 113#define IRQ_PH7 110
143#define IRQ_PH8 111 114#define IRQ_PH8 111
144#define IRQ_PH9 112 115#define IRQ_PH9 112
145#define IRQ_PH10 113 116#define IRQ_PH10 113
146#define IRQ_PH11 114 117#define IRQ_PH11 114
147#define IRQ_PH12 115 118#define IRQ_PH12 115
148#define IRQ_PH13 116 119#define IRQ_PH13 116
149#define IRQ_PH14 117 120#define IRQ_PH14 117
150#define IRQ_PH15 118 121#define IRQ_PH15 118
151 122
152#define GPIO_IRQ_BASE IRQ_PF0 123#define GPIO_IRQ_BASE IRQ_PF0
153 124
154#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */ 125#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
155#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */ 126#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
156#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */ 127#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
157#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */ 128#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
158#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */ 129#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
159#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */ 130#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
160#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */ 131#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
161#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ 132#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
162 133
163#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 134#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
164#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
165
166#define IVG7 7
167#define IVG8 8
168#define IVG9 9
169#define IVG10 10
170#define IVG11 11
171#define IVG12 12
172#define IVG13 13
173#define IVG14 14
174#define IVG15 15
175 135
176/* IAR0 BIT FIELDS */ 136/* IAR0 BIT FIELDS */
177#define IRQ_PLL_WAKEUP_POS 0 137#define IRQ_PLL_WAKEUP_POS 0
178#define IRQ_DMA0_ERROR_POS 4 138#define IRQ_DMA0_ERROR_POS 4
179#define IRQ_DMAR0_BLK_POS 8 139#define IRQ_DMAR0_BLK_POS 8
180#define IRQ_DMAR1_BLK_POS 12 140#define IRQ_DMAR1_BLK_POS 12
181#define IRQ_DMAR0_OVR_POS 16 141#define IRQ_DMAR0_OVR_POS 16
182#define IRQ_DMAR1_OVR_POS 20 142#define IRQ_DMAR1_OVR_POS 20
183#define IRQ_PPI_ERROR_POS 24 143#define IRQ_PPI_ERROR_POS 24
184#define IRQ_MAC_ERROR_POS 28 144#define IRQ_MAC_ERROR_POS 28
185 145
186/* IAR1 BIT FIELDS */ 146/* IAR1 BIT FIELDS */
187#define IRQ_SPORT0_ERROR_POS 0 147#define IRQ_SPORT0_ERROR_POS 0
188#define IRQ_SPORT1_ERROR_POS 4 148#define IRQ_SPORT1_ERROR_POS 4
189#define IRQ_PTP_ERROR_POS 8 149#define IRQ_PTP_ERROR_POS 8
190#define IRQ_UART0_ERROR_POS 16 150#define IRQ_UART0_ERROR_POS 16
191#define IRQ_UART1_ERROR_POS 20 151#define IRQ_UART1_ERROR_POS 20
192#define IRQ_RTC_POS 24 152#define IRQ_RTC_POS 24
193#define IRQ_PPI_POS 28 153#define IRQ_PPI_POS 28
194 154
195/* IAR2 BIT FIELDS */ 155/* IAR2 BIT FIELDS */
196#define IRQ_SPORT0_RX_POS 0 156#define IRQ_SPORT0_RX_POS 0
@@ -199,19 +159,19 @@
199#define IRQ_SPORT1_RX_POS 8 159#define IRQ_SPORT1_RX_POS 8
200#define IRQ_SPI1_POS 8 160#define IRQ_SPI1_POS 8
201#define IRQ_SPORT1_TX_POS 12 161#define IRQ_SPORT1_TX_POS 12
202#define IRQ_TWI_POS 16 162#define IRQ_TWI_POS 16
203#define IRQ_SPI0_POS 20 163#define IRQ_SPI0_POS 20
204#define IRQ_UART0_RX_POS 24 164#define IRQ_UART0_RX_POS 24
205#define IRQ_UART0_TX_POS 28 165#define IRQ_UART0_TX_POS 28
206 166
207/* IAR3 BIT FIELDS */ 167/* IAR3 BIT FIELDS */
208#define IRQ_UART1_RX_POS 0 168#define IRQ_UART1_RX_POS 0
209#define IRQ_UART1_TX_POS 4 169#define IRQ_UART1_TX_POS 4
210#define IRQ_OPTSEC_POS 8 170#define IRQ_OPTSEC_POS 8
211#define IRQ_CNT_POS 12 171#define IRQ_CNT_POS 12
212#define IRQ_MAC_RX_POS 16 172#define IRQ_MAC_RX_POS 16
213#define IRQ_PORTH_INTA_POS 20 173#define IRQ_PORTH_INTA_POS 20
214#define IRQ_MAC_TX_POS 24 174#define IRQ_MAC_TX_POS 24
215#define IRQ_PORTH_INTB_POS 28 175#define IRQ_PORTH_INTB_POS 28
216 176
217/* IAR4 BIT FIELDS */ 177/* IAR4 BIT FIELDS */
@@ -227,19 +187,19 @@
227/* IAR5 BIT FIELDS */ 187/* IAR5 BIT FIELDS */
228#define IRQ_PORTG_INTA_POS 0 188#define IRQ_PORTG_INTA_POS 0
229#define IRQ_PORTG_INTB_POS 4 189#define IRQ_PORTG_INTB_POS 4
230#define IRQ_MEM_DMA0_POS 8 190#define IRQ_MEM_DMA0_POS 8
231#define IRQ_MEM_DMA1_POS 12 191#define IRQ_MEM_DMA1_POS 12
232#define IRQ_WATCH_POS 16 192#define IRQ_WATCH_POS 16
233#define IRQ_PORTF_INTA_POS 20 193#define IRQ_PORTF_INTA_POS 20
234#define IRQ_PORTF_INTB_POS 24 194#define IRQ_PORTF_INTB_POS 24
235#define IRQ_SPI0_ERROR_POS 28 195#define IRQ_SPI0_ERROR_POS 28
236 196
237/* IAR6 BIT FIELDS */ 197/* IAR6 BIT FIELDS */
238#define IRQ_SPI1_ERROR_POS 0 198#define IRQ_SPI1_ERROR_POS 0
239#define IRQ_RSI_INT0_POS 12 199#define IRQ_RSI_INT0_POS 12
240#define IRQ_RSI_INT1_POS 16 200#define IRQ_RSI_INT1_POS 16
241#define IRQ_PWM_TRIP_POS 20 201#define IRQ_PWM_TRIP_POS 20
242#define IRQ_PWM_SYNC_POS 24 202#define IRQ_PWM_SYNC_POS 24
243#define IRQ_PTP_STAT_POS 28 203#define IRQ_PTP_STAT_POS 28
244 204
245#endif /* _BF518_IRQ_H_ */ 205#endif
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 2cd2ff6f304..e67ac772066 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -26,6 +26,7 @@
26#include <asm/portmux.h> 26#include <asm/portmux.h>
27#include <asm/dpmc.h> 27#include <asm/dpmc.h>
28#include <linux/spi/ad7877.h> 28#include <linux/spi/ad7877.h>
29#include <asm/bfin_sport.h>
29 30
30/* 31/*
31 * Name the Board for the /proc/cpuinfo 32 * Name the Board for the /proc/cpuinfo
@@ -526,11 +527,69 @@ static struct bfin5xx_spi_chip spidev_chip_info = {
526}; 527};
527#endif 528#endif
528 529
530#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
531 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
532
533static const u16 bfin_snd_pin[][7] = {
534 {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
535 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0, 0},
536 {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
537 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_TFS, 0},
538};
539
540static struct bfin_snd_platform_data bfin_snd_data[] = {
541 {
542 .pin_req = &bfin_snd_pin[0][0],
543 },
544 {
545 .pin_req = &bfin_snd_pin[1][0],
546 },
547};
548
549#define BFIN_SND_RES(x) \
550 [x] = { \
551 { \
552 .start = SPORT##x##_TCR1, \
553 .end = SPORT##x##_TCR1, \
554 .flags = IORESOURCE_MEM \
555 }, \
556 { \
557 .start = CH_SPORT##x##_RX, \
558 .end = CH_SPORT##x##_RX, \
559 .flags = IORESOURCE_DMA, \
560 }, \
561 { \
562 .start = CH_SPORT##x##_TX, \
563 .end = CH_SPORT##x##_TX, \
564 .flags = IORESOURCE_DMA, \
565 }, \
566 { \
567 .start = IRQ_SPORT##x##_ERROR, \
568 .end = IRQ_SPORT##x##_ERROR, \
569 .flags = IORESOURCE_IRQ, \
570 } \
571 }
572
573static struct resource bfin_snd_resources[][4] = {
574 BFIN_SND_RES(0),
575 BFIN_SND_RES(1),
576};
577
578static struct platform_device bfin_pcm = {
579 .name = "bfin-pcm-audio",
580 .id = -1,
581};
582#endif
583
529#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 584#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
530static struct platform_device bfin_i2s = { 585static struct platform_device bfin_i2s = {
531 .name = "bfin-i2s", 586 .name = "bfin-i2s",
532 .id = CONFIG_SND_BF5XX_SPORT_NUM, 587 .id = CONFIG_SND_BF5XX_SPORT_NUM,
533 /* TODO: add platform data here */ 588 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
589 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
590 .dev = {
591 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
592 },
534}; 593};
535#endif 594#endif
536 595
@@ -538,7 +597,11 @@ static struct platform_device bfin_i2s = {
538static struct platform_device bfin_tdm = { 597static struct platform_device bfin_tdm = {
539 .name = "bfin-tdm", 598 .name = "bfin-tdm",
540 .id = CONFIG_SND_BF5XX_SPORT_NUM, 599 .id = CONFIG_SND_BF5XX_SPORT_NUM,
541 /* TODO: add platform data here */ 600 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
601 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
602 .dev = {
603 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
604 },
542}; 605};
543#endif 606#endif
544 607
@@ -583,7 +646,9 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
583 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 646 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
584 .bus_num = 0, 647 .bus_num = 0,
585 .chip_select = 4, 648 .chip_select = 4,
649 .platform_data = "ad1836",
586 .controller_data = &ad1836_spi_chip_info, 650 .controller_data = &ad1836_spi_chip_info,
651 .mode = SPI_MODE_3,
587 }, 652 },
588#endif 653#endif
589#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 654#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -1211,6 +1276,11 @@ static struct platform_device *stamp_devices[] __initdata = {
1211 &ezkit_flash_device, 1276 &ezkit_flash_device,
1212#endif 1277#endif
1213 1278
1279#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
1280 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1281 &bfin_pcm,
1282#endif
1283
1214#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 1284#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1215 &bfin_i2s, 1285 &bfin_i2s,
1216#endif 1286#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 9358afa05c9..e66a7e89cd3 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -5,14 +5,14 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2010 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List 14 * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
15 * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List 15 * - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List
16 */ 16 */
17 17
18#ifndef _MACH_ANOMALY_H_ 18#ifndef _MACH_ANOMALY_H_
@@ -220,6 +220,8 @@
220#define ANOMALY_05000483 (1) 220#define ANOMALY_05000483 (1)
221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ 221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3)) 222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
223/* The CODEC Zero-Cross Detect Feature is not Functional */
224#define ANOMALY_05000487 (1)
223/* IFLUSH sucks at life */ 225/* IFLUSH sucks at life */
224#define ANOMALY_05000491 (1) 226#define ANOMALY_05000491 (1)
225 227
@@ -268,11 +270,13 @@
268#define ANOMALY_05000323 (0) 270#define ANOMALY_05000323 (0)
269#define ANOMALY_05000362 (1) 271#define ANOMALY_05000362 (1)
270#define ANOMALY_05000363 (0) 272#define ANOMALY_05000363 (0)
273#define ANOMALY_05000383 (0)
271#define ANOMALY_05000400 (0) 274#define ANOMALY_05000400 (0)
272#define ANOMALY_05000402 (0) 275#define ANOMALY_05000402 (0)
273#define ANOMALY_05000412 (0) 276#define ANOMALY_05000412 (0)
274#define ANOMALY_05000447 (0) 277#define ANOMALY_05000447 (0)
275#define ANOMALY_05000448 (0) 278#define ANOMALY_05000448 (0)
276#define ANOMALY_05000474 (0) 279#define ANOMALY_05000474 (0)
280#define ANOMALY_05000480 (0)
277 281
278#endif 282#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
index 618dfcdfa91..2c12e879aa4 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
@@ -1007,18 +1007,18 @@
1007#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) 1007#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
1008#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) 1008#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
1009#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) 1009#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
1010#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) 1010#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
1011#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) 1011#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
1012#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) 1012#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
1013#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) 1013#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
1014#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) 1014#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
1015#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) 1015#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
1016#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) 1016#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1017#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) 1017#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1018#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) 1018#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1019#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) 1019#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1020#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) 1020#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
1021#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) 1021#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
1022 1022
1023/* HOST Port Registers */ 1023/* HOST Port Registers */
1024 1024
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
index 84ef11e5264..37d353a1972 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h
@@ -562,12 +562,12 @@
562#define PORTF_SLEW 0xFFC03230 /* Port F slew control */ 562#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
563#define PORTG_SLEW 0xFFC03234 /* Port G slew control */ 563#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
564#define PORTH_SLEW 0xFFC03238 /* Port H slew control */ 564#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
565#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */ 565#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
566#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */ 566#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
567#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */ 567#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
568#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ 568#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
569#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ 569#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
570#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */ 570#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
571 571
572 572
573/*********************************************************************************** 573/***********************************************************************************
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
index 704d9253e41..ed7310ff819 100644
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ b/arch/blackfin/mach-bf527/include/mach/irq.h
@@ -7,38 +7,9 @@
7#ifndef _BF527_IRQ_H_ 7#ifndef _BF527_IRQ_H_
8#define _BF527_IRQ_H_ 8#define _BF527_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions 11
12 Event Source Core Event Name 12#define NR_PERI_INTS (2 * 32)
13 Core Emulation **
14 Events (highest priority) EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21
22 .....
23
24 Software Interrupt 1 IVG14 31
25 Software Interrupt 2 --
26 (lowest priority) IVG15 32 *
27*/
28
29#define NR_PERI_INTS (2 * 32)
30
31/* The ABSTRACT IRQ definitions */
32/** the first seven of the following are fixed, the rest you change if you need to **/
33#define IRQ_EMU 0 /* Emulation */
34#define IRQ_RST 1 /* reset */
35#define IRQ_NMI 2 /* Non Maskable */
36#define IRQ_EVX 3 /* Exception */
37#define IRQ_UNUSED 4 /* - unused interrupt */
38#define IRQ_HWERR 5 /* Hardware Error */
39#define IRQ_CORETMR 6 /* Core timer */
40
41#define BFIN_IRQ(x) ((x) + 7)
42 13
43#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
@@ -53,21 +24,21 @@
53#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ 24#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
54#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ 25#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
55#define IRQ_RTC BFIN_IRQ(14) /* RTC */ 26#define IRQ_RTC BFIN_IRQ(14) /* RTC */
56#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */ 27#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
57#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ 28#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
58#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ 29#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
59#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */ 30#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
60#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ 31#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
61#define IRQ_TWI BFIN_IRQ(20) /* TWI */ 32#define IRQ_TWI BFIN_IRQ(20) /* TWI */
62#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */ 33#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
63#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ 34#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
64#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ 35#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
65#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ 36#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
66#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ 37#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
67#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ 38#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
68#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ 39#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
69#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */ 40#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
70#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ 41#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
71#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 42#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
72#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 43#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
73#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ 44#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
@@ -96,119 +67,108 @@
96#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */ 67#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
97#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */ 68#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
98 69
99#define SYS_IRQS BFIN_IRQ(63) /* 70 */ 70#define SYS_IRQS BFIN_IRQ(63) /* 70 */
100 71
101#define IRQ_PF0 71 72#define IRQ_PF0 71
102#define IRQ_PF1 72 73#define IRQ_PF1 72
103#define IRQ_PF2 73 74#define IRQ_PF2 73
104#define IRQ_PF3 74 75#define IRQ_PF3 74
105#define IRQ_PF4 75 76#define IRQ_PF4 75
106#define IRQ_PF5 76 77#define IRQ_PF5 76
107#define IRQ_PF6 77 78#define IRQ_PF6 77
108#define IRQ_PF7 78 79#define IRQ_PF7 78
109#define IRQ_PF8 79 80#define IRQ_PF8 79
110#define IRQ_PF9 80 81#define IRQ_PF9 80
111#define IRQ_PF10 81 82#define IRQ_PF10 81
112#define IRQ_PF11 82 83#define IRQ_PF11 82
113#define IRQ_PF12 83 84#define IRQ_PF12 83
114#define IRQ_PF13 84 85#define IRQ_PF13 84
115#define IRQ_PF14 85 86#define IRQ_PF14 85
116#define IRQ_PF15 86 87#define IRQ_PF15 86
117 88
118#define IRQ_PG0 87 89#define IRQ_PG0 87
119#define IRQ_PG1 88 90#define IRQ_PG1 88
120#define IRQ_PG2 89 91#define IRQ_PG2 89
121#define IRQ_PG3 90 92#define IRQ_PG3 90
122#define IRQ_PG4 91 93#define IRQ_PG4 91
123#define IRQ_PG5 92 94#define IRQ_PG5 92
124#define IRQ_PG6 93 95#define IRQ_PG6 93
125#define IRQ_PG7 94 96#define IRQ_PG7 94
126#define IRQ_PG8 95 97#define IRQ_PG8 95
127#define IRQ_PG9 96 98#define IRQ_PG9 96
128#define IRQ_PG10 97 99#define IRQ_PG10 97
129#define IRQ_PG11 98 100#define IRQ_PG11 98
130#define IRQ_PG12 99 101#define IRQ_PG12 99
131#define IRQ_PG13 100 102#define IRQ_PG13 100
132#define IRQ_PG14 101 103#define IRQ_PG14 101
133#define IRQ_PG15 102 104#define IRQ_PG15 102
134 105
135#define IRQ_PH0 103 106#define IRQ_PH0 103
136#define IRQ_PH1 104 107#define IRQ_PH1 104
137#define IRQ_PH2 105 108#define IRQ_PH2 105
138#define IRQ_PH3 106 109#define IRQ_PH3 106
139#define IRQ_PH4 107 110#define IRQ_PH4 107
140#define IRQ_PH5 108 111#define IRQ_PH5 108
141#define IRQ_PH6 109 112#define IRQ_PH6 109
142#define IRQ_PH7 110 113#define IRQ_PH7 110
143#define IRQ_PH8 111 114#define IRQ_PH8 111
144#define IRQ_PH9 112 115#define IRQ_PH9 112
145#define IRQ_PH10 113 116#define IRQ_PH10 113
146#define IRQ_PH11 114 117#define IRQ_PH11 114
147#define IRQ_PH12 115 118#define IRQ_PH12 115
148#define IRQ_PH13 116 119#define IRQ_PH13 116
149#define IRQ_PH14 117 120#define IRQ_PH14 117
150#define IRQ_PH15 118 121#define IRQ_PH15 118
151 122
152#define GPIO_IRQ_BASE IRQ_PF0 123#define GPIO_IRQ_BASE IRQ_PF0
153 124
154#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */ 125#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
155#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */ 126#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
156#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */ 127#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
157#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */ 128#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
158#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */ 129#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
159#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */ 130#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
160#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */ 131#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
161#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ 132#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
162 133
163#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 134#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
164#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
165
166#define IVG7 7
167#define IVG8 8
168#define IVG9 9
169#define IVG10 10
170#define IVG11 11
171#define IVG12 12
172#define IVG13 13
173#define IVG14 14
174#define IVG15 15
175 135
176/* IAR0 BIT FIELDS */ 136/* IAR0 BIT FIELDS */
177#define IRQ_PLL_WAKEUP_POS 0 137#define IRQ_PLL_WAKEUP_POS 0
178#define IRQ_DMA0_ERROR_POS 4 138#define IRQ_DMA0_ERROR_POS 4
179#define IRQ_DMAR0_BLK_POS 8 139#define IRQ_DMAR0_BLK_POS 8
180#define IRQ_DMAR1_BLK_POS 12 140#define IRQ_DMAR1_BLK_POS 12
181#define IRQ_DMAR0_OVR_POS 16 141#define IRQ_DMAR0_OVR_POS 16
182#define IRQ_DMAR1_OVR_POS 20 142#define IRQ_DMAR1_OVR_POS 20
183#define IRQ_PPI_ERROR_POS 24 143#define IRQ_PPI_ERROR_POS 24
184#define IRQ_MAC_ERROR_POS 28 144#define IRQ_MAC_ERROR_POS 28
185 145
186/* IAR1 BIT FIELDS */ 146/* IAR1 BIT FIELDS */
187#define IRQ_SPORT0_ERROR_POS 0 147#define IRQ_SPORT0_ERROR_POS 0
188#define IRQ_SPORT1_ERROR_POS 4 148#define IRQ_SPORT1_ERROR_POS 4
189#define IRQ_UART0_ERROR_POS 16 149#define IRQ_UART0_ERROR_POS 16
190#define IRQ_UART1_ERROR_POS 20 150#define IRQ_UART1_ERROR_POS 20
191#define IRQ_RTC_POS 24 151#define IRQ_RTC_POS 24
192#define IRQ_PPI_POS 28 152#define IRQ_PPI_POS 28
193 153
194/* IAR2 BIT FIELDS */ 154/* IAR2 BIT FIELDS */
195#define IRQ_SPORT0_RX_POS 0 155#define IRQ_SPORT0_RX_POS 0
196#define IRQ_SPORT0_TX_POS 4 156#define IRQ_SPORT0_TX_POS 4
197#define IRQ_SPORT1_RX_POS 8 157#define IRQ_SPORT1_RX_POS 8
198#define IRQ_SPORT1_TX_POS 12 158#define IRQ_SPORT1_TX_POS 12
199#define IRQ_TWI_POS 16 159#define IRQ_TWI_POS 16
200#define IRQ_SPI_POS 20 160#define IRQ_SPI_POS 20
201#define IRQ_UART0_RX_POS 24 161#define IRQ_UART0_RX_POS 24
202#define IRQ_UART0_TX_POS 28 162#define IRQ_UART0_TX_POS 28
203 163
204/* IAR3 BIT FIELDS */ 164/* IAR3 BIT FIELDS */
205#define IRQ_UART1_RX_POS 0 165#define IRQ_UART1_RX_POS 0
206#define IRQ_UART1_TX_POS 4 166#define IRQ_UART1_TX_POS 4
207#define IRQ_OPTSEC_POS 8 167#define IRQ_OPTSEC_POS 8
208#define IRQ_CNT_POS 12 168#define IRQ_CNT_POS 12
209#define IRQ_MAC_RX_POS 16 169#define IRQ_MAC_RX_POS 16
210#define IRQ_PORTH_INTA_POS 20 170#define IRQ_PORTH_INTA_POS 20
211#define IRQ_MAC_TX_POS 24 171#define IRQ_MAC_TX_POS 24
212#define IRQ_PORTH_INTB_POS 28 172#define IRQ_PORTH_INTB_POS 28
213 173
214/* IAR4 BIT FIELDS */ 174/* IAR4 BIT FIELDS */
@@ -224,21 +184,21 @@
224/* IAR5 BIT FIELDS */ 184/* IAR5 BIT FIELDS */
225#define IRQ_PORTG_INTA_POS 0 185#define IRQ_PORTG_INTA_POS 0
226#define IRQ_PORTG_INTB_POS 4 186#define IRQ_PORTG_INTB_POS 4
227#define IRQ_MEM_DMA0_POS 8 187#define IRQ_MEM_DMA0_POS 8
228#define IRQ_MEM_DMA1_POS 12 188#define IRQ_MEM_DMA1_POS 12
229#define IRQ_WATCH_POS 16 189#define IRQ_WATCH_POS 16
230#define IRQ_PORTF_INTA_POS 20 190#define IRQ_PORTF_INTA_POS 20
231#define IRQ_PORTF_INTB_POS 24 191#define IRQ_PORTF_INTB_POS 24
232#define IRQ_SPI_ERROR_POS 28 192#define IRQ_SPI_ERROR_POS 28
233 193
234/* IAR6 BIT FIELDS */ 194/* IAR6 BIT FIELDS */
235#define IRQ_NFC_ERROR_POS 0 195#define IRQ_NFC_ERROR_POS 0
236#define IRQ_HDMA_ERROR_POS 4 196#define IRQ_HDMA_ERROR_POS 4
237#define IRQ_HDMA_POS 8 197#define IRQ_HDMA_POS 8
238#define IRQ_USB_EINT_POS 12 198#define IRQ_USB_EINT_POS 12
239#define IRQ_USB_INT0_POS 16 199#define IRQ_USB_INT0_POS 16
240#define IRQ_USB_INT1_POS 20 200#define IRQ_USB_INT1_POS 20
241#define IRQ_USB_INT2_POS 24 201#define IRQ_USB_INT2_POS 24
242#define IRQ_USB_DMA_POS 28 202#define IRQ_USB_DMA_POS 28
243 203
244#endif /* _BF527_IRQ_H_ */ 204#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 78f87218791..72aa59440f8 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -5,13 +5,13 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2010 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List 14 * - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -206,6 +206,10 @@
206#define ANOMALY_05000443 (1) 206#define ANOMALY_05000443 (1)
207/* False Hardware Error when RETI Points to Invalid Memory */ 207/* False Hardware Error when RETI Points to Invalid Memory */
208#define ANOMALY_05000461 (1) 208#define ANOMALY_05000461 (1)
209/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
210#define ANOMALY_05000462 (1)
211/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
212#define ANOMALY_05000471 (1)
209/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 213/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
210#define ANOMALY_05000473 (1) 214#define ANOMALY_05000473 (1)
211/* Possible Lockup Condition whem Modifying PLL from External Memory */ 215/* Possible Lockup Condition whem Modifying PLL from External Memory */
@@ -351,12 +355,14 @@
351#define ANOMALY_05000362 (1) 355#define ANOMALY_05000362 (1)
352#define ANOMALY_05000364 (0) 356#define ANOMALY_05000364 (0)
353#define ANOMALY_05000380 (0) 357#define ANOMALY_05000380 (0)
358#define ANOMALY_05000383 (0)
354#define ANOMALY_05000386 (1) 359#define ANOMALY_05000386 (1)
355#define ANOMALY_05000389 (0) 360#define ANOMALY_05000389 (0)
356#define ANOMALY_05000412 (0) 361#define ANOMALY_05000412 (0)
357#define ANOMALY_05000430 (0) 362#define ANOMALY_05000430 (0)
358#define ANOMALY_05000432 (0) 363#define ANOMALY_05000432 (0)
359#define ANOMALY_05000435 (0) 364#define ANOMALY_05000435 (0)
365#define ANOMALY_05000440 (0)
360#define ANOMALY_05000447 (0) 366#define ANOMALY_05000447 (0)
361#define ANOMALY_05000448 (0) 367#define ANOMALY_05000448 (0)
362#define ANOMALY_05000456 (0) 368#define ANOMALY_05000456 (0)
@@ -364,6 +370,7 @@
364#define ANOMALY_05000465 (0) 370#define ANOMALY_05000465 (0)
365#define ANOMALY_05000467 (0) 371#define ANOMALY_05000467 (0)
366#define ANOMALY_05000474 (0) 372#define ANOMALY_05000474 (0)
373#define ANOMALY_05000480 (0)
367#define ANOMALY_05000485 (0) 374#define ANOMALY_05000485 (0)
368 375
369#endif 376#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
index 1f7e9765d95..70973375414 100644
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -7,83 +7,36 @@
7#ifndef _BF533_IRQ_H_ 7#ifndef _BF533_IRQ_H_
8#define _BF533_IRQ_H_ 8#define _BF533_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions
12 Event Source Core Event Name
13Core Emulation **
14 Events (highest priority) EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21 PLL Wakeup Interrupt IVG7 7
22 DMA Error (generic) IVG7 8
23 PPI Error Interrupt IVG7 9
24 SPORT0 Error Interrupt IVG7 10
25 SPORT1 Error Interrupt IVG7 11
26 SPI Error Interrupt IVG7 12
27 UART Error Interrupt IVG7 13
28 RTC Interrupt IVG8 14
29 DMA0 Interrupt (PPI) IVG8 15
30 DMA1 (SPORT0 RX) IVG9 16
31 DMA2 (SPORT0 TX) IVG9 17
32 DMA3 (SPORT1 RX) IVG9 18
33 DMA4 (SPORT1 TX) IVG9 19
34 DMA5 (PPI) IVG10 20
35 DMA6 (UART RX) IVG10 21
36 DMA7 (UART TX) IVG10 22
37 Timer0 IVG11 23
38 Timer1 IVG11 24
39 Timer2 IVG11 25
40 PF Interrupt A IVG12 26
41 PF Interrupt B IVG12 27
42 DMA8/9 Interrupt IVG13 28
43 DMA10/11 Interrupt IVG13 29
44 Watchdog Timer IVG13 30
45 11
46 Softirq IVG14 31 12#define NR_PERI_INTS 24
47 System Call --
48 (lowest priority) IVG15 32 *
49 */
50#define SYS_IRQS 31
51#define NR_PERI_INTS 24
52 13
53/* The ABSTRACT IRQ definitions */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
54/** the first seven of the following are fixed, the rest you change if you need to **/ 15#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
55#define IRQ_EMU 0 /*Emulation */ 16#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error Interrupt */
56#define IRQ_RST 1 /*reset */ 17#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
57#define IRQ_NMI 2 /*Non Maskable */ 18#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
58#define IRQ_EVX 3 /*Exception */ 19#define IRQ_SPI_ERROR BFIN_IRQ(5) /* SPI Error Interrupt */
59#define IRQ_UNUSED 4 /*- unused interrupt*/ 20#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART Error Interrupt */
60#define IRQ_HWERR 5 /*Hardware Error */ 21#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
61#define IRQ_CORETMR 6 /*Core timer */ 22#define IRQ_PPI BFIN_IRQ(8) /* DMA0 Interrupt (PPI) */
23#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA1 Interrupt (SPORT0 RX) */
24#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA2 Interrupt (SPORT0 TX) */
25#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA3 Interrupt (SPORT1 RX) */
26#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA4 Interrupt (SPORT1 TX) */
27#define IRQ_SPI BFIN_IRQ(13) /* DMA5 Interrupt (SPI) */
28#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA6 Interrupt (UART RX) */
29#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA7 Interrupt (UART TX) */
30#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
31#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
32#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
33#define IRQ_PROG_INTA BFIN_IRQ(19) /* Programmable Flags A (8) */
34#define IRQ_PROG_INTB BFIN_IRQ(20) /* Programmable Flags B (8) */
35#define IRQ_MEM_DMA0 BFIN_IRQ(21) /* DMA8/9 Interrupt (Memory DMA Stream 0) */
36#define IRQ_MEM_DMA1 BFIN_IRQ(22) /* DMA10/11 Interrupt (Memory DMA Stream 1) */
37#define IRQ_WATCH BFIN_IRQ(23) /* Watch Dog Timer */
62 38
63#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */ 39#define SYS_IRQS 31
64#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
65#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
66#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
67#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
68#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
69#define IRQ_UART0_ERROR 13 /*UART Error Interrupt */
70#define IRQ_RTC 14 /*RTC Interrupt */
71#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
72#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
73#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
74#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
75#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
76#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
77#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */
78#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */
79#define IRQ_TIMER0 23 /*Timer 0 */
80#define IRQ_TIMER1 24 /*Timer 1 */
81#define IRQ_TIMER2 25 /*Timer 2 */
82#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
83#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
84#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
85#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
86#define IRQ_WATCH 30 /*Watch Dog Timer */
87 40
88#define IRQ_PF0 33 41#define IRQ_PF0 33
89#define IRQ_PF1 34 42#define IRQ_PF1 34
@@ -105,46 +58,35 @@ Core Emulation **
105#define GPIO_IRQ_BASE IRQ_PF0 58#define GPIO_IRQ_BASE IRQ_PF0
106 59
107#define NR_MACH_IRQS (IRQ_PF15 + 1) 60#define NR_MACH_IRQS (IRQ_PF15 + 1)
108#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
109
110#define IVG7 7
111#define IVG8 8
112#define IVG9 9
113#define IVG10 10
114#define IVG11 11
115#define IVG12 12
116#define IVG13 13
117#define IVG14 14
118#define IVG15 15
119 61
120/* IAR0 BIT FIELDS*/ 62/* IAR0 BIT FIELDS */
121#define RTC_ERROR_POS 28 63#define RTC_ERROR_POS 28
122#define UART_ERROR_POS 24 64#define UART_ERROR_POS 24
123#define SPORT1_ERROR_POS 20 65#define SPORT1_ERROR_POS 20
124#define SPI_ERROR_POS 16 66#define SPI_ERROR_POS 16
125#define SPORT0_ERROR_POS 12 67#define SPORT0_ERROR_POS 12
126#define PPI_ERROR_POS 8 68#define PPI_ERROR_POS 8
127#define DMA_ERROR_POS 4 69#define DMA_ERROR_POS 4
128#define PLLWAKE_ERROR_POS 0 70#define PLLWAKE_ERROR_POS 0
129 71
130/* IAR1 BIT FIELDS*/ 72/* IAR1 BIT FIELDS */
131#define DMA7_UARTTX_POS 28 73#define DMA7_UARTTX_POS 28
132#define DMA6_UARTRX_POS 24 74#define DMA6_UARTRX_POS 24
133#define DMA5_SPI_POS 20 75#define DMA5_SPI_POS 20
134#define DMA4_SPORT1TX_POS 16 76#define DMA4_SPORT1TX_POS 16
135#define DMA3_SPORT1RX_POS 12 77#define DMA3_SPORT1RX_POS 12
136#define DMA2_SPORT0TX_POS 8 78#define DMA2_SPORT0TX_POS 8
137#define DMA1_SPORT0RX_POS 4 79#define DMA1_SPORT0RX_POS 4
138#define DMA0_PPI_POS 0 80#define DMA0_PPI_POS 0
139 81
140/* IAR2 BIT FIELDS*/ 82/* IAR2 BIT FIELDS */
141#define WDTIMER_POS 28 83#define WDTIMER_POS 28
142#define MEMDMA1_POS 24 84#define MEMDMA1_POS 24
143#define MEMDMA0_POS 20 85#define MEMDMA0_POS 20
144#define PFB_POS 16 86#define PFB_POS 16
145#define PFA_POS 12 87#define PFA_POS 12
146#define TIMER2_POS 8 88#define TIMER2_POS 8
147#define TIMER1_POS 4 89#define TIMER1_POS 4
148#define TIMER0_POS 0 90#define TIMER0_POS 0
149 91
150#endif /* _BF533_IRQ_H_ */ 92#endif
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 3fa335405b3..e16dc456004 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -35,6 +35,7 @@
35#include <asm/reboot.h> 35#include <asm/reboot.h>
36#include <asm/portmux.h> 36#include <asm/portmux.h>
37#include <asm/dpmc.h> 37#include <asm/dpmc.h>
38#include <asm/bfin_sport.h>
38#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE 39#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
39#include <linux/regulator/fixed.h> 40#include <linux/regulator/fixed.h>
40#endif 41#endif
@@ -2585,27 +2586,103 @@ static struct platform_device bfin_dpmc = {
2585 }, 2586 },
2586}; 2587};
2587 2588
2588#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 2589#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
2590 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
2591 defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
2592
2593#define SPORT_REQ(x) \
2594 [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
2595 P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
2596
2597static const u16 bfin_snd_pin[][7] = {
2598 SPORT_REQ(0),
2599 SPORT_REQ(1),
2600};
2601
2602static struct bfin_snd_platform_data bfin_snd_data[] = {
2603 {
2604 .pin_req = &bfin_snd_pin[0][0],
2605 },
2606 {
2607 .pin_req = &bfin_snd_pin[1][0],
2608 },
2609};
2610
2611#define BFIN_SND_RES(x) \
2612 [x] = { \
2613 { \
2614 .start = SPORT##x##_TCR1, \
2615 .end = SPORT##x##_TCR1, \
2616 .flags = IORESOURCE_MEM \
2617 }, \
2618 { \
2619 .start = CH_SPORT##x##_RX, \
2620 .end = CH_SPORT##x##_RX, \
2621 .flags = IORESOURCE_DMA, \
2622 }, \
2623 { \
2624 .start = CH_SPORT##x##_TX, \
2625 .end = CH_SPORT##x##_TX, \
2626 .flags = IORESOURCE_DMA, \
2627 }, \
2628 { \
2629 .start = IRQ_SPORT##x##_ERROR, \
2630 .end = IRQ_SPORT##x##_ERROR, \
2631 .flags = IORESOURCE_IRQ, \
2632 } \
2633 }
2634
2635static struct resource bfin_snd_resources[][4] = {
2636 BFIN_SND_RES(0),
2637 BFIN_SND_RES(1),
2638};
2639
2640static struct platform_device bfin_pcm = {
2641 .name = "bfin-pcm-audio",
2642 .id = -1,
2643};
2644#endif
2645
2646#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
2647static struct platform_device bfin_ad73311_codec_device = {
2648 .name = "ad73311",
2649 .id = -1,
2650};
2651#endif
2652
2653#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
2589static struct platform_device bfin_i2s = { 2654static struct platform_device bfin_i2s = {
2590 .name = "bfin-i2s", 2655 .name = "bfin-i2s",
2591 .id = CONFIG_SND_BF5XX_SPORT_NUM, 2656 .id = CONFIG_SND_BF5XX_SPORT_NUM,
2592 /* TODO: add platform data here */ 2657 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
2658 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
2659 .dev = {
2660 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
2661 },
2593}; 2662};
2594#endif 2663#endif
2595 2664
2596#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) 2665#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
2597static struct platform_device bfin_tdm = { 2666static struct platform_device bfin_tdm = {
2598 .name = "bfin-tdm", 2667 .name = "bfin-tdm",
2599 .id = CONFIG_SND_BF5XX_SPORT_NUM, 2668 .id = CONFIG_SND_BF5XX_SPORT_NUM,
2600 /* TODO: add platform data here */ 2669 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
2670 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
2671 .dev = {
2672 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
2673 },
2601}; 2674};
2602#endif 2675#endif
2603 2676
2604#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) 2677#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
2605static struct platform_device bfin_ac97 = { 2678static struct platform_device bfin_ac97 = {
2606 .name = "bfin-ac97", 2679 .name = "bfin-ac97",
2607 .id = CONFIG_SND_BF5XX_SPORT_NUM, 2680 .id = CONFIG_SND_BF5XX_SPORT_NUM,
2608 /* TODO: add platform data here */ 2681 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
2682 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
2683 .dev = {
2684 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
2685 },
2609}; 2686};
2610#endif 2687#endif
2611 2688
@@ -2796,17 +2873,28 @@ static struct platform_device *stamp_devices[] __initdata = {
2796 &stamp_flash_device, 2873 &stamp_flash_device,
2797#endif 2874#endif
2798 2875
2799#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 2876#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
2877 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
2878 defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
2879 &bfin_pcm,
2880#endif
2881
2882#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
2883 &bfin_ad73311_codec_device,
2884#endif
2885
2886#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
2800 &bfin_i2s, 2887 &bfin_i2s,
2801#endif 2888#endif
2802 2889
2803#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) 2890#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
2804 &bfin_tdm, 2891 &bfin_tdm,
2805#endif 2892#endif
2806 2893
2807#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) 2894#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
2808 &bfin_ac97, 2895 &bfin_ac97,
2809#endif 2896#endif
2897
2810#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE) 2898#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
2811#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \ 2899#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \
2812 defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE) 2900 defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE)
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 43df6afd22a..7f8e5a9f5db 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -5,13 +5,13 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2010 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List 14 * - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -160,12 +160,16 @@
160#define ANOMALY_05000443 (1) 160#define ANOMALY_05000443 (1)
161/* False Hardware Error when RETI Points to Invalid Memory */ 161/* False Hardware Error when RETI Points to Invalid Memory */
162#define ANOMALY_05000461 (1) 162#define ANOMALY_05000461 (1)
163/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
164#define ANOMALY_05000462 (1)
163/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 165/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
164#define ANOMALY_05000473 (1) 166#define ANOMALY_05000473 (1)
165/* Possible Lockup Condition whem Modifying PLL from External Memory */ 167/* Possible Lockup Condition whem Modifying PLL from External Memory */
166#define ANOMALY_05000475 (1) 168#define ANOMALY_05000475 (1)
167/* TESTSET Instruction Cannot Be Interrupted */ 169/* TESTSET Instruction Cannot Be Interrupted */
168#define ANOMALY_05000477 (1) 170#define ANOMALY_05000477 (1)
171/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
172#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
169/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 173/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
170#define ANOMALY_05000481 (1) 174#define ANOMALY_05000481 (1)
171/* IFLUSH sucks at life */ 175/* IFLUSH sucks at life */
@@ -204,6 +208,7 @@
204#define ANOMALY_05000363 (0) 208#define ANOMALY_05000363 (0)
205#define ANOMALY_05000364 (0) 209#define ANOMALY_05000364 (0)
206#define ANOMALY_05000380 (0) 210#define ANOMALY_05000380 (0)
211#define ANOMALY_05000383 (0)
207#define ANOMALY_05000386 (1) 212#define ANOMALY_05000386 (1)
208#define ANOMALY_05000389 (0) 213#define ANOMALY_05000389 (0)
209#define ANOMALY_05000400 (0) 214#define ANOMALY_05000400 (0)
@@ -211,6 +216,7 @@
211#define ANOMALY_05000430 (0) 216#define ANOMALY_05000430 (0)
212#define ANOMALY_05000432 (0) 217#define ANOMALY_05000432 (0)
213#define ANOMALY_05000435 (0) 218#define ANOMALY_05000435 (0)
219#define ANOMALY_05000440 (0)
214#define ANOMALY_05000447 (0) 220#define ANOMALY_05000447 (0)
215#define ANOMALY_05000448 (0) 221#define ANOMALY_05000448 (0)
216#define ANOMALY_05000456 (0) 222#define ANOMALY_05000456 (0)
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 1a6d617c5fc..b6ed8235bda 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -7,193 +7,178 @@
7#ifndef _BF537_IRQ_H_ 7#ifndef _BF537_IRQ_H_
8#define _BF537_IRQ_H_ 8#define _BF537_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions 11
12 * Event Source Core Event Name 12#define NR_PERI_INTS 32
13 * Core Emulation ** 13
14 * Events (highest priority) EMU 0 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
15 * Reset RST 1 15#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
16 * NMI NMI 2 16#define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */
17 * Exception EVX 3 17#define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */
18 * Reserved -- 4 18#define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */
19 * Hardware Error IVHW 5 19#define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */
20 * Core Timer IVTMR 6 20#define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */
21 * ..... 21#define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */
22 * 22#define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */
23 * Softirq IVG14 23#define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */
24 * System Call -- 24#define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */
25 * (lowest priority) IVG15 25#define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */
26 */ 26#define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */
27 27#define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */
28#define SYS_IRQS 39 28#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */
29#define NR_PERI_INTS 32 29#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */
30 30#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */
31/* The ABSTRACT IRQ definitions */ 31#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
32/** the first seven of the following are fixed, the rest you change if you need to **/ 32#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
33#define IRQ_EMU 0 /*Emulation */ 33#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */
34#define IRQ_RST 1 /*reset */ 34#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */
35#define IRQ_NMI 2 /*Non Maskable */ 35#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */
36#define IRQ_EVX 3 /*Exception */ 36#define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */
37#define IRQ_UNUSED 4 /*- unused interrupt*/ 37#define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */
38#define IRQ_HWERR 5 /*Hardware Error */ 38#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */
39#define IRQ_CORETMR 6 /*Core timer */ 39#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */
40 40#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */
41#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */ 41#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */
42#define IRQ_DMA_ERROR 8 /*DMA Error (general) */ 42#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */
43#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */ 43#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
44#define IRQ_RTC 10 /*RTC Interrupt */ 44#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
45#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */ 45#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */
46#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */ 46
47#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */ 47#define SYS_IRQS 39
48#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */ 48
49#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */ 49#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
50#define IRQ_TWI 16 /*TWI Interrupt */ 50#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
51#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */ 51#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
52#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */ 52#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
53#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */ 53#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
54#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */ 54#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
55#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */ 55#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
56#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */ 56#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
57#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */ 57
58#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */ 58#define IRQ_PF0 50
59#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */ 59#define IRQ_PF1 51
60#define IRQ_TIMER0 26 /*Timer 0 */ 60#define IRQ_PF2 52
61#define IRQ_TIMER1 27 /*Timer 1 */ 61#define IRQ_PF3 53
62#define IRQ_TIMER2 28 /*Timer 2 */ 62#define IRQ_PF4 54
63#define IRQ_TIMER3 29 /*Timer 3 */ 63#define IRQ_PF5 55
64#define IRQ_TIMER4 30 /*Timer 4 */ 64#define IRQ_PF6 56
65#define IRQ_TIMER5 31 /*Timer 5 */ 65#define IRQ_PF7 57
66#define IRQ_TIMER6 32 /*Timer 6 */ 66#define IRQ_PF8 58
67#define IRQ_TIMER7 33 /*Timer 7 */ 67#define IRQ_PF9 59
68#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */ 68#define IRQ_PF10 60
69#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ 69#define IRQ_PF11 61
70#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ 70#define IRQ_PF12 62
71#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */ 71#define IRQ_PF13 63
72#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ 72#define IRQ_PF14 64
73#define IRQ_WATCH 38 /*Watch Dog Timer */ 73#define IRQ_PF15 65
74 74
75#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */ 75#define IRQ_PG0 66
76#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */ 76#define IRQ_PG1 67
77#define IRQ_MAC_ERROR 44 /*MAC Status/Error Interrupt */ 77#define IRQ_PG2 68
78#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */ 78#define IRQ_PG3 69
79#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */ 79#define IRQ_PG4 70
80#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */ 80#define IRQ_PG5 71
81#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */ 81#define IRQ_PG6 72
82#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */ 82#define IRQ_PG7 73
83 83#define IRQ_PG8 74
84#define IRQ_PF0 50 84#define IRQ_PG9 75
85#define IRQ_PF1 51 85#define IRQ_PG10 76
86#define IRQ_PF2 52 86#define IRQ_PG11 77
87#define IRQ_PF3 53 87#define IRQ_PG12 78
88#define IRQ_PF4 54 88#define IRQ_PG13 79
89#define IRQ_PF5 55 89#define IRQ_PG14 80
90#define IRQ_PF6 56 90#define IRQ_PG15 81
91#define IRQ_PF7 57 91
92#define IRQ_PF8 58 92#define IRQ_PH0 82
93#define IRQ_PF9 59 93#define IRQ_PH1 83
94#define IRQ_PF10 60 94#define IRQ_PH2 84
95#define IRQ_PF11 61 95#define IRQ_PH3 85
96#define IRQ_PF12 62 96#define IRQ_PH4 86
97#define IRQ_PF13 63 97#define IRQ_PH5 87
98#define IRQ_PF14 64 98#define IRQ_PH6 88
99#define IRQ_PF15 65 99#define IRQ_PH7 89
100 100#define IRQ_PH8 90
101#define IRQ_PG0 66 101#define IRQ_PH9 91
102#define IRQ_PG1 67 102#define IRQ_PH10 92
103#define IRQ_PG2 68 103#define IRQ_PH11 93
104#define IRQ_PG3 69 104#define IRQ_PH12 94
105#define IRQ_PG4 70 105#define IRQ_PH13 95
106#define IRQ_PG5 71 106#define IRQ_PH14 96
107#define IRQ_PG6 72 107#define IRQ_PH15 97
108#define IRQ_PG7 73 108
109#define IRQ_PG8 74 109#define GPIO_IRQ_BASE IRQ_PF0
110#define IRQ_PG9 75 110
111#define IRQ_PG10 76 111#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
112#define IRQ_PG11 77 112#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
113#define IRQ_PG12 78 113#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
114#define IRQ_PG13 79 114#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
115#define IRQ_PG14 80 115#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
116#define IRQ_PG15 81 116#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
117 117#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
118#define IRQ_PH0 82 118#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
119#define IRQ_PH1 83 119
120#define IRQ_PH2 84 120#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */
121#define IRQ_PH3 85 121#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */
122#define IRQ_PH4 86 122
123#define IRQ_PH5 87 123#if 0 /* No Interrupt B support (yet) */
124#define IRQ_PH6 88 124#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */
125#define IRQ_PH7 89 125#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */
126#define IRQ_PH8 90 126#else
127#define IRQ_PH9 91 127#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX
128#define IRQ_PH10 92 128#endif
129#define IRQ_PH11 93 129
130#define IRQ_PH12 94 130#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */
131#define IRQ_PH13 95 131#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */
132#define IRQ_PH14 96 132
133#define IRQ_PH15 97 133#if 0 /* No Interrupt B support (yet) */
134 134#define IRQ_WATCH 112 /* Watchdog Timer */
135#define GPIO_IRQ_BASE IRQ_PF0 135#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */
136 136#else
137#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */ 137#define IRQ_WATCH IRQ_PF_INTB_WATCH
138#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */ 138#endif
139#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */ 139
140#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */ 140#define NR_MACH_IRQS (113 + 1)
141#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */ 141
142#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */ 142/* IAR0 BIT FIELDS */
143#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */ 143#define IRQ_PLL_WAKEUP_POS 0
144#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */ 144#define IRQ_DMA_ERROR_POS 4
145 145#define IRQ_ERROR_POS 8
146#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 146#define IRQ_RTC_POS 12
147#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) 147#define IRQ_PPI_POS 16
148 148#define IRQ_SPORT0_RX_POS 20
149#define IVG7 7 149#define IRQ_SPORT0_TX_POS 24
150#define IVG8 8 150#define IRQ_SPORT1_RX_POS 28
151#define IVG9 9 151
152#define IVG10 10 152/* IAR1 BIT FIELDS */
153#define IVG11 11 153#define IRQ_SPORT1_TX_POS 0
154#define IVG12 12 154#define IRQ_TWI_POS 4
155#define IVG13 13 155#define IRQ_SPI_POS 8
156#define IVG14 14 156#define IRQ_UART0_RX_POS 12
157#define IVG15 15 157#define IRQ_UART0_TX_POS 16
158 158#define IRQ_UART1_RX_POS 20
159/* IAR0 BIT FIELDS*/ 159#define IRQ_UART1_TX_POS 24
160#define IRQ_PLL_WAKEUP_POS 0 160#define IRQ_CAN_RX_POS 28
161#define IRQ_DMA_ERROR_POS 4 161
162#define IRQ_ERROR_POS 8 162/* IAR2 BIT FIELDS */
163#define IRQ_RTC_POS 12 163#define IRQ_CAN_TX_POS 0
164#define IRQ_PPI_POS 16 164#define IRQ_MAC_RX_POS 4
165#define IRQ_SPORT0_RX_POS 20 165#define IRQ_MAC_TX_POS 8
166#define IRQ_SPORT0_TX_POS 24 166#define IRQ_TIMER0_POS 12
167#define IRQ_SPORT1_RX_POS 28 167#define IRQ_TIMER1_POS 16
168 168#define IRQ_TIMER2_POS 20
169/* IAR1 BIT FIELDS*/ 169#define IRQ_TIMER3_POS 24
170#define IRQ_SPORT1_TX_POS 0 170#define IRQ_TIMER4_POS 28
171#define IRQ_TWI_POS 4 171
172#define IRQ_SPI_POS 8 172/* IAR3 BIT FIELDS */
173#define IRQ_UART0_RX_POS 12 173#define IRQ_TIMER5_POS 0
174#define IRQ_UART0_TX_POS 16 174#define IRQ_TIMER6_POS 4
175#define IRQ_UART1_RX_POS 20 175#define IRQ_TIMER7_POS 8
176#define IRQ_UART1_TX_POS 24 176#define IRQ_PROG_INTA_POS 12
177#define IRQ_CAN_RX_POS 28 177#define IRQ_PORTG_INTB_POS 16
178 178#define IRQ_MEM_DMA0_POS 20
179/* IAR2 BIT FIELDS*/ 179#define IRQ_MEM_DMA1_POS 24
180#define IRQ_CAN_TX_POS 0 180#define IRQ_WATCH_POS 28
181#define IRQ_MAC_RX_POS 4 181
182#define IRQ_MAC_TX_POS 8 182#define init_mach_irq init_mach_irq
183#define IRQ_TIMER0_POS 12 183
184#define IRQ_TIMER1_POS 16 184#endif
185#define IRQ_TIMER2_POS 20
186#define IRQ_TIMER3_POS 24
187#define IRQ_TIMER4_POS 28
188
189/* IAR3 BIT FIELDS*/
190#define IRQ_TIMER5_POS 0
191#define IRQ_TIMER6_POS 4
192#define IRQ_TIMER7_POS 8
193#define IRQ_PROG_INTA_POS 12
194#define IRQ_PORTG_INTB_POS 16
195#define IRQ_MEM_DMA0_POS 20
196#define IRQ_MEM_DMA1_POS 24
197#define IRQ_WATCH_POS 28
198
199#endif /* _BF537_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
index f6500622b35..2137a209a22 100644
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ b/arch/blackfin/mach-bf537/ints-priority.c
@@ -10,6 +10,13 @@
10#include <linux/irq.h> 10#include <linux/irq.h>
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12 12
13#include <asm/irq_handler.h>
14#include <asm/bfin5xx_spi.h>
15#include <asm/bfin_sport.h>
16#include <asm/bfin_can.h>
17#include <asm/bfin_dma.h>
18#include <asm/dpmc.h>
19
13void __init program_IAR(void) 20void __init program_IAR(void)
14{ 21{
15 /* Program the IAR0 Register with the configured priority */ 22 /* Program the IAR0 Register with the configured priority */
@@ -51,3 +58,159 @@ void __init program_IAR(void)
51 58
52 SSYNC(); 59 SSYNC();
53} 60}
61
62#define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
63#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
64#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
65#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
66#define UART_ERR_MASK (0x6) /* UART_IIR */
67#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
68
69static int error_int_mask;
70
71static void bf537_generic_error_mask_irq(struct irq_data *d)
72{
73 error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
74 if (!error_int_mask)
75 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
76}
77
78static void bf537_generic_error_unmask_irq(struct irq_data *d)
79{
80 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
81 error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
82}
83
84static struct irq_chip bf537_generic_error_irqchip = {
85 .name = "ERROR",
86 .irq_ack = bfin_ack_noop,
87 .irq_mask_ack = bf537_generic_error_mask_irq,
88 .irq_mask = bf537_generic_error_mask_irq,
89 .irq_unmask = bf537_generic_error_unmask_irq,
90};
91
92static void bf537_demux_error_irq(unsigned int int_err_irq,
93 struct irq_desc *inta_desc)
94{
95 int irq = 0;
96
97#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
98 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
99 irq = IRQ_MAC_ERROR;
100 else
101#endif
102 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
103 irq = IRQ_SPORT0_ERROR;
104 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
105 irq = IRQ_SPORT1_ERROR;
106 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
107 irq = IRQ_PPI_ERROR;
108 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
109 irq = IRQ_CAN_ERROR;
110 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
111 irq = IRQ_SPI_ERROR;
112 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
113 irq = IRQ_UART0_ERROR;
114 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
115 irq = IRQ_UART1_ERROR;
116
117 if (irq) {
118 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
119 bfin_handle_irq(irq);
120 else {
121
122 switch (irq) {
123 case IRQ_PPI_ERROR:
124 bfin_write_PPI_STATUS(PPI_ERR_MASK);
125 break;
126#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
127 case IRQ_MAC_ERROR:
128 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
129 break;
130#endif
131 case IRQ_SPORT0_ERROR:
132 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
133 break;
134
135 case IRQ_SPORT1_ERROR:
136 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
137 break;
138
139 case IRQ_CAN_ERROR:
140 bfin_write_CAN_GIS(CAN_ERR_MASK);
141 break;
142
143 case IRQ_SPI_ERROR:
144 bfin_write_SPI_STAT(SPI_ERR_MASK);
145 break;
146
147 default:
148 break;
149 }
150
151 pr_debug("IRQ %d:"
152 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
153 irq);
154 }
155 } else
156 pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
157 __func__);
158
159}
160
161#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
162static int mac_rx_int_mask;
163
164static void bf537_mac_rx_mask_irq(struct irq_data *d)
165{
166 mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
167 if (!mac_rx_int_mask)
168 bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
169}
170
171static void bf537_mac_rx_unmask_irq(struct irq_data *d)
172{
173 bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
174 mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
175}
176
177static struct irq_chip bf537_mac_rx_irqchip = {
178 .name = "ERROR",
179 .irq_ack = bfin_ack_noop,
180 .irq_mask_ack = bf537_mac_rx_mask_irq,
181 .irq_mask = bf537_mac_rx_mask_irq,
182 .irq_unmask = bf537_mac_rx_unmask_irq,
183};
184
185static void bf537_demux_mac_rx_irq(unsigned int int_irq,
186 struct irq_desc *desc)
187{
188 if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
189 bfin_handle_irq(IRQ_MAC_RX);
190 else
191 bfin_demux_gpio_irq(int_irq, desc);
192}
193#endif
194
195void __init init_mach_irq(void)
196{
197 int irq;
198
199#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
200 /* Clear EMAC Interrupt Status bits so we can demux it later */
201 bfin_write_EMAC_SYSTAT(-1);
202#endif
203
204 irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq);
205 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
206 irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip,
207 handle_level_irq);
208
209#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
210 irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
211 irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
212 irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
213
214 irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
215#endif
216}
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index 8774b481c78..55e7d0712a9 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -5,14 +5,14 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2010 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision H, 07/10/2009; ADSP-BF538/BF538F Blackfin Processor Anomaly List 14 * - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List
15 * - Revision M, 07/10/2009; ADSP-BF539/BF539F Blackfin Processor Anomaly List 15 * - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List
16 */ 16 */
17 17
18#ifndef _MACH_ANOMALY_H_ 18#ifndef _MACH_ANOMALY_H_
@@ -179,6 +179,7 @@
179#define ANOMALY_05000363 (0) 179#define ANOMALY_05000363 (0)
180#define ANOMALY_05000364 (0) 180#define ANOMALY_05000364 (0)
181#define ANOMALY_05000380 (0) 181#define ANOMALY_05000380 (0)
182#define ANOMALY_05000383 (0)
182#define ANOMALY_05000386 (1) 183#define ANOMALY_05000386 (1)
183#define ANOMALY_05000389 (0) 184#define ANOMALY_05000389 (0)
184#define ANOMALY_05000400 (0) 185#define ANOMALY_05000400 (0)
@@ -186,6 +187,7 @@
186#define ANOMALY_05000430 (0) 187#define ANOMALY_05000430 (0)
187#define ANOMALY_05000432 (0) 188#define ANOMALY_05000432 (0)
188#define ANOMALY_05000435 (0) 189#define ANOMALY_05000435 (0)
190#define ANOMALY_05000440 (0)
189#define ANOMALY_05000447 (0) 191#define ANOMALY_05000447 (0)
190#define ANOMALY_05000448 (0) 192#define ANOMALY_05000448 (0)
191#define ANOMALY_05000456 (0) 193#define ANOMALY_05000456 (0)
@@ -193,6 +195,7 @@
193#define ANOMALY_05000465 (0) 195#define ANOMALY_05000465 (0)
194#define ANOMALY_05000467 (0) 196#define ANOMALY_05000467 (0)
195#define ANOMALY_05000474 (0) 197#define ANOMALY_05000474 (0)
198#define ANOMALY_05000480 (0)
196#define ANOMALY_05000485 (0) 199#define ANOMALY_05000485 (0)
197 200
198#endif 201#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
index 7a479d224dc..07ca069d37c 100644
--- a/arch/blackfin/mach-bf538/include/mach/irq.h
+++ b/arch/blackfin/mach-bf538/include/mach/irq.h
@@ -7,38 +7,9 @@
7#ifndef _BF538_IRQ_H_ 7#ifndef _BF538_IRQ_H_
8#define _BF538_IRQ_H_ 8#define _BF538_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions 11
12 Event Source Core Event Name 12#define NR_PERI_INTS (2 * 32)
13 Core Emulation **
14 Events (highest priority) EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21
22 .....
23
24 Software Interrupt 1 IVG14 31
25 Software Interrupt 2 --
26 (lowest priority) IVG15 32 *
27*/
28
29#define NR_PERI_INTS (2 * 32)
30
31/* The ABSTRACT IRQ definitions */
32/** the first seven of the following are fixed, the rest you change if you need to **/
33#define IRQ_EMU 0 /* Emulation */
34#define IRQ_RST 1 /* reset */
35#define IRQ_NMI 2 /* Non Maskable */
36#define IRQ_EVX 3 /* Exception */
37#define IRQ_UNUSED 4 /* - unused interrupt */
38#define IRQ_HWERR 5 /* Hardware Error */
39#define IRQ_CORETMR 6 /* Core timer */
40
41#define BFIN_IRQ(x) ((x) + 7)
42 13
43#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
@@ -91,37 +62,26 @@
91 62
92#define SYS_IRQS BFIN_IRQ(63) /* 70 */ 63#define SYS_IRQS BFIN_IRQ(63) /* 70 */
93 64
94#define IRQ_PF0 71 65#define IRQ_PF0 71
95#define IRQ_PF1 72 66#define IRQ_PF1 72
96#define IRQ_PF2 73 67#define IRQ_PF2 73
97#define IRQ_PF3 74 68#define IRQ_PF3 74
98#define IRQ_PF4 75 69#define IRQ_PF4 75
99#define IRQ_PF5 76 70#define IRQ_PF5 76
100#define IRQ_PF6 77 71#define IRQ_PF6 77
101#define IRQ_PF7 78 72#define IRQ_PF7 78
102#define IRQ_PF8 79 73#define IRQ_PF8 79
103#define IRQ_PF9 80 74#define IRQ_PF9 80
104#define IRQ_PF10 81 75#define IRQ_PF10 81
105#define IRQ_PF11 82 76#define IRQ_PF11 82
106#define IRQ_PF12 83 77#define IRQ_PF12 83
107#define IRQ_PF13 84 78#define IRQ_PF13 84
108#define IRQ_PF14 85 79#define IRQ_PF14 85
109#define IRQ_PF15 86 80#define IRQ_PF15 86
110 81
111#define GPIO_IRQ_BASE IRQ_PF0 82#define GPIO_IRQ_BASE IRQ_PF0
112 83
113#define NR_MACH_IRQS (IRQ_PF15 + 1) 84#define NR_MACH_IRQS (IRQ_PF15 + 1)
114#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
115
116#define IVG7 7
117#define IVG8 8
118#define IVG9 9
119#define IVG10 10
120#define IVG11 11
121#define IVG12 12
122#define IVG13 13
123#define IVG14 14
124#define IVG15 15
125 85
126/* IAR0 BIT FIELDS */ 86/* IAR0 BIT FIELDS */
127#define IRQ_PLL_WAKEUP_POS 0 87#define IRQ_PLL_WAKEUP_POS 0
@@ -184,4 +144,5 @@
184#define IRQ_CAN_TX_POS 0 144#define IRQ_CAN_TX_POS 0
185#define IRQ_MEM1_DMA0_POS 4 145#define IRQ_MEM1_DMA0_POS 4
186#define IRQ_MEM1_DMA1_POS 8 146#define IRQ_MEM1_DMA1_POS 8
187#endif /* _BF538_IRQ_H_ */ 147
148#endif
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 93e19a54a88..311bf9970fe 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -22,6 +22,7 @@
22#include <asm/gpio.h> 22#include <asm/gpio.h>
23#include <asm/nand.h> 23#include <asm/nand.h>
24#include <asm/dpmc.h> 24#include <asm/dpmc.h>
25#include <asm/bfin_sport.h>
25#include <asm/portmux.h> 26#include <asm/portmux.h>
26#include <asm/bfin_sdh.h> 27#include <asm/bfin_sdh.h>
27#include <mach/bf54x_keys.h> 28#include <mach/bf54x_keys.h>
@@ -956,7 +957,15 @@ static struct mtd_partition ezkit_partitions[] = {
956 .offset = MTDPART_OFS_APPEND, 957 .offset = MTDPART_OFS_APPEND,
957 }, { 958 }, {
958 .name = "file system(nor)", 959 .name = "file system(nor)",
959 .size = MTDPART_SIZ_FULL, 960 .size = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4,
961 .offset = MTDPART_OFS_APPEND,
962 }, {
963 .name = "config(nor)",
964 .size = 0x8000 * 3,
965 .offset = MTDPART_OFS_APPEND,
966 }, {
967 .name = "u-boot env(nor)",
968 .size = 0x8000,
960 .offset = MTDPART_OFS_APPEND, 969 .offset = MTDPART_OFS_APPEND,
961 } 970 }
962}; 971};
@@ -1312,27 +1321,110 @@ static struct platform_device bfin_dpmc = {
1312 }, 1321 },
1313}; 1322};
1314 1323
1315#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 1324#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
1325 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
1326 defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1327
1328#define SPORT_REQ(x) \
1329 [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
1330 P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
1331
1332static const u16 bfin_snd_pin[][7] = {
1333 SPORT_REQ(0),
1334 SPORT_REQ(1),
1335};
1336
1337static struct bfin_snd_platform_data bfin_snd_data[] = {
1338 {
1339 .pin_req = &bfin_snd_pin[0][0],
1340 },
1341 {
1342 .pin_req = &bfin_snd_pin[1][0],
1343 },
1344};
1345
1346#define BFIN_SND_RES(x) \
1347 [x] = { \
1348 { \
1349 .start = SPORT##x##_TCR1, \
1350 .end = SPORT##x##_TCR1, \
1351 .flags = IORESOURCE_MEM \
1352 }, \
1353 { \
1354 .start = CH_SPORT##x##_RX, \
1355 .end = CH_SPORT##x##_RX, \
1356 .flags = IORESOURCE_DMA, \
1357 }, \
1358 { \
1359 .start = CH_SPORT##x##_TX, \
1360 .end = CH_SPORT##x##_TX, \
1361 .flags = IORESOURCE_DMA, \
1362 }, \
1363 { \
1364 .start = IRQ_SPORT##x##_ERROR, \
1365 .end = IRQ_SPORT##x##_ERROR, \
1366 .flags = IORESOURCE_IRQ, \
1367 } \
1368 }
1369
1370static struct resource bfin_snd_resources[][4] = {
1371 BFIN_SND_RES(0),
1372 BFIN_SND_RES(1),
1373};
1374
1375static struct platform_device bfin_pcm = {
1376 .name = "bfin-pcm-audio",
1377 .id = -1,
1378};
1379#endif
1380
1381#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
1382static struct platform_device bfin_ad73311_codec_device = {
1383 .name = "ad73311",
1384 .id = -1,
1385};
1386#endif
1387
1388#if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
1389static struct platform_device bfin_ad1980_codec_device = {
1390 .name = "ad1980",
1391 .id = -1,
1392};
1393#endif
1394
1395#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
1316static struct platform_device bfin_i2s = { 1396static struct platform_device bfin_i2s = {
1317 .name = "bfin-i2s", 1397 .name = "bfin-i2s",
1318 .id = CONFIG_SND_BF5XX_SPORT_NUM, 1398 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1319 /* TODO: add platform data here */ 1399 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
1400 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
1401 .dev = {
1402 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
1403 },
1320}; 1404};
1321#endif 1405#endif
1322 1406
1323#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) 1407#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
1324static struct platform_device bfin_tdm = { 1408static struct platform_device bfin_tdm = {
1325 .name = "bfin-tdm", 1409 .name = "bfin-tdm",
1326 .id = CONFIG_SND_BF5XX_SPORT_NUM, 1410 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1327 /* TODO: add platform data here */ 1411 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
1412 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
1413 .dev = {
1414 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
1415 },
1328}; 1416};
1329#endif 1417#endif
1330 1418
1331#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) 1419#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
1332static struct platform_device bfin_ac97 = { 1420static struct platform_device bfin_ac97 = {
1333 .name = "bfin-ac97", 1421 .name = "bfin-ac97",
1334 .id = CONFIG_SND_BF5XX_SPORT_NUM, 1422 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1335 /* TODO: add platform data here */ 1423 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
1424 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
1425 .dev = {
1426 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
1427 },
1336}; 1428};
1337#endif 1429#endif
1338 1430
@@ -1450,6 +1542,16 @@ static struct platform_device *ezkit_devices[] __initdata = {
1450 &ezkit_flash_device, 1542 &ezkit_flash_device,
1451#endif 1543#endif
1452 1544
1545#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
1546 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
1547 defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1548 &bfin_pcm,
1549#endif
1550
1551#if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
1552 &bfin_ad1980_codec_device,
1553#endif
1554
1453#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 1555#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1454 &bfin_i2s, 1556 &bfin_i2s,
1455#endif 1557#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index ffd0537295a..9e70785bdde 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -5,13 +5,13 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2010 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List 14 * - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -220,6 +220,8 @@
220#define ANOMALY_05000481 (1) 220#define ANOMALY_05000481 (1)
221/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ 221/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
222#define ANOMALY_05000483 (1) 222#define ANOMALY_05000483 (1)
223/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
224#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
223/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ 225/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
224#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2) 226#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
225/* IFLUSH sucks at life */ 227/* IFLUSH sucks at life */
@@ -274,6 +276,8 @@
274#define ANOMALY_05000412 (0) 276#define ANOMALY_05000412 (0)
275#define ANOMALY_05000432 (0) 277#define ANOMALY_05000432 (0)
276#define ANOMALY_05000435 (0) 278#define ANOMALY_05000435 (0)
279#define ANOMALY_05000440 (0)
277#define ANOMALY_05000475 (0) 280#define ANOMALY_05000475 (0)
281#define ANOMALY_05000480 (0)
278 282
279#endif 283#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 7f87787e773..533b8095b54 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -7,38 +7,9 @@
7#ifndef _BF548_IRQ_H_ 7#ifndef _BF548_IRQ_H_
8#define _BF548_IRQ_H_ 8#define _BF548_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions
12 Event Source Core Event Name
13Core Emulation **
14Events (highest priority) EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21
22.....
23
24 Software Interrupt 1 IVG14 31
25 Software Interrupt 2 --
26 (lowest priority) IVG15 32 *
27 */
28
29#define NR_PERI_INTS (32 * 3)
30
31/* The ABSTRACT IRQ definitions */
32/** the first seven of the following are fixed, the rest you change if you need to **/
33#define IRQ_EMU 0 /* Emulation */
34#define IRQ_RST 1 /* reset */
35#define IRQ_NMI 2 /* Non Maskable */
36#define IRQ_EVX 3 /* Exception */
37#define IRQ_UNUSED 4 /* - unused interrupt*/
38#define IRQ_HWERR 5 /* Hardware Error */
39#define IRQ_CORETMR 6 /* Core timer */
40 11
41#define BFIN_IRQ(x) ((x) + 7) 12#define NR_PERI_INTS (3 * 32)
42 13
43#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ 15#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
@@ -311,49 +282,37 @@ Events (highest priority) EMU 0
311#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ 282#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
312#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ 283#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
313 284
314#define GPIO_IRQ_BASE IRQ_PA0 285#define GPIO_IRQ_BASE IRQ_PA0
315 286
316#define NR_MACH_IRQS (IRQ_PJ15 + 1) 287#define NR_MACH_IRQS (IRQ_PJ15 + 1)
317#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
318 288
319/* For compatibility reasons with existing code */ 289/* For compatibility reasons with existing code */
320 290
321#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR 291#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
322#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR 292#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
323#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR 293#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
324#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR 294#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
325#define IRQ_SPI0_ERR IRQ_SPI0_ERROR 295#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
326#define IRQ_UART0_ERR IRQ_UART0_ERROR 296#define IRQ_UART0_ERR IRQ_UART0_ERROR
327#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR 297#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
328#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR 298#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
329#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR 299#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
330#define IRQ_SPI1_ERR IRQ_SPI1_ERROR 300#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
331#define IRQ_SPI2_ERR IRQ_SPI2_ERROR 301#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
332#define IRQ_UART1_ERR IRQ_UART1_ERROR 302#define IRQ_UART1_ERR IRQ_UART1_ERROR
333#define IRQ_UART2_ERR IRQ_UART2_ERROR 303#define IRQ_UART2_ERR IRQ_UART2_ERROR
334#define IRQ_CAN0_ERR IRQ_CAN0_ERROR 304#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
335#define IRQ_MXVR_ERR IRQ_MXVR_ERROR 305#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
336#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR 306#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
337#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR 307#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
338#define IRQ_UART3_ERR IRQ_UART3_ERROR 308#define IRQ_UART3_ERR IRQ_UART3_ERROR
339#define IRQ_HOST_ERR IRQ_HOST_ERROR 309#define IRQ_HOST_ERR IRQ_HOST_ERROR
340#define IRQ_PIXC_ERR IRQ_PIXC_ERROR 310#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
341#define IRQ_NFC_ERR IRQ_NFC_ERROR 311#define IRQ_NFC_ERR IRQ_NFC_ERROR
342#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR 312#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
343#define IRQ_CAN1_ERR IRQ_CAN1_ERROR 313#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
344#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR 314#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
345 315
346
347#define IVG7 7
348#define IVG8 8
349#define IVG9 9
350#define IVG10 10
351#define IVG11 11
352#define IVG12 12
353#define IVG13 13
354#define IVG14 14
355#define IVG15 15
356
357/* IAR0 BIT FIELDS */ 316/* IAR0 BIT FIELDS */
358#define IRQ_PLL_WAKEUP_POS 0 317#define IRQ_PLL_WAKEUP_POS 0
359#define IRQ_DMAC0_ERR_POS 4 318#define IRQ_DMAC0_ERR_POS 4
@@ -492,4 +451,4 @@ struct bfin_pint_regs {
492 451
493#endif 452#endif
494 453
495#endif /* _BF548_IRQ_H_ */ 454#endif
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index f667e770419..5067984a62e 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -247,7 +247,15 @@ static struct mtd_partition ezkit_partitions[] = {
247 .offset = MTDPART_OFS_APPEND, 247 .offset = MTDPART_OFS_APPEND,
248 }, { 248 }, {
249 .name = "file system(nor)", 249 .name = "file system(nor)",
250 .size = MTDPART_SIZ_FULL, 250 .size = 0x800000 - 0x40000 - 0x1C0000 - 0x2000 * 8,
251 .offset = MTDPART_OFS_APPEND,
252 }, {
253 .name = "config(nor)",
254 .size = 0x2000 * 7,
255 .offset = MTDPART_OFS_APPEND,
256 }, {
257 .name = "u-boot env(nor)",
258 .size = 0x2000,
251 .offset = MTDPART_OFS_APPEND, 259 .offset = MTDPART_OFS_APPEND,
252 } 260 }
253}; 261};
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 6a3499b0209..22b5ab77302 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -5,13 +5,13 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2010 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List 14 * - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -290,12 +290,18 @@
290#define ANOMALY_05000428 (__SILICON_REVISION__ > 3) 290#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
291/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 291/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
292#define ANOMALY_05000443 (1) 292#define ANOMALY_05000443 (1)
293/* SCKELOW Feature Is Not Functional */
294#define ANOMALY_05000458 (1)
293/* False Hardware Error when RETI Points to Invalid Memory */ 295/* False Hardware Error when RETI Points to Invalid Memory */
294#define ANOMALY_05000461 (1) 296#define ANOMALY_05000461 (1)
297/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
298#define ANOMALY_05000462 (1)
299/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
300#define ANOMALY_05000471 (1)
295/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 301/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
296#define ANOMALY_05000473 (1) 302#define ANOMALY_05000473 (1)
297/* Possible Lockup Condition whem Modifying PLL from External Memory */ 303/* Possible Lockup Condition whem Modifying PLL from External Memory */
298#define ANOMALY_05000475 (__SILICON_REVISION__ < 4) 304#define ANOMALY_05000475 (1)
299/* TESTSET Instruction Cannot Be Interrupted */ 305/* TESTSET Instruction Cannot Be Interrupted */
300#define ANOMALY_05000477 (1) 306#define ANOMALY_05000477 (1)
301/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 307/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
@@ -314,12 +320,14 @@
314#define ANOMALY_05000353 (1) 320#define ANOMALY_05000353 (1)
315#define ANOMALY_05000364 (0) 321#define ANOMALY_05000364 (0)
316#define ANOMALY_05000380 (0) 322#define ANOMALY_05000380 (0)
323#define ANOMALY_05000383 (0)
317#define ANOMALY_05000386 (1) 324#define ANOMALY_05000386 (1)
318#define ANOMALY_05000389 (0) 325#define ANOMALY_05000389 (0)
319#define ANOMALY_05000400 (0) 326#define ANOMALY_05000400 (0)
320#define ANOMALY_05000430 (0) 327#define ANOMALY_05000430 (0)
321#define ANOMALY_05000432 (0) 328#define ANOMALY_05000432 (0)
322#define ANOMALY_05000435 (0) 329#define ANOMALY_05000435 (0)
330#define ANOMALY_05000440 (0)
323#define ANOMALY_05000447 (0) 331#define ANOMALY_05000447 (0)
324#define ANOMALY_05000448 (0) 332#define ANOMALY_05000448 (0)
325#define ANOMALY_05000456 (0) 333#define ANOMALY_05000456 (0)
@@ -327,6 +335,7 @@
327#define ANOMALY_05000465 (0) 335#define ANOMALY_05000465 (0)
328#define ANOMALY_05000467 (0) 336#define ANOMALY_05000467 (0)
329#define ANOMALY_05000474 (0) 337#define ANOMALY_05000474 (0)
338#define ANOMALY_05000480 (0)
330#define ANOMALY_05000485 (0) 339#define ANOMALY_05000485 (0)
331 340
332#endif 341#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h
index c95566ade51..d6998520f70 100644
--- a/arch/blackfin/mach-bf561/include/mach/irq.h
+++ b/arch/blackfin/mach-bf561/include/mach/irq.h
@@ -7,212 +7,98 @@
7#ifndef _BF561_IRQ_H_ 7#ifndef _BF561_IRQ_H_
8#define _BF561_IRQ_H_ 8#define _BF561_IRQ_H_
9 9
10/*********************************************************************** 10#include <mach-common/irq.h>
11 * Interrupt source definitions: 11
12 Event Source Core Event Name IRQ No 12#define NR_PERI_INTS (2 * 32)
13 (highest priority) 13
14 Emulation Events EMU 0 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
15 Reset RST 1 15#define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */
16 NMI NMI 2 16#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
17 Exception EVX 3 17#define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */
18 Reserved -- 4 18#define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */
19 Hardware Error IVHW 5 19#define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */
20 Core Timer IVTMR 6 * 20#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
21 21#define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */
22 PLL Wakeup Interrupt IVG7 7 22#define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */
23 DMA1 Error (generic) IVG7 8 23#define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */
24 DMA2 Error (generic) IVG7 9 24#define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */
25 IMDMA Error (generic) IVG7 10 25#define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */
26 PPI1 Error Interrupt IVG7 11 26#define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */
27 PPI2 Error Interrupt IVG7 12 27#define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */
28 SPORT0 Error Interrupt IVG7 13 28#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
29 SPORT1 Error Interrupt IVG7 14 29#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
30 SPI Error Interrupt IVG7 15 30#define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */
31 UART Error Interrupt IVG7 16 31#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
32 Reserved Interrupt IVG7 17 32#define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */
33 33#define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */
34 DMA1 0 Interrupt(PPI1) IVG8 18 34#define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */
35 DMA1 1 Interrupt(PPI2) IVG8 19 35#define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */
36 DMA1 2 Interrupt IVG8 20 36#define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */
37 DMA1 3 Interrupt IVG8 21 37#define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */
38 DMA1 4 Interrupt IVG8 22 38#define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */
39 DMA1 5 Interrupt IVG8 23 39#define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */
40 DMA1 6 Interrupt IVG8 24 40#define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */
41 DMA1 7 Interrupt IVG8 25 41#define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */
42 DMA1 8 Interrupt IVG8 26 42#define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */
43 DMA1 9 Interrupt IVG8 27 43#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
44 DMA1 10 Interrupt IVG8 28 44#define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */
45 DMA1 11 Interrupt IVG8 29 45#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
46 46#define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */
47 DMA2 0 (SPORT0 RX) IVG9 30 47#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
48 DMA2 1 (SPORT0 TX) IVG9 31 48#define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */
49 DMA2 2 (SPORT1 RX) IVG9 32 49#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
50 DMA2 3 (SPORT2 TX) IVG9 33 50#define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */
51 DMA2 4 (SPI) IVG9 34 51#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
52 DMA2 5 (UART RX) IVG9 35 52#define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */
53 DMA2 6 (UART TX) IVG9 36 53#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
54 DMA2 7 Interrupt IVG9 37 54#define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */
55 DMA2 8 Interrupt IVG9 38 55#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
56 DMA2 9 Interrupt IVG9 39 56#define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */
57 DMA2 10 Interrupt IVG9 40 57#define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */
58 DMA2 11 Interrupt IVG9 41 58#define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */
59 59#define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */
60 TIMER 0 Interrupt IVG10 42 60#define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */
61 TIMER 1 Interrupt IVG10 43 61#define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */
62 TIMER 2 Interrupt IVG10 44 62#define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */
63 TIMER 3 Interrupt IVG10 45 63#define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */
64 TIMER 4 Interrupt IVG10 46 64#define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */
65 TIMER 5 Interrupt IVG10 47 65#define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */
66 TIMER 6 Interrupt IVG10 48 66#define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */
67 TIMER 7 Interrupt IVG10 49 67#define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */
68 TIMER 8 Interrupt IVG10 50 68#define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */
69 TIMER 9 Interrupt IVG10 51 69#define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */
70 TIMER 10 Interrupt IVG10 52 70#define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */
71 TIMER 11 Interrupt IVG10 53 71#define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */
72 72#define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */
73 Programmable Flags0 A (8) IVG11 54 73#define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */
74 Programmable Flags0 B (8) IVG11 55 74#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
75 Programmable Flags1 A (8) IVG11 56 75#define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */
76 Programmable Flags1 B (8) IVG11 57 76#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
77 Programmable Flags2 A (8) IVG11 58 77#define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */
78 Programmable Flags2 B (8) IVG11 59 78#define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */
79 79#define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */
80 MDMA1 0 write/read INT IVG8 60 80#define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */
81 MDMA1 1 write/read INT IVG8 61 81#define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */
82 82#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
83 MDMA2 0 write/read INT IVG9 62
84 MDMA2 1 write/read INT IVG9 63
85
86 IMDMA 0 write/read INT IVG12 64
87 IMDMA 1 write/read INT IVG12 65
88
89 Watch Dog Timer IVG13 66
90
91 Reserved interrupt IVG7 67
92 Reserved interrupt IVG7 68
93 Supplemental interrupt 0 IVG7 69
94 supplemental interrupt 1 IVG7 70
95
96 Softirq IVG14
97 System Call --
98 (lowest priority) IVG15
99
100 **********************************************************************/
101
102#define SYS_IRQS 71
103#define NR_PERI_INTS 64
104
105/*
106 * The ABSTRACT IRQ definitions
107 * the first seven of the following are fixed,
108 * the rest you change if you need to.
109 */
110/* IVG 0-6*/
111#define IRQ_EMU 0 /* Emulation */
112#define IRQ_RST 1 /* Reset */
113#define IRQ_NMI 2 /* Non Maskable Interrupt */
114#define IRQ_EVX 3 /* Exception */
115#define IRQ_UNUSED 4 /* Reserved interrupt */
116#define IRQ_HWERR 5 /* Hardware Error */
117#define IRQ_CORETMR 6 /* Core timer */
118
119#define IVG_BASE 7
120/* IVG 7 */
121#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
122#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
123#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
124#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */
125#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */
126#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */
127#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
128#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */
129#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */
130#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
131#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
132#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
133#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */
134/* IVG 8 */
135#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
136#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
137#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
138#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */
139#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
140#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */
141#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */
142#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */
143#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */
144#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */
145#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */
146#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */
147#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
148#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
149#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
150/* IVG 9 */
151#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
152#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
153#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
154#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
155#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */
156#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
157#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */
158#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
159#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */
160#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
161#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */
162#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
163#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */
164#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
165#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */
166#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */
167#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
168#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
169#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
170/* IVG 10 */
171#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
172#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
173#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
174#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */
175#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */
176#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */
177#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */
178#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */
179#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */
180#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
181#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
182#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
183/* IVG 11 */
184#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
185#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
186#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
187#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
188#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */
189#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
190#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
191#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
192/* IVG 8 */
193#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
194#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
195#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0 83#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
196#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */ 84#define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */
197#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */ 85#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
198#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1 86#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
199/* IVG 9 */ 87#define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */
200#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
201#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0 88#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
202#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */ 89#define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */
203#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1 90#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
204/* IVG 12 */ 91#define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */
205#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
206#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0 92#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
207#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */ 93#define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */
208#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1 94#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
209/* IVG 13 */ 95#define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */
210#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */ 96#define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */
211/* IVG 7 */ 97#define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */
212#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */ 98#define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */
213#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */ 99#define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */
214#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ 100
215#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */ 101#define SYS_IRQS 71
216 102
217#define IRQ_PF0 73 103#define IRQ_PF0 73
218#define IRQ_PF1 74 104#define IRQ_PF1 74
@@ -266,158 +152,85 @@
266#define GPIO_IRQ_BASE IRQ_PF0 152#define GPIO_IRQ_BASE IRQ_PF0
267 153
268#define NR_MACH_IRQS (IRQ_PF47 + 1) 154#define NR_MACH_IRQS (IRQ_PF47 + 1)
269#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
270
271#define IVG7 7
272#define IVG8 8
273#define IVG9 9
274#define IVG10 10
275#define IVG11 11
276#define IVG12 12
277#define IVG13 13
278#define IVG14 14
279#define IVG15 15
280
281/*
282 * DEFAULT PRIORITIES:
283 */
284
285#define CONFIG_DEF_PLL_WAKEUP 7
286#define CONFIG_DEF_DMA1_ERROR 7
287#define CONFIG_DEF_DMA2_ERROR 7
288#define CONFIG_DEF_IMDMA_ERROR 7
289#define CONFIG_DEF_PPI1_ERROR 7
290#define CONFIG_DEF_PPI2_ERROR 7
291#define CONFIG_DEF_SPORT0_ERROR 7
292#define CONFIG_DEF_SPORT1_ERROR 7
293#define CONFIG_DEF_SPI_ERROR 7
294#define CONFIG_DEF_UART_ERROR 7
295#define CONFIG_DEF_RESERVED_ERROR 7
296#define CONFIG_DEF_DMA1_0 8
297#define CONFIG_DEF_DMA1_1 8
298#define CONFIG_DEF_DMA1_2 8
299#define CONFIG_DEF_DMA1_3 8
300#define CONFIG_DEF_DMA1_4 8
301#define CONFIG_DEF_DMA1_5 8
302#define CONFIG_DEF_DMA1_6 8
303#define CONFIG_DEF_DMA1_7 8
304#define CONFIG_DEF_DMA1_8 8
305#define CONFIG_DEF_DMA1_9 8
306#define CONFIG_DEF_DMA1_10 8
307#define CONFIG_DEF_DMA1_11 8
308#define CONFIG_DEF_DMA2_0 9
309#define CONFIG_DEF_DMA2_1 9
310#define CONFIG_DEF_DMA2_2 9
311#define CONFIG_DEF_DMA2_3 9
312#define CONFIG_DEF_DMA2_4 9
313#define CONFIG_DEF_DMA2_5 9
314#define CONFIG_DEF_DMA2_6 9
315#define CONFIG_DEF_DMA2_7 9
316#define CONFIG_DEF_DMA2_8 9
317#define CONFIG_DEF_DMA2_9 9
318#define CONFIG_DEF_DMA2_10 9
319#define CONFIG_DEF_DMA2_11 9
320#define CONFIG_DEF_TIMER0 10
321#define CONFIG_DEF_TIMER1 10
322#define CONFIG_DEF_TIMER2 10
323#define CONFIG_DEF_TIMER3 10
324#define CONFIG_DEF_TIMER4 10
325#define CONFIG_DEF_TIMER5 10
326#define CONFIG_DEF_TIMER6 10
327#define CONFIG_DEF_TIMER7 10
328#define CONFIG_DEF_TIMER8 10
329#define CONFIG_DEF_TIMER9 10
330#define CONFIG_DEF_TIMER10 10
331#define CONFIG_DEF_TIMER11 10
332#define CONFIG_DEF_PROG0_INTA 11
333#define CONFIG_DEF_PROG0_INTB 11
334#define CONFIG_DEF_PROG1_INTA 11
335#define CONFIG_DEF_PROG1_INTB 11
336#define CONFIG_DEF_PROG2_INTA 11
337#define CONFIG_DEF_PROG2_INTB 11
338#define CONFIG_DEF_DMA1_WRRD0 8
339#define CONFIG_DEF_DMA1_WRRD1 8
340#define CONFIG_DEF_DMA2_WRRD0 9
341#define CONFIG_DEF_DMA2_WRRD1 9
342#define CONFIG_DEF_IMDMA_WRRD0 12
343#define CONFIG_DEF_IMDMA_WRRD1 12
344#define CONFIG_DEF_WATCH 13
345#define CONFIG_DEF_RESERVED_1 7
346#define CONFIG_DEF_RESERVED_2 7
347#define CONFIG_DEF_SUPPLE_0 7
348#define CONFIG_DEF_SUPPLE_1 7
349 155
350/* IAR0 BIT FIELDS */ 156/* IAR0 BIT FIELDS */
351#define IRQ_PLL_WAKEUP_POS 0 157#define IRQ_PLL_WAKEUP_POS 0
352#define IRQ_DMA1_ERROR_POS 4 158#define IRQ_DMA1_ERROR_POS 4
353#define IRQ_DMA2_ERROR_POS 8 159#define IRQ_DMA2_ERROR_POS 8
354#define IRQ_IMDMA_ERROR_POS 12 160#define IRQ_IMDMA_ERROR_POS 12
355#define IRQ_PPI0_ERROR_POS 16 161#define IRQ_PPI0_ERROR_POS 16
356#define IRQ_PPI1_ERROR_POS 20 162#define IRQ_PPI1_ERROR_POS 20
357#define IRQ_SPORT0_ERROR_POS 24 163#define IRQ_SPORT0_ERROR_POS 24
358#define IRQ_SPORT1_ERROR_POS 28 164#define IRQ_SPORT1_ERROR_POS 28
165
359/* IAR1 BIT FIELDS */ 166/* IAR1 BIT FIELDS */
360#define IRQ_SPI_ERROR_POS 0 167#define IRQ_SPI_ERROR_POS 0
361#define IRQ_UART_ERROR_POS 4 168#define IRQ_UART_ERROR_POS 4
362#define IRQ_RESERVED_ERROR_POS 8 169#define IRQ_RESERVED_ERROR_POS 8
363#define IRQ_DMA1_0_POS 12 170#define IRQ_DMA1_0_POS 12
364#define IRQ_DMA1_1_POS 16 171#define IRQ_DMA1_1_POS 16
365#define IRQ_DMA1_2_POS 20 172#define IRQ_DMA1_2_POS 20
366#define IRQ_DMA1_3_POS 24 173#define IRQ_DMA1_3_POS 24
367#define IRQ_DMA1_4_POS 28 174#define IRQ_DMA1_4_POS 28
175
368/* IAR2 BIT FIELDS */ 176/* IAR2 BIT FIELDS */
369#define IRQ_DMA1_5_POS 0 177#define IRQ_DMA1_5_POS 0
370#define IRQ_DMA1_6_POS 4 178#define IRQ_DMA1_6_POS 4
371#define IRQ_DMA1_7_POS 8 179#define IRQ_DMA1_7_POS 8
372#define IRQ_DMA1_8_POS 12 180#define IRQ_DMA1_8_POS 12
373#define IRQ_DMA1_9_POS 16 181#define IRQ_DMA1_9_POS 16
374#define IRQ_DMA1_10_POS 20 182#define IRQ_DMA1_10_POS 20
375#define IRQ_DMA1_11_POS 24 183#define IRQ_DMA1_11_POS 24
376#define IRQ_DMA2_0_POS 28 184#define IRQ_DMA2_0_POS 28
185
377/* IAR3 BIT FIELDS */ 186/* IAR3 BIT FIELDS */
378#define IRQ_DMA2_1_POS 0 187#define IRQ_DMA2_1_POS 0
379#define IRQ_DMA2_2_POS 4 188#define IRQ_DMA2_2_POS 4
380#define IRQ_DMA2_3_POS 8 189#define IRQ_DMA2_3_POS 8
381#define IRQ_DMA2_4_POS 12 190#define IRQ_DMA2_4_POS 12
382#define IRQ_DMA2_5_POS 16 191#define IRQ_DMA2_5_POS 16
383#define IRQ_DMA2_6_POS 20 192#define IRQ_DMA2_6_POS 20
384#define IRQ_DMA2_7_POS 24 193#define IRQ_DMA2_7_POS 24
385#define IRQ_DMA2_8_POS 28 194#define IRQ_DMA2_8_POS 28
195
386/* IAR4 BIT FIELDS */ 196/* IAR4 BIT FIELDS */
387#define IRQ_DMA2_9_POS 0 197#define IRQ_DMA2_9_POS 0
388#define IRQ_DMA2_10_POS 4 198#define IRQ_DMA2_10_POS 4
389#define IRQ_DMA2_11_POS 8 199#define IRQ_DMA2_11_POS 8
390#define IRQ_TIMER0_POS 12 200#define IRQ_TIMER0_POS 12
391#define IRQ_TIMER1_POS 16 201#define IRQ_TIMER1_POS 16
392#define IRQ_TIMER2_POS 20 202#define IRQ_TIMER2_POS 20
393#define IRQ_TIMER3_POS 24 203#define IRQ_TIMER3_POS 24
394#define IRQ_TIMER4_POS 28 204#define IRQ_TIMER4_POS 28
205
395/* IAR5 BIT FIELDS */ 206/* IAR5 BIT FIELDS */
396#define IRQ_TIMER5_POS 0 207#define IRQ_TIMER5_POS 0
397#define IRQ_TIMER6_POS 4 208#define IRQ_TIMER6_POS 4
398#define IRQ_TIMER7_POS 8 209#define IRQ_TIMER7_POS 8
399#define IRQ_TIMER8_POS 12 210#define IRQ_TIMER8_POS 12
400#define IRQ_TIMER9_POS 16 211#define IRQ_TIMER9_POS 16
401#define IRQ_TIMER10_POS 20 212#define IRQ_TIMER10_POS 20
402#define IRQ_TIMER11_POS 24 213#define IRQ_TIMER11_POS 24
403#define IRQ_PROG0_INTA_POS 28 214#define IRQ_PROG0_INTA_POS 28
215
404/* IAR6 BIT FIELDS */ 216/* IAR6 BIT FIELDS */
405#define IRQ_PROG0_INTB_POS 0 217#define IRQ_PROG0_INTB_POS 0
406#define IRQ_PROG1_INTA_POS 4 218#define IRQ_PROG1_INTA_POS 4
407#define IRQ_PROG1_INTB_POS 8 219#define IRQ_PROG1_INTB_POS 8
408#define IRQ_PROG2_INTA_POS 12 220#define IRQ_PROG2_INTA_POS 12
409#define IRQ_PROG2_INTB_POS 16 221#define IRQ_PROG2_INTB_POS 16
410#define IRQ_DMA1_WRRD0_POS 20 222#define IRQ_DMA1_WRRD0_POS 20
411#define IRQ_DMA1_WRRD1_POS 24 223#define IRQ_DMA1_WRRD1_POS 24
412#define IRQ_DMA2_WRRD0_POS 28 224#define IRQ_DMA2_WRRD0_POS 28
413/* IAR7 BIT FIELDS */
414#define IRQ_DMA2_WRRD1_POS 0
415#define IRQ_IMDMA_WRRD0_POS 4
416#define IRQ_IMDMA_WRRD1_POS 8
417#define IRQ_WDTIMER_POS 12
418#define IRQ_RESERVED_1_POS 16
419#define IRQ_RESERVED_2_POS 20
420#define IRQ_SUPPLE_0_POS 24
421#define IRQ_SUPPLE_1_POS 28
422 225
423#endif /* _BF561_IRQ_H_ */ 226/* IAR7 BIT FIELDS */
227#define IRQ_DMA2_WRRD1_POS 0
228#define IRQ_IMDMA_WRRD0_POS 4
229#define IRQ_IMDMA_WRRD1_POS 8
230#define IRQ_WDTIMER_POS 12
231#define IRQ_RESERVED_1_POS 16
232#define IRQ_RESERVED_2_POS 20
233#define IRQ_SUPPLE_0_POS 24
234#define IRQ_SUPPLE_1_POS 28
235
236#endif
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 7b07740cf68..85abd8be134 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -24,17 +24,23 @@ static DEFINE_SPINLOCK(boot_lock);
24 24
25void __init platform_init_cpus(void) 25void __init platform_init_cpus(void)
26{ 26{
27 cpu_set(0, cpu_possible_map); /* CoreA */ 27 struct cpumask mask;
28 cpu_set(1, cpu_possible_map); /* CoreB */ 28
29 cpumask_set_cpu(0, &mask); /* CoreA */
30 cpumask_set_cpu(1, &mask); /* CoreB */
31 init_cpu_possible(&mask);
29} 32}
30 33
31void __init platform_prepare_cpus(unsigned int max_cpus) 34void __init platform_prepare_cpus(unsigned int max_cpus)
32{ 35{
36 struct cpumask mask;
37
33 bfin_relocate_coreb_l1_mem(); 38 bfin_relocate_coreb_l1_mem();
34 39
35 /* Both cores ought to be present on a bf561! */ 40 /* Both cores ought to be present on a bf561! */
36 cpu_set(0, cpu_present_map); /* CoreA */ 41 cpumask_set_cpu(0, &mask); /* CoreA */
37 cpu_set(1, cpu_present_map); /* CoreB */ 42 cpumask_set_cpu(1, &mask); /* CoreB */
43 init_cpu_present(&mask);
38} 44}
39 45
40int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ 46int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
@@ -62,9 +68,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
62 bfin_write_SICB_IWR1(IWR_DISABLE_ALL); 68 bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
63 SSYNC(); 69 SSYNC();
64 70
65 /* Store CPU-private information to the cpu_data array. */
66 bfin_setup_cpudata(cpu);
67
68 /* We are done with local CPU inits, unblock the boot CPU. */ 71 /* We are done with local CPU inits, unblock the boot CPU. */
69 set_cpu_online(cpu, true); 72 set_cpu_online(cpu, true);
70 spin_lock(&boot_lock); 73 spin_lock(&boot_lock);
diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c
index 5e4112e518a..f5685a496c5 100644
--- a/arch/blackfin/mach-common/dpmc.c
+++ b/arch/blackfin/mach-common/dpmc.c
@@ -85,10 +85,11 @@ static void bfin_wakeup_cpu(void)
85{ 85{
86 unsigned int cpu; 86 unsigned int cpu;
87 unsigned int this_cpu = smp_processor_id(); 87 unsigned int this_cpu = smp_processor_id();
88 cpumask_t mask = cpu_online_map; 88 cpumask_t mask;
89 89
90 cpu_clear(this_cpu, mask); 90 cpumask_copy(&mask, cpu_online_mask);
91 for_each_cpu_mask(cpu, mask) 91 cpumask_clear_cpu(this_cpu, &mask);
92 for_each_cpu(cpu, &mask)
92 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); 93 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
93} 94}
94 95
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 43d9fb195c1..1177369f992 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -19,32 +19,14 @@
19#ifdef CONFIG_IPIPE 19#ifdef CONFIG_IPIPE
20#include <linux/ipipe.h> 20#include <linux/ipipe.h>
21#endif 21#endif
22#ifdef CONFIG_KGDB
23#include <linux/kgdb.h>
24#endif
25#include <asm/traps.h> 22#include <asm/traps.h>
26#include <asm/blackfin.h> 23#include <asm/blackfin.h>
27#include <asm/gpio.h> 24#include <asm/gpio.h>
28#include <asm/irq_handler.h> 25#include <asm/irq_handler.h>
29#include <asm/dpmc.h> 26#include <asm/dpmc.h>
30#include <asm/bfin5xx_spi.h>
31#include <asm/bfin_sport.h>
32#include <asm/bfin_can.h>
33 27
34#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) 28#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
35 29
36#ifdef BF537_FAMILY
37# define BF537_GENERIC_ERROR_INT_DEMUX
38# define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
39# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
40# define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
41# define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
42# define UART_ERR_MASK (0x6) /* UART_IIR */
43# define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
44#else
45# undef BF537_GENERIC_ERROR_INT_DEMUX
46#endif
47
48/* 30/*
49 * NOTES: 31 * NOTES:
50 * - we have separated the physical Hardware interrupt from the 32 * - we have separated the physical Hardware interrupt from the
@@ -63,22 +45,19 @@ unsigned long bfin_irq_flags = 0x1f;
63EXPORT_SYMBOL(bfin_irq_flags); 45EXPORT_SYMBOL(bfin_irq_flags);
64#endif 46#endif
65 47
66/* The number of spurious interrupts */
67atomic_t num_spurious;
68
69#ifdef CONFIG_PM 48#ifdef CONFIG_PM
70unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */ 49unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
71unsigned vr_wakeup; 50unsigned vr_wakeup;
72#endif 51#endif
73 52
74struct ivgx { 53static struct ivgx {
75 /* irq number for request_irq, available in mach-bf5xx/irq.h */ 54 /* irq number for request_irq, available in mach-bf5xx/irq.h */
76 unsigned int irqno; 55 unsigned int irqno;
77 /* corresponding bit in the SIC_ISR register */ 56 /* corresponding bit in the SIC_ISR register */
78 unsigned int isrflag; 57 unsigned int isrflag;
79} ivg_table[NR_PERI_INTS]; 58} ivg_table[NR_PERI_INTS];
80 59
81struct ivg_slice { 60static struct ivg_slice {
82 /* position of first irq in ivg_table for given ivg */ 61 /* position of first irq in ivg_table for given ivg */
83 struct ivgx *ifirst; 62 struct ivgx *ifirst;
84 struct ivgx *istop; 63 struct ivgx *istop;
@@ -125,7 +104,7 @@ static void __init search_IAR(void)
125 * This is for core internal IRQs 104 * This is for core internal IRQs
126 */ 105 */
127 106
128static void bfin_ack_noop(struct irq_data *d) 107void bfin_ack_noop(struct irq_data *d)
129{ 108{
130 /* Dummy function. */ 109 /* Dummy function. */
131} 110}
@@ -154,26 +133,24 @@ static void bfin_core_unmask_irq(struct irq_data *d)
154 return; 133 return;
155} 134}
156 135
157static void bfin_internal_mask_irq(unsigned int irq) 136void bfin_internal_mask_irq(unsigned int irq)
158{ 137{
159 unsigned long flags; 138 unsigned long flags = hard_local_irq_save();
160 139
161#ifdef CONFIG_BF53x 140#ifdef SIC_IMASK0
162 flags = hard_local_irq_save(); 141 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
163 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 142 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
164 ~(1 << SIC_SYSIRQ(irq)));
165#else
166 unsigned mask_bank, mask_bit;
167 flags = hard_local_irq_save();
168 mask_bank = SIC_SYSIRQ(irq) / 32;
169 mask_bit = SIC_SYSIRQ(irq) % 32;
170 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & 143 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
171 ~(1 << mask_bit)); 144 ~(1 << mask_bit));
172#ifdef CONFIG_SMP 145# ifdef CONFIG_SMP
173 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) & 146 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
174 ~(1 << mask_bit)); 147 ~(1 << mask_bit));
148# endif
149#else
150 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
151 ~(1 << SIC_SYSIRQ(irq)));
175#endif 152#endif
176#endif 153
177 hard_local_irq_restore(flags); 154 hard_local_irq_restore(flags);
178} 155}
179 156
@@ -186,33 +163,31 @@ static void bfin_internal_mask_irq_chip(struct irq_data *d)
186static void bfin_internal_unmask_irq_affinity(unsigned int irq, 163static void bfin_internal_unmask_irq_affinity(unsigned int irq,
187 const struct cpumask *affinity) 164 const struct cpumask *affinity)
188#else 165#else
189static void bfin_internal_unmask_irq(unsigned int irq) 166void bfin_internal_unmask_irq(unsigned int irq)
190#endif 167#endif
191{ 168{
192 unsigned long flags; 169 unsigned long flags = hard_local_irq_save();
193 170
194#ifdef CONFIG_BF53x 171#ifdef SIC_IMASK0
195 flags = hard_local_irq_save(); 172 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
196 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 173 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
197 (1 << SIC_SYSIRQ(irq))); 174# ifdef CONFIG_SMP
198#else
199 unsigned mask_bank, mask_bit;
200 flags = hard_local_irq_save();
201 mask_bank = SIC_SYSIRQ(irq) / 32;
202 mask_bit = SIC_SYSIRQ(irq) % 32;
203#ifdef CONFIG_SMP
204 if (cpumask_test_cpu(0, affinity)) 175 if (cpumask_test_cpu(0, affinity))
205#endif 176# endif
206 bfin_write_SIC_IMASK(mask_bank, 177 bfin_write_SIC_IMASK(mask_bank,
207 bfin_read_SIC_IMASK(mask_bank) | 178 bfin_read_SIC_IMASK(mask_bank) |
208 (1 << mask_bit)); 179 (1 << mask_bit));
209#ifdef CONFIG_SMP 180# ifdef CONFIG_SMP
210 if (cpumask_test_cpu(1, affinity)) 181 if (cpumask_test_cpu(1, affinity))
211 bfin_write_SICB_IMASK(mask_bank, 182 bfin_write_SICB_IMASK(mask_bank,
212 bfin_read_SICB_IMASK(mask_bank) | 183 bfin_read_SICB_IMASK(mask_bank) |
213 (1 << mask_bit)); 184 (1 << mask_bit));
185# endif
186#else
187 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
188 (1 << SIC_SYSIRQ(irq)));
214#endif 189#endif
215#endif 190
216 hard_local_irq_restore(flags); 191 hard_local_irq_restore(flags);
217} 192}
218 193
@@ -295,6 +270,8 @@ static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
295{ 270{
296 return bfin_internal_set_wake(d->irq, state); 271 return bfin_internal_set_wake(d->irq, state);
297} 272}
273#else
274# define bfin_internal_set_wake_chip NULL
298#endif 275#endif
299 276
300static struct irq_chip bfin_core_irqchip = { 277static struct irq_chip bfin_core_irqchip = {
@@ -315,12 +292,10 @@ static struct irq_chip bfin_internal_irqchip = {
315#ifdef CONFIG_SMP 292#ifdef CONFIG_SMP
316 .irq_set_affinity = bfin_internal_set_affinity, 293 .irq_set_affinity = bfin_internal_set_affinity,
317#endif 294#endif
318#ifdef CONFIG_PM
319 .irq_set_wake = bfin_internal_set_wake_chip, 295 .irq_set_wake = bfin_internal_set_wake_chip,
320#endif
321}; 296};
322 297
323static void bfin_handle_irq(unsigned irq) 298void bfin_handle_irq(unsigned irq)
324{ 299{
325#ifdef CONFIG_IPIPE 300#ifdef CONFIG_IPIPE
326 struct pt_regs regs; /* Contents not used. */ 301 struct pt_regs regs; /* Contents not used. */
@@ -332,102 +307,6 @@ static void bfin_handle_irq(unsigned irq)
332#endif /* !CONFIG_IPIPE */ 307#endif /* !CONFIG_IPIPE */
333} 308}
334 309
335#ifdef BF537_GENERIC_ERROR_INT_DEMUX
336static int error_int_mask;
337
338static void bfin_generic_error_mask_irq(struct irq_data *d)
339{
340 error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
341 if (!error_int_mask)
342 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
343}
344
345static void bfin_generic_error_unmask_irq(struct irq_data *d)
346{
347 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
348 error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
349}
350
351static struct irq_chip bfin_generic_error_irqchip = {
352 .name = "ERROR",
353 .irq_ack = bfin_ack_noop,
354 .irq_mask_ack = bfin_generic_error_mask_irq,
355 .irq_mask = bfin_generic_error_mask_irq,
356 .irq_unmask = bfin_generic_error_unmask_irq,
357};
358
359static void bfin_demux_error_irq(unsigned int int_err_irq,
360 struct irq_desc *inta_desc)
361{
362 int irq = 0;
363
364#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
365 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
366 irq = IRQ_MAC_ERROR;
367 else
368#endif
369 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
370 irq = IRQ_SPORT0_ERROR;
371 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
372 irq = IRQ_SPORT1_ERROR;
373 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
374 irq = IRQ_PPI_ERROR;
375 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
376 irq = IRQ_CAN_ERROR;
377 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
378 irq = IRQ_SPI_ERROR;
379 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
380 irq = IRQ_UART0_ERROR;
381 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
382 irq = IRQ_UART1_ERROR;
383
384 if (irq) {
385 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
386 bfin_handle_irq(irq);
387 else {
388
389 switch (irq) {
390 case IRQ_PPI_ERROR:
391 bfin_write_PPI_STATUS(PPI_ERR_MASK);
392 break;
393#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
394 case IRQ_MAC_ERROR:
395 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
396 break;
397#endif
398 case IRQ_SPORT0_ERROR:
399 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
400 break;
401
402 case IRQ_SPORT1_ERROR:
403 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
404 break;
405
406 case IRQ_CAN_ERROR:
407 bfin_write_CAN_GIS(CAN_ERR_MASK);
408 break;
409
410 case IRQ_SPI_ERROR:
411 bfin_write_SPI_STAT(SPI_ERR_MASK);
412 break;
413
414 default:
415 break;
416 }
417
418 pr_debug("IRQ %d:"
419 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
420 irq);
421 }
422 } else
423 printk(KERN_ERR
424 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
425 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
426 __func__, __FILE__, __LINE__);
427
428}
429#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
430
431#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 310#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
432static int mac_stat_int_mask; 311static int mac_stat_int_mask;
433 312
@@ -468,7 +347,7 @@ static void bfin_mac_status_mask_irq(struct irq_data *d)
468 unsigned int irq = d->irq; 347 unsigned int irq = d->irq;
469 348
470 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT)); 349 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
471#ifdef BF537_GENERIC_ERROR_INT_DEMUX 350#ifdef BF537_FAMILY
472 switch (irq) { 351 switch (irq) {
473 case IRQ_MAC_PHYINT: 352 case IRQ_MAC_PHYINT:
474 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE); 353 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
@@ -487,7 +366,7 @@ static void bfin_mac_status_unmask_irq(struct irq_data *d)
487{ 366{
488 unsigned int irq = d->irq; 367 unsigned int irq = d->irq;
489 368
490#ifdef BF537_GENERIC_ERROR_INT_DEMUX 369#ifdef BF537_FAMILY
491 switch (irq) { 370 switch (irq) {
492 case IRQ_MAC_PHYINT: 371 case IRQ_MAC_PHYINT:
493 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE); 372 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
@@ -505,12 +384,14 @@ static void bfin_mac_status_unmask_irq(struct irq_data *d)
505#ifdef CONFIG_PM 384#ifdef CONFIG_PM
506int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state) 385int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
507{ 386{
508#ifdef BF537_GENERIC_ERROR_INT_DEMUX 387#ifdef BF537_FAMILY
509 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state); 388 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
510#else 389#else
511 return bfin_internal_set_wake(IRQ_MAC_ERROR, state); 390 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
512#endif 391#endif
513} 392}
393#else
394# define bfin_mac_status_set_wake NULL
514#endif 395#endif
515 396
516static struct irq_chip bfin_mac_status_irqchip = { 397static struct irq_chip bfin_mac_status_irqchip = {
@@ -519,13 +400,11 @@ static struct irq_chip bfin_mac_status_irqchip = {
519 .irq_mask_ack = bfin_mac_status_mask_irq, 400 .irq_mask_ack = bfin_mac_status_mask_irq,
520 .irq_mask = bfin_mac_status_mask_irq, 401 .irq_mask = bfin_mac_status_mask_irq,
521 .irq_unmask = bfin_mac_status_unmask_irq, 402 .irq_unmask = bfin_mac_status_unmask_irq,
522#ifdef CONFIG_PM
523 .irq_set_wake = bfin_mac_status_set_wake, 403 .irq_set_wake = bfin_mac_status_set_wake,
524#endif
525}; 404};
526 405
527static void bfin_demux_mac_status_irq(unsigned int int_err_irq, 406void bfin_demux_mac_status_irq(unsigned int int_err_irq,
528 struct irq_desc *inta_desc) 407 struct irq_desc *inta_desc)
529{ 408{
530 int i, irq = 0; 409 int i, irq = 0;
531 u32 status = bfin_read_EMAC_SYSTAT(); 410 u32 status = bfin_read_EMAC_SYSTAT();
@@ -680,29 +559,48 @@ static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
680} 559}
681 560
682#ifdef CONFIG_PM 561#ifdef CONFIG_PM
683int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) 562static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
684{ 563{
685 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state); 564 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
686} 565}
566#else
567# define bfin_gpio_set_wake NULL
687#endif 568#endif
688 569
689static void bfin_demux_gpio_irq(unsigned int inta_irq, 570static void bfin_demux_gpio_block(unsigned int irq)
690 struct irq_desc *desc)
691{ 571{
692 unsigned int i, gpio, mask, irq, search = 0; 572 unsigned int gpio, mask;
573
574 gpio = irq_to_gpio(irq);
575 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
576
577 while (mask) {
578 if (mask & 1)
579 bfin_handle_irq(irq);
580 irq++;
581 mask >>= 1;
582 }
583}
584
585void bfin_demux_gpio_irq(unsigned int inta_irq,
586 struct irq_desc *desc)
587{
588 unsigned int irq;
693 589
694 switch (inta_irq) { 590 switch (inta_irq) {
695#if defined(CONFIG_BF53x) 591#if defined(BF537_FAMILY)
696 case IRQ_PROG_INTA: 592 case IRQ_PF_INTA_PG_INTA:
697 irq = IRQ_PF0; 593 bfin_demux_gpio_block(IRQ_PF0);
698 search = 1; 594 irq = IRQ_PG0;
699 break; 595 break;
700# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) 596 case IRQ_PH_INTA_MAC_RX:
701 case IRQ_MAC_RX:
702 irq = IRQ_PH0; 597 irq = IRQ_PH0;
703 break; 598 break;
704# endif 599#elif defined(BF533_FAMILY)
705#elif defined(CONFIG_BF538) || defined(CONFIG_BF539) 600 case IRQ_PROG_INTA:
601 irq = IRQ_PF0;
602 break;
603#elif defined(BF538_FAMILY)
706 case IRQ_PORTF_INTA: 604 case IRQ_PORTF_INTA:
707 irq = IRQ_PF0; 605 irq = IRQ_PF0;
708 break; 606 break;
@@ -732,31 +630,7 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
732 return; 630 return;
733 } 631 }
734 632
735 if (search) { 633 bfin_demux_gpio_block(irq);
736 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
737 irq += i;
738
739 mask = get_gpiop_data(i) & get_gpiop_maska(i);
740
741 while (mask) {
742 if (mask & 1)
743 bfin_handle_irq(irq);
744 irq++;
745 mask >>= 1;
746 }
747 }
748 } else {
749 gpio = irq_to_gpio(irq);
750 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
751
752 do {
753 if (mask & 1)
754 bfin_handle_irq(irq);
755 irq++;
756 mask >>= 1;
757 } while (mask);
758 }
759
760} 634}
761 635
762#else /* CONFIG_BF54x */ 636#else /* CONFIG_BF54x */
@@ -974,15 +848,11 @@ static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
974} 848}
975 849
976#ifdef CONFIG_PM 850#ifdef CONFIG_PM
977u32 pint_saved_masks[NR_PINT_SYS_IRQS]; 851static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
978u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
979
980int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
981{ 852{
982 u32 pint_irq; 853 u32 pint_irq;
983 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; 854 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
984 u32 bank = PINT_2_BANK(pint_val); 855 u32 bank = PINT_2_BANK(pint_val);
985 u32 pintbit = PINT_BIT(pint_val);
986 856
987 switch (bank) { 857 switch (bank) {
988 case 0: 858 case 0:
@@ -1003,46 +873,14 @@ int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
1003 873
1004 bfin_internal_set_wake(pint_irq, state); 874 bfin_internal_set_wake(pint_irq, state);
1005 875
1006 if (state)
1007 pint_wakeup_masks[bank] |= pintbit;
1008 else
1009 pint_wakeup_masks[bank] &= ~pintbit;
1010
1011 return 0; 876 return 0;
1012} 877}
1013 878#else
1014u32 bfin_pm_setup(void) 879# define bfin_gpio_set_wake NULL
1015{
1016 u32 val, i;
1017
1018 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1019 val = pint[i]->mask_clear;
1020 pint_saved_masks[i] = val;
1021 if (val ^ pint_wakeup_masks[i]) {
1022 pint[i]->mask_clear = val;
1023 pint[i]->mask_set = pint_wakeup_masks[i];
1024 }
1025 }
1026
1027 return 0;
1028}
1029
1030void bfin_pm_restore(void)
1031{
1032 u32 i, val;
1033
1034 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1035 val = pint_saved_masks[i];
1036 if (val ^ pint_wakeup_masks[i]) {
1037 pint[i]->mask_clear = pint[i]->mask_clear;
1038 pint[i]->mask_set = val;
1039 }
1040 }
1041}
1042#endif 880#endif
1043 881
1044static void bfin_demux_gpio_irq(unsigned int inta_irq, 882void bfin_demux_gpio_irq(unsigned int inta_irq,
1045 struct irq_desc *desc) 883 struct irq_desc *desc)
1046{ 884{
1047 u32 bank, pint_val; 885 u32 bank, pint_val;
1048 u32 request, irq; 886 u32 request, irq;
@@ -1091,9 +929,7 @@ static struct irq_chip bfin_gpio_irqchip = {
1091 .irq_set_type = bfin_gpio_irq_type, 929 .irq_set_type = bfin_gpio_irq_type,
1092 .irq_startup = bfin_gpio_irq_startup, 930 .irq_startup = bfin_gpio_irq_startup,
1093 .irq_shutdown = bfin_gpio_irq_shutdown, 931 .irq_shutdown = bfin_gpio_irq_shutdown,
1094#ifdef CONFIG_PM
1095 .irq_set_wake = bfin_gpio_set_wake, 932 .irq_set_wake = bfin_gpio_set_wake,
1096#endif
1097}; 933};
1098 934
1099void __cpuinit init_exception_vectors(void) 935void __cpuinit init_exception_vectors(void)
@@ -1127,12 +963,12 @@ int __init init_arch_irq(void)
1127{ 963{
1128 int irq; 964 int irq;
1129 unsigned long ilat = 0; 965 unsigned long ilat = 0;
966
1130 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ 967 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
1131#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ 968#ifdef SIC_IMASK0
1132 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1133 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); 969 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1134 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); 970 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1135# ifdef CONFIG_BF54x 971# ifdef SIC_IMASK2
1136 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); 972 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1137# endif 973# endif
1138# ifdef CONFIG_SMP 974# ifdef CONFIG_SMP
@@ -1145,11 +981,6 @@ int __init init_arch_irq(void)
1145 981
1146 local_irq_disable(); 982 local_irq_disable();
1147 983
1148#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1149 /* Clear EMAC Interrupt Status bits so we can demux it later */
1150 bfin_write_EMAC_SYSTAT(-1);
1151#endif
1152
1153#ifdef CONFIG_BF54x 984#ifdef CONFIG_BF54x
1154# ifdef CONFIG_PINTx_REASSIGN 985# ifdef CONFIG_PINTx_REASSIGN
1155 pint[0]->assign = CONFIG_PINT0_ASSIGN; 986 pint[0]->assign = CONFIG_PINT0_ASSIGN;
@@ -1168,11 +999,11 @@ int __init init_arch_irq(void)
1168 irq_set_chip(irq, &bfin_internal_irqchip); 999 irq_set_chip(irq, &bfin_internal_irqchip);
1169 1000
1170 switch (irq) { 1001 switch (irq) {
1171#if defined(CONFIG_BF53x) 1002#if defined(BF537_FAMILY)
1003 case IRQ_PH_INTA_MAC_RX:
1004 case IRQ_PF_INTA_PG_INTA:
1005#elif defined(BF533_FAMILY)
1172 case IRQ_PROG_INTA: 1006 case IRQ_PROG_INTA:
1173# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1174 case IRQ_MAC_RX:
1175# endif
1176#elif defined(CONFIG_BF54x) 1007#elif defined(CONFIG_BF54x)
1177 case IRQ_PINT0: 1008 case IRQ_PINT0:
1178 case IRQ_PINT1: 1009 case IRQ_PINT1:
@@ -1186,16 +1017,11 @@ int __init init_arch_irq(void)
1186 case IRQ_PROG0_INTA: 1017 case IRQ_PROG0_INTA:
1187 case IRQ_PROG1_INTA: 1018 case IRQ_PROG1_INTA:
1188 case IRQ_PROG2_INTA: 1019 case IRQ_PROG2_INTA:
1189#elif defined(CONFIG_BF538) || defined(CONFIG_BF539) 1020#elif defined(BF538_FAMILY)
1190 case IRQ_PORTF_INTA: 1021 case IRQ_PORTF_INTA:
1191#endif 1022#endif
1192 irq_set_chained_handler(irq, bfin_demux_gpio_irq); 1023 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1193 break; 1024 break;
1194#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1195 case IRQ_GENERIC_ERROR:
1196 irq_set_chained_handler(irq, bfin_demux_error_irq);
1197 break;
1198#endif
1199#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1025#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1200 case IRQ_MAC_ERROR: 1026 case IRQ_MAC_ERROR:
1201 irq_set_chained_handler(irq, 1027 irq_set_chained_handler(irq,
@@ -1213,11 +1039,10 @@ int __init init_arch_irq(void)
1213 case IRQ_CORETMR: 1039 case IRQ_CORETMR:
1214# ifdef CONFIG_SMP 1040# ifdef CONFIG_SMP
1215 irq_set_handler(irq, handle_percpu_irq); 1041 irq_set_handler(irq, handle_percpu_irq);
1216 break;
1217# else 1042# else
1218 irq_set_handler(irq, handle_simple_irq); 1043 irq_set_handler(irq, handle_simple_irq);
1219 break;
1220# endif 1044# endif
1045 break;
1221#endif 1046#endif
1222 1047
1223#ifdef CONFIG_TICKSOURCE_GPTMR0 1048#ifdef CONFIG_TICKSOURCE_GPTMR0
@@ -1226,26 +1051,17 @@ int __init init_arch_irq(void)
1226 break; 1051 break;
1227#endif 1052#endif
1228 1053
1229#ifdef CONFIG_IPIPE
1230 default: 1054 default:
1055#ifdef CONFIG_IPIPE
1231 irq_set_handler(irq, handle_level_irq); 1056 irq_set_handler(irq, handle_level_irq);
1232 break; 1057#else
1233#else /* !CONFIG_IPIPE */
1234 default:
1235 irq_set_handler(irq, handle_simple_irq); 1058 irq_set_handler(irq, handle_simple_irq);
1059#endif
1236 break; 1060 break;
1237#endif /* !CONFIG_IPIPE */
1238 } 1061 }
1239 } 1062 }
1240 1063
1241#ifdef BF537_GENERIC_ERROR_INT_DEMUX 1064 init_mach_irq();
1242 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1243 irq_set_chip_and_handler(irq, &bfin_generic_error_irqchip,
1244 handle_level_irq);
1245#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1246 irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1247#endif
1248#endif
1249 1065
1250#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1066#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1251 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) 1067 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
@@ -1307,53 +1123,54 @@ int __init init_arch_irq(void)
1307#ifdef CONFIG_DO_IRQ_L1 1123#ifdef CONFIG_DO_IRQ_L1
1308__attribute__((l1_text)) 1124__attribute__((l1_text))
1309#endif 1125#endif
1310void do_irq(int vec, struct pt_regs *fp) 1126static int vec_to_irq(int vec)
1311{ 1127{
1312 if (vec == EVT_IVTMR_P) { 1128 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1313 vec = IRQ_CORETMR; 1129 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1314 } else { 1130 unsigned long sic_status[3];
1315 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; 1131
1316 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; 1132 if (likely(vec == EVT_IVTMR_P))
1317#if defined(SIC_ISR0) 1133 return IRQ_CORETMR;
1318 unsigned long sic_status[3];
1319 1134
1320 if (smp_processor_id()) { 1135#ifdef SIC_ISR
1136 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1137#else
1138 if (smp_processor_id()) {
1321# ifdef SICB_ISR0 1139# ifdef SICB_ISR0
1322 /* This will be optimized out in UP mode. */ 1140 /* This will be optimized out in UP mode. */
1323 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0(); 1141 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1324 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1(); 1142 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1325# endif
1326 } else {
1327 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1328 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1329 }
1330# ifdef SIC_ISR2
1331 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1332# endif 1143# endif
1333 for (;; ivg++) { 1144 } else {
1334 if (ivg >= ivg_stop) { 1145 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1335 atomic_inc(&num_spurious); 1146 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1336 return; 1147 }
1337 } 1148#endif
1338 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) 1149#ifdef SIC_ISR2
1339 break; 1150 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1340 } 1151#endif
1341#else
1342 unsigned long sic_status;
1343
1344 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1345 1152
1346 for (;; ivg++) { 1153 for (;; ivg++) {
1347 if (ivg >= ivg_stop) { 1154 if (ivg >= ivg_stop)
1348 atomic_inc(&num_spurious); 1155 return -1;
1349 return; 1156#ifdef SIC_ISR
1350 } else if (sic_status & ivg->isrflag) 1157 if (sic_status[0] & ivg->isrflag)
1351 break; 1158#else
1352 } 1159 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1353#endif 1160#endif
1354 vec = ivg->irqno; 1161 return ivg->irqno;
1355 } 1162 }
1356 asm_do_IRQ(vec, fp); 1163}
1164
1165#ifdef CONFIG_DO_IRQ_L1
1166__attribute__((l1_text))
1167#endif
1168void do_irq(int vec, struct pt_regs *fp)
1169{
1170 int irq = vec_to_irq(vec);
1171 if (irq == -1)
1172 return;
1173 asm_do_IRQ(irq, fp);
1357} 1174}
1358 1175
1359#ifdef CONFIG_IPIPE 1176#ifdef CONFIG_IPIPE
@@ -1391,40 +1208,9 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1391 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; 1208 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1392 int irq, s = 0; 1209 int irq, s = 0;
1393 1210
1394 if (likely(vec == EVT_IVTMR_P)) 1211 irq = vec_to_irq(vec);
1395 irq = IRQ_CORETMR; 1212 if (irq == -1)
1396 else { 1213 return 0;
1397#if defined(SIC_ISR0)
1398 unsigned long sic_status[3];
1399
1400 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1401 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1402# ifdef SIC_ISR2
1403 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1404# endif
1405 for (;; ivg++) {
1406 if (ivg >= ivg_stop) {
1407 atomic_inc(&num_spurious);
1408 return 0;
1409 }
1410 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1411 break;
1412 }
1413#else
1414 unsigned long sic_status;
1415
1416 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1417
1418 for (;; ivg++) {
1419 if (ivg >= ivg_stop) {
1420 atomic_inc(&num_spurious);
1421 return 0;
1422 } else if (sic_status & ivg->isrflag)
1423 break;
1424 }
1425#endif
1426 irq = ivg->irqno;
1427 }
1428 1214
1429 if (irq == IRQ_SYSTMR) { 1215 if (irq == IRQ_SYSTMR) {
1430#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0) 1216#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 1fbd94c4445..35e7e1eb018 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -25,6 +25,7 @@
25#include <linux/slab.h> 25#include <linux/slab.h>
26#include <asm/atomic.h> 26#include <asm/atomic.h>
27#include <asm/cacheflush.h> 27#include <asm/cacheflush.h>
28#include <asm/irq_handler.h>
28#include <asm/mmu_context.h> 29#include <asm/mmu_context.h>
29#include <asm/pgtable.h> 30#include <asm/pgtable.h>
30#include <asm/pgalloc.h> 31#include <asm/pgalloc.h>
@@ -96,7 +97,7 @@ static void ipi_cpu_stop(unsigned int cpu)
96 dump_stack(); 97 dump_stack();
97 spin_unlock(&stop_lock); 98 spin_unlock(&stop_lock);
98 99
99 cpu_clear(cpu, cpu_online_map); 100 set_cpu_online(cpu, false);
100 101
101 local_irq_disable(); 102 local_irq_disable();
102 103
@@ -146,7 +147,7 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
146 */ 147 */
147 resync_core_dcache(); 148 resync_core_dcache();
148#endif 149#endif
149 cpu_clear(cpu, *msg->call_struct.waitmask); 150 cpumask_clear_cpu(cpu, msg->call_struct.waitmask);
150 } 151 }
151} 152}
152 153
@@ -222,9 +223,10 @@ static inline void smp_send_message(cpumask_t callmap, unsigned long type,
222 struct ipi_message_queue *msg_queue; 223 struct ipi_message_queue *msg_queue;
223 struct ipi_message *msg; 224 struct ipi_message *msg;
224 unsigned long flags, next_msg; 225 unsigned long flags, next_msg;
225 cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */ 226 cpumask_t waitmask; /* waitmask is shared by all cpus */
226 227
227 for_each_cpu_mask(cpu, callmap) { 228 cpumask_copy(&waitmask, &callmap);
229 for_each_cpu(cpu, &callmap) {
228 msg_queue = &per_cpu(ipi_msg_queue, cpu); 230 msg_queue = &per_cpu(ipi_msg_queue, cpu);
229 spin_lock_irqsave(&msg_queue->lock, flags); 231 spin_lock_irqsave(&msg_queue->lock, flags);
230 if (msg_queue->count < BFIN_IPI_MSGQ_LEN) { 232 if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
@@ -246,7 +248,7 @@ static inline void smp_send_message(cpumask_t callmap, unsigned long type,
246 } 248 }
247 249
248 if (wait) { 250 if (wait) {
249 while (!cpus_empty(waitmask)) 251 while (!cpumask_empty(&waitmask))
250 blackfin_dcache_invalidate_range( 252 blackfin_dcache_invalidate_range(
251 (unsigned long)(&waitmask), 253 (unsigned long)(&waitmask),
252 (unsigned long)(&waitmask)); 254 (unsigned long)(&waitmask));
@@ -265,9 +267,9 @@ int smp_call_function(void (*func)(void *info), void *info, int wait)
265 cpumask_t callmap; 267 cpumask_t callmap;
266 268
267 preempt_disable(); 269 preempt_disable();
268 callmap = cpu_online_map; 270 cpumask_copy(&callmap, cpu_online_mask);
269 cpu_clear(smp_processor_id(), callmap); 271 cpumask_clear_cpu(smp_processor_id(), &callmap);
270 if (!cpus_empty(callmap)) 272 if (!cpumask_empty(&callmap))
271 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait); 273 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
272 274
273 preempt_enable(); 275 preempt_enable();
@@ -284,8 +286,8 @@ int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
284 286
285 if (cpu_is_offline(cpu)) 287 if (cpu_is_offline(cpu))
286 return 0; 288 return 0;
287 cpus_clear(callmap); 289 cpumask_clear(&callmap);
288 cpu_set(cpu, callmap); 290 cpumask_set_cpu(cpu, &callmap);
289 291
290 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait); 292 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
291 293
@@ -308,9 +310,9 @@ void smp_send_stop(void)
308 cpumask_t callmap; 310 cpumask_t callmap;
309 311
310 preempt_disable(); 312 preempt_disable();
311 callmap = cpu_online_map; 313 cpumask_copy(&callmap, cpu_online_mask);
312 cpu_clear(smp_processor_id(), callmap); 314 cpumask_clear_cpu(smp_processor_id(), &callmap);
313 if (!cpus_empty(callmap)) 315 if (!cpumask_empty(&callmap))
314 smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0); 316 smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
315 317
316 preempt_enable(); 318 preempt_enable();
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
index dfd304a4a3e..29d98faa1ef 100644
--- a/arch/blackfin/mm/sram-alloc.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/poll.h> 16#include <linux/poll.h>
17#include <linux/proc_fs.h> 17#include <linux/proc_fs.h>
18#include <linux/seq_file.h>
18#include <linux/spinlock.h> 19#include <linux/spinlock.h>
19#include <linux/rtc.h> 20#include <linux/rtc.h>
20#include <linux/slab.h> 21#include <linux/slab.h>
@@ -764,7 +765,7 @@ EXPORT_SYMBOL(sram_alloc_with_lsl);
764/* Need to keep line of output the same. Currently, that is 44 bytes 765/* Need to keep line of output the same. Currently, that is 44 bytes
765 * (including newline). 766 * (including newline).
766 */ 767 */
767static int _sram_proc_read(char *buf, int *len, int count, const char *desc, 768static int _sram_proc_show(struct seq_file *m, const char *desc,
768 struct sram_piece *pfree_head, 769 struct sram_piece *pfree_head,
769 struct sram_piece *pused_head) 770 struct sram_piece *pused_head)
770{ 771{
@@ -773,13 +774,13 @@ static int _sram_proc_read(char *buf, int *len, int count, const char *desc,
773 if (!pfree_head || !pused_head) 774 if (!pfree_head || !pused_head)
774 return -1; 775 return -1;
775 776
776 *len += sprintf(&buf[*len], "--- SRAM %-14s Size PID State \n", desc); 777 seq_printf(m, "--- SRAM %-14s Size PID State \n", desc);
777 778
778 /* search the relevant memory slot */ 779 /* search the relevant memory slot */
779 pslot = pused_head->next; 780 pslot = pused_head->next;
780 781
781 while (pslot != NULL) { 782 while (pslot != NULL) {
782 *len += sprintf(&buf[*len], "%p-%p %10i %5i %-10s\n", 783 seq_printf(m, "%p-%p %10i %5i %-10s\n",
783 pslot->paddr, pslot->paddr + pslot->size, 784 pslot->paddr, pslot->paddr + pslot->size,
784 pslot->size, pslot->pid, "ALLOCATED"); 785 pslot->size, pslot->pid, "ALLOCATED");
785 786
@@ -789,7 +790,7 @@ static int _sram_proc_read(char *buf, int *len, int count, const char *desc,
789 pslot = pfree_head->next; 790 pslot = pfree_head->next;
790 791
791 while (pslot != NULL) { 792 while (pslot != NULL) {
792 *len += sprintf(&buf[*len], "%p-%p %10i %5i %-10s\n", 793 seq_printf(m, "%p-%p %10i %5i %-10s\n",
793 pslot->paddr, pslot->paddr + pslot->size, 794 pslot->paddr, pslot->paddr + pslot->size,
794 pslot->size, pslot->pid, "FREE"); 795 pslot->size, pslot->pid, "FREE");
795 796
@@ -798,54 +799,62 @@ static int _sram_proc_read(char *buf, int *len, int count, const char *desc,
798 799
799 return 0; 800 return 0;
800} 801}
801static int sram_proc_read(char *buf, char **start, off_t offset, int count, 802static int sram_proc_show(struct seq_file *m, void *v)
802 int *eof, void *data)
803{ 803{
804 int len = 0;
805 unsigned int cpu; 804 unsigned int cpu;
806 805
807 for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { 806 for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
808 if (_sram_proc_read(buf, &len, count, "Scratchpad", 807 if (_sram_proc_show(m, "Scratchpad",
809 &per_cpu(free_l1_ssram_head, cpu), &per_cpu(used_l1_ssram_head, cpu))) 808 &per_cpu(free_l1_ssram_head, cpu), &per_cpu(used_l1_ssram_head, cpu)))
810 goto not_done; 809 goto not_done;
811#if L1_DATA_A_LENGTH != 0 810#if L1_DATA_A_LENGTH != 0
812 if (_sram_proc_read(buf, &len, count, "L1 Data A", 811 if (_sram_proc_show(m, "L1 Data A",
813 &per_cpu(free_l1_data_A_sram_head, cpu), 812 &per_cpu(free_l1_data_A_sram_head, cpu),
814 &per_cpu(used_l1_data_A_sram_head, cpu))) 813 &per_cpu(used_l1_data_A_sram_head, cpu)))
815 goto not_done; 814 goto not_done;
816#endif 815#endif
817#if L1_DATA_B_LENGTH != 0 816#if L1_DATA_B_LENGTH != 0
818 if (_sram_proc_read(buf, &len, count, "L1 Data B", 817 if (_sram_proc_show(m, "L1 Data B",
819 &per_cpu(free_l1_data_B_sram_head, cpu), 818 &per_cpu(free_l1_data_B_sram_head, cpu),
820 &per_cpu(used_l1_data_B_sram_head, cpu))) 819 &per_cpu(used_l1_data_B_sram_head, cpu)))
821 goto not_done; 820 goto not_done;
822#endif 821#endif
823#if L1_CODE_LENGTH != 0 822#if L1_CODE_LENGTH != 0
824 if (_sram_proc_read(buf, &len, count, "L1 Instruction", 823 if (_sram_proc_show(m, "L1 Instruction",
825 &per_cpu(free_l1_inst_sram_head, cpu), 824 &per_cpu(free_l1_inst_sram_head, cpu),
826 &per_cpu(used_l1_inst_sram_head, cpu))) 825 &per_cpu(used_l1_inst_sram_head, cpu)))
827 goto not_done; 826 goto not_done;
828#endif 827#endif
829 } 828 }
830#if L2_LENGTH != 0 829#if L2_LENGTH != 0
831 if (_sram_proc_read(buf, &len, count, "L2", &free_l2_sram_head, 830 if (_sram_proc_show(m, "L2", &free_l2_sram_head, &used_l2_sram_head))
832 &used_l2_sram_head))
833 goto not_done; 831 goto not_done;
834#endif 832#endif
835 *eof = 1;
836 not_done: 833 not_done:
837 return len; 834 return 0;
835}
836
837static int sram_proc_open(struct inode *inode, struct file *file)
838{
839 return single_open(file, sram_proc_show, NULL);
838} 840}
839 841
842static const struct file_operations sram_proc_ops = {
843 .open = sram_proc_open,
844 .read = seq_read,
845 .llseek = seq_lseek,
846 .release = single_release,
847};
848
840static int __init sram_proc_init(void) 849static int __init sram_proc_init(void)
841{ 850{
842 struct proc_dir_entry *ptr; 851 struct proc_dir_entry *ptr;
843 ptr = create_proc_entry("sram", S_IFREG | S_IRUGO, NULL); 852
853 ptr = proc_create("sram", S_IRUGO, NULL, &sram_proc_ops);
844 if (!ptr) { 854 if (!ptr) {
845 printk(KERN_WARNING "unable to create /proc/sram\n"); 855 printk(KERN_WARNING "unable to create /proc/sram\n");
846 return -1; 856 return -1;
847 } 857 }
848 ptr->read_proc = sram_proc_read;
849 return 0; 858 return 0;
850} 859}
851late_initcall(sram_proc_init); 860late_initcall(sram_proc_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 20:52:05 -0400