diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2010-07-28 15:59:03 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-08-06 12:55:55 -0400 |
| commit | ba3f5973ce3eb7ef4894ccd3df78c5cb410b17cc (patch) | |
| tree | 45880a04101440fe731ab15bca490886aaf50754 /arch/blackfin | |
| parent | ada091729e8737edc3d455681fda9f745cfd2b63 (diff) | |
Blackfin: TWI: clean up the MMR names
The standard short name for control is CTL and not CTRL. Use TWI0_xxx
even on parts that only have one TWI bus to keep things simple. Drop
all the cdef helpers since the bus driver takes care of everything.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/defBF51x_base.h | 36 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/defBF52x_base.h | 36 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/defBF534.h | 36 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf538/include/mach/cdefBF538.h | 64 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf538/include/mach/defBF539.h | 14 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF544.h | 6 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF547.h | 6 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF54x_base.h | 6 |
8 files changed, 70 insertions, 134 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h index 9241205fb99..543c53da88b 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h | |||
| @@ -458,22 +458,22 @@ | |||
| 458 | 458 | ||
| 459 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | 459 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ |
| 460 | #define TWI0_REGBASE 0xFFC01400 | 460 | #define TWI0_REGBASE 0xFFC01400 |
| 461 | #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ | 461 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
| 462 | #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ | 462 | #define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ |
| 463 | #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ | 463 | #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ |
| 464 | #define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | 464 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
| 465 | #define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | 465 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
| 466 | #define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ | 466 | #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
| 467 | #define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | 467 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
| 468 | #define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | 468 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
| 469 | #define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ | 469 | #define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ |
| 470 | #define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ | 470 | #define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ |
| 471 | #define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ | 471 | #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
| 472 | #define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | 472 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
| 473 | #define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | 473 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
| 474 | #define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | 474 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
| 475 | #define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ | 475 | #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ |
| 476 | #define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ | 476 | #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ |
| 477 | 477 | ||
| 478 | 478 | ||
| 479 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | 479 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ |
| @@ -1319,7 +1319,7 @@ | |||
| 1319 | #define TWI_ENA 0x0080 /* TWI Enable */ | 1319 | #define TWI_ENA 0x0080 /* TWI Enable */ |
| 1320 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ | 1320 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ |
| 1321 | 1321 | ||
| 1322 | /* TWI_SLAVE_CTRL Masks */ | 1322 | /* TWI_SLAVE_CTL Masks */ |
| 1323 | #define SEN 0x0001 /* Slave Enable */ | 1323 | #define SEN 0x0001 /* Slave Enable */ |
| 1324 | #define SADD_LEN 0x0002 /* Slave Address Length */ | 1324 | #define SADD_LEN 0x0002 /* Slave Address Length */ |
| 1325 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ | 1325 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ |
| @@ -1330,7 +1330,7 @@ | |||
| 1330 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ | 1330 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ |
| 1331 | #define GCALL 0x0002 /* General Call Indicator */ | 1331 | #define GCALL 0x0002 /* General Call Indicator */ |
| 1332 | 1332 | ||
| 1333 | /* TWI_MASTER_CTRL Masks */ | 1333 | /* TWI_MASTER_CTL Masks */ |
| 1334 | #define MEN 0x0001 /* Master Mode Enable */ | 1334 | #define MEN 0x0001 /* Master Mode Enable */ |
| 1335 | #define MADD_LEN 0x0002 /* Master Address Length */ | 1335 | #define MADD_LEN 0x0002 /* Master Address Length */ |
| 1336 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ | 1336 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ |
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h index 62083409763..f08dae0d513 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h | |||
| @@ -458,22 +458,22 @@ | |||
| 458 | 458 | ||
| 459 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | 459 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ |
| 460 | #define TWI0_REGBASE 0xFFC01400 | 460 | #define TWI0_REGBASE 0xFFC01400 |
| 461 | #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ | 461 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
| 462 | #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ | 462 | #define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ |
| 463 | #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ | 463 | #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ |
| 464 | #define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | 464 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
| 465 | #define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | 465 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
| 466 | #define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ | 466 | #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
| 467 | #define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | 467 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
| 468 | #define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | 468 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
| 469 | #define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ | 469 | #define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ |
| 470 | #define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ | 470 | #define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ |
| 471 | #define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ | 471 | #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
| 472 | #define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | 472 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
| 473 | #define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | 473 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
| 474 | #define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | 474 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
| 475 | #define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ | 475 | #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ |
| 476 | #define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ | 476 | #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ |
| 477 | 477 | ||
| 478 | 478 | ||
| 479 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | 479 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ |
| @@ -1328,7 +1328,7 @@ | |||
| 1328 | #define TWI_ENA 0x0080 /* TWI Enable */ | 1328 | #define TWI_ENA 0x0080 /* TWI Enable */ |
| 1329 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ | 1329 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ |
| 1330 | 1330 | ||
| 1331 | /* TWI_SLAVE_CTRL Masks */ | 1331 | /* TWI_SLAVE_CTL Masks */ |
| 1332 | #define SEN 0x0001 /* Slave Enable */ | 1332 | #define SEN 0x0001 /* Slave Enable */ |
| 1333 | #define SADD_LEN 0x0002 /* Slave Address Length */ | 1333 | #define SADD_LEN 0x0002 /* Slave Address Length */ |
| 1334 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ | 1334 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ |
| @@ -1339,7 +1339,7 @@ | |||
| 1339 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ | 1339 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ |
| 1340 | #define GCALL 0x0002 /* General Call Indicator */ | 1340 | #define GCALL 0x0002 /* General Call Indicator */ |
| 1341 | 1341 | ||
| 1342 | /* TWI_MASTER_CTRL Masks */ | 1342 | /* TWI_MASTER_CTL Masks */ |
| 1343 | #define MEN 0x0001 /* Master Mode Enable */ | 1343 | #define MEN 0x0001 /* Master Mode Enable */ |
| 1344 | #define MADD_LEN 0x0002 /* Master Address Length */ | 1344 | #define MADD_LEN 0x0002 /* Master Address Length */ |
| 1345 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ | 1345 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ |
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index cf396ea4009..aad61b88737 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h | |||
| @@ -434,22 +434,22 @@ | |||
| 434 | 434 | ||
| 435 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | 435 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ |
| 436 | #define TWI0_REGBASE 0xFFC01400 | 436 | #define TWI0_REGBASE 0xFFC01400 |
| 437 | #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ | 437 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
| 438 | #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ | 438 | #define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ |
| 439 | #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ | 439 | #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ |
| 440 | #define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | 440 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
| 441 | #define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | 441 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
| 442 | #define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ | 442 | #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
| 443 | #define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | 443 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
| 444 | #define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | 444 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
| 445 | #define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ | 445 | #define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ |
| 446 | #define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ | 446 | #define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ |
| 447 | #define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ | 447 | #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
| 448 | #define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | 448 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
| 449 | #define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | 449 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
| 450 | #define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | 450 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
| 451 | #define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ | 451 | #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ |
| 452 | #define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ | 452 | #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ |
| 453 | 453 | ||
| 454 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | 454 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ |
| 455 | #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ | 455 | #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ |
| @@ -1642,7 +1642,7 @@ | |||
| 1642 | #define TWI_ENA 0x0080 /* TWI Enable */ | 1642 | #define TWI_ENA 0x0080 /* TWI Enable */ |
| 1643 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ | 1643 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ |
| 1644 | 1644 | ||
| 1645 | /* TWI_SLAVE_CTRL Masks */ | 1645 | /* TWI_SLAVE_CTL Masks */ |
| 1646 | #define SEN 0x0001 /* Slave Enable */ | 1646 | #define SEN 0x0001 /* Slave Enable */ |
| 1647 | #define SADD_LEN 0x0002 /* Slave Address Length */ | 1647 | #define SADD_LEN 0x0002 /* Slave Address Length */ |
| 1648 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ | 1648 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ |
| @@ -1653,7 +1653,7 @@ | |||
| 1653 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ | 1653 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ |
| 1654 | #define GCALL 0x0002 /* General Call Indicator */ | 1654 | #define GCALL 0x0002 /* General Call Indicator */ |
| 1655 | 1655 | ||
| 1656 | /* TWI_MASTER_CTRL Masks */ | 1656 | /* TWI_MASTER_CTL Masks */ |
| 1657 | #define MEN 0x0001 /* Master Mode Enable */ | 1657 | #define MEN 0x0001 /* Master Mode Enable */ |
| 1658 | #define MADD_LEN 0x0002 /* Master Address Length */ | 1658 | #define MADD_LEN 0x0002 /* Master Address Length */ |
| 1659 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ | 1659 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ |
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h index 401ebd79d0a..66aa722cf6c 100644 --- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h +++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h | |||
| @@ -1293,70 +1293,6 @@ | |||
| 1293 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) | 1293 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) |
| 1294 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) | 1294 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) |
| 1295 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) | 1295 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) |
| 1296 | #define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) | ||
| 1297 | #define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) | ||
| 1298 | #define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) | ||
| 1299 | #define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) | ||
| 1300 | #define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) | ||
| 1301 | #define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) | ||
| 1302 | #define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) | ||
| 1303 | #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) | ||
| 1304 | #define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) | ||
| 1305 | #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) | ||
| 1306 | #define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) | ||
| 1307 | #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) | ||
| 1308 | #define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) | ||
| 1309 | #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) | ||
| 1310 | #define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) | ||
| 1311 | #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) | ||
| 1312 | #define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) | ||
| 1313 | #define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) | ||
| 1314 | #define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) | ||
| 1315 | #define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) | ||
| 1316 | #define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) | ||
| 1317 | #define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) | ||
| 1318 | #define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) | ||
| 1319 | #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) | ||
| 1320 | #define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) | ||
| 1321 | #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) | ||
| 1322 | #define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) | ||
| 1323 | #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) | ||
| 1324 | #define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) | ||
| 1325 | #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) | ||
| 1326 | #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) | ||
| 1327 | #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) | ||
| 1328 | #define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) | ||
| 1329 | #define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) | ||
| 1330 | #define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) | ||
| 1331 | #define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) | ||
| 1332 | #define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) | ||
| 1333 | #define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) | ||
| 1334 | #define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) | ||
| 1335 | #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) | ||
| 1336 | #define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) | ||
| 1337 | #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) | ||
| 1338 | #define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) | ||
| 1339 | #define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) | ||
| 1340 | #define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) | ||
| 1341 | #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) | ||
| 1342 | #define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) | ||
| 1343 | #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) | ||
| 1344 | #define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) | ||
| 1345 | #define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) | ||
| 1346 | #define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) | ||
| 1347 | #define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) | ||
| 1348 | #define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) | ||
| 1349 | #define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) | ||
| 1350 | #define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) | ||
| 1351 | #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) | ||
| 1352 | #define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) | ||
| 1353 | #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) | ||
| 1354 | #define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) | ||
| 1355 | #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) | ||
| 1356 | #define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) | ||
| 1357 | #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) | ||
| 1358 | #define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) | ||
| 1359 | #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) | ||
| 1360 | #define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) | 1296 | #define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) |
| 1361 | #define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) | 1297 | #define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) |
| 1362 | #define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) | 1298 | #define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) |
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h index d7061d9f2a8..b674a1c4aef 100644 --- a/arch/blackfin/mach-bf538/include/mach/defBF539.h +++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h | |||
| @@ -442,15 +442,15 @@ | |||
| 442 | /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ | 442 | /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ |
| 443 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ | 443 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
| 444 | #define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ | 444 | #define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ |
| 445 | #define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */ | 445 | #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ |
| 446 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | 446 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
| 447 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | 447 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
| 448 | #define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */ | 448 | #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
| 449 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | 449 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
| 450 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | 450 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
| 451 | #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ | 451 | #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ |
| 452 | #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ | 452 | #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ |
| 453 | #define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */ | 453 | #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
| 454 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | 454 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
| 455 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | 455 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
| 456 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | 456 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
| @@ -761,15 +761,15 @@ | |||
| 761 | /* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ | 761 | /* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ |
| 762 | #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ | 762 | #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ |
| 763 | #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ | 763 | #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ |
| 764 | #define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */ | 764 | #define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */ |
| 765 | #define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ | 765 | #define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ |
| 766 | #define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ | 766 | #define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ |
| 767 | #define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */ | 767 | #define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */ |
| 768 | #define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ | 768 | #define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ |
| 769 | #define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ | 769 | #define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ |
| 770 | #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ | 770 | #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ |
| 771 | #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ | 771 | #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ |
| 772 | #define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */ | 772 | #define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */ |
| 773 | #define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ | 773 | #define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ |
| 774 | #define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ | 774 | #define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ |
| 775 | #define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ | 775 | #define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ |
| @@ -2401,7 +2401,7 @@ | |||
| 2401 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ | 2401 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ |
| 2402 | #define RCVSERV 0x0080 /* Receive FIFO Service */ | 2402 | #define RCVSERV 0x0080 /* Receive FIFO Service */ |
| 2403 | 2403 | ||
| 2404 | /* TWIx_FIFO_CTRL Masks */ | 2404 | /* TWIx_FIFO_CTL Masks */ |
| 2405 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ | 2405 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ |
| 2406 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ | 2406 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ |
| 2407 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ | 2407 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ |
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h index f916c52a148..e2771094de0 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF544.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h | |||
| @@ -60,15 +60,15 @@ | |||
| 60 | #define TWI1_REGBASE 0xffc02200 | 60 | #define TWI1_REGBASE 0xffc02200 |
| 61 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ | 61 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ |
| 62 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ | 62 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ |
| 63 | #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ | 63 | #define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */ |
| 64 | #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ | 64 | #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ |
| 65 | #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ | 65 | #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ |
| 66 | #define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ | 66 | #define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */ |
| 67 | #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ | 67 | #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ |
| 68 | #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ | 68 | #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ |
| 69 | #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ | 69 | #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ |
| 70 | #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ | 70 | #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ |
| 71 | #define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ | 71 | #define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */ |
| 72 | #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ | 72 | #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ |
| 73 | #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ | 73 | #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ |
| 74 | #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ | 74 | #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ |
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h index 72c343646b2..3d131065f8e 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF547.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h | |||
| @@ -99,15 +99,15 @@ | |||
| 99 | #define TWI1_REGBASE 0xffc02200 | 99 | #define TWI1_REGBASE 0xffc02200 |
| 100 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ | 100 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ |
| 101 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ | 101 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ |
| 102 | #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ | 102 | #define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */ |
| 103 | #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ | 103 | #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ |
| 104 | #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ | 104 | #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ |
| 105 | #define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ | 105 | #define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */ |
| 106 | #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ | 106 | #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ |
| 107 | #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ | 107 | #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ |
| 108 | #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ | 108 | #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ |
| 109 | #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ | 109 | #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ |
| 110 | #define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ | 110 | #define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */ |
| 111 | #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ | 111 | #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ |
| 112 | #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ | 112 | #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ |
| 113 | #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ | 113 | #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ |
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index 54143441af5..01d52fade45 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h | |||
| @@ -105,15 +105,15 @@ | |||
| 105 | #define TWI0_REGBASE 0xffc00700 | 105 | #define TWI0_REGBASE 0xffc00700 |
| 106 | #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ | 106 | #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ |
| 107 | #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ | 107 | #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ |
| 108 | #define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ | 108 | #define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */ |
| 109 | #define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */ | 109 | #define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */ |
| 110 | #define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */ | 110 | #define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */ |
| 111 | #define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */ | 111 | #define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */ |
| 112 | #define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */ | 112 | #define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */ |
| 113 | #define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */ | 113 | #define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */ |
| 114 | #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ | 114 | #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ |
| 115 | #define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */ | 115 | #define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */ |
| 116 | #define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */ | 116 | #define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */ |
| 117 | #define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */ | 117 | #define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */ |
| 118 | #define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */ | 118 | #define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */ |
| 119 | #define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */ | 119 | #define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */ |