diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2009-12-18 13:00:10 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-10-18 02:49:39 -0400 |
| commit | 5e8592dca303fb429d1641c205fe509f4b781ca2 (patch) | |
| tree | 14bbd03eeec15e99bb9ea1aefcb1a953be31159e /arch/blackfin | |
| parent | 5b47bcd48b3bd53c86040321de0d348aadebed87 (diff) | |
spi/bfin_spi: combine duplicate SPI_CTL read/write logic
While combining things, also switch to the proper SPI bit define names.
This lets us punt the rarely used SPI defines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
| -rw-r--r-- | arch/blackfin/include/asm/bfin5xx_spi.h | 68 |
1 files changed, 0 insertions, 68 deletions
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h index 6f011dac378..4223cf08ce8 100644 --- a/arch/blackfin/include/asm/bfin5xx_spi.h +++ b/arch/blackfin/include/asm/bfin5xx_spi.h | |||
| @@ -11,18 +11,6 @@ | |||
| 11 | 11 | ||
| 12 | #define MIN_SPI_BAUD_VAL 2 | 12 | #define MIN_SPI_BAUD_VAL 2 |
| 13 | 13 | ||
| 14 | #define SPI_READ 0 | ||
| 15 | #define SPI_WRITE 1 | ||
| 16 | |||
| 17 | #define SPI_CTRL_OFF 0x0 | ||
| 18 | #define SPI_FLAG_OFF 0x4 | ||
| 19 | #define SPI_STAT_OFF 0x8 | ||
| 20 | #define SPI_TXBUFF_OFF 0xc | ||
| 21 | #define SPI_RXBUFF_OFF 0x10 | ||
| 22 | #define SPI_BAUD_OFF 0x14 | ||
| 23 | #define SPI_SHAW_OFF 0x18 | ||
| 24 | |||
| 25 | |||
| 26 | #define BIT_CTL_ENABLE 0x4000 | 14 | #define BIT_CTL_ENABLE 0x4000 |
| 27 | #define BIT_CTL_OPENDRAIN 0x2000 | 15 | #define BIT_CTL_OPENDRAIN 0x2000 |
| 28 | #define BIT_CTL_MASTER 0x1000 | 16 | #define BIT_CTL_MASTER 0x1000 |
| @@ -53,62 +41,6 @@ | |||
| 53 | #define BIT_STU_SENDOVER 0x0001 | 41 | #define BIT_STU_SENDOVER 0x0001 |
| 54 | #define BIT_STU_RECVFULL 0x0020 | 42 | #define BIT_STU_RECVFULL 0x0020 |
| 55 | 43 | ||
| 56 | #define CFG_SPI_ENABLE 1 | ||
| 57 | #define CFG_SPI_DISABLE 0 | ||
| 58 | |||
| 59 | #define CFG_SPI_OUTENABLE 1 | ||
| 60 | #define CFG_SPI_OUTDISABLE 0 | ||
| 61 | |||
| 62 | #define CFG_SPI_ACTLOW 1 | ||
| 63 | #define CFG_SPI_ACTHIGH 0 | ||
| 64 | |||
| 65 | #define CFG_SPI_PHASESTART 1 | ||
| 66 | #define CFG_SPI_PHASEMID 0 | ||
| 67 | |||
| 68 | #define CFG_SPI_MASTER 1 | ||
| 69 | #define CFG_SPI_SLAVE 0 | ||
| 70 | |||
| 71 | #define CFG_SPI_SENELAST 0 | ||
| 72 | #define CFG_SPI_SENDZERO 1 | ||
| 73 | |||
| 74 | #define CFG_SPI_RCVFLUSH 1 | ||
| 75 | #define CFG_SPI_RCVDISCARD 0 | ||
| 76 | |||
| 77 | #define CFG_SPI_LSBFIRST 1 | ||
| 78 | #define CFG_SPI_MSBFIRST 0 | ||
| 79 | |||
| 80 | #define CFG_SPI_WORDSIZE16 1 | ||
| 81 | #define CFG_SPI_WORDSIZE8 0 | ||
| 82 | |||
| 83 | #define CFG_SPI_MISOENABLE 1 | ||
| 84 | #define CFG_SPI_MISODISABLE 0 | ||
| 85 | |||
| 86 | #define CFG_SPI_READ 0x00 | ||
| 87 | #define CFG_SPI_WRITE 0x01 | ||
| 88 | #define CFG_SPI_DMAREAD 0x02 | ||
| 89 | #define CFG_SPI_DMAWRITE 0x03 | ||
| 90 | |||
| 91 | #define CFG_SPI_CSCLEARALL 0 | ||
| 92 | #define CFG_SPI_CHIPSEL1 1 | ||
| 93 | #define CFG_SPI_CHIPSEL2 2 | ||
| 94 | #define CFG_SPI_CHIPSEL3 3 | ||
| 95 | #define CFG_SPI_CHIPSEL4 4 | ||
| 96 | #define CFG_SPI_CHIPSEL5 5 | ||
| 97 | #define CFG_SPI_CHIPSEL6 6 | ||
| 98 | #define CFG_SPI_CHIPSEL7 7 | ||
| 99 | |||
| 100 | #define CFG_SPI_CS1VALUE 1 | ||
| 101 | #define CFG_SPI_CS2VALUE 2 | ||
| 102 | #define CFG_SPI_CS3VALUE 3 | ||
| 103 | #define CFG_SPI_CS4VALUE 4 | ||
| 104 | #define CFG_SPI_CS5VALUE 5 | ||
| 105 | #define CFG_SPI_CS6VALUE 6 | ||
| 106 | #define CFG_SPI_CS7VALUE 7 | ||
| 107 | |||
| 108 | #define CMD_SPI_SET_BAUDRATE 2 | ||
| 109 | #define CMD_SPI_GET_SYSTEMCLOCK 25 | ||
| 110 | #define CMD_SPI_SET_WRITECONTINUOUS 26 | ||
| 111 | |||
| 112 | #define MAX_CTRL_CS 8 /* cs in spi controller */ | 44 | #define MAX_CTRL_CS 8 /* cs in spi controller */ |
| 113 | 45 | ||
| 114 | /* device.platform_data for SSP controller devices */ | 46 | /* device.platform_data for SSP controller devices */ |