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authorGraf Yang <graf.yang@analog.com>2009-05-06 05:59:11 -0400
committerMike Frysinger <vapier@gentoo.org>2009-06-12 06:11:26 -0400
commitf5879fda09ea98d7aa845a0e0fa7e508452e5f9f (patch)
treeb1404b8cbaa64758f0d1caac3349384e42e34057 /arch/blackfin/mach-bf561/include/mach/defBF561.h
parentf339f46b05cfe289024b15a0525c8b61f1426a88 (diff)
Blackfin: add MDMA defines to make cross-variant coding easier
Add some defines to make the BF538/BF561 look like most other Blackfin parts in that it has a MDMA0 channel available for low level init. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561/include/mach/defBF561.h')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h56
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index cf922295f4c..5fc0f05026e 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -796,6 +796,62 @@
796#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ 796#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
797#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ 797#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
798 798
799#define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
800#define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR
801#define MDMA_D0_CONFIG MDMA1_D0_CONFIG
802#define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT
803#define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY
804#define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT
805#define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY
806#define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR
807#define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR
808#define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS
809#define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP
810#define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT
811#define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT
812
813#define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
814#define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR
815#define MDMA_S0_CONFIG MDMA1_S0_CONFIG
816#define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT
817#define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY
818#define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT
819#define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY
820#define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR
821#define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR
822#define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS
823#define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP
824#define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT
825#define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT
826
827#define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR
828#define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR
829#define MDMA_D1_CONFIG MDMA1_D1_CONFIG
830#define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT
831#define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY
832#define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT
833#define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY
834#define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR
835#define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR
836#define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS
837#define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP
838#define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT
839#define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT
840
841#define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR
842#define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR
843#define MDMA_S1_CONFIG MDMA1_S1_CONFIG
844#define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT
845#define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY
846#define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT
847#define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY
848#define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR
849#define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR
850#define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS
851#define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP
852#define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT
853#define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT
854
799/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ 855/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
800#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ 856#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
801#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */ 857#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */