aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin/mach-bf548/include/mach
diff options
context:
space:
mode:
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-01-08 00:24:38 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-01-08 00:24:38 -0500
commit24f030175d30f019be41766cdf88c2ff03de19ff (patch)
tree354232a84e82d5a721ed7b1a9af580ff2a59be8f /arch/blackfin/mach-bf548/include/mach
parent4aa12f7b927c3cac0e0cf3503642597527d0ece0 (diff)
parent9e42d0cf5020aaf217433cad1a224745241d212a (diff)
Merge commit 'origin/master' into next
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach')
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h5
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bf548.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_sir.h166
-rw-r--r--arch/blackfin/mach-bf548/include/mach/blackfin.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h114
-rw-r--r--arch/blackfin/mach-bf548/include/mach/dma.h32
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/mem_init.h255
-rw-r--r--arch/blackfin/mach-bf548/include/mach/mem_map.h6
9 files changed, 77 insertions, 507 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 816b09278f6..3b5430999f4 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -157,6 +157,8 @@
157#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) 157#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
158/* Software System Reset Corrupts PLL_LOCKCNT Register */ 158/* Software System Reset Corrupts PLL_LOCKCNT Register */
159#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) 159#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
160/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
161#define ANOMALY_05000443 (1)
160 162
161/* Anomalies that don't exist on this proc */ 163/* Anomalies that don't exist on this proc */
162#define ANOMALY_05000125 (0) 164#define ANOMALY_05000125 (0)
@@ -173,5 +175,8 @@
173#define ANOMALY_05000311 (0) 175#define ANOMALY_05000311 (0)
174#define ANOMALY_05000323 (0) 176#define ANOMALY_05000323 (0)
175#define ANOMALY_05000363 (0) 177#define ANOMALY_05000363 (0)
178#define ANOMALY_05000412 (0)
179#define ANOMALY_05000432 (0)
180#define ANOMALY_05000435 (0)
176 181
177#endif 182#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h
index 49f9b403d45..f0e56998481 100644
--- a/arch/blackfin/mach-bf548/include/mach/bf548.h
+++ b/arch/blackfin/mach-bf548/include/mach/bf548.h
@@ -122,7 +122,7 @@
122#endif 122#endif
123 123
124#ifndef CPU 124#ifndef CPU
125#error Unknown CPU type - This kernel doesn't seem to be configured properly 125#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
126#endif 126#endif
127 127
128#endif /* __MACH_BF48_H__ */ 128#endif /* __MACH_BF48_H__ */
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_sir.h b/arch/blackfin/mach-bf548/include/mach/bfin_sir.h
deleted file mode 100644
index c41f9cf0026..00000000000
--- a/arch/blackfin/mach-bf548/include/mach/bfin_sir.h
+++ /dev/null
@@ -1,166 +0,0 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
21#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
27#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
28#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
29#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
30#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
31#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
32#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
33
34#ifdef CONFIG_SIR_BFIN_DMA
35struct dma_rx_buf {
36 char *buf;
37 int head;
38 int tail;
39 };
40#endif /* CONFIG_SIR_BFIN_DMA */
41
42struct bfin_sir_port {
43 unsigned char __iomem *membase;
44 unsigned int irq;
45 unsigned int lsr;
46 unsigned long clk;
47 struct net_device *dev;
48#ifdef CONFIG_SIR_BFIN_DMA
49 int tx_done;
50 struct dma_rx_buf rx_dma_buf;
51 struct timer_list rx_dma_timer;
52 int rx_dma_nrows;
53#endif /* CONFIG_SIR_BFIN_DMA */
54 unsigned int tx_dma_channel;
55 unsigned int rx_dma_channel;
56};
57
58struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
59
60struct bfin_sir_port_res {
61 unsigned long base_addr;
62 int irq;
63 unsigned int rx_dma_channel;
64 unsigned int tx_dma_channel;
65};
66
67struct bfin_sir_port_res bfin_sir_port_resource[] = {
68#ifdef CONFIG_BFIN_SIR0
69 {
70 0xFFC00400,
71 IRQ_UART0_RX,
72 CH_UART0_RX,
73 CH_UART0_TX,
74 },
75#endif
76#ifdef CONFIG_BFIN_SIR1
77 {
78 0xFFC02000,
79 IRQ_UART1_RX,
80 CH_UART1_RX,
81 CH_UART1_TX,
82 },
83#endif
84#ifdef CONFIG_BFIN_SIR2
85 {
86 0xFFC02100,
87 IRQ_UART2_RX,
88 CH_UART2_RX,
89 CH_UART2_TX,
90 },
91#endif
92#ifdef CONFIG_BFIN_SIR3
93 {
94 0xFFC03100,
95 IRQ_UART3_RX,
96 CH_UART3_RX,
97 CH_UART3_TX,
98 },
99#endif
100};
101
102int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
103
104struct bfin_sir_self {
105 struct bfin_sir_port *sir_port;
106 spinlock_t lock;
107 unsigned int open;
108 int speed;
109 int newspeed;
110
111 struct sk_buff *txskb;
112 struct sk_buff *rxskb;
113 struct net_device_stats stats;
114 struct device *dev;
115 struct irlap_cb *irlap;
116 struct qos_info qos;
117
118 iobuff_t tx_buff;
119 iobuff_t rx_buff;
120
121 struct work_struct work;
122 int mtt;
123};
124
125#define DRIVER_NAME "bfin_sir"
126
127static int bfin_sir_hw_init(void)
128{
129 int ret = -ENODEV;
130#ifdef CONFIG_BFIN_SIR0
131 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
132 if (ret)
133 return ret;
134 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
135 if (ret)
136 return ret;
137#endif
138
139#ifdef CONFIG_BFIN_SIR1
140 ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
141 if (ret)
142 return ret;
143 ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
144 if (ret)
145 return ret;
146#endif
147
148#ifdef CONFIG_BFIN_SIR2
149 ret = peripheral_request(P_UART2_TX, DRIVER_NAME);
150 if (ret)
151 return ret;
152 ret = peripheral_request(P_UART2_RX, DRIVER_NAME);
153 if (ret)
154 return ret;
155#endif
156
157#ifdef CONFIG_BFIN_SIR3
158 ret = peripheral_request(P_UART3_TX, DRIVER_NAME);
159 if (ret)
160 return ret;
161 ret = peripheral_request(P_UART3_RX, DRIVER_NAME);
162 if (ret)
163 return ret;
164#endif
165 return ret;
166}
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index d6ee74ac046..0c0e3e2c3c2 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -111,7 +111,7 @@
111 111
112/* UART 0*/ 112/* UART 0*/
113 113
114/* DMA Channnel */ 114/* DMA Channel */
115#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX() 115#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX()
116#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val) 116#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val)
117#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX() 117#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX()
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index 57ac8cb9b1f..6e636c418cb 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -34,7 +34,6 @@
34#include <asm/blackfin.h> 34#include <asm/blackfin.h>
35 35
36#include "defBF54x_base.h" 36#include "defBF54x_base.h"
37#include <asm/system.h>
38 37
39/* ************************************************************** */ 38/* ************************************************************** */
40/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ 39/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
@@ -43,63 +42,9 @@
43/* PLL Registers */ 42/* PLL Registers */
44 43
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 44#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1, iwr2;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 iwr2 = bfin_read32(SIC_IWR2);
59 /* Only allow PPL Wakeup) */
60 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
61 bfin_write32(SIC_IWR1, 0);
62 bfin_write32(SIC_IWR2, 0);
63
64 bfin_write16(PLL_CTL, val);
65 SSYNC();
66 asm("IDLE;");
67
68 bfin_write32(SIC_IWR0, iwr0);
69 bfin_write32(SIC_IWR1, iwr1);
70 bfin_write32(SIC_IWR2, iwr2);
71 local_irq_restore(flags);
72}
73#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 45#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
74#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 46#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
75#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 47#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
76/* Writing to VR_CTL initiates a PLL relock sequence. */
77static __inline__ void bfin_write_VR_CTL(unsigned int val)
78{
79 unsigned long flags, iwr0, iwr1, iwr2;
80
81 if (val == bfin_read_VR_CTL())
82 return;
83
84 local_irq_save(flags);
85 /* Enable the PLL Wakeup bit in SIC IWR */
86 iwr0 = bfin_read32(SIC_IWR0);
87 iwr1 = bfin_read32(SIC_IWR1);
88 iwr2 = bfin_read32(SIC_IWR2);
89 /* Only allow PPL Wakeup) */
90 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
91 bfin_write32(SIC_IWR1, 0);
92 bfin_write32(SIC_IWR2, 0);
93
94 bfin_write16(VR_CTL, val);
95 SSYNC();
96 asm("IDLE;");
97
98 bfin_write32(SIC_IWR0, iwr0);
99 bfin_write32(SIC_IWR1, iwr1);
100 bfin_write32(SIC_IWR2, iwr2);
101 local_irq_restore(flags);
102}
103#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 48#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
104#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 49#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
105#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 50#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -2746,5 +2691,64 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
2746#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST 2691#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST
2747#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST 2692#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST
2748 2693
2694/* These need to be last due to the cdef/linux inter-dependencies */
2695#include <asm/irq.h>
2696
2697/* Writing to PLL_CTL initiates a PLL relock sequence. */
2698static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2699{
2700 unsigned long flags, iwr0, iwr1, iwr2;
2701
2702 if (val == bfin_read_PLL_CTL())
2703 return;
2704
2705 local_irq_save_hw(flags);
2706 /* Enable the PLL Wakeup bit in SIC IWR */
2707 iwr0 = bfin_read32(SIC_IWR0);
2708 iwr1 = bfin_read32(SIC_IWR1);
2709 iwr2 = bfin_read32(SIC_IWR2);
2710 /* Only allow PPL Wakeup) */
2711 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2712 bfin_write32(SIC_IWR1, 0);
2713 bfin_write32(SIC_IWR2, 0);
2714
2715 bfin_write16(PLL_CTL, val);
2716 SSYNC();
2717 asm("IDLE;");
2718
2719 bfin_write32(SIC_IWR0, iwr0);
2720 bfin_write32(SIC_IWR1, iwr1);
2721 bfin_write32(SIC_IWR2, iwr2);
2722 local_irq_restore_hw(flags);
2723}
2724
2725/* Writing to VR_CTL initiates a PLL relock sequence. */
2726static __inline__ void bfin_write_VR_CTL(unsigned int val)
2727{
2728 unsigned long flags, iwr0, iwr1, iwr2;
2729
2730 if (val == bfin_read_VR_CTL())
2731 return;
2732
2733 local_irq_save_hw(flags);
2734 /* Enable the PLL Wakeup bit in SIC IWR */
2735 iwr0 = bfin_read32(SIC_IWR0);
2736 iwr1 = bfin_read32(SIC_IWR1);
2737 iwr2 = bfin_read32(SIC_IWR2);
2738 /* Only allow PPL Wakeup) */
2739 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2740 bfin_write32(SIC_IWR1, 0);
2741 bfin_write32(SIC_IWR2, 0);
2742
2743 bfin_write16(VR_CTL, val);
2744 SSYNC();
2745 asm("IDLE;");
2746
2747 bfin_write32(SIC_IWR0, iwr0);
2748 bfin_write32(SIC_IWR1, iwr1);
2749 bfin_write32(SIC_IWR2, iwr2);
2750 local_irq_restore_hw(flags);
2751}
2752
2749#endif /* _CDEF_BF54X_H */ 2753#endif /* _CDEF_BF54X_H */
2750 2754
diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h
index 36a2ef7e784..a30d242c739 100644
--- a/arch/blackfin/mach-bf548/include/mach/dma.h
+++ b/arch/blackfin/mach-bf548/include/mach/dma.h
@@ -1,32 +1,8 @@
1/* 1/* mach/dma.h - arch-specific DMA defines
2 * file: include/asm-blackfin/mach-bf548/dma.h
3 * based on:
4 * author:
5 * 2 *
6 * created: 3 * Copyright 2004-2008 Analog Devices Inc.
7 * description:
8 * system mmr register map
9 * rev:
10 * 4 *
11 * modified: 5 * Licensed under the GPL-2 or later.
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */ 6 */
31 7
32#ifndef _MACH_DMA_H_ 8#ifndef _MACH_DMA_H_
@@ -71,6 +47,6 @@
71#define CH_MEM_STREAM3_DEST 30 47#define CH_MEM_STREAM3_DEST 30
72#define CH_MEM_STREAM3_SRC 31 48#define CH_MEM_STREAM3_SRC 31
73 49
74#define MAX_BLACKFIN_DMA_CHANNEL 32 50#define MAX_DMA_CHANNELS 32
75 51
76#endif 52#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index ad380d1f587..60299a71e09 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -158,7 +158,7 @@ Events (highest priority) EMU 0
158#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ 158#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
159#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ 159#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
160 160
161#define SYS_IRQS IRQ_PINT3 161#define SYS_IRQS IRQ_PINT3
162 162
163#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) 163#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
164#define IRQ_PA0 BFIN_PA_IRQ(0) 164#define IRQ_PA0 BFIN_PA_IRQ(0)
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_init.h b/arch/blackfin/mach-bf548/include/mach/mem_init.h
deleted file mode 100644
index ab0b863eee6..00000000000
--- a/arch/blackfin/mach-bf548/include/mach/mem_init.h
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
32#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
33#define DDR_CLK_HZ(x) (1000*1000*1000/x)
34
35#if (CONFIG_MEM_MT46V32M16_6T)
36#define DDR_SIZE DEVSZ_512
37#define DDR_WIDTH DEVWD_16
38#define DDR_MAX_tCK 13
39
40#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
41#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
42#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
43#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
44#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
45
46#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
47#define DDR_tWTR DDR_TWTR(1)
48#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
49#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
50#endif
51
52#if (CONFIG_MEM_MT46V32M16_5B)
53#define DDR_SIZE DEVSZ_512
54#define DDR_WIDTH DEVWD_16
55#define DDR_MAX_tCK 13
56
57#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
58#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
59#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
60#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
61#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
62
63#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
64#define DDR_tWTR DDR_TWTR(2)
65#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
66#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
67#endif
68
69#if (CONFIG_MEM_GENERIC_BOARD)
70#define DDR_SIZE DEVSZ_512
71#define DDR_WIDTH DEVWD_16
72#define DDR_MAX_tCK 13
73
74#define DDR_tRCD DDR_TRCD(3)
75#define DDR_tWTR DDR_TWTR(2)
76#define DDR_tWR DDR_TWR(2)
77#define DDR_tMRD DDR_TMRD(2)
78#define DDR_tRP DDR_TRP(3)
79#define DDR_tRAS DDR_TRAS(7)
80#define DDR_tRC DDR_TRC(10)
81#define DDR_tRFC DDR_TRFC(12)
82#define DDR_tREFI DDR_TREFI(1288)
83#endif
84
85#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
86# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
87#elif(CONFIG_SCLK_HZ <= 133333333)
88# define DDR_CL CL_2
89#else
90# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
91#endif
92
93
94#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
95#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
96 | DDR_tMRD | DDR_tWR | DDR_tRCD)
97#define mem_DDRCTL2 DDR_CL
98
99
100#if defined CONFIG_CLKIN_HALF
101#define CLKIN_HALF 1
102#else
103#define CLKIN_HALF 0
104#endif
105
106#if defined CONFIG_PLL_BYPASS
107#define PLL_BYPASS 1
108#else
109#define PLL_BYPASS 0
110#endif
111
112/***************************************Currently Not Being Used *********************************/
113#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
114#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
115#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
116#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
117#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
118
119#if (flash_EBIU_AMBCTL_TT > 3)
120#define flash_EBIU_AMBCTL0_TT B0TT_4
121#endif
122#if (flash_EBIU_AMBCTL_TT == 3)
123#define flash_EBIU_AMBCTL0_TT B0TT_3
124#endif
125#if (flash_EBIU_AMBCTL_TT == 2)
126#define flash_EBIU_AMBCTL0_TT B0TT_2
127#endif
128#if (flash_EBIU_AMBCTL_TT < 2)
129#define flash_EBIU_AMBCTL0_TT B0TT_1
130#endif
131
132#if (flash_EBIU_AMBCTL_ST > 3)
133#define flash_EBIU_AMBCTL0_ST B0ST_4
134#endif
135#if (flash_EBIU_AMBCTL_ST == 3)
136#define flash_EBIU_AMBCTL0_ST B0ST_3
137#endif
138#if (flash_EBIU_AMBCTL_ST == 2)
139#define flash_EBIU_AMBCTL0_ST B0ST_2
140#endif
141#if (flash_EBIU_AMBCTL_ST < 2)
142#define flash_EBIU_AMBCTL0_ST B0ST_1
143#endif
144
145#if (flash_EBIU_AMBCTL_HT > 2)
146#define flash_EBIU_AMBCTL0_HT B0HT_3
147#endif
148#if (flash_EBIU_AMBCTL_HT == 2)
149#define flash_EBIU_AMBCTL0_HT B0HT_2
150#endif
151#if (flash_EBIU_AMBCTL_HT == 1)
152#define flash_EBIU_AMBCTL0_HT B0HT_1
153#endif
154#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
155#define flash_EBIU_AMBCTL0_HT B0HT_0
156#endif
157#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
158#define flash_EBIU_AMBCTL0_HT B0HT_1
159#endif
160
161#if (flash_EBIU_AMBCTL_WAT > 14)
162#define flash_EBIU_AMBCTL0_WAT B0WAT_15
163#endif
164#if (flash_EBIU_AMBCTL_WAT == 14)
165#define flash_EBIU_AMBCTL0_WAT B0WAT_14
166#endif
167#if (flash_EBIU_AMBCTL_WAT == 13)
168#define flash_EBIU_AMBCTL0_WAT B0WAT_13
169#endif
170#if (flash_EBIU_AMBCTL_WAT == 12)
171#define flash_EBIU_AMBCTL0_WAT B0WAT_12
172#endif
173#if (flash_EBIU_AMBCTL_WAT == 11)
174#define flash_EBIU_AMBCTL0_WAT B0WAT_11
175#endif
176#if (flash_EBIU_AMBCTL_WAT == 10)
177#define flash_EBIU_AMBCTL0_WAT B0WAT_10
178#endif
179#if (flash_EBIU_AMBCTL_WAT == 9)
180#define flash_EBIU_AMBCTL0_WAT B0WAT_9
181#endif
182#if (flash_EBIU_AMBCTL_WAT == 8)
183#define flash_EBIU_AMBCTL0_WAT B0WAT_8
184#endif
185#if (flash_EBIU_AMBCTL_WAT == 7)
186#define flash_EBIU_AMBCTL0_WAT B0WAT_7
187#endif
188#if (flash_EBIU_AMBCTL_WAT == 6)
189#define flash_EBIU_AMBCTL0_WAT B0WAT_6
190#endif
191#if (flash_EBIU_AMBCTL_WAT == 5)
192#define flash_EBIU_AMBCTL0_WAT B0WAT_5
193#endif
194#if (flash_EBIU_AMBCTL_WAT == 4)
195#define flash_EBIU_AMBCTL0_WAT B0WAT_4
196#endif
197#if (flash_EBIU_AMBCTL_WAT == 3)
198#define flash_EBIU_AMBCTL0_WAT B0WAT_3
199#endif
200#if (flash_EBIU_AMBCTL_WAT == 2)
201#define flash_EBIU_AMBCTL0_WAT B0WAT_2
202#endif
203#if (flash_EBIU_AMBCTL_WAT == 1)
204#define flash_EBIU_AMBCTL0_WAT B0WAT_1
205#endif
206
207#if (flash_EBIU_AMBCTL_RAT > 14)
208#define flash_EBIU_AMBCTL0_RAT B0RAT_15
209#endif
210#if (flash_EBIU_AMBCTL_RAT == 14)
211#define flash_EBIU_AMBCTL0_RAT B0RAT_14
212#endif
213#if (flash_EBIU_AMBCTL_RAT == 13)
214#define flash_EBIU_AMBCTL0_RAT B0RAT_13
215#endif
216#if (flash_EBIU_AMBCTL_RAT == 12)
217#define flash_EBIU_AMBCTL0_RAT B0RAT_12
218#endif
219#if (flash_EBIU_AMBCTL_RAT == 11)
220#define flash_EBIU_AMBCTL0_RAT B0RAT_11
221#endif
222#if (flash_EBIU_AMBCTL_RAT == 10)
223#define flash_EBIU_AMBCTL0_RAT B0RAT_10
224#endif
225#if (flash_EBIU_AMBCTL_RAT == 9)
226#define flash_EBIU_AMBCTL0_RAT B0RAT_9
227#endif
228#if (flash_EBIU_AMBCTL_RAT == 8)
229#define flash_EBIU_AMBCTL0_RAT B0RAT_8
230#endif
231#if (flash_EBIU_AMBCTL_RAT == 7)
232#define flash_EBIU_AMBCTL0_RAT B0RAT_7
233#endif
234#if (flash_EBIU_AMBCTL_RAT == 6)
235#define flash_EBIU_AMBCTL0_RAT B0RAT_6
236#endif
237#if (flash_EBIU_AMBCTL_RAT == 5)
238#define flash_EBIU_AMBCTL0_RAT B0RAT_5
239#endif
240#if (flash_EBIU_AMBCTL_RAT == 4)
241#define flash_EBIU_AMBCTL0_RAT B0RAT_4
242#endif
243#if (flash_EBIU_AMBCTL_RAT == 3)
244#define flash_EBIU_AMBCTL0_RAT B0RAT_3
245#endif
246#if (flash_EBIU_AMBCTL_RAT == 2)
247#define flash_EBIU_AMBCTL0_RAT B0RAT_2
248#endif
249#if (flash_EBIU_AMBCTL_RAT == 1)
250#define flash_EBIU_AMBCTL0_RAT B0RAT_1
251#endif
252
253#define flash_EBIU_AMBCTL0 \
254 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
255 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h
index a2228428dc0..70b9c119402 100644
--- a/arch/blackfin/mach-bf548/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf548/include/mach/mem_map.h
@@ -108,4 +108,10 @@
108#define L1_SCRATCH_START 0xFFB00000 108#define L1_SCRATCH_START 0xFFB00000
109#define L1_SCRATCH_LENGTH 0x1000 109#define L1_SCRATCH_LENGTH 0x1000
110 110
111#define GET_PDA_SAFE(preg) \
112 preg.l = _cpu_pda; \
113 preg.h = _cpu_pda;
114
115#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
116
111#endif/* _MEM_MAP_548_H_ */ 117#endif/* _MEM_MAP_548_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 04:45:32 -0400