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authorBryan Wu <bryan.wu@analog.com>2007-05-06 17:50:22 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-07 15:12:58 -0400
commit1394f03221790a988afc3e4b3cb79f2e477246a9 (patch)
tree2c1963c9a4f2d84a5e021307fde240c5d567cf70 /arch/blackfin/mach-bf537
parent73243284463a761e04d69d22c7516b2be7de096c (diff)
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/blackfin/mach-bf537')
-rw-r--r--arch/blackfin/mach-bf537/Kconfig141
-rw-r--r--arch/blackfin/mach-bf537/Makefile9
-rw-r--r--arch/blackfin/mach-bf537/boards/Makefile9
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537.c364
-rw-r--r--arch/blackfin/mach-bf537/boards/eth_mac.c51
-rw-r--r--arch/blackfin/mach-bf537/boards/generic_board.c445
-rw-r--r--arch/blackfin/mach-bf537/boards/led.S183
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c523
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c615
-rw-r--r--arch/blackfin/mach-bf537/cpu.c161
-rw-r--r--arch/blackfin/mach-bf537/head.S602
-rw-r--r--arch/blackfin/mach-bf537/ints-priority.c74
12 files changed, 3177 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig
new file mode 100644
index 00000000000..cc9ae38a4dd
--- /dev/null
+++ b/arch/blackfin/mach-bf537/Kconfig
@@ -0,0 +1,141 @@
1if (BF537 || BF534 || BF536)
2
3menu "BF537 Specific Configuration"
4
5comment "PORT F/G Selection"
6choice
7 prompt "Select BF537/6/4 default GPIO PFx PORTx"
8 help
9 Quick Hack for BF537/6/4 default GPIO PFx PORTF.
10
11config BF537_PORT_F
12 bool "Select BF537/6/4 default GPIO PFx PORTF"
13 depends on (BF537 || BF536 || BF534)
14 help
15 Quick Hack for BF537/6/4 default GPIO PFx PORTF.
16
17config BF537_PORT_G
18 bool "Select BF537/6/4 default GPIO PFx PORTG"
19 depends on (BF537 || BF536 || BF534)
20 help
21 Quick Hack for BF537/6/4 default GPIO PFx PORTG.
22
23config BF537_PORT_H
24 bool "Select BF537/6/4 default GPIO PFx PORTH"
25 depends on (BF537 || BF536 || BF534)
26 help
27 Quick Hack for BF537/6/4 default GPIO PFx PORTH
28 Use only when Blackfin EMAC support is not required.
29
30endchoice
31
32comment "Interrupt Priority Assignment"
33menu "Priority"
34
35config IRQ_PLL_WAKEUP
36 int "IRQ_PLL_WAKEUP"
37 default 7
38config IRQ_DMA_ERROR
39 int "IRQ_DMA_ERROR Generic"
40 default 7
41config IRQ_ERROR
42 int "IRQ_ERROR: CAN MAC SPORT0 SPORT1 SPI UART0 UART1"
43 default 7
44config IRQ_RTC
45 int "IRQ_RTC"
46 default 8
47config IRQ_PPI
48 int "IRQ_PPI"
49 default 8
50config IRQ_SPORT0_RX
51 int "IRQ_SPORT0_RX"
52 default 9
53config IRQ_SPORT0_TX
54 int "IRQ_SPORT0_TX"
55 default 9
56config IRQ_SPORT1_RX
57 int "IRQ_SPORT1_RX"
58 default 9
59config IRQ_SPORT1_TX
60 int "IRQ_SPORT1_TX"
61 default 9
62config IRQ_TWI
63 int "IRQ_TWI"
64 default 10
65config IRQ_SPI
66 int "IRQ_SPI"
67 default 10
68config IRQ_UART0_RX
69 int "IRQ_UART0_RX"
70 default 10
71config IRQ_UART0_TX
72 int "IRQ_UART0_TX"
73 default 10
74config IRQ_UART1_RX
75 int "IRQ_UART1_RX"
76 default 10
77config IRQ_UART1_TX
78 int "IRQ_UART1_TX"
79 default 10
80config IRQ_CAN_RX
81 int "IRQ_CAN_RX"
82 default 11
83config IRQ_CAN_TX
84 int "IRQ_CAN_TX"
85 default 11
86config IRQ_MAC_RX
87 int "IRQ_MAC_RX"
88 default 11
89config IRQ_MAC_TX
90 int "IRQ_MAC_TX"
91 default 11
92config IRQ_TMR0
93 int "IRQ_TMR0"
94 default 12
95config IRQ_TMR1
96 int "IRQ_TMR1"
97 default 12
98config IRQ_TMR2
99 int "IRQ_TMR2"
100 default 12
101config IRQ_TMR3
102 int "IRQ_TMR3"
103 default 12
104config IRQ_TMR4
105 int "IRQ_TMR4"
106 default 12
107config IRQ_TMR5
108 int "IRQ_TMR5"
109 default 12
110config IRQ_TMR6
111 int "IRQ_TMR6"
112 default 12
113config IRQ_TMR7
114 int "IRQ_TMR7"
115 default 12
116config IRQ_PROG_INTA
117 int "IRQ_PROG_INTA"
118 default 12
119config IRQ_PORTG_INTB
120 int "IRQ_PORTG_INTB"
121 default 12
122config IRQ_MEM_DMA0
123 int "IRQ_MEM_DMA0"
124 default 13
125config IRQ_MEM_DMA1
126 int "IRQ_MEM_DMA1"
127 default 13
128config IRQ_WATCH
129 int "IRQ_WATCH"
130 default 13
131
132 help
133 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
134 This applies to all the above. It is not recommended to assign the
135 highest priority number 7 to UART or any other device.
136
137endmenu
138
139endmenu
140
141endif
diff --git a/arch/blackfin/mach-bf537/Makefile b/arch/blackfin/mach-bf537/Makefile
new file mode 100644
index 00000000000..f32d44215bb
--- /dev/null
+++ b/arch/blackfin/mach-bf537/Makefile
@@ -0,0 +1,9 @@
1#
2# arch/blackfin/mach-bf537/Makefile
3#
4
5extra-y := head.o
6
7obj-y := ints-priority.o
8
9obj-$(CONFIG_CPU_FREQ) += cpu.o
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
new file mode 100644
index 00000000000..23323cacc3a
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/Makefile
@@ -0,0 +1,9 @@
1#
2# arch/blackfin/mach-bf537/boards/Makefile
3#
4
5obj-y += eth_mac.o
6obj-$(CONFIG_GENERIC_BOARD) += generic_board.o
7obj-$(CONFIG_BFIN537_STAMP) += stamp.o led.o
8obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o
9obj-$(CONFIG_PNAV10) += pnav10.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c
new file mode 100644
index 00000000000..6a60618a78e
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c
@@ -0,0 +1,364 @@
1/*
2 * File: arch/blackfin/mach-bf537/boards/cm_bf537.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created: 2005
7 * Description: Board description file
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h>
37#include <linux/usb_isp1362.h>
38#include <asm/irq.h>
39#include <asm/bfin5xx_spi.h>
40
41/*
42 * Name the Board for the /proc/cpuinfo
43 */
44char *bfin_board_name = "Bluetechnix CM BF537";
45
46#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
47/* all SPI peripherals info goes here */
48
49#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
50static struct mtd_partition bfin_spi_flash_partitions[] = {
51 {
52 .name = "bootloader",
53 .size = 0x00020000,
54 .offset = 0,
55 .mask_flags = MTD_CAP_ROM
56 },{
57 .name = "kernel",
58 .size = 0xe0000,
59 .offset = 0x20000
60 },{
61 .name = "file system",
62 .size = 0x700000,
63 .offset = 0x00100000,
64 }
65};
66
67static struct flash_platform_data bfin_spi_flash_data = {
68 .name = "m25p80",
69 .parts = bfin_spi_flash_partitions,
70 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
71 .type = "m25p64",
72};
73
74/* SPI flash chip (m25p64) */
75static struct bfin5xx_spi_chip spi_flash_chip_info = {
76 .enable_dma = 0, /* use dma transfer with this chip*/
77 .bits_per_word = 8,
78};
79#endif
80
81#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
82/* SPI ADC chip */
83static struct bfin5xx_spi_chip spi_adc_chip_info = {
84 .enable_dma = 1, /* use dma transfer with this chip*/
85 .bits_per_word = 16,
86};
87#endif
88
89#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
90static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
91 .enable_dma = 0,
92 .bits_per_word = 16,
93};
94#endif
95
96#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
97static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
98 .enable_dma = 0,
99 .bits_per_word = 16,
100};
101#endif
102
103#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
104static struct bfin5xx_spi_chip spi_mmc_chip_info = {
105 .enable_dma = 1,
106 .bits_per_word = 8,
107};
108#endif
109
110static struct spi_board_info bfin_spi_board_info[] __initdata = {
111#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
112 {
113 /* the modalias must be the same as spi device driver name */
114 .modalias = "m25p80", /* Name of spi_driver for this device */
115 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
116 .bus_num = 1, /* Framework bus number */
117 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
118 .platform_data = &bfin_spi_flash_data,
119 .controller_data = &spi_flash_chip_info,
120 .mode = SPI_MODE_3,
121 },
122#endif
123
124#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
125 {
126 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
127 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
128 .bus_num = 1, /* Framework bus number */
129 .chip_select = 1, /* Framework chip select. */
130 .platform_data = NULL, /* No spi_driver specific config */
131 .controller_data = &spi_adc_chip_info,
132 },
133#endif
134
135#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
136 {
137 .modalias = "ad1836-spi",
138 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
139 .bus_num = 1,
140 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
141 .controller_data = &ad1836_spi_chip_info,
142 },
143#endif
144
145#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
146 {
147 .modalias = "ad9960-spi",
148 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
149 .bus_num = 1,
150 .chip_select = 1,
151 .controller_data = &ad9960_spi_chip_info,
152 },
153#endif
154
155#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
156 {
157 .modalias = "spi_mmc_dummy",
158 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
159 .bus_num = 1,
160 .chip_select = 7,
161 .platform_data = NULL,
162 .controller_data = &spi_mmc_chip_info,
163 .mode = SPI_MODE_3,
164 },
165 {
166 .modalias = "spi_mmc",
167 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
168 .bus_num = 1,
169 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
170 .platform_data = NULL,
171 .controller_data = &spi_mmc_chip_info,
172 .mode = SPI_MODE_3,
173 },
174#endif
175};
176
177/* SPI controller data */
178static struct bfin5xx_spi_master spi_bfin_master_info = {
179 .num_chipselect = 8,
180 .enable_dma = 1, /* master has the ability to do dma transfer */
181};
182
183static struct platform_device spi_bfin_master_device = {
184 .name = "bfin-spi-master",
185 .id = 1, /* Bus number */
186 .dev = {
187 .platform_data = &spi_bfin_master_info, /* Passed to driver */
188 },
189};
190#endif /* spi master and devices */
191
192#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
193static struct platform_device rtc_device = {
194 .name = "rtc-bfin",
195 .id = -1,
196};
197#endif
198
199#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
200static struct resource smc91x_resources[] = {
201 {
202 .start = 0x20200300,
203 .end = 0x20200300 + 16,
204 .flags = IORESOURCE_MEM,
205 },{
206 .start = IRQ_PF14,
207 .end = IRQ_PF14,
208 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
209 },
210};
211
212static struct platform_device smc91x_device = {
213 .name = "smc91x",
214 .id = 0,
215 .num_resources = ARRAY_SIZE(smc91x_resources),
216 .resource = smc91x_resources,
217};
218#endif
219
220#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
221static struct resource isp1362_hcd_resources[] = {
222 {
223 .start = 0x20308000,
224 .end = 0x20308000,
225 .flags = IORESOURCE_MEM,
226 },{
227 .start = 0x20308004,
228 .end = 0x20308004,
229 .flags = IORESOURCE_MEM,
230 },{
231 .start = IRQ_PG15,
232 .end = IRQ_PG15,
233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
234 },
235};
236
237static struct isp1362_platform_data isp1362_priv = {
238 .sel15Kres = 1,
239 .clknotstop = 0,
240 .oc_enable = 0,
241 .int_act_high = 0,
242 .int_edge_triggered = 0,
243 .remote_wakeup_connected = 0,
244 .no_power_switching = 1,
245 .power_switching_mode = 0,
246};
247
248static struct platform_device isp1362_hcd_device = {
249 .name = "isp1362-hcd",
250 .id = 0,
251 .dev = {
252 .platform_data = &isp1362_priv,
253 },
254 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
255 .resource = isp1362_hcd_resources,
256};
257#endif
258
259#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
260static struct resource net2272_bfin_resources[] = {
261 {
262 .start = 0x20200000,
263 .end = 0x20200000 + 0x100,
264 .flags = IORESOURCE_MEM,
265 },{
266 .start = IRQ_PF7,
267 .end = IRQ_PF7,
268 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
269 },
270};
271
272static struct platform_device net2272_bfin_device = {
273 .name = "net2272",
274 .id = -1,
275 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
276 .resource = net2272_bfin_resources,
277};
278#endif
279
280#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
281static struct resource bfin_uart_resources[] = {
282 {
283 .start = 0xFFC00400,
284 .end = 0xFFC004FF,
285 .flags = IORESOURCE_MEM,
286 },{
287 .start = 0xFFC02000,
288 .end = 0xFFC020FF,
289 .flags = IORESOURCE_MEM,
290 },
291};
292
293static struct platform_device bfin_uart_device = {
294 .name = "bfin-uart",
295 .id = 1,
296 .num_resources = ARRAY_SIZE(bfin_uart_resources),
297 .resource = bfin_uart_resources,
298};
299#endif
300
301#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
302static struct platform_device bfin_sport0_uart_device = {
303 .name = "bfin-sport-uart",
304 .id = 0,
305};
306
307static struct platform_device bfin_sport1_uart_device = {
308 .name = "bfin-sport-uart",
309 .id = 1,
310};
311#endif
312
313#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
314static struct platform_device bfin_mac_device = {
315 .name = "bfin_mac",
316};
317#endif
318
319static struct platform_device *cm_bf537_devices[] __initdata = {
320#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
321 &rtc_device,
322#endif
323
324#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
325 &bfin_uart_device,
326#endif
327
328#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
329 &bfin_sport0_uart_device,
330 &bfin_sport1_uart_device,
331#endif
332
333#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
334 &isp1362_hcd_device,
335#endif
336
337#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
338 &smc91x_device,
339#endif
340
341#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
342 &bfin_mac_device,
343#endif
344
345#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
346 &net2272_bfin_device,
347#endif
348
349#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
350 &spi_bfin_master_device,
351#endif
352};
353
354static int __init cm_bf537_init(void)
355{
356 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
357 platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices));
358#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
359 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
360#endif
361 return 0;
362}
363
364arch_initcall(cm_bf537_init);
diff --git a/arch/blackfin/mach-bf537/boards/eth_mac.c b/arch/blackfin/mach-bf537/boards/eth_mac.c
new file mode 100644
index 00000000000..e129a08d63d
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/eth_mac.c
@@ -0,0 +1,51 @@
1/*
2 * arch/blackfin/mach-bf537/board/eth_mac.c
3 *
4 * Copyright (C) 2007 Analog Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/module.h>
21#include <asm/blackfin.h>
22
23#if defined(CONFIG_GENERIC_BOARD) \
24 || defined(CONFIG_BFIN537_STAMP)
25
26/*
27 * Currently the MAC address is saved in Flash by U-Boot
28 */
29#define FLASH_MAC 0x203f0000
30
31void get_bf537_ether_addr(char *addr)
32{
33 unsigned int flash_mac = (unsigned int) FLASH_MAC;
34 *(u32 *)(&(addr[0])) = bfin_read32(flash_mac);
35 flash_mac += 4;
36 *(u16 *)(&(addr[4])) = bfin_read16(flash_mac);
37}
38
39#else
40
41/*
42 * Provide MAC address function for other specific board setting
43 */
44void get_bf537_ether_addr(char *addr)
45{
46 printk(KERN_WARNING "%s: No valid Ethernet MAC address found\n",__FILE__);
47}
48
49#endif
50
51EXPORT_SYMBOL(get_bf537_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c
new file mode 100644
index 00000000000..9019c0edbe7
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/generic_board.c
@@ -0,0 +1,445 @@
1/*
2 * File: arch/blackfin/mach-bf537/boards/generic_board.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h>
37#include <linux/usb_isp1362.h>
38#include <asm/irq.h>
39#include <asm/bfin5xx_spi.h>
40#include <linux/usb_sl811.h>
41
42/*
43 * Name the Board for the /proc/cpuinfo
44 */
45char *bfin_board_name = "UNKNOWN BOARD";
46
47/*
48 * Driver needs to know address, irq and flag pin.
49 */
50
51#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
52static struct resource bfin_pcmcia_cf_resources[] = {
53 {
54 .start = 0x20310000, /* IO PORT */
55 .end = 0x20312000,
56 .flags = IORESOURCE_MEM,
57 },{
58 .start = 0x20311000, /* Attribute Memeory */
59 .end = 0x20311FFF,
60 .flags = IORESOURCE_MEM,
61 },{
62 .start = IRQ_PROG_INTA,
63 .end = IRQ_PROG_INTA,
64 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
65 },{
66 .start = IRQ_PF4,
67 .end = IRQ_PF4,
68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
69 },{
70 .start = 6, /* Card Detect PF6 */
71 .end = 6,
72 .flags = IORESOURCE_IRQ,
73 },
74};
75
76static struct platform_device bfin_pcmcia_cf_device = {
77 .name = "bfin_cf_pcmcia",
78 .id = -1,
79 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
80 .resource = bfin_pcmcia_cf_resources,
81};
82#endif
83
84#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
85static struct platform_device rtc_device = {
86 .name = "rtc-bfin",
87 .id = -1,
88};
89#endif
90
91#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
92static struct resource smc91x_resources[] = {
93 {
94 .name = "smc91x-regs",
95 .start = 0x20300300,
96 .end = 0x20300300 + 16,
97 .flags = IORESOURCE_MEM,
98 },{
99 .start = IRQ_PROG_INTB,
100 .end = IRQ_PROG_INTB,
101 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
102 },{
103 /*
104 * denotes the flag pin and is used directly if
105 * CONFIG_IRQCHIP_DEMUX_GPIO is defined.
106 */
107 .start = IRQ_PF7,
108 .end = IRQ_PF7,
109 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
110 },
111};
112static struct platform_device smc91x_device = {
113 .name = "smc91x",
114 .id = 0,
115 .num_resources = ARRAY_SIZE(smc91x_resources),
116 .resource = smc91x_resources,
117};
118#endif
119
120#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
121static struct resource sl811_hcd_resources[] = {
122 {
123 .start = 0x20340000,
124 .end = 0x20340000,
125 .flags = IORESOURCE_MEM,
126 },{
127 .start = 0x20340004,
128 .end = 0x20340004,
129 .flags = IORESOURCE_MEM,
130 },{
131 .start = IRQ_PROG_INTA,
132 .end = IRQ_PROG_INTA,
133 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
134 },{
135 .start = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO,
136 .end = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO,
137 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
138 },
139};
140
141#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
142void sl811_port_power(struct device *dev, int is_on)
143{
144 unsigned short mask = (1<<CONFIG_USB_SL811_BFIN_GPIO_VBUS);
145
146 bfin_write_PORT_FER(bfin_read_PORT_FER() & ~mask);
147 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | mask);
148
149 if (is_on)
150 bfin_write_FIO_FLAG_S(mask);
151 else
152 bfin_write_FIO_FLAG_C(mask);
153}
154#endif
155
156static struct sl811_platform_data sl811_priv = {
157 .potpg = 10,
158 .power = 250, /* == 500mA */
159#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
160 .port_power = &sl811_port_power,
161#endif
162};
163
164static struct platform_device sl811_hcd_device = {
165 .name = "sl811-hcd",
166 .id = 0,
167 .dev = {
168 .platform_data = &sl811_priv,
169 },
170 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
171 .resource = sl811_hcd_resources,
172};
173
174#endif
175
176#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
177static struct resource isp1362_hcd_resources[] = {
178 {
179 .start = 0x20360000,
180 .end = 0x20360000,
181 .flags = IORESOURCE_MEM,
182 },{
183 .start = 0x20360004,
184 .end = 0x20360004,
185 .flags = IORESOURCE_MEM,
186 },{
187 .start = IRQ_PROG_INTA,
188 .end = IRQ_PROG_INTA,
189 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
190 },{
191 .start = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO,
192 .end = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO,
193 .flags = IORESOURCE_IRQ,
194 },
195};
196
197static struct isp1362_platform_data isp1362_priv = {
198 .sel15Kres = 1,
199 .clknotstop = 0,
200 .oc_enable = 0,
201 .int_act_high = 0,
202 .int_edge_triggered = 0,
203 .remote_wakeup_connected = 0,
204 .no_power_switching = 1,
205 .power_switching_mode = 0,
206};
207
208static struct platform_device isp1362_hcd_device = {
209 .name = "isp1362-hcd",
210 .id = 0,
211 .dev = {
212 .platform_data = &isp1362_priv,
213 },
214 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
215 .resource = isp1362_hcd_resources,
216};
217#endif
218
219#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
220static struct platform_device bfin_mac_device = {
221 .name = "bfin_mac",
222};
223#endif
224
225#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
226static struct resource net2272_bfin_resources[] = {
227 {
228 .start = 0x20300000,
229 .end = 0x20300000 + 0x100,
230 .flags = IORESOURCE_MEM,
231 },{
232 .start = IRQ_PF7,
233 .end = IRQ_PF7,
234 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
235 },
236};
237
238static struct platform_device net2272_bfin_device = {
239 .name = "net2272",
240 .id = -1,
241 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
242 .resource = net2272_bfin_resources,
243};
244#endif
245
246#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
247/* all SPI peripherals info goes here */
248
249#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
250static struct mtd_partition bfin_spi_flash_partitions[] = {
251 {
252 .name = "bootloader",
253 .size = 0x00020000,
254 .offset = 0,
255 .mask_flags = MTD_CAP_ROM
256 },{
257 .name = "kernel",
258 .size = 0xe0000,
259 .offset = 0x20000
260 },{
261 .name = "file system",
262 .size = 0x700000,
263 .offset = 0x00100000,
264 }
265};
266
267static struct flash_platform_data bfin_spi_flash_data = {
268 .name = "m25p80",
269 .parts = bfin_spi_flash_partitions,
270 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
271 .type = "m25p64",
272};
273
274/* SPI flash chip (m25p64) */
275static struct bfin5xx_spi_chip spi_flash_chip_info = {
276 .enable_dma = 0, /* use dma transfer with this chip*/
277 .bits_per_word = 8,
278};
279#endif
280
281#if defined(CONFIG_SPI_ADC_BF533) \
282 || defined(CONFIG_SPI_ADC_BF533_MODULE)
283/* SPI ADC chip */
284static struct bfin5xx_spi_chip spi_adc_chip_info = {
285 .enable_dma = 1, /* use dma transfer with this chip*/
286 .bits_per_word = 16,
287};
288#endif
289
290#if defined(CONFIG_SND_BLACKFIN_AD1836) \
291 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
292static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
293 .enable_dma = 0,
294 .bits_per_word = 16,
295};
296#endif
297
298#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
299static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
300 .enable_dma = 0,
301 .bits_per_word = 16,
302};
303#endif
304
305static struct spi_board_info bfin_spi_board_info[] __initdata = {
306#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
307 {
308 /* the modalias must be the same as spi device driver name */
309 .modalias = "m25p80", /* Name of spi_driver for this device */
310 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
311 .bus_num = 1, /* Framework bus number */
312 .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL1*/
313 .platform_data = &bfin_spi_flash_data,
314 .controller_data = &spi_flash_chip_info,
315 .mode = SPI_MODE_3,
316 },
317#endif
318
319#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
320 {
321 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
322 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
323 .bus_num = 1, /* Framework bus number */
324 .chip_select = 1, /* Framework chip select. */
325 .platform_data = NULL, /* No spi_driver specific config */
326 .controller_data = &spi_adc_chip_info,
327 },
328#endif
329
330#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
331 {
332 .modalias = "ad1836-spi",
333 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
334 .bus_num = 1,
335 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
336 .controller_data = &ad1836_spi_chip_info,
337 },
338#endif
339
340#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
341 {
342 .modalias = "ad9960-spi",
343 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
344 .bus_num = 1,
345 .chip_select = 1,
346 .controller_data = &ad9960_spi_chip_info,
347 },
348#endif
349};
350
351/* SPI controller data */
352static struct bfin5xx_spi_master spi_bfin_master_info = {
353 .num_chipselect = 8,
354 .enable_dma = 1, /* master has the ability to do dma transfer */
355};
356
357static struct platform_device spi_bfin_master_device = {
358 .name = "bfin-spi-master",
359 .id = 1, /* Bus number */
360 .dev = {
361 .platform_data = &spi_bfin_master_info, /* Passed to driver */
362 },
363};
364#endif /* spi master and devices */
365
366#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
367static struct platform_device bfin_fb_device = {
368 .name = "bf537-fb",
369};
370#endif
371
372#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
373static struct resource bfin_uart_resources[] = {
374 {
375 .start = 0xFFC00400,
376 .end = 0xFFC004FF,
377 .flags = IORESOURCE_MEM,
378 },{
379 .start = 0xFFC02000,
380 .end = 0xFFC020FF,
381 .flags = IORESOURCE_MEM,
382 },
383};
384
385static struct platform_device bfin_uart_device = {
386 .name = "bfin-uart",
387 .id = 1,
388 .num_resources = ARRAY_SIZE(bfin_uart_resources),
389 .resource = bfin_uart_resources,
390};
391#endif
392
393static struct platform_device *stamp_devices[] __initdata = {
394#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
395 &rtc_device,
396#endif
397
398#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
399 &bfin_pcmcia_cf_device,
400#endif
401
402#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
403 &sl811_hcd_device,
404#endif
405
406#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
407 &isp1362_hcd_device,
408#endif
409
410#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
411 &smc91x_device,
412#endif
413
414#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
415 &bfin_mac_device,
416#endif
417
418#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
419 &net2272_bfin_device,
420#endif
421
422#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
423 &spi_bfin_master_device,
424#endif
425
426#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
427 &bfin_fb_device,
428#endif
429
430#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
431 &bfin_uart_device,
432#endif
433};
434
435static int __init stamp_init(void)
436{
437 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
438 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
439#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
440 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
441#endif
442 return 0;
443}
444
445arch_initcall(stamp_init);
diff --git a/arch/blackfin/mach-bf537/boards/led.S b/arch/blackfin/mach-bf537/boards/led.S
new file mode 100644
index 00000000000..4e9ea4283e5
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/led.S
@@ -0,0 +1,183 @@
1/****************************************************
2 * LED1 ---- PF6 LED2 ---- PF7 *
3 * LED3 ---- PF8 LED4 ---- PF9 *
4 * LED5 ---- PF10 LED6 ---- PF11 *
5 ****************************************************/
6
7#include <linux/linkage.h>
8#include <asm/blackfin.h>
9
10/* All functions in this file save the registers they uses.
11 So there is no need to save any registers before calling them. */
12
13 .text;
14
15/* Initialize LEDs. */
16
17ENTRY(_led_init)
18 LINK 12;
19 [--SP] = P0;
20 [--SP] = R0;
21 [--SP] = R1;
22 [--SP] = R2;
23 R1 = PF6|PF7|PF8|PF9|PF10|PF11 (Z);
24 R2 = ~R1;
25
26 P0.H = hi(PORTF_FER);
27 P0.L = lo(PORTF_FER);
28 R0 = W[P0](Z);
29 SSYNC;
30 R0 = R0 & R2;
31 W[P0] = R0.L;
32 SSYNC;
33
34 P0.H = hi(PORTFIO_DIR);
35 P0.L = lo(PORTFIO_DIR);
36 R0 = W[P0](Z);
37 SSYNC;
38 R0 = R0 | R1;
39 W[P0] = R0.L;
40 SSYNC;
41
42 P0.H = hi(PORTFIO_INEN);
43 P0.L = lo(PORTFIO_INEN);
44 R0 = W[P0](Z);
45 SSYNC;
46 R0 = R0 & R2;
47 W[P0] = R0.L;
48 SSYNC;
49
50 R2 = [SP++];
51 R1 = [SP++];
52 R0 = [SP++];
53 P0 = [SP++];
54 UNLINK;
55 RTS;
56 .size _led_init, .-_led_init
57
58/* Set one LED on. Leave other LEDs unchanged.
59 It expects the LED number passed through R0. */
60
61ENTRY(_led_on)
62 LINK 12;
63 [--SP] = P0;
64 [--SP] = R1;
65 CALL _led_init;
66 R1 = 1;
67 R0 += 5;
68 R1 <<= R0;
69 P0.H = hi(PORTFIO);
70 P0.L = lo(PORTFIO);
71 R0 = W[P0](Z);
72 SSYNC;
73 R0 = R0 | R1;
74 W[P0] = R0.L;
75 SSYNC;
76 R1 = [SP++];
77 P0 = [SP++];
78 UNLINK;
79 RTS;
80 .size _led_on, .-_led_on
81
82/* Set one LED off. Leave other LEDs unchanged. */
83
84ENTRY(_led_off)
85 LINK 12;
86 [--SP] = P0;
87 [--SP] = R1;
88 CALL _led_init;
89 R1 = 1;
90 R0 += 5;
91 R1 <<= R0;
92 R1 = ~R1;
93 P0.H = hi(PORTFIO);
94 P0.L = lo(PORTFIO);
95 R0 = W[P0](Z);
96 SSYNC;
97 R0 = R0 & R1;
98 W[P0] = R0.L;
99 SSYNC;
100 R1 = [SP++];
101 P0 = [SP++];
102 UNLINK;
103 RTS;
104 .size _led_off, .-_led_off
105
106/* Toggle one LED. Leave other LEDs unchanged. */
107
108ENTRY(_led_toggle)
109 LINK 12;
110 [--SP] = P0;
111 [--SP] = R1;
112 CALL _led_init;
113 R1 = 1;
114 R0 += 5;
115 R1 <<= R0;
116 P0.H = hi(PORTFIO);
117 P0.L = lo(PORTFIO);
118 R0 = W[P0](Z);
119 SSYNC;
120 R0 = R0 ^ R1;
121 W[P0] = R0.L;
122 SSYNC;
123 R1 = [SP++];
124 P0 = [SP++];
125 UNLINK;
126 RTS;
127 .size _led_toggle, .-_led_toggle
128
129/* Display the number using LEDs in binary format. */
130
131ENTRY(_led_disp_num)
132 LINK 12;
133 [--SP] = P0;
134 [--SP] = R1;
135 [--SP] = R2;
136 CALL _led_init;
137 R1 = 0x3f(X);
138 R0 = R0 & R1;
139 R2 = 6(X);
140 R0 <<= R2;
141 R1 <<= R2;
142 P0.H = hi(PORTFIO);
143 P0.L = lo(PORTFIO);
144 R2 = W[P0](Z);
145 SSYNC;
146 R1 = ~R1;
147 R2 = R2 & R1;
148 R2 = R2 | R0;
149 W[P0] = R2.L;
150 SSYNC;
151 R2 = [SP++];
152 R1 = [SP++];
153 P0 = [SP++];
154 UNLINK;
155 RTS;
156 .size _led_disp_num, .-_led_disp_num
157
158/* Toggle the number using LEDs in binary format. */
159
160ENTRY(_led_toggle_num)
161 LINK 12;
162 [--SP] = P0;
163 [--SP] = R1;
164 [--SP] = R2;
165 CALL _led_init;
166 R1 = 0x3f(X);
167 R0 = R0 & R1;
168 R1 = 6(X);
169 R0 <<= R1;
170 P0.H = hi(PORTFIO);
171 P0.L = lo(PORTFIO);
172 R1 = W[P0](Z);
173 SSYNC;
174 R1 = R1 ^ R0;
175 W[P0] = R1.L;
176 SSYNC;
177 R2 = [SP++];
178 R1 = [SP++];
179 P0 = [SP++];
180 UNLINK;
181 RTS;
182 .size _led_toggle_num, .-_led_toggle_num
183
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
new file mode 100644
index 00000000000..40d3a1b70ee
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -0,0 +1,523 @@
1/*
2 * File: arch/blackfin/mach-bf537/boards/stamp.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h>
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
38#include <linux/usb_isp1362.h>
39#endif
40#include <asm/irq.h>
41#include <asm/bfin5xx_spi.h>
42#include <linux/usb_sl811.h>
43
44#include <linux/spi/ad7877.h>
45
46/*
47 * Name the Board for the /proc/cpuinfo
48 */
49char *bfin_board_name = "PNAV-1.0";
50
51/*
52 * Driver needs to know address, irq and flag pin.
53 */
54
55#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
56static struct resource bfin_pcmcia_cf_resources[] = {
57 {
58 .start = 0x20310000, /* IO PORT */
59 .end = 0x20312000,
60 .flags = IORESOURCE_MEM,
61 },{
62 .start = 0x20311000, /* Attribute Memeory */
63 .end = 0x20311FFF,
64 .flags = IORESOURCE_MEM,
65 },{
66 .start = IRQ_PF4,
67 .end = IRQ_PF4,
68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
69 },{
70 .start = 6, /* Card Detect PF6 */
71 .end = 6,
72 .flags = IORESOURCE_IRQ,
73 },
74};
75
76static struct platform_device bfin_pcmcia_cf_device = {
77 .name = "bfin_cf_pcmcia",
78 .id = -1,
79 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
80 .resource = bfin_pcmcia_cf_resources,
81};
82#endif
83
84#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
85static struct platform_device rtc_device = {
86 .name = "rtc-bfin",
87 .id = -1,
88};
89#endif
90
91#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
92static struct resource smc91x_resources[] = {
93 {
94 .name = "smc91x-regs",
95 .start = 0x20300300,
96 .end = 0x20300300 + 16,
97 .flags = IORESOURCE_MEM,
98 },{
99
100 .start = IRQ_PF7,
101 .end = IRQ_PF7,
102 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
103 },
104};
105static struct platform_device smc91x_device = {
106 .name = "smc91x",
107 .id = 0,
108 .num_resources = ARRAY_SIZE(smc91x_resources),
109 .resource = smc91x_resources,
110};
111#endif
112
113#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
114static struct resource sl811_hcd_resources[] = {
115 {
116 .start = 0x20340000,
117 .end = 0x20340000,
118 .flags = IORESOURCE_MEM,
119 },{
120 .start = 0x20340004,
121 .end = 0x20340004,
122 .flags = IORESOURCE_MEM,
123 },{
124 .start = CONFIG_USB_SL811_BFIN_IRQ,
125 .end = CONFIG_USB_SL811_BFIN_IRQ,
126 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
127 },
128};
129
130#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
131void sl811_port_power(struct device *dev, int is_on)
132{
133 unsigned short mask = (1 << CONFIG_USB_SL811_BFIN_GPIO_VBUS);
134
135 bfin_write_PORT_FER(bfin_read_PORT_FER() & ~mask);
136 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | mask);
137
138 if (is_on)
139 bfin_write_FIO_FLAG_S(mask);
140 else
141 bfin_write_FIO_FLAG_C(mask);
142}
143#endif
144
145static struct sl811_platform_data sl811_priv = {
146 .potpg = 10,
147 .power = 250, /* == 500mA */
148#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
149 .port_power = &sl811_port_power,
150#endif
151};
152
153static struct platform_device sl811_hcd_device = {
154 .name = "sl811-hcd",
155 .id = 0,
156 .dev = {
157 .platform_data = &sl811_priv,
158 },
159 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
160 .resource = sl811_hcd_resources,
161};
162#endif
163
164#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
165static struct resource isp1362_hcd_resources[] = {
166 {
167 .start = 0x20360000,
168 .end = 0x20360000,
169 .flags = IORESOURCE_MEM,
170 },{
171 .start = 0x20360004,
172 .end = 0x20360004,
173 .flags = IORESOURCE_MEM,
174 },{
175 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
176 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
177 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
178 },
179};
180
181static struct isp1362_platform_data isp1362_priv = {
182 .sel15Kres = 1,
183 .clknotstop = 0,
184 .oc_enable = 0,
185 .int_act_high = 0,
186 .int_edge_triggered = 0,
187 .remote_wakeup_connected = 0,
188 .no_power_switching = 1,
189 .power_switching_mode = 0,
190};
191
192static struct platform_device isp1362_hcd_device = {
193 .name = "isp1362-hcd",
194 .id = 0,
195 .dev = {
196 .platform_data = &isp1362_priv,
197 },
198 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
199 .resource = isp1362_hcd_resources,
200};
201#endif
202
203#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
204static struct platform_device bfin_mac_device = {
205 .name = "bfin_mac",
206};
207#endif
208
209#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
210static struct resource net2272_bfin_resources[] = {
211 {
212 .start = 0x20300000,
213 .end = 0x20300000 + 0x100,
214 .flags = IORESOURCE_MEM,
215 },{
216 .start = IRQ_PF7,
217 .end = IRQ_PF7,
218 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
219 },
220};
221
222static struct platform_device net2272_bfin_device = {
223 .name = "net2272",
224 .id = -1,
225 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
226 .resource = net2272_bfin_resources,
227};
228#endif
229
230#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
231/* all SPI peripherals info goes here */
232
233#if defined(CONFIG_MTD_M25P80) \
234 || defined(CONFIG_MTD_M25P80_MODULE)
235static struct mtd_partition bfin_spi_flash_partitions[] = {
236 {
237 .name = "bootloader",
238 .size = 0x00020000,
239 .offset = 0,
240 .mask_flags = MTD_CAP_ROM
241 },{
242 .name = "kernel",
243 .size = 0xe0000,
244 .offset = 0x20000
245 },{
246 .name = "file system",
247 .size = 0x700000,
248 .offset = 0x00100000,
249 }
250};
251
252static struct flash_platform_data bfin_spi_flash_data = {
253 .name = "m25p80",
254 .parts = bfin_spi_flash_partitions,
255 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
256 .type = "m25p64",
257};
258
259/* SPI flash chip (m25p64) */
260static struct bfin5xx_spi_chip spi_flash_chip_info = {
261 .enable_dma = 0, /* use dma transfer with this chip*/
262 .bits_per_word = 8,
263};
264#endif
265
266#if defined(CONFIG_SPI_ADC_BF533) \
267 || defined(CONFIG_SPI_ADC_BF533_MODULE)
268/* SPI ADC chip */
269static struct bfin5xx_spi_chip spi_adc_chip_info = {
270 .enable_dma = 1, /* use dma transfer with this chip*/
271 .bits_per_word = 16,
272};
273#endif
274
275#if defined(CONFIG_SND_BLACKFIN_AD1836) \
276 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
277static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
278 .enable_dma = 0,
279 .bits_per_word = 16,
280};
281#endif
282
283#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
284static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
285 .enable_dma = 0,
286 .bits_per_word = 16,
287};
288#endif
289
290#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
291static struct bfin5xx_spi_chip spi_mmc_chip_info = {
292 .enable_dma = 1,
293 .bits_per_word = 8,
294};
295#endif
296
297#if defined(CONFIG_PBX)
298static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
299 .ctl_reg = 0x4, /* send zero */
300 .enable_dma = 0,
301 .bits_per_word = 8,
302 .cs_change_per_word = 1,
303};
304#endif
305
306
307#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
308static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
309 .cs_change_per_word = 1,
310 .enable_dma = 0,
311 .bits_per_word = 16,
312};
313
314static const struct ad7877_platform_data bfin_ad7877_ts_info = {
315 .model = 7877,
316 .vref_delay_usecs = 50, /* internal, no capacitor */
317 .x_plate_ohms = 419,
318 .y_plate_ohms = 486,
319 .pressure_max = 1000,
320 .pressure_min = 0,
321 .stopacq_polarity = 1,
322 .first_conversion_delay = 3,
323 .acquisition_time = 1,
324 .averaging = 1,
325 .pen_down_acc_interval = 1,
326};
327#endif
328
329static struct spi_board_info bfin_spi_board_info[] __initdata = {
330#if defined(CONFIG_MTD_M25P80) \
331 || defined(CONFIG_MTD_M25P80_MODULE)
332 {
333 /* the modalias must be the same as spi device driver name */
334 .modalias = "m25p80", /* Name of spi_driver for this device */
335 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
336 .bus_num = 1, /* Framework bus number */
337 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
338 .platform_data = &bfin_spi_flash_data,
339 .controller_data = &spi_flash_chip_info,
340 .mode = SPI_MODE_3,
341 },
342#endif
343
344#if defined(CONFIG_SPI_ADC_BF533) \
345 || defined(CONFIG_SPI_ADC_BF533_MODULE)
346 {
347 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
348 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
349 .bus_num = 1, /* Framework bus number */
350 .chip_select = 1, /* Framework chip select. */
351 .platform_data = NULL, /* No spi_driver specific config */
352 .controller_data = &spi_adc_chip_info,
353 },
354#endif
355
356#if defined(CONFIG_SND_BLACKFIN_AD1836) \
357 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
358 {
359 .modalias = "ad1836-spi",
360 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
361 .bus_num = 1,
362 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
363 .controller_data = &ad1836_spi_chip_info,
364 },
365#endif
366#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
367 {
368 .modalias = "ad9960-spi",
369 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
370 .bus_num = 1,
371 .chip_select = 1,
372 .controller_data = &ad9960_spi_chip_info,
373 },
374#endif
375#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
376 {
377 .modalias = "spi_mmc_dummy",
378 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
379 .bus_num = 1,
380 .chip_select = 7,
381 .platform_data = NULL,
382 .controller_data = &spi_mmc_chip_info,
383 .mode = SPI_MODE_3,
384 },
385 {
386 .modalias = "spi_mmc",
387 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
388 .bus_num = 1,
389 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
390 .platform_data = NULL,
391 .controller_data = &spi_mmc_chip_info,
392 .mode = SPI_MODE_3,
393 },
394#endif
395#if defined(CONFIG_PBX)
396 {
397 .modalias = "fxs-spi",
398 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
399 .bus_num = 1,
400 .chip_select = 3,
401 .controller_data= &spi_si3xxx_chip_info,
402 .mode = SPI_MODE_3,
403 },
404 {
405 .modalias = "fxo-spi",
406 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
407 .bus_num = 1,
408 .chip_select = 2,
409 .controller_data= &spi_si3xxx_chip_info,
410 .mode = SPI_MODE_3,
411 },
412#endif
413#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
414{
415 .modalias = "ad7877",
416 .platform_data = &bfin_ad7877_ts_info,
417 .irq = IRQ_PF2,
418 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
419 .bus_num = 1,
420 .chip_select = 5,
421 .controller_data = &spi_ad7877_chip_info,
422},
423#endif
424
425};
426
427/* SPI controller data */
428static struct bfin5xx_spi_master spi_bfin_master_info = {
429 .num_chipselect = 8,
430 .enable_dma = 1, /* master has the ability to do dma transfer */
431};
432
433static struct platform_device spi_bfin_master_device = {
434 .name = "bfin-spi-master",
435 .id = 1, /* Bus number */
436 .dev = {
437 .platform_data = &spi_bfin_master_info, /* Passed to driver */
438 },
439};
440#endif /* spi master and devices */
441
442#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
443static struct platform_device bfin_fb_device = {
444 .name = "bf537-fb",
445};
446#endif
447
448#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
449static struct resource bfin_uart_resources[] = {
450 {
451 .start = 0xFFC00400,
452 .end = 0xFFC004FF,
453 .flags = IORESOURCE_MEM,
454 },{
455 .start = 0xFFC02000,
456 .end = 0xFFC020FF,
457 .flags = IORESOURCE_MEM,
458 },
459};
460
461static struct platform_device bfin_uart_device = {
462 .name = "bfin-uart",
463 .id = 1,
464 .num_resources = ARRAY_SIZE(bfin_uart_resources),
465 .resource = bfin_uart_resources,
466};
467#endif
468
469
470static struct platform_device *stamp_devices[] __initdata = {
471#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
472 &bfin_pcmcia_cf_device,
473#endif
474
475#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
476 &rtc_device,
477#endif
478
479#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
480 &sl811_hcd_device,
481#endif
482
483#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
484 &isp1362_hcd_device,
485#endif
486
487#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
488 &smc91x_device,
489#endif
490
491#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
492 &bfin_mac_device,
493#endif
494
495#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
496 &net2272_bfin_device,
497#endif
498
499#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
500 &spi_bfin_master_device,
501#endif
502
503#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
504 &bfin_fb_device,
505#endif
506
507#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
508 &bfin_uart_device,
509#endif
510};
511
512static int __init stamp_init(void)
513{
514 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
515 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
516#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
517 spi_register_board_info(bfin_spi_board_info,
518 ARRAY_SIZE(bfin_spi_board_info));
519#endif
520 return 0;
521}
522
523arch_initcall(stamp_init);
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
new file mode 100644
index 00000000000..ba2f875a7f7
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -0,0 +1,615 @@
1/*
2 * File: arch/blackfin/mach-bf537/boards/stamp.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h>
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
38#include <linux/usb_isp1362.h>
39#endif
40#include <asm/irq.h>
41#include <linux/irq.h>
42#include <linux/interrupt.h>
43#include <asm/bfin5xx_spi.h>
44#include <linux/usb_sl811.h>
45
46#include <linux/spi/ad7877.h>
47
48/*
49 * Name the Board for the /proc/cpuinfo
50 */
51char *bfin_board_name = "ADDS-BF537-STAMP";
52
53/*
54 * Driver needs to know address, irq and flag pin.
55 */
56
57#define ISP1761_BASE 0x203C0000
58#define ISP1761_IRQ IRQ_PF7
59
60#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
61static struct resource bfin_isp1761_resources[] = {
62 [0] = {
63 .name = "isp1761-regs",
64 .start = ISP1761_BASE + 0x00000000,
65 .end = ISP1761_BASE + 0x000fffff,
66 .flags = IORESOURCE_MEM,
67 },
68 [1] = {
69 .start = ISP1761_IRQ,
70 .end = ISP1761_IRQ,
71 .flags = IORESOURCE_IRQ,
72 },
73};
74
75static struct platform_device bfin_isp1761_device = {
76 .name = "isp1761",
77 .id = 0,
78 .num_resources = ARRAY_SIZE(bfin_isp1761_resources),
79 .resource = bfin_isp1761_resources,
80};
81
82static struct platform_device *bfin_isp1761_devices[] = {
83 &bfin_isp1761_device,
84};
85
86int __init bfin_isp1761_init(void)
87{
88 unsigned int num_devices=ARRAY_SIZE(bfin_isp1761_devices);
89
90 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
91 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
92
93 return platform_add_devices(bfin_isp1761_devices, num_devices);
94}
95
96void __exit bfin_isp1761_exit(void)
97{
98 platform_device_unregister(&bfin_isp1761_device);
99}
100
101arch_initcall(bfin_isp1761_init);
102#endif
103
104#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
105static struct resource bfin_pcmcia_cf_resources[] = {
106 {
107 .start = 0x20310000, /* IO PORT */
108 .end = 0x20312000,
109 .flags = IORESOURCE_MEM,
110 },{
111 .start = 0x20311000, /* Attribute Memeory */
112 .end = 0x20311FFF,
113 .flags = IORESOURCE_MEM,
114 },{
115 .start = IRQ_PF4,
116 .end = IRQ_PF4,
117 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
118 },{
119 .start = 6, /* Card Detect PF6 */
120 .end = 6,
121 .flags = IORESOURCE_IRQ,
122 },
123};
124
125static struct platform_device bfin_pcmcia_cf_device = {
126 .name = "bfin_cf_pcmcia",
127 .id = -1,
128 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
129 .resource = bfin_pcmcia_cf_resources,
130};
131#endif
132
133#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
134static struct platform_device rtc_device = {
135 .name = "rtc-bfin",
136 .id = -1,
137};
138#endif
139
140#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
141static struct resource smc91x_resources[] = {
142 {
143 .name = "smc91x-regs",
144 .start = 0x20300300,
145 .end = 0x20300300 + 16,
146 .flags = IORESOURCE_MEM,
147 },{
148
149 .start = IRQ_PF7,
150 .end = IRQ_PF7,
151 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
152 },
153};
154static struct platform_device smc91x_device = {
155 .name = "smc91x",
156 .id = 0,
157 .num_resources = ARRAY_SIZE(smc91x_resources),
158 .resource = smc91x_resources,
159};
160#endif
161
162#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
163static struct resource sl811_hcd_resources[] = {
164 {
165 .start = 0x20340000,
166 .end = 0x20340000,
167 .flags = IORESOURCE_MEM,
168 },{
169 .start = 0x20340004,
170 .end = 0x20340004,
171 .flags = IORESOURCE_MEM,
172 },{
173 .start = CONFIG_USB_SL811_BFIN_IRQ,
174 .end = CONFIG_USB_SL811_BFIN_IRQ,
175 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
176 },
177};
178
179#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
180void sl811_port_power(struct device *dev, int is_on)
181{
182 unsigned short mask = (1 << CONFIG_USB_SL811_BFIN_GPIO_VBUS);
183
184 bfin_write_PORT_FER(bfin_read_PORT_FER() & ~mask);
185 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | mask);
186
187 if (is_on)
188 bfin_write_FIO_FLAG_S(mask);
189 else
190 bfin_write_FIO_FLAG_C(mask);
191}
192#endif
193
194static struct sl811_platform_data sl811_priv = {
195 .potpg = 10,
196 .power = 250, /* == 500mA */
197#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
198 .port_power = &sl811_port_power,
199#endif
200};
201
202static struct platform_device sl811_hcd_device = {
203 .name = "sl811-hcd",
204 .id = 0,
205 .dev = {
206 .platform_data = &sl811_priv,
207 },
208 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
209 .resource = sl811_hcd_resources,
210};
211#endif
212
213#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
214static struct resource isp1362_hcd_resources[] = {
215 {
216 .start = 0x20360000,
217 .end = 0x20360000,
218 .flags = IORESOURCE_MEM,
219 },{
220 .start = 0x20360004,
221 .end = 0x20360004,
222 .flags = IORESOURCE_MEM,
223 },{
224 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
225 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
226 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
227 },
228};
229
230static struct isp1362_platform_data isp1362_priv = {
231 .sel15Kres = 1,
232 .clknotstop = 0,
233 .oc_enable = 0,
234 .int_act_high = 0,
235 .int_edge_triggered = 0,
236 .remote_wakeup_connected = 0,
237 .no_power_switching = 1,
238 .power_switching_mode = 0,
239};
240
241static struct platform_device isp1362_hcd_device = {
242 .name = "isp1362-hcd",
243 .id = 0,
244 .dev = {
245 .platform_data = &isp1362_priv,
246 },
247 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
248 .resource = isp1362_hcd_resources,
249};
250#endif
251
252#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
253static struct platform_device bfin_mac_device = {
254 .name = "bfin_mac",
255};
256#endif
257
258#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
259static struct resource net2272_bfin_resources[] = {
260 {
261 .start = 0x20300000,
262 .end = 0x20300000 + 0x100,
263 .flags = IORESOURCE_MEM,
264 },{
265 .start = IRQ_PF7,
266 .end = IRQ_PF7,
267 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
268 },
269};
270
271static struct platform_device net2272_bfin_device = {
272 .name = "net2272",
273 .id = -1,
274 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
275 .resource = net2272_bfin_resources,
276};
277#endif
278
279#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
280/* all SPI peripherals info goes here */
281
282#if defined(CONFIG_MTD_M25P80) \
283 || defined(CONFIG_MTD_M25P80_MODULE)
284static struct mtd_partition bfin_spi_flash_partitions[] = {
285 {
286 .name = "bootloader",
287 .size = 0x00020000,
288 .offset = 0,
289 .mask_flags = MTD_CAP_ROM
290 },{
291 .name = "kernel",
292 .size = 0xe0000,
293 .offset = 0x20000
294 },{
295 .name = "file system",
296 .size = 0x700000,
297 .offset = 0x00100000,
298 }
299};
300
301static struct flash_platform_data bfin_spi_flash_data = {
302 .name = "m25p80",
303 .parts = bfin_spi_flash_partitions,
304 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
305 .type = "m25p64",
306};
307
308/* SPI flash chip (m25p64) */
309static struct bfin5xx_spi_chip spi_flash_chip_info = {
310 .enable_dma = 0, /* use dma transfer with this chip*/
311 .bits_per_word = 8,
312};
313#endif
314
315#if defined(CONFIG_SPI_ADC_BF533) \
316 || defined(CONFIG_SPI_ADC_BF533_MODULE)
317/* SPI ADC chip */
318static struct bfin5xx_spi_chip spi_adc_chip_info = {
319 .enable_dma = 1, /* use dma transfer with this chip*/
320 .bits_per_word = 16,
321};
322#endif
323
324#if defined(CONFIG_SND_BLACKFIN_AD1836) \
325 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
326static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
327 .enable_dma = 0,
328 .bits_per_word = 16,
329};
330#endif
331
332#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
333static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
334 .enable_dma = 0,
335 .bits_per_word = 16,
336};
337#endif
338
339#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
340static struct bfin5xx_spi_chip spi_mmc_chip_info = {
341 .enable_dma = 1,
342 .bits_per_word = 8,
343};
344#endif
345
346#if defined(CONFIG_PBX)
347static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
348 .ctl_reg = 0x4, /* send zero */
349 .enable_dma = 0,
350 .bits_per_word = 8,
351 .cs_change_per_word = 1,
352};
353#endif
354
355#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
356static struct bfin5xx_spi_chip ad5304_chip_info = {
357 .enable_dma = 0,
358 .bits_per_word = 16,
359};
360#endif
361
362#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
363static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
364// .cs_change_per_word = 1,
365 .enable_dma = 0,
366 .bits_per_word = 16,
367};
368
369static const struct ad7877_platform_data bfin_ad7877_ts_info = {
370 .model = 7877,
371 .vref_delay_usecs = 50, /* internal, no capacitor */
372 .x_plate_ohms = 419,
373 .y_plate_ohms = 486,
374 .pressure_max = 1000,
375 .pressure_min = 0,
376 .stopacq_polarity = 1,
377 .first_conversion_delay = 3,
378 .acquisition_time = 1,
379 .averaging = 1,
380 .pen_down_acc_interval = 1,
381};
382#endif
383
384static struct spi_board_info bfin_spi_board_info[] __initdata = {
385#if defined(CONFIG_MTD_M25P80) \
386 || defined(CONFIG_MTD_M25P80_MODULE)
387 {
388 /* the modalias must be the same as spi device driver name */
389 .modalias = "m25p80", /* Name of spi_driver for this device */
390 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
391 .bus_num = 1, /* Framework bus number */
392 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
393 .platform_data = &bfin_spi_flash_data,
394 .controller_data = &spi_flash_chip_info,
395 .mode = SPI_MODE_3,
396 },
397#endif
398
399#if defined(CONFIG_SPI_ADC_BF533) \
400 || defined(CONFIG_SPI_ADC_BF533_MODULE)
401 {
402 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
403 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
404 .bus_num = 1, /* Framework bus number */
405 .chip_select = 1, /* Framework chip select. */
406 .platform_data = NULL, /* No spi_driver specific config */
407 .controller_data = &spi_adc_chip_info,
408 },
409#endif
410
411#if defined(CONFIG_SND_BLACKFIN_AD1836) \
412 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
413 {
414 .modalias = "ad1836-spi",
415 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
416 .bus_num = 1,
417 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
418 .controller_data = &ad1836_spi_chip_info,
419 },
420#endif
421#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
422 {
423 .modalias = "ad9960-spi",
424 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
425 .bus_num = 1,
426 .chip_select = 1,
427 .controller_data = &ad9960_spi_chip_info,
428 },
429#endif
430#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
431 {
432 .modalias = "spi_mmc_dummy",
433 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
434 .bus_num = 1,
435 .chip_select = 0,
436 .platform_data = NULL,
437 .controller_data = &spi_mmc_chip_info,
438 .mode = SPI_MODE_3,
439 },
440 {
441 .modalias = "spi_mmc",
442 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
443 .bus_num = 1,
444 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
445 .platform_data = NULL,
446 .controller_data = &spi_mmc_chip_info,
447 .mode = SPI_MODE_3,
448 },
449#endif
450#if defined(CONFIG_PBX)
451 {
452 .modalias = "fxs-spi",
453 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
454 .bus_num = 1,
455 .chip_select = 3,
456 .controller_data= &spi_si3xxx_chip_info,
457 .mode = SPI_MODE_3,
458 },
459 {
460 .modalias = "fxo-spi",
461 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
462 .bus_num = 1,
463 .chip_select = 2,
464 .controller_data= &spi_si3xxx_chip_info,
465 .mode = SPI_MODE_3,
466 },
467#endif
468#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
469 {
470 .modalias = "ad5304_spi",
471 .max_speed_hz = 1250000, /* max spi clock (SCK) speed in HZ */
472 .bus_num = 1,
473 .chip_select = 2,
474 .platform_data = NULL,
475 .controller_data = &ad5304_chip_info,
476 .mode = SPI_MODE_2,
477 },
478#endif
479#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
480 {
481 .modalias = "ad7877",
482 .platform_data = &bfin_ad7877_ts_info,
483 .irq = IRQ_PF6,
484 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
485 .bus_num = 1,
486 .chip_select = 1,
487 .controller_data = &spi_ad7877_chip_info,
488 },
489#endif
490};
491
492/* SPI controller data */
493static struct bfin5xx_spi_master spi_bfin_master_info = {
494 .num_chipselect = 8,
495 .enable_dma = 1, /* master has the ability to do dma transfer */
496};
497
498static struct platform_device spi_bfin_master_device = {
499 .name = "bfin-spi-master",
500 .id = 1, /* Bus number */
501 .dev = {
502 .platform_data = &spi_bfin_master_info, /* Passed to driver */
503 },
504};
505#endif /* spi master and devices */
506
507#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
508static struct platform_device bfin_fb_device = {
509 .name = "bf537-fb",
510};
511#endif
512
513#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
514static struct resource bfin_uart_resources[] = {
515 {
516 .start = 0xFFC00400,
517 .end = 0xFFC004FF,
518 .flags = IORESOURCE_MEM,
519 },{
520 .start = 0xFFC02000,
521 .end = 0xFFC020FF,
522 .flags = IORESOURCE_MEM,
523 },
524};
525
526static struct platform_device bfin_uart_device = {
527 .name = "bfin-uart",
528 .id = 1,
529 .num_resources = ARRAY_SIZE(bfin_uart_resources),
530 .resource = bfin_uart_resources,
531};
532#endif
533
534#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
535static struct platform_device i2c_bfin_twi_device = {
536 .name = "i2c-bfin-twi",
537 .id = 0,
538};
539#endif
540
541#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
542static struct platform_device bfin_sport0_uart_device = {
543 .name = "bfin-sport-uart",
544 .id = 0,
545};
546
547static struct platform_device bfin_sport1_uart_device = {
548 .name = "bfin-sport-uart",
549 .id = 1,
550};
551#endif
552
553static struct platform_device *stamp_devices[] __initdata = {
554#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
555 &bfin_pcmcia_cf_device,
556#endif
557
558#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
559 &rtc_device,
560#endif
561
562#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
563 &sl811_hcd_device,
564#endif
565
566#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
567 &isp1362_hcd_device,
568#endif
569
570#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
571 &smc91x_device,
572#endif
573
574#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
575 &bfin_mac_device,
576#endif
577
578#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
579 &net2272_bfin_device,
580#endif
581
582#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
583 &spi_bfin_master_device,
584#endif
585
586#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
587 &bfin_fb_device,
588#endif
589
590#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
591 &bfin_uart_device,
592#endif
593
594#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
595 &i2c_bfin_twi_device,
596#endif
597
598#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
599 &bfin_sport0_uart_device,
600 &bfin_sport1_uart_device,
601#endif
602};
603
604static int __init stamp_init(void)
605{
606 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
607 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
608#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
609 spi_register_board_info(bfin_spi_board_info,
610 ARRAY_SIZE(bfin_spi_board_info));
611#endif
612 return 0;
613}
614
615arch_initcall(stamp_init);
diff --git a/arch/blackfin/mach-bf537/cpu.c b/arch/blackfin/mach-bf537/cpu.c
new file mode 100644
index 00000000000..2d83b7e3546
--- /dev/null
+++ b/arch/blackfin/mach-bf537/cpu.c
@@ -0,0 +1,161 @@
1/*
2 * File: arch/blackfin/mach-bf537/cpu.c
3 * Based on:
4 * Author: michael.kang@analog.com
5 *
6 * Created:
7 * Description: clock scaling for the bf537
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/init.h>
33#include <linux/cpufreq.h>
34#include <asm/dpmc.h>
35#include <linux/fs.h>
36#include <asm/bfin-global.h>
37
38/* CONFIG_CLKIN_HZ=11059200 */
39#define VCO5 (CONFIG_CLKIN_HZ*45) /*497664000 */
40#define VCO4 (CONFIG_CLKIN_HZ*36) /*398131200 */
41#define VCO3 (CONFIG_CLKIN_HZ*27) /*298598400 */
42#define VCO2 (CONFIG_CLKIN_HZ*18) /*199065600 */
43#define VCO1 (CONFIG_CLKIN_HZ*9) /*99532800 */
44#define VCO(x) VCO##x
45
46#define FREQ(x) {VCO(x),VCO(x)/4},{VCO(x),VCO(x)/2},{VCO(x),VCO(x)}
47/* frequency */
48static struct cpufreq_frequency_table bf537_freq_table[] = {
49 FREQ(1),
50 FREQ(3),
51 {VCO4, VCO4 / 2}, {VCO4, VCO4},
52 FREQ(5),
53 {0, CPUFREQ_TABLE_END},
54};
55
56/*
57 * dpmc_fops->ioctl()
58 * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
59 */
60static int bf537_getfreq(unsigned int cpu)
61{
62 unsigned long cclk_mhz, vco_mhz;
63
64 /* The driver only support single cpu */
65 if (cpu == 0)
66 dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz);
67 else
68 cclk_mhz = -1;
69 return cclk_mhz;
70}
71
72static int bf537_target(struct cpufreq_policy *policy,
73 unsigned int target_freq, unsigned int relation)
74{
75 unsigned long cclk_mhz;
76 unsigned long vco_mhz;
77 unsigned long flags;
78 unsigned int index, vco_index;
79 int i;
80
81 struct cpufreq_freqs freqs;
82 if (cpufreq_frequency_table_target
83 (policy, bf537_freq_table, target_freq, relation, &index))
84 return -EINVAL;
85 cclk_mhz = bf537_freq_table[index].frequency;
86 vco_mhz = bf537_freq_table[index].index;
87
88 dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz);
89 freqs.old = bf537_getfreq(0);
90 freqs.new = cclk_mhz;
91 freqs.cpu = 0;
92
93 pr_debug("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n",
94 cclk_mhz, vco_mhz, index, target_freq, freqs.old);
95
96 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
97 local_irq_save(flags);
98 dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz);
99 local_irq_restore(flags);
100 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
101
102 vco_mhz = get_vco();
103 cclk_mhz = get_cclk();
104 return 0;
105}
106
107/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
108 * this platform, anyway.
109 */
110static int bf537_verify_speed(struct cpufreq_policy *policy)
111{
112 return cpufreq_frequency_table_verify(policy, &bf537_freq_table);
113}
114
115static int __init __bf537_cpu_init(struct cpufreq_policy *policy)
116{
117 int result;
118
119 if (policy->cpu != 0)
120 return -EINVAL;
121
122 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
123
124 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
125 /*Now ,only support one cpu */
126 policy->cur = bf537_getfreq(0);
127 cpufreq_frequency_table_get_attr(bf537_freq_table, policy->cpu);
128 return cpufreq_frequency_table_cpuinfo(policy, bf537_freq_table);
129}
130
131static struct freq_attr *bf537_freq_attr[] = {
132 &cpufreq_freq_attr_scaling_available_freqs,
133 NULL,
134};
135
136static struct cpufreq_driver bf537_driver = {
137 .verify = bf537_verify_speed,
138 .target = bf537_target,
139 .get = bf537_getfreq,
140 .init = __bf537_cpu_init,
141 .name = "bf537",
142 .owner = THIS_MODULE,
143 .attr = bf537_freq_attr,
144};
145
146static int __init bf537_cpu_init(void)
147{
148 return cpufreq_register_driver(&bf537_driver);
149}
150
151static void __exit bf537_cpu_exit(void)
152{
153 cpufreq_unregister_driver(&bf537_driver);
154}
155
156MODULE_AUTHOR("Mickael Kang");
157MODULE_DESCRIPTION("cpufreq driver for BF537 CPU");
158MODULE_LICENSE("GPL");
159
160module_init(bf537_cpu_init);
161module_exit(bf537_cpu_exit);
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
new file mode 100644
index 00000000000..d104e1d8e07
--- /dev/null
+++ b/arch/blackfin/mach-bf537/head.S
@@ -0,0 +1,602 @@
1/*
2 * File: arch/blackfin/mach-bf537/head.S
3 * Based on: arch/blackfin/mach-bf533/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5 *
6 * Created: 1998
7 * Description: Startup code for Blackfin BF537
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <asm/blackfin.h>
32#if CONFIG_BFIN_KERNEL_CLOCK
33#include <asm/mach/mem_init.h>
34#endif
35
36.global __rambase
37.global __ramstart
38.global __ramend
39.extern ___bss_stop
40.extern ___bss_start
41.extern _bf53x_relocate_l1_mem
42
43#define INITIAL_STACK 0xFFB01000
44
45.text
46
47ENTRY(__start)
48ENTRY(__stext)
49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0;
51 /* Set the SYSCFG register */
52 R0 = 0x36;
53 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
54 R0 = 0;
55
56 /* Clear Out All the data and pointer Registers*/
57 R1 = R0;
58 R2 = R0;
59 R3 = R0;
60 R4 = R0;
61 R5 = R0;
62 R6 = R0;
63
64 P0 = R0;
65 P1 = R0;
66 P2 = R0;
67 P3 = R0;
68 P4 = R0;
69 P5 = R0;
70
71 LC0 = r0;
72 LC1 = r0;
73 L0 = r0;
74 L1 = r0;
75 L2 = r0;
76 L3 = r0;
77
78 /* Clear Out All the DAG Registers*/
79 B0 = r0;
80 B1 = r0;
81 B2 = r0;
82 B3 = r0;
83
84 I0 = r0;
85 I1 = r0;
86 I2 = r0;
87 I3 = r0;
88
89 M0 = r0;
90 M1 = r0;
91 M2 = r0;
92 M3 = r0;
93
94 /* Turn off the icache */
95 p0.l = (IMEM_CONTROL & 0xFFFF);
96 p0.h = (IMEM_CONTROL >> 16);
97 R1 = [p0];
98 R0 = ~ENICPLB;
99 R0 = R0 & R1;
100
101 /* Anomaly 05000125 */
102#ifdef ANOMALY_05000125
103 CLI R2;
104 SSYNC;
105#endif
106 [p0] = R0;
107 SSYNC;
108#ifdef ANOMALY_05000125
109 STI R2;
110#endif
111
112 /* Turn off the dcache */
113 p0.l = (DMEM_CONTROL & 0xFFFF);
114 p0.h = (DMEM_CONTROL >> 16);
115 R1 = [p0];
116 R0 = ~ENDCPLB;
117 R0 = R0 & R1;
118
119 /* Anomaly 05000125 */
120#ifdef ANOMALY_05000125
121 CLI R2;
122 SSYNC;
123#endif
124 [p0] = R0;
125 SSYNC;
126#ifdef ANOMALY_05000125
127 STI R2;
128#endif
129
130 /* Initialise General-Purpose I/O Modules on BF537 */
131 /* Rev 0.0 Anomaly 05000212 - PORTx_FER,
132 * PORT_MUX Registers Do Not accept "writes" correctly:
133 */
134 p0.h = hi(BFIN_PORT_MUX);
135 p0.l = lo(BFIN_PORT_MUX);
136#ifdef ANOMALY_05000212
137 R0.L = W[P0]; /* Read */
138 SSYNC;
139#endif
140 R0 = (PGDE_UART | PFTE_UART)(Z);
141#ifdef ANOMALY_05000212
142 W[P0] = R0.L; /* Write */
143 SSYNC;
144#endif
145 W[P0] = R0.L; /* Enable both UARTS */
146 SSYNC;
147
148 p0.h = hi(PORTF_FER);
149 p0.l = lo(PORTF_FER);
150#ifdef ANOMALY_05000212
151 R0.L = W[P0]; /* Read */
152 SSYNC;
153#endif
154 R0 = 0x000F(Z);
155#ifdef ANOMALY_05000212
156 W[P0] = R0.L; /* Write */
157 SSYNC;
158#endif
159 /* Enable peripheral function of PORTF for UART0 and UART1 */
160 W[P0] = R0.L;
161 SSYNC;
162
163#if !defined(CONFIG_BF534)
164 p0.h = hi(EMAC_SYSTAT);
165 p0.l = lo(EMAC_SYSTAT);
166 R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
167 R0.l = 0xFFFF;
168 [P0] = R0;
169 SSYNC;
170#endif
171
172#ifdef CONFIG_BF537_PORT_H
173 p0.h = hi(PORTH_FER);
174 p0.l = lo(PORTH_FER);
175 R0.L = W[P0]; /* Read */
176 SSYNC;
177 R0 = 0x0000;
178 W[P0] = R0.L; /* Write */
179 SSYNC;
180 W[P0] = R0.L; /* Disable peripheral function of PORTH */
181 SSYNC;
182#endif
183
184 /*Initialise UART*/
185 p0.h = hi(UART_LCR);
186 p0.l = lo(UART_LCR);
187 r0 = 0x0(Z);
188 w[p0] = r0.L; /* To enable DLL writes */
189 ssync;
190
191 p0.h = hi(UART_DLL);
192 p0.l = lo(UART_DLL);
193 r0 = 0x00(Z);
194 w[p0] = r0.L;
195 ssync;
196
197 p0.h = hi(UART_DLH);
198 p0.l = lo(UART_DLH);
199 r0 = 0x00(Z);
200 w[p0] = r0.L;
201 ssync;
202
203 p0.h = hi(UART_GCTL);
204 p0.l = lo(UART_GCTL);
205 r0 = 0x0(Z);
206 w[p0] = r0.L; /* To enable UART clock */
207 ssync;
208
209 /* Initialize stack pointer */
210 sp.l = lo(INITIAL_STACK);
211 sp.h = hi(INITIAL_STACK);
212 fp = sp;
213 usp = sp;
214
215 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
216 call _bf53x_relocate_l1_mem;
217#if CONFIG_BFIN_KERNEL_CLOCK
218 call _start_dma_code;
219#endif
220 /* Code for initializing Async memory banks */
221
222 p2.h = hi(EBIU_AMBCTL1);
223 p2.l = lo(EBIU_AMBCTL1);
224 r0.h = hi(AMBCTL1VAL);
225 r0.l = lo(AMBCTL1VAL);
226 [p2] = r0;
227 ssync;
228
229 p2.h = hi(EBIU_AMBCTL0);
230 p2.l = lo(EBIU_AMBCTL0);
231 r0.h = hi(AMBCTL0VAL);
232 r0.l = lo(AMBCTL0VAL);
233 [p2] = r0;
234 ssync;
235
236 p2.h = hi(EBIU_AMGCTL);
237 p2.l = lo(EBIU_AMGCTL);
238 r0 = AMGCTLVAL;
239 w[p2] = r0;
240 ssync;
241
242 /* This section keeps the processor in supervisor mode
243 * during kernel boot. Switches to user mode at end of boot.
244 * See page 3-9 of Hardware Reference manual for documentation.
245 */
246
247 /* EVT15 = _real_start */
248
249 p0.l = lo(EVT15);
250 p0.h = hi(EVT15);
251 p1.l = _real_start;
252 p1.h = _real_start;
253 [p0] = p1;
254 csync;
255
256 p0.l = lo(IMASK);
257 p0.h = hi(IMASK);
258 p1.l = IMASK_IVG15;
259 p1.h = 0x0;
260 [p0] = p1;
261 csync;
262
263 raise 15;
264 p0.l = .LWAIT_HERE;
265 p0.h = .LWAIT_HERE;
266 reti = p0;
267#if defined(ANOMALY_05000281)
268 nop; nop; nop;
269#endif
270 rti;
271
272.LWAIT_HERE:
273 jump .LWAIT_HERE;
274
275ENTRY(_real_start)
276 [ -- sp ] = reti;
277 p0.l = lo(WDOG_CTL);
278 p0.h = hi(WDOG_CTL);
279 r0 = 0xAD6(z);
280 w[p0] = r0; /* watchdog off for now */
281 ssync;
282
283 /* Code update for BSS size == 0
284 * Zero out the bss region.
285 */
286
287 p1.l = ___bss_start;
288 p1.h = ___bss_start;
289 p2.l = ___bss_stop;
290 p2.h = ___bss_stop;
291 r0 = 0;
292 p2 -= p1;
293 lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
294.L_clear_bss:
295 B[p1++] = r0;
296
297 /* In case there is a NULL pointer reference
298 * Zero out region before stext
299 */
300
301 p1.l = 0x0;
302 p1.h = 0x0;
303 r0.l = __stext;
304 r0.h = __stext;
305 r0 = r0 >> 1;
306 p2 = r0;
307 r0 = 0;
308 lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
309.L_clear_zero:
310 W[p1++] = r0;
311
312 /* pass the uboot arguments to the global value command line */
313 R0 = R7;
314 call _cmdline_init;
315
316 p1.l = __rambase;
317 p1.h = __rambase;
318 r0.l = __sdata;
319 r0.h = __sdata;
320 [p1] = r0;
321
322 p1.l = __ramstart;
323 p1.h = __ramstart;
324 p3.l = ___bss_stop;
325 p3.h = ___bss_stop;
326
327 r1 = p3;
328 [p1] = r1;
329
330
331 /*
332 * load the current thread pointer and stack
333 */
334 r1.l = _init_thread_union;
335 r1.h = _init_thread_union;
336
337 r2.l = 0x2000;
338 r2.h = 0x0000;
339 r1 = r1 + r2;
340 sp = r1;
341 usp = sp;
342 fp = sp;
343 call _start_kernel;
344.L_exit:
345 jump.s .L_exit;
346
347.section .l1.text
348#if CONFIG_BFIN_KERNEL_CLOCK
349ENTRY(_start_dma_code)
350
351 /* Enable PHY CLK buffer output */
352 p0.h = hi(VR_CTL);
353 p0.l = lo(VR_CTL);
354 r0.l = w[p0];
355 bitset(r0, 14);
356 w[p0] = r0.l;
357 ssync;
358
359 p0.h = hi(SIC_IWR);
360 p0.l = lo(SIC_IWR);
361 r0.l = 0x1;
362 r0.h = 0x0;
363 [p0] = r0;
364 SSYNC;
365
366 /*
367 * Set PLL_CTL
368 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
369 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
370 * - [7] = output delay (add 200ps of delay to mem signals)
371 * - [6] = input delay (add 200ps of input delay to mem signals)
372 * - [5] = PDWN : 1=All Clocks off
373 * - [3] = STOPCK : 1=Core Clock off
374 * - [1] = PLL_OFF : 1=Disable Power to PLL
375 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
376 * all other bits set to zero
377 */
378
379 p0.h = hi(PLL_LOCKCNT);
380 p0.l = lo(PLL_LOCKCNT);
381 r0 = 0x300(Z);
382 w[p0] = r0.l;
383 ssync;
384
385 P2.H = hi(EBIU_SDGCTL);
386 P2.L = lo(EBIU_SDGCTL);
387 R0 = [P2];
388 BITSET (R0, 24);
389 [P2] = R0;
390 SSYNC;
391
392 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
393 r0 = r0 << 9; /* Shift it over, */
394 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
395 r0 = r1 | r0;
396 r1 = PLL_BYPASS; /* Bypass the PLL? */
397 r1 = r1 << 8; /* Shift it over */
398 r0 = r1 | r0; /* add them all together */
399
400 p0.h = hi(PLL_CTL);
401 p0.l = lo(PLL_CTL); /* Load the address */
402 cli r2; /* Disable interrupts */
403 ssync;
404 w[p0] = r0.l; /* Set the value */
405 idle; /* Wait for the PLL to stablize */
406 sti r2; /* Enable interrupts */
407
408.Lcheck_again:
409 p0.h = hi(PLL_STAT);
410 p0.l = lo(PLL_STAT);
411 R0 = W[P0](Z);
412 CC = BITTST(R0,5);
413 if ! CC jump .Lcheck_again;
414
415 /* Configure SCLK & CCLK Dividers */
416 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
417 p0.h = hi(PLL_DIV);
418 p0.l = lo(PLL_DIV);
419 w[p0] = r0.l;
420 ssync;
421
422 p0.l = lo(EBIU_SDRRC);
423 p0.h = hi(EBIU_SDRRC);
424 r0 = mem_SDRRC;
425 w[p0] = r0.l;
426 ssync;
427
428 p0.l = (EBIU_SDBCTL & 0xFFFF);
429 p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
430 r0 = mem_SDBCTL;
431 w[p0] = r0.l;
432 ssync;
433
434 P2.H = hi(EBIU_SDGCTL);
435 P2.L = lo(EBIU_SDGCTL);
436 R0 = [P2];
437 BITCLR (R0, 24);
438 p0.h = hi(EBIU_SDSTAT);
439 p0.l = lo(EBIU_SDSTAT);
440 r2.l = w[p0];
441 cc = bittst(r2,3);
442 if !cc jump .Lskip;
443 NOP;
444 BITSET (R0, 23);
445.Lskip:
446 [P2] = R0;
447 SSYNC;
448
449 R0.L = lo(mem_SDGCTL);
450 R0.H = hi(mem_SDGCTL);
451 R1 = [p2];
452 R1 = R1 | R0;
453 [P2] = R1;
454 SSYNC;
455
456 p0.h = hi(SIC_IWR);
457 p0.l = lo(SIC_IWR);
458 r0.l = lo(IWR_ENABLE_ALL);
459 r0.h = hi(IWR_ENABLE_ALL);
460 [p0] = r0;
461 SSYNC;
462
463 RTS;
464#endif /* CONFIG_BFIN_KERNEL_CLOCK */
465
466ENTRY(_bfin_reset)
467 /* No more interrupts to be handled*/
468 CLI R6;
469 SSYNC;
470
471#if defined(CONFIG_MTD_M25P80)
472/*
473 * The following code fix the SPI flash reboot issue,
474 * /CS signal of the chip which is using PF10 return to GPIO mode
475 */
476 p0.h = hi(PORTF_FER);
477 p0.l = lo(PORTF_FER);
478 r0.l = 0x0000;
479 w[p0] = r0.l;
480 SSYNC;
481
482/* /CS return to high */
483 p0.h = hi(PORTFIO);
484 p0.l = lo(PORTFIO);
485 r0.l = 0xFFFF;
486 w[p0] = r0.l;
487 SSYNC;
488
489/* Delay some time, This is necessary */
490 r1.h = 0;
491 r1.l = 0x400;
492 p1 = r1;
493 lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1;
494_delay_lab1:
495 r0.h = 0;
496 r0.l = 0x8000;
497 p0 = r0;
498 lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0;
499_delay_lab0:
500 nop;
501_delay_lab0_end:
502 nop;
503_delay_lab1_end:
504 nop;
505#endif
506
507 /* Clear the bits 13-15 in SWRST if they werent cleared */
508 p0.h = hi(SWRST);
509 p0.l = lo(SWRST);
510 csync;
511 r0.l = w[p0];
512
513 /* Clear the IMASK register */
514 p0.h = hi(IMASK);
515 p0.l = lo(IMASK);
516 r0 = 0x0;
517 [p0] = r0;
518
519 /* Clear the ILAT register */
520 p0.h = hi(ILAT);
521 p0.l = lo(ILAT);
522 r0 = [p0];
523 [p0] = r0;
524 SSYNC;
525
526 /* Disable the WDOG TIMER */
527 p0.h = hi(WDOG_CTL);
528 p0.l = lo(WDOG_CTL);
529 r0.l = 0xAD6;
530 w[p0] = r0.l;
531 SSYNC;
532
533 /* Clear the sticky bit incase it is already set */
534 p0.h = hi(WDOG_CTL);
535 p0.l = lo(WDOG_CTL);
536 r0.l = 0x8AD6;
537 w[p0] = r0.l;
538 SSYNC;
539
540 /* Program the count value */
541 R0.l = 0x100;
542 R0.h = 0x0;
543 P0.h = hi(WDOG_CNT);
544 P0.l = lo(WDOG_CNT);
545 [P0] = R0;
546 SSYNC;
547
548 /* Program WDOG_STAT if necessary */
549 P0.h = hi(WDOG_CTL);
550 P0.l = lo(WDOG_CTL);
551 R0 = W[P0](Z);
552 CC = BITTST(R0,1);
553 if !CC JUMP .LWRITESTAT;
554 CC = BITTST(R0,2);
555 if !CC JUMP .LWRITESTAT;
556 JUMP .LSKIP_WRITE;
557
558.LWRITESTAT:
559 /* When watch dog timer is enabled,
560 * a write to STAT will load the contents of CNT to STAT
561 */
562 R0 = 0x0000(z);
563 P0.h = hi(WDOG_STAT);
564 P0.l = lo(WDOG_STAT)
565 [P0] = R0;
566 SSYNC;
567
568.LSKIP_WRITE:
569 /* Enable the reset event */
570 P0.h = hi(WDOG_CTL);
571 P0.l = lo(WDOG_CTL);
572 R0 = W[P0](Z);
573 BITCLR(R0,1);
574 BITCLR(R0,2);
575 W[P0] = R0.L;
576 SSYNC;
577 NOP;
578
579 /* Enable the wdog counter */
580 R0 = W[P0](Z);
581 BITCLR(R0,4);
582 W[P0] = R0.L;
583 SSYNC;
584
585 IDLE;
586
587 RTS;
588
589.data
590
591/*
592 * Set up the usable of RAM stuff. Size of RAM is determined then
593 * an initial stack set up at the end.
594 */
595
596.align 4
597__rambase:
598.long 0
599__ramstart:
600.long 0
601__ramend:
602.long 0
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
new file mode 100644
index 00000000000..fd6308eccbe
--- /dev/null
+++ b/arch/blackfin/mach-bf537/ints-priority.c
@@ -0,0 +1,74 @@
1/*
2 * File: arch/blackfin/mach-bf537/ints-priority.c
3 * Based on: arch/blackfin/mach-bf533/ints-priority.c
4 * Author: Michael Hennerich
5 *
6 * Created:
7 * Description: Set up the interupt priorities
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <asm/blackfin.h>
32#include <asm/irq.h>
33
34void program_IAR(void)
35{
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
38 ((CONFIG_IRQ_DMA_ERROR - 7) << IRQ_DMA_ERROR_POS) |
39 ((CONFIG_IRQ_ERROR - 7) << IRQ_ERROR_POS) |
40 ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
41 ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
42 ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
43 ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
44 ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS));
45
46 bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
47 ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
48 ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
49 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
50 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS) |
51 ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
52 ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
53 ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
54
55 bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
56 ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
57 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
58 ((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
59 ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
60 ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
61 ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) |
62 ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS));
63
64 bfin_write_SIC_IAR3(((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) |
65 ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) |
66 ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS) |
67 ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
68 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
69 ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
70 ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
71 ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
72
73 SSYNC();
74}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 15:48:15 -0400