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authorMike Frysinger <vapier@gentoo.org>2010-07-29 01:53:33 -0400
committerMike Frysinger <vapier@gentoo.org>2010-08-06 12:55:56 -0400
commit39750324053c2aa4314e460b5ce1767f4dfbeff1 (patch)
treefecee75496cdc5b3ab05dcb8f0c441b6ef8d408f /arch/blackfin/mach-bf518
parentc385acceb4db55a492cb16b24b6102af90348440 (diff)
Blackfin: unify rotary encoder bitmasks
Avoid duplication and ugly global namespace pollution. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf518')
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h108
1 files changed, 0 insertions, 108 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index 543c53da88b..2bc8f4f9801 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -1576,114 +1576,6 @@
1576 1576
1577#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ 1577#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1578 1578
1579/* Bit masks for CNT_CONFIG */
1580
1581#define CNTE 0x1 /* Counter Enable */
1582#define nCNTE 0x0
1583#define DEBE 0x2 /* Debounce Enable */
1584#define nDEBE 0x0
1585#define CDGINV 0x10 /* CDG Pin Polarity Invert */
1586#define nCDGINV 0x0
1587#define CUDINV 0x20 /* CUD Pin Polarity Invert */
1588#define nCUDINV 0x0
1589#define CZMINV 0x40 /* CZM Pin Polarity Invert */
1590#define nCZMINV 0x0
1591#define CNTMODE 0x700 /* Counter Operating Mode */
1592#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
1593#define nZMZC 0x0
1594#define BNDMODE 0x3000 /* Boundary register Mode */
1595#define INPDIS 0x8000 /* CUG and CDG Input Disable */
1596#define nINPDIS 0x0
1597
1598/* Bit masks for CNT_IMASK */
1599
1600#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
1601#define nICIE 0x0
1602#define UCIE 0x2 /* Up count Interrupt Enable */
1603#define nUCIE 0x0
1604#define DCIE 0x4 /* Down count Interrupt Enable */
1605#define nDCIE 0x0
1606#define MINCIE 0x8 /* Min Count Interrupt Enable */
1607#define nMINCIE 0x0
1608#define MAXCIE 0x10 /* Max Count Interrupt Enable */
1609#define nMAXCIE 0x0
1610#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
1611#define nCOV31IE 0x0
1612#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
1613#define nCOV15IE 0x0
1614#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
1615#define nCZEROIE 0x0
1616#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
1617#define nCZMIE 0x0
1618#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
1619#define nCZMEIE 0x0
1620#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
1621#define nCZMZIE 0x0
1622
1623/* Bit masks for CNT_STATUS */
1624
1625#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
1626#define nICII 0x0
1627#define UCII 0x2 /* Up count Interrupt Identifier */
1628#define nUCII 0x0
1629#define DCII 0x4 /* Down count Interrupt Identifier */
1630#define nDCII 0x0
1631#define MINCII 0x8 /* Min Count Interrupt Identifier */
1632#define nMINCII 0x0
1633#define MAXCII 0x10 /* Max Count Interrupt Identifier */
1634#define nMAXCII 0x0
1635#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
1636#define nCOV31II 0x0
1637#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
1638#define nCOV15II 0x0
1639#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
1640#define nCZEROII 0x0
1641#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
1642#define nCZMII 0x0
1643#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
1644#define nCZMEII 0x0
1645#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
1646#define nCZMZII 0x0
1647
1648/* Bit masks for CNT_COMMAND */
1649
1650#define W1LCNT 0xf /* Load Counter Register */
1651#define W1LMIN 0xf0 /* Load Min Register */
1652#define W1LMAX 0xf00 /* Load Max Register */
1653#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
1654#define nW1ZMONCE 0x0
1655
1656/* Bit masks for CNT_DEBOUNCE */
1657
1658#define DPRESCALE 0xf /* Load Counter Register */
1659
1660/* CNT_COMMAND bit field options */
1661
1662#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
1663#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
1664#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
1665
1666#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
1667#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
1668#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
1669
1670#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
1671#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
1672#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
1673
1674/* CNT_CONFIG bit field options */
1675
1676#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
1677#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
1678#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
1679#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
1680#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
1681
1682#define BNDMODE_COMP 0x0000 /* boundary compare mode */
1683#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
1684#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
1685#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
1686
1687/* Bit masks for SECURE_SYSSWT */ 1579/* Bit masks for SECURE_SYSSWT */
1688 1580
1689#define EMUDABL 0x1 /* Emulation Disable. */ 1581#define EMUDABL 0x1 /* Emulation Disable. */