diff options
| author | MyungJoo Ham <myungjoo.ham@samsung.com> | 2011-07-20 22:21:56 -0400 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-07-20 22:21:56 -0400 |
| commit | d40474c819b484ded7da520a174117b65d56e1c1 (patch) | |
| tree | 6d074e66b81236911be5c1ccf258201e801ba0c5 /arch/arm | |
| parent | d79195897e610bd0d3563ec401cfd29d836ce0e6 (diff) | |
ARM: EXYNOS4: Add more register addresses of CMU
These registers are crucial for PM to work properly.
Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-exynos4/include/mach/regs-clock.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h index 64bdd240f88..d493fdb422f 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h | |||
| @@ -36,7 +36,9 @@ | |||
| 36 | #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) | 36 | #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) |
| 37 | #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) | 37 | #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) |
| 38 | #define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) | 38 | #define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) |
| 39 | #define S5P_CLKSRC_TV S5P_CLKREG(0x0C224) | ||
| 39 | #define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) | 40 | #define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) |
| 41 | #define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C) | ||
| 40 | #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) | 42 | #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) |
| 41 | #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) | 43 | #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) |
| 42 | #define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) | 44 | #define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) |
| @@ -64,6 +66,7 @@ | |||
| 64 | #define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) | 66 | #define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) |
| 65 | #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) | 67 | #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) |
| 66 | #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) | 68 | #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) |
| 69 | #define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580) | ||
| 67 | 70 | ||
| 68 | #define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) | 71 | #define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) |
| 69 | #define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) | 72 | #define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) |