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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-22 18:50:46 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-22 18:50:46 -0400
commita481991467d38afb43c3921d5b5b59ccb61b04ba (patch)
treea4b0b9a14da6fd5ef7b9b512bb32dbfcfcf2cd71 /arch/arm
parentf6a26ae7699416d86bea8cb68ce413571e9cab3c (diff)
parentcda4db53e9c28061c100400e1a4d273ea61dfba9 (diff)
Merge tag 'usb-3.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB 3.5-rc1 changes from Greg Kroah-Hartman: "Here is the big USB 3.5-rc1 pull request for the 3.5-rc1 merge window. It's touches a lot of different parts of the kernel, all USB drivers, due to some API cleanups (getting rid of the ancient err() macro) and some changes that are needed for USB 3.0 power management updates. There are also lots of new drivers, pimarily gadget, but others as well. We deleted a staging driver, which was nice, and finally dropped the obsolete usbfs code, which will make Al happy to never have to touch that again. There were some build errors in the tree that linux-next found a few days ago, but those were fixed by the most recent changes (all were due to us not building with CONFIG_PM disabled.) Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>" * tag 'usb-3.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (477 commits) xhci: Fix DIV_ROUND_UP compile error. xhci: Fix compile with CONFIG_USB_SUSPEND=n USB: Fix core compile with CONFIG_USB_SUSPEND=n brcm80211: Fix compile error for .disable_hub_initiated_lpm. Revert "USB: EHCI: work around bug in the Philips ISP1562 controller" MAINTAINERS: Add myself as maintainer to the USB PHY Layer USB: EHCI: fix command register configuration lost problem USB: Remove races in devio.c USB: ehci-platform: remove update_device USB: Disable hub-initiated LPM for comms devices. xhci: Add Intel U1/U2 timeout policy. xhci: Add infrastructure for host-specific LPM policies. USB: Add macros for interrupt endpoint types. xhci: Reserve one command for USB3 LPM disable. xhci: Some Evaluate Context commands must succeed. USB: Disable USB 3.0 LPM in critical sections. USB: Add support to enable/disable USB3 link states. USB: Allow drivers to disable hub-initiated LPM. USB: Calculate USB 3.0 exit latencies for LPM. USB: Refactor code to set LPM support flag. ... Conflicts: arch/arm/mach-exynos/mach-nuri.c arch/arm/mach-exynos/mach-universal_c210.c drivers/net/wireless/ath/ath6kl/usb.c
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-exynos/Kconfig3
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h4
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h3
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c10
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c11
-rw-r--r--arch/arm/mach-exynos/setup-usb-phy.c100
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smartq.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c2
-rw-r--r--arch/arm/mach-s5pv210/Kconfig1
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c6
-rw-r--r--arch/arm/plat-samsung/devs.c2
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h379
-rw-r--r--arch/arm/plat-samsung/include/plat/udc-hs.h34
15 files changed, 114 insertions, 446 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 2808e471cdc..15b05b89cc3 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -251,6 +251,7 @@ config MACH_UNIVERSAL_C210
251 select S3C_DEV_I2C1 251 select S3C_DEV_I2C1
252 select S3C_DEV_I2C3 252 select S3C_DEV_I2C3
253 select S3C_DEV_I2C5 253 select S3C_DEV_I2C5
254 select S3C_DEV_USB_HSOTG
254 select S5P_DEV_I2C_HDMIPHY 255 select S5P_DEV_I2C_HDMIPHY
255 select S5P_DEV_MFC 256 select S5P_DEV_MFC
256 select S5P_DEV_ONENAND 257 select S5P_DEV_ONENAND
@@ -264,6 +265,7 @@ config MACH_UNIVERSAL_C210
264 select EXYNOS4_SETUP_SDHCI 265 select EXYNOS4_SETUP_SDHCI
265 select EXYNOS4_SETUP_FIMC 266 select EXYNOS4_SETUP_FIMC
266 select S5P_SETUP_MIPIPHY 267 select S5P_SETUP_MIPIPHY
268 select EXYNOS4_SETUP_USB_PHY
267 help 269 help
268 Machine support for Samsung Mobile Universal S5PC210 Reference 270 Machine support for Samsung Mobile Universal S5PC210 Reference
269 Board. 271 Board.
@@ -282,6 +284,7 @@ config MACH_NURI
282 select S3C_DEV_I2C3 284 select S3C_DEV_I2C3
283 select S3C_DEV_I2C5 285 select S3C_DEV_I2C5
284 select S3C_DEV_I2C6 286 select S3C_DEV_I2C6
287 select S3C_DEV_USB_HSOTG
285 select S5P_DEV_CSIS0 288 select S5P_DEV_CSIS0
286 select S5P_DEV_JPEG 289 select S5P_DEV_JPEG
287 select S5P_DEV_FIMC0 290 select S5P_DEV_FIMC0
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 591e78521a9..c02dae7bf4a 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -189,6 +189,7 @@
189#define IRQ_IIC7 EXYNOS4_IRQ_IIC7 189#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
190 190
191#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST 191#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
192#define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG
192 193
193#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0 194#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
194#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1 195#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 6e6d11ff352..e009a66477f 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -130,6 +130,9 @@
130#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 130#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
131#define EXYNOS4_PA_DWMCI 0x12550000 131#define EXYNOS4_PA_DWMCI 0x12550000
132 132
133#define EXYNOS4_PA_HSOTG 0x12480000
134#define EXYNOS4_PA_USB_HSPHY 0x125B0000
135
133#define EXYNOS4_PA_SATA 0x12560000 136#define EXYNOS4_PA_SATA 0x12560000
134#define EXYNOS4_PA_SATAPHY 0x125D0000 137#define EXYNOS4_PA_SATAPHY 0x125D0000
135#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000 138#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
@@ -186,6 +189,7 @@
186#define S3C_PA_SPI0 EXYNOS4_PA_SPI0 189#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
187#define S3C_PA_SPI1 EXYNOS4_PA_SPI1 190#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
188#define S3C_PA_SPI2 EXYNOS4_PA_SPI2 191#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
192#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG
189 193
190#define S5P_PA_EHCI EXYNOS4_PA_EHCI 194#define S5P_PA_EHCI EXYNOS4_PA_EHCI
191#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 195#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4c53f38b5a9..d457d052a42 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -163,6 +163,9 @@
163#define S5P_CHECK_SLEEP 0x00000BAD 163#define S5P_CHECK_SLEEP 0x00000BAD
164 164
165/* Only for EXYNOS4210 */ 165/* Only for EXYNOS4210 */
166#define S5P_USBDEVICE_PHY_CONTROL S5P_PMUREG(0x0704)
167#define S5P_USBDEVICE_PHY_ENABLE (1 << 0)
168
166#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) 169#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
167#define S5P_USBHOST_PHY_ENABLE (1 << 0) 170#define S5P_USBHOST_PHY_ENABLE (1 << 0)
168 171
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 5784b0abfe9..6c31f2ad765 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -25,6 +25,7 @@
25#include <linux/mmc/host.h> 25#include <linux/mmc/host.h>
26#include <linux/fb.h> 26#include <linux/fb.h>
27#include <linux/pwm_backlight.h> 27#include <linux/pwm_backlight.h>
28#include <linux/platform_data/s3c-hsotg.h>
28#include <drm/exynos_drm.h> 29#include <drm/exynos_drm.h>
29 30
30#include <video/platform_lcd.h> 31#include <video/platform_lcd.h>
@@ -373,6 +374,7 @@ static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
373 REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */ 374 REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
374}; 375};
375static struct regulator_consumer_supply __initdata max8997_ldo3_[] = { 376static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
377 REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */
376 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */ 378 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
377}; 379};
378static struct regulator_consumer_supply __initdata max8997_ldo4_[] = { 380static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
@@ -388,7 +390,7 @@ static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
388 REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */ 390 REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
389}; 391};
390static struct regulator_consumer_supply __initdata max8997_ldo8_[] = { 392static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
391 REGULATOR_SUPPLY("vusb_d", NULL), /* Used by CPU */ 393 REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* USB */
392 REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */ 394 REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
393}; 395};
394static struct regulator_consumer_supply __initdata max8997_ldo11_[] = { 396static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
@@ -844,6 +846,7 @@ static struct regulator_init_data __initdata max8997_esafeout1_data = {
844 .constraints = { 846 .constraints = {
845 .name = "SAFEOUT1", 847 .name = "SAFEOUT1",
846 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 848 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
849 .always_on = 1,
847 .state_mem = { 850 .state_mem = {
848 .disabled = 1, 851 .disabled = 1,
849 }, 852 },
@@ -1101,6 +1104,9 @@ static void __init nuri_ehci_init(void)
1101 s5p_ehci_set_platdata(pdata); 1104 s5p_ehci_set_platdata(pdata);
1102} 1105}
1103 1106
1107/* USB OTG */
1108static struct s3c_hsotg_plat nuri_hsotg_pdata;
1109
1104/* CAMERA */ 1110/* CAMERA */
1105static struct regulator_consumer_supply cam_vt_cam15_supply = 1111static struct regulator_consumer_supply cam_vt_cam15_supply =
1106 REGULATOR_SUPPLY("vdd_core", "6-003c"); 1112 REGULATOR_SUPPLY("vdd_core", "6-003c");
@@ -1313,6 +1319,7 @@ static struct platform_device *nuri_devices[] __initdata = {
1313 &s5p_device_mfc_l, 1319 &s5p_device_mfc_l,
1314 &s5p_device_mfc_r, 1320 &s5p_device_mfc_r,
1315 &s5p_device_fimc_md, 1321 &s5p_device_fimc_md,
1322 &s3c_device_usb_hsotg,
1316 1323
1317 /* NURI Devices */ 1324 /* NURI Devices */
1318 &nuri_gpio_keys, 1325 &nuri_gpio_keys,
@@ -1369,6 +1376,7 @@ static void __init nuri_machine_init(void)
1369 nuri_camera_init(); 1376 nuri_camera_init();
1370 1377
1371 nuri_ehci_init(); 1378 nuri_ehci_init();
1379 s3c_hsotg_set_platdata(&nuri_hsotg_pdata);
1372 1380
1373 /* Last */ 1381 /* Last */
1374 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); 1382 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 27fab5389d7..6b731b86327 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -23,6 +23,7 @@
23#include <linux/i2c-gpio.h> 23#include <linux/i2c-gpio.h>
24#include <linux/i2c/mcs.h> 24#include <linux/i2c/mcs.h>
25#include <linux/i2c/atmel_mxt_ts.h> 25#include <linux/i2c/atmel_mxt_ts.h>
26#include <linux/platform_data/s3c-hsotg.h>
26#include <drm/exynos_drm.h> 27#include <drm/exynos_drm.h>
27 28
28#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
@@ -206,6 +207,7 @@ static struct regulator_init_data lp3974_ldo2_data = {
206}; 207};
207 208
208static struct regulator_consumer_supply lp3974_ldo3_consumer[] = { 209static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
210 REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
209 REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), 211 REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
210 REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), 212 REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
211 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), 213 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
@@ -291,6 +293,7 @@ static struct regulator_init_data lp3974_ldo7_data = {
291}; 293};
292 294
293static struct regulator_consumer_supply lp3974_ldo8_consumer[] = { 295static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
296 REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
294 REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"), 297 REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
295}; 298};
296 299
@@ -487,7 +490,10 @@ static struct regulator_init_data lp3974_vichg_data = {
487static struct regulator_init_data lp3974_esafeout1_data = { 490static struct regulator_init_data lp3974_esafeout1_data = {
488 .constraints = { 491 .constraints = {
489 .name = "SAFEOUT1", 492 .name = "SAFEOUT1",
493 .min_uV = 4800000,
494 .max_uV = 4800000,
490 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 495 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
496 .always_on = 1,
491 .state_mem = { 497 .state_mem = {
492 .enabled = 1, 498 .enabled = 1,
493 }, 499 },
@@ -1017,6 +1023,9 @@ static struct gpio universal_camera_gpios[] = {
1017 { GPIO_CAM_VGA_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" }, 1023 { GPIO_CAM_VGA_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
1018}; 1024};
1019 1025
1026/* USB OTG */
1027static struct s3c_hsotg_plat universal_hsotg_pdata;
1028
1020static void __init universal_camera_init(void) 1029static void __init universal_camera_init(void)
1021{ 1030{
1022 s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata), 1031 s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
@@ -1075,6 +1084,7 @@ static struct platform_device *universal_devices[] __initdata = {
1075#ifdef CONFIG_DRM_EXYNOS 1084#ifdef CONFIG_DRM_EXYNOS
1076 &exynos_device_drm, 1085 &exynos_device_drm,
1077#endif 1086#endif
1087 &s3c_device_usb_hsotg,
1078 &s5p_device_mfc, 1088 &s5p_device_mfc,
1079 &s5p_device_mfc_l, 1089 &s5p_device_mfc_l,
1080 &s5p_device_mfc_r, 1090 &s5p_device_mfc_r,
@@ -1133,6 +1143,7 @@ static void __init universal_machine_init(void)
1133 i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs, 1143 i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
1134 ARRAY_SIZE(i2c_gpio12_devs)); 1144 ARRAY_SIZE(i2c_gpio12_devs));
1135 1145
1146 s3c_hsotg_set_platdata(&universal_hsotg_pdata);
1136 universal_camera_init(); 1147 universal_camera_init();
1137 1148
1138 /* Last */ 1149 /* Last */
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 41743d21e8c..1af0a7f44e0 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -26,11 +26,71 @@ static int exynos4_usb_host_phy_is_on(void)
26 return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1; 26 return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
27} 27}
28 28
29static int exynos4_usb_phy1_init(struct platform_device *pdev) 29static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
30{ 30{
31 struct clk *otg_clk;
32 struct clk *xusbxti_clk; 31 struct clk *xusbxti_clk;
33 u32 phyclk; 32 u32 phyclk;
33
34 /* set clock frequency for PLL */
35 phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
36
37 xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
38 if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
39 switch (clk_get_rate(xusbxti_clk)) {
40 case 12 * MHZ:
41 phyclk |= CLKSEL_12M;
42 break;
43 case 24 * MHZ:
44 phyclk |= CLKSEL_24M;
45 break;
46 default:
47 case 48 * MHZ:
48 /* default reference clock */
49 break;
50 }
51 clk_put(xusbxti_clk);
52 }
53
54 writel(phyclk, EXYNOS4_PHYCLK);
55}
56
57static int exynos4210_usb_phy0_init(struct platform_device *pdev)
58{
59 u32 rstcon;
60
61 writel(readl(S5P_USBDEVICE_PHY_CONTROL) | S5P_USBDEVICE_PHY_ENABLE,
62 S5P_USBDEVICE_PHY_CONTROL);
63
64 exynos4210_usb_phy_clkset(pdev);
65
66 /* set to normal PHY0 */
67 writel((readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK), EXYNOS4_PHYPWR);
68
69 /* reset PHY0 and Link */
70 rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
71 writel(rstcon, EXYNOS4_RSTCON);
72 udelay(10);
73
74 rstcon &= ~PHY0_SWRST_MASK;
75 writel(rstcon, EXYNOS4_RSTCON);
76
77 return 0;
78}
79
80static int exynos4210_usb_phy0_exit(struct platform_device *pdev)
81{
82 writel((readl(EXYNOS4_PHYPWR) | PHY0_ANALOG_POWERDOWN |
83 PHY0_OTG_DISABLE), EXYNOS4_PHYPWR);
84
85 writel(readl(S5P_USBDEVICE_PHY_CONTROL) & ~S5P_USBDEVICE_PHY_ENABLE,
86 S5P_USBDEVICE_PHY_CONTROL);
87
88 return 0;
89}
90
91static int exynos4210_usb_phy1_init(struct platform_device *pdev)
92{
93 struct clk *otg_clk;
34 u32 rstcon; 94 u32 rstcon;
35 int err; 95 int err;
36 96
@@ -54,27 +114,7 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
54 writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE, 114 writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
55 S5P_USBHOST_PHY_CONTROL); 115 S5P_USBHOST_PHY_CONTROL);
56 116
57 /* set clock frequency for PLL */ 117 exynos4210_usb_phy_clkset(pdev);
58 phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
59
60 xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
61 if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
62 switch (clk_get_rate(xusbxti_clk)) {
63 case 12 * MHZ:
64 phyclk |= CLKSEL_12M;
65 break;
66 case 24 * MHZ:
67 phyclk |= CLKSEL_24M;
68 break;
69 default:
70 case 48 * MHZ:
71 /* default reference clock */
72 break;
73 }
74 clk_put(xusbxti_clk);
75 }
76
77 writel(phyclk, EXYNOS4_PHYCLK);
78 118
79 /* floating prevention logic: disable */ 119 /* floating prevention logic: disable */
80 writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON); 120 writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
@@ -102,7 +142,7 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
102 return 0; 142 return 0;
103} 143}
104 144
105static int exynos4_usb_phy1_exit(struct platform_device *pdev) 145static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
106{ 146{
107 struct clk *otg_clk; 147 struct clk *otg_clk;
108 int err; 148 int err;
@@ -136,16 +176,20 @@ static int exynos4_usb_phy1_exit(struct platform_device *pdev)
136 176
137int s5p_usb_phy_init(struct platform_device *pdev, int type) 177int s5p_usb_phy_init(struct platform_device *pdev, int type)
138{ 178{
139 if (type == S5P_USB_PHY_HOST) 179 if (type == S5P_USB_PHY_DEVICE)
140 return exynos4_usb_phy1_init(pdev); 180 return exynos4210_usb_phy0_init(pdev);
181 else if (type == S5P_USB_PHY_HOST)
182 return exynos4210_usb_phy1_init(pdev);
141 183
142 return -EINVAL; 184 return -EINVAL;
143} 185}
144 186
145int s5p_usb_phy_exit(struct platform_device *pdev, int type) 187int s5p_usb_phy_exit(struct platform_device *pdev, int type)
146{ 188{
147 if (type == S5P_USB_PHY_HOST) 189 if (type == S5P_USB_PHY_DEVICE)
148 return exynos4_usb_phy1_exit(pdev); 190 return exynos4210_usb_phy0_exit(pdev);
191 else if (type == S5P_USB_PHY_HOST)
192 return exynos4210_usb_phy1_exit(pdev);
149 193
150 return -EINVAL; 194 return -EINVAL;
151} 195}
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 0569765a8e9..aa1137fb47e 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -31,6 +31,7 @@
31#include <linux/spi/spi.h> 31#include <linux/spi/spi.h>
32 32
33#include <linux/i2c/pca953x.h> 33#include <linux/i2c/pca953x.h>
34#include <linux/platform_data/s3c-hsotg.h>
34 35
35#include <video/platform_lcd.h> 36#include <video/platform_lcd.h>
36 37
@@ -61,7 +62,6 @@
61#include <plat/sdhci.h> 62#include <plat/sdhci.h>
62#include <plat/gpio-cfg.h> 63#include <plat/gpio-cfg.h>
63#include <plat/s3c64xx-spi.h> 64#include <plat/s3c64xx-spi.h>
64#include <plat/udc-hs.h>
65 65
66#include <plat/keypad.h> 66#include <plat/keypad.h>
67#include <plat/clock.h> 67#include <plat/clock.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index ce745e19aa2..ceeb1de4037 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -18,6 +18,7 @@
18#include <linux/serial_core.h> 18#include <linux/serial_core.h>
19#include <linux/spi/spi_gpio.h> 19#include <linux/spi/spi_gpio.h>
20#include <linux/usb/gpio_vbus.h> 20#include <linux/usb/gpio_vbus.h>
21#include <linux/platform_data/s3c-hsotg.h>
21 22
22#include <asm/mach-types.h> 23#include <asm/mach-types.h>
23#include <asm/mach/map.h> 24#include <asm/mach/map.h>
@@ -33,7 +34,6 @@
33#include <plat/gpio-cfg.h> 34#include <plat/gpio-cfg.h>
34#include <plat/hwmon.h> 35#include <plat/hwmon.h>
35#include <plat/regs-serial.h> 36#include <plat/regs-serial.h>
36#include <plat/udc-hs.h>
37#include <plat/usb-control.h> 37#include <plat/usb-control.h>
38#include <plat/sdhci.h> 38#include <plat/sdhci.h>
39#include <plat/ts.h> 39#include <plat/ts.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 1ecd0485a9b..7da044f738a 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -30,6 +30,7 @@
30#include <linux/regulator/fixed.h> 30#include <linux/regulator/fixed.h>
31#include <linux/regulator/machine.h> 31#include <linux/regulator/machine.h>
32#include <linux/pwm_backlight.h> 32#include <linux/pwm_backlight.h>
33#include <linux/platform_data/s3c-hsotg.h>
33 34
34#ifdef CONFIG_SMDK6410_WM1190_EV1 35#ifdef CONFIG_SMDK6410_WM1190_EV1
35#include <linux/mfd/wm8350/core.h> 36#include <linux/mfd/wm8350/core.h>
@@ -72,7 +73,6 @@
72#include <plat/keypad.h> 73#include <plat/keypad.h>
73#include <plat/backlight.h> 74#include <plat/backlight.h>
74#include <plat/regs-fb-v4.h> 75#include <plat/regs-fb-v4.h>
75#include <plat/udc-hs.h>
76 76
77#include "common.h" 77#include "common.h"
78 78
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 29594fc4fdf..88e983b0c82 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -85,6 +85,7 @@ config MACH_AQUILA
85 select S5P_DEV_ONENAND 85 select S5P_DEV_ONENAND
86 select S5PV210_SETUP_FB_24BPP 86 select S5PV210_SETUP_FB_24BPP
87 select S5PV210_SETUP_SDHCI 87 select S5PV210_SETUP_SDHCI
88 select S5PV210_SETUP_USB_PHY
88 help 89 help
89 Machine support for the Samsung Aquila target based on S5PC110 SoC 90 Machine support for the Samsung Aquila target based on S5PC110 SoC
90 91
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 32395664e87..f20a97c8e41 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -27,6 +27,7 @@
27#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/mmc/host.h> 28#include <linux/mmc/host.h>
29#include <linux/interrupt.h> 29#include <linux/interrupt.h>
30#include <linux/platform_data/s3c-hsotg.h>
30 31
31#include <asm/hardware/vic.h> 32#include <asm/hardware/vic.h>
32#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
@@ -278,6 +279,9 @@ static void __init goni_tsp_init(void)
278 i2c2_devs[0].irq = gpio_to_irq(gpio); 279 i2c2_devs[0].irq = gpio_to_irq(gpio);
279} 280}
280 281
282/* USB OTG */
283static struct s3c_hsotg_plat goni_hsotg_pdata;
284
281static void goni_camera_init(void) 285static void goni_camera_init(void)
282{ 286{
283 s5pv210_fimc_setup_gpio(S5P_CAMPORT_A); 287 s5pv210_fimc_setup_gpio(S5P_CAMPORT_A);
@@ -941,6 +945,8 @@ static void __init goni_machine_init(void)
941 s3c_set_platdata(&goni_fimc_md_platdata, sizeof(goni_fimc_md_platdata), 945 s3c_set_platdata(&goni_fimc_md_platdata, sizeof(goni_fimc_md_platdata),
942 &s5p_device_fimc_md); 946 &s5p_device_fimc_md);
943 947
948 s3c_hsotg_set_platdata(&goni_hsotg_pdata);
949
944 goni_camera_init(); 950 goni_camera_init();
945 951
946 /* SPI */ 952 /* SPI */
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 1013a341b0f..1d214cb9d77 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -30,6 +30,7 @@
30#include <linux/mmc/host.h> 30#include <linux/mmc/host.h>
31#include <linux/ioport.h> 31#include <linux/ioport.h>
32#include <linux/platform_data/s3c-hsudc.h> 32#include <linux/platform_data/s3c-hsudc.h>
33#include <linux/platform_data/s3c-hsotg.h>
33 34
34#include <asm/irq.h> 35#include <asm/irq.h>
35#include <asm/pmu.h> 36#include <asm/pmu.h>
@@ -57,7 +58,6 @@
57#include <plat/sdhci.h> 58#include <plat/sdhci.h>
58#include <plat/ts.h> 59#include <plat/ts.h>
59#include <plat/udc.h> 60#include <plat/udc.h>
60#include <plat/udc-hs.h>
61#include <plat/usb-control.h> 61#include <plat/usb-control.h>
62#include <plat/usb-phy.h> 62#include <plat/usb-phy.h>
63#include <plat/regs-iic.h> 63#include <plat/regs-iic.h>
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
deleted file mode 100644
index dc90f5ede88..00000000000
--- a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
+++ /dev/null
@@ -1,379 +0,0 @@
1/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - USB2.0 Highspeed/OtG device block registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H
16#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__
17
18#define S3C_HSOTG_REG(x) (x)
19
20#define S3C_GOTGCTL S3C_HSOTG_REG(0x000)
21#define S3C_GOTGCTL_BSESVLD (1 << 19)
22#define S3C_GOTGCTL_ASESVLD (1 << 18)
23#define S3C_GOTGCTL_DBNC_SHORT (1 << 17)
24#define S3C_GOTGCTL_CONID_B (1 << 16)
25#define S3C_GOTGCTL_DEVHNPEN (1 << 11)
26#define S3C_GOTGCTL_HSSETHNPEN (1 << 10)
27#define S3C_GOTGCTL_HNPREQ (1 << 9)
28#define S3C_GOTGCTL_HSTNEGSCS (1 << 8)
29#define S3C_GOTGCTL_SESREQ (1 << 1)
30#define S3C_GOTGCTL_SESREQSCS (1 << 0)
31
32#define S3C_GOTGINT S3C_HSOTG_REG(0x004)
33#define S3C_GOTGINT_DbnceDone (1 << 19)
34#define S3C_GOTGINT_ADevTOUTChg (1 << 18)
35#define S3C_GOTGINT_HstNegDet (1 << 17)
36#define S3C_GOTGINT_HstnegSucStsChng (1 << 9)
37#define S3C_GOTGINT_SesReqSucStsChng (1 << 8)
38#define S3C_GOTGINT_SesEndDet (1 << 2)
39
40#define S3C_GAHBCFG S3C_HSOTG_REG(0x008)
41#define S3C_GAHBCFG_PTxFEmpLvl (1 << 8)
42#define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7)
43#define S3C_GAHBCFG_DMAEn (1 << 5)
44#define S3C_GAHBCFG_HBstLen_MASK (0xf << 1)
45#define S3C_GAHBCFG_HBstLen_SHIFT (1)
46#define S3C_GAHBCFG_HBstLen_Single (0x0 << 1)
47#define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1)
48#define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1)
49#define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1)
50#define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1)
51#define S3C_GAHBCFG_GlblIntrEn (1 << 0)
52
53#define S3C_GUSBCFG S3C_HSOTG_REG(0x00C)
54#define S3C_GUSBCFG_PHYLPClkSel (1 << 15)
55#define S3C_GUSBCFG_HNPCap (1 << 9)
56#define S3C_GUSBCFG_SRPCap (1 << 8)
57#define S3C_GUSBCFG_PHYIf16 (1 << 3)
58#define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0)
59#define S3C_GUSBCFG_TOutCal_SHIFT (0)
60#define S3C_GUSBCFG_TOutCal_LIMIT (0x7)
61#define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0)
62
63#define S3C_GRSTCTL S3C_HSOTG_REG(0x010)
64
65#define S3C_GRSTCTL_AHBIdle (1 << 31)
66#define S3C_GRSTCTL_DMAReq (1 << 30)
67#define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6)
68#define S3C_GRSTCTL_TxFNum_SHIFT (6)
69#define S3C_GRSTCTL_TxFNum_LIMIT (0x1f)
70#define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6)
71#define S3C_GRSTCTL_TxFFlsh (1 << 5)
72#define S3C_GRSTCTL_RxFFlsh (1 << 4)
73#define S3C_GRSTCTL_INTknQFlsh (1 << 3)
74#define S3C_GRSTCTL_FrmCntrRst (1 << 2)
75#define S3C_GRSTCTL_HSftRst (1 << 1)
76#define S3C_GRSTCTL_CSftRst (1 << 0)
77
78#define S3C_GINTSTS S3C_HSOTG_REG(0x014)
79#define S3C_GINTMSK S3C_HSOTG_REG(0x018)
80
81#define S3C_GINTSTS_WkUpInt (1 << 31)
82#define S3C_GINTSTS_SessReqInt (1 << 30)
83#define S3C_GINTSTS_DisconnInt (1 << 29)
84#define S3C_GINTSTS_ConIDStsChng (1 << 28)
85#define S3C_GINTSTS_PTxFEmp (1 << 26)
86#define S3C_GINTSTS_HChInt (1 << 25)
87#define S3C_GINTSTS_PrtInt (1 << 24)
88#define S3C_GINTSTS_FetSusp (1 << 22)
89#define S3C_GINTSTS_incompIP (1 << 21)
90#define S3C_GINTSTS_IncomplSOIN (1 << 20)
91#define S3C_GINTSTS_OEPInt (1 << 19)
92#define S3C_GINTSTS_IEPInt (1 << 18)
93#define S3C_GINTSTS_EPMis (1 << 17)
94#define S3C_GINTSTS_EOPF (1 << 15)
95#define S3C_GINTSTS_ISOutDrop (1 << 14)
96#define S3C_GINTSTS_EnumDone (1 << 13)
97#define S3C_GINTSTS_USBRst (1 << 12)
98#define S3C_GINTSTS_USBSusp (1 << 11)
99#define S3C_GINTSTS_ErlySusp (1 << 10)
100#define S3C_GINTSTS_GOUTNakEff (1 << 7)
101#define S3C_GINTSTS_GINNakEff (1 << 6)
102#define S3C_GINTSTS_NPTxFEmp (1 << 5)
103#define S3C_GINTSTS_RxFLvl (1 << 4)
104#define S3C_GINTSTS_SOF (1 << 3)
105#define S3C_GINTSTS_OTGInt (1 << 2)
106#define S3C_GINTSTS_ModeMis (1 << 1)
107#define S3C_GINTSTS_CurMod_Host (1 << 0)
108
109#define S3C_GRXSTSR S3C_HSOTG_REG(0x01C)
110#define S3C_GRXSTSP S3C_HSOTG_REG(0x020)
111
112#define S3C_GRXSTS_FN_MASK (0x7f << 25)
113#define S3C_GRXSTS_FN_SHIFT (25)
114
115#define S3C_GRXSTS_PktSts_MASK (0xf << 17)
116#define S3C_GRXSTS_PktSts_SHIFT (17)
117#define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17)
118#define S3C_GRXSTS_PktSts_OutRX (0x2 << 17)
119#define S3C_GRXSTS_PktSts_OutDone (0x3 << 17)
120#define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17)
121#define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17)
122
123#define S3C_GRXSTS_DPID_MASK (0x3 << 15)
124#define S3C_GRXSTS_DPID_SHIFT (15)
125#define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4)
126#define S3C_GRXSTS_ByteCnt_SHIFT (4)
127#define S3C_GRXSTS_EPNum_MASK (0xf << 0)
128#define S3C_GRXSTS_EPNum_SHIFT (0)
129
130#define S3C_GRXFSIZ S3C_HSOTG_REG(0x024)
131
132#define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028)
133
134#define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16)
135#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16)
136#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff)
137#define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16)
138#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0)
139#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0)
140#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff)
141#define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0)
142
143#define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C)
144
145#define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24)
146#define S3C_GNPTXSTS_NPtxQTop_SHIFT (24)
147
148#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16)
149#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16)
150#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff)
151
152#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0)
153#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0)
154#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff)
155
156
157#define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100)
158
159#define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4))
160
161#define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16)
162#define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16)
163#define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff)
164#define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff)
165#define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16)
166
167#define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0)
168#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0)
169
170/* Device mode registers */
171#define S3C_DCFG S3C_HSOTG_REG(0x800)
172
173#define S3C_DCFG_EPMisCnt_MASK (0x1f << 18)
174#define S3C_DCFG_EPMisCnt_SHIFT (18)
175#define S3C_DCFG_EPMisCnt_LIMIT (0x1f)
176#define S3C_DCFG_EPMisCnt(_x) ((_x) << 18)
177
178#define S3C_DCFG_PerFrInt_MASK (0x3 << 11)
179#define S3C_DCFG_PerFrInt_SHIFT (11)
180#define S3C_DCFG_PerFrInt_LIMIT (0x3)
181#define S3C_DCFG_PerFrInt(_x) ((_x) << 11)
182
183#define S3C_DCFG_DevAddr_MASK (0x7f << 4)
184#define S3C_DCFG_DevAddr_SHIFT (4)
185#define S3C_DCFG_DevAddr_LIMIT (0x7f)
186#define S3C_DCFG_DevAddr(_x) ((_x) << 4)
187
188#define S3C_DCFG_NZStsOUTHShk (1 << 2)
189
190#define S3C_DCFG_DevSpd_MASK (0x3 << 0)
191#define S3C_DCFG_DevSpd_SHIFT (0)
192#define S3C_DCFG_DevSpd_HS (0x0 << 0)
193#define S3C_DCFG_DevSpd_FS (0x1 << 0)
194#define S3C_DCFG_DevSpd_LS (0x2 << 0)
195#define S3C_DCFG_DevSpd_FS48 (0x3 << 0)
196
197#define S3C_DCTL S3C_HSOTG_REG(0x804)
198
199#define S3C_DCTL_PWROnPrgDone (1 << 11)
200#define S3C_DCTL_CGOUTNak (1 << 10)
201#define S3C_DCTL_SGOUTNak (1 << 9)
202#define S3C_DCTL_CGNPInNAK (1 << 8)
203#define S3C_DCTL_SGNPInNAK (1 << 7)
204#define S3C_DCTL_TstCtl_MASK (0x7 << 4)
205#define S3C_DCTL_TstCtl_SHIFT (4)
206#define S3C_DCTL_GOUTNakSts (1 << 3)
207#define S3C_DCTL_GNPINNakSts (1 << 2)
208#define S3C_DCTL_SftDiscon (1 << 1)
209#define S3C_DCTL_RmtWkUpSig (1 << 0)
210
211#define S3C_DSTS S3C_HSOTG_REG(0x808)
212
213#define S3C_DSTS_SOFFN_MASK (0x3fff << 8)
214#define S3C_DSTS_SOFFN_SHIFT (8)
215#define S3C_DSTS_SOFFN_LIMIT (0x3fff)
216#define S3C_DSTS_SOFFN(_x) ((_x) << 8)
217#define S3C_DSTS_ErraticErr (1 << 3)
218#define S3C_DSTS_EnumSpd_MASK (0x3 << 1)
219#define S3C_DSTS_EnumSpd_SHIFT (1)
220#define S3C_DSTS_EnumSpd_HS (0x0 << 1)
221#define S3C_DSTS_EnumSpd_FS (0x1 << 1)
222#define S3C_DSTS_EnumSpd_LS (0x2 << 1)
223#define S3C_DSTS_EnumSpd_FS48 (0x3 << 1)
224
225#define S3C_DSTS_SuspSts (1 << 0)
226
227#define S3C_DIEPMSK S3C_HSOTG_REG(0x810)
228
229#define S3C_DIEPMSK_TxFIFOEmpty (1 << 7)
230#define S3C_DIEPMSK_INEPNakEffMsk (1 << 6)
231#define S3C_DIEPMSK_INTknEPMisMsk (1 << 5)
232#define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4)
233#define S3C_DIEPMSK_TimeOUTMsk (1 << 3)
234#define S3C_DIEPMSK_AHBErrMsk (1 << 2)
235#define S3C_DIEPMSK_EPDisbldMsk (1 << 1)
236#define S3C_DIEPMSK_XferComplMsk (1 << 0)
237
238#define S3C_DOEPMSK S3C_HSOTG_REG(0x814)
239
240#define S3C_DOEPMSK_Back2BackSetup (1 << 6)
241#define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4)
242#define S3C_DOEPMSK_SetupMsk (1 << 3)
243#define S3C_DOEPMSK_AHBErrMsk (1 << 2)
244#define S3C_DOEPMSK_EPDisbldMsk (1 << 1)
245#define S3C_DOEPMSK_XferComplMsk (1 << 0)
246
247#define S3C_DAINT S3C_HSOTG_REG(0x818)
248#define S3C_DAINTMSK S3C_HSOTG_REG(0x81C)
249
250#define S3C_DAINT_OutEP_SHIFT (16)
251#define S3C_DAINT_OutEP(x) (1 << ((x) + 16))
252#define S3C_DAINT_InEP(x) (1 << (x))
253
254#define S3C_DTKNQR1 S3C_HSOTG_REG(0x820)
255#define S3C_DTKNQR2 S3C_HSOTG_REG(0x824)
256#define S3C_DTKNQR3 S3C_HSOTG_REG(0x830)
257#define S3C_DTKNQR4 S3C_HSOTG_REG(0x834)
258
259#define S3C_DVBUSDIS S3C_HSOTG_REG(0x828)
260#define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C)
261
262#define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900)
263#define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00)
264#define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20))
265#define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20))
266
267/* EP0 specialness:
268 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
269 * bits[25..22] - should always be zero, this isn't a periodic endpoint
270 * bits[10..0] - MPS setting differenct for EP0
271*/
272#define S3C_D0EPCTL_MPS_MASK (0x3 << 0)
273#define S3C_D0EPCTL_MPS_SHIFT (0)
274#define S3C_D0EPCTL_MPS_64 (0x0 << 0)
275#define S3C_D0EPCTL_MPS_32 (0x1 << 0)
276#define S3C_D0EPCTL_MPS_16 (0x2 << 0)
277#define S3C_D0EPCTL_MPS_8 (0x3 << 0)
278
279#define S3C_DxEPCTL_EPEna (1 << 31)
280#define S3C_DxEPCTL_EPDis (1 << 30)
281#define S3C_DxEPCTL_SetD1PID (1 << 29)
282#define S3C_DxEPCTL_SetOddFr (1 << 29)
283#define S3C_DxEPCTL_SetD0PID (1 << 28)
284#define S3C_DxEPCTL_SetEvenFr (1 << 28)
285#define S3C_DxEPCTL_SNAK (1 << 27)
286#define S3C_DxEPCTL_CNAK (1 << 26)
287#define S3C_DxEPCTL_TxFNum_MASK (0xf << 22)
288#define S3C_DxEPCTL_TxFNum_SHIFT (22)
289#define S3C_DxEPCTL_TxFNum_LIMIT (0xf)
290#define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22)
291
292#define S3C_DxEPCTL_Stall (1 << 21)
293#define S3C_DxEPCTL_Snp (1 << 20)
294#define S3C_DxEPCTL_EPType_MASK (0x3 << 18)
295#define S3C_DxEPCTL_EPType_SHIFT (18)
296#define S3C_DxEPCTL_EPType_Control (0x0 << 18)
297#define S3C_DxEPCTL_EPType_Iso (0x1 << 18)
298#define S3C_DxEPCTL_EPType_Bulk (0x2 << 18)
299#define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18)
300
301#define S3C_DxEPCTL_NAKsts (1 << 17)
302#define S3C_DxEPCTL_DPID (1 << 16)
303#define S3C_DxEPCTL_EOFrNum (1 << 16)
304#define S3C_DxEPCTL_USBActEp (1 << 15)
305#define S3C_DxEPCTL_NextEp_MASK (0xf << 11)
306#define S3C_DxEPCTL_NextEp_SHIFT (11)
307#define S3C_DxEPCTL_NextEp_LIMIT (0xf)
308#define S3C_DxEPCTL_NextEp(_x) ((_x) << 11)
309
310#define S3C_DxEPCTL_MPS_MASK (0x7ff << 0)
311#define S3C_DxEPCTL_MPS_SHIFT (0)
312#define S3C_DxEPCTL_MPS_LIMIT (0x7ff)
313#define S3C_DxEPCTL_MPS(_x) ((_x) << 0)
314
315#define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20))
316#define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20))
317
318#define S3C_DxEPINT_INEPNakEff (1 << 6)
319#define S3C_DxEPINT_Back2BackSetup (1 << 6)
320#define S3C_DxEPINT_INTknEPMis (1 << 5)
321#define S3C_DxEPINT_INTknTXFEmp (1 << 4)
322#define S3C_DxEPINT_OUTTknEPdis (1 << 4)
323#define S3C_DxEPINT_Timeout (1 << 3)
324#define S3C_DxEPINT_Setup (1 << 3)
325#define S3C_DxEPINT_AHBErr (1 << 2)
326#define S3C_DxEPINT_EPDisbld (1 << 1)
327#define S3C_DxEPINT_XferCompl (1 << 0)
328
329#define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910)
330
331#define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19)
332#define S3C_DIEPTSIZ0_PktCnt_SHIFT (19)
333#define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3)
334#define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19)
335
336#define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0)
337#define S3C_DIEPTSIZ0_XferSize_SHIFT (0)
338#define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f)
339#define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0)
340
341
342#define DOEPTSIZ0 S3C_HSOTG_REG(0xB10)
343#define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29)
344#define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29)
345#define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3)
346#define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29)
347
348#define S3C_DOEPTSIZ0_PktCnt (1 << 19)
349#define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0)
350#define S3C_DOEPTSIZ0_XferSize_SHIFT (0)
351
352#define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20))
353#define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20))
354
355#define S3C_DxEPTSIZ_MC_MASK (0x3 << 29)
356#define S3C_DxEPTSIZ_MC_SHIFT (29)
357#define S3C_DxEPTSIZ_MC_LIMIT (0x3)
358#define S3C_DxEPTSIZ_MC(_x) ((_x) << 29)
359
360#define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19)
361#define S3C_DxEPTSIZ_PktCnt_SHIFT (19)
362#define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff)
363#define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff)
364#define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19)
365
366#define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0)
367#define S3C_DxEPTSIZ_XferSize_SHIFT (0)
368#define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff)
369#define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff)
370#define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0)
371
372
373#define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20))
374#define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20))
375#define S3C_DTXFSTS(_a) S3C_HSOTG_REG(0x918 + ((_a) * 0x20))
376
377#define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000))
378
379#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */
diff --git a/arch/arm/plat-samsung/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h
deleted file mode 100644
index c9e3667cb2b..00000000000
--- a/arch/arm/plat-samsung/include/plat/udc-hs.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/* arch/arm/plat-s3c/include/plat/udc-hs.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C USB2.0 High-speed / OtG platform information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15enum s3c_hsotg_dmamode {
16 S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */
17 S3C_HSOTG_DMA_ONLY, /* always use DMA */
18 S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */
19};
20
21/**
22 * struct s3c_hsotg_plat - platform data for high-speed otg/udc
23 * @dma: Whether to use DMA or not.
24 * @is_osc: The clock source is an oscillator, not a crystal
25 */
26struct s3c_hsotg_plat {
27 enum s3c_hsotg_dmamode dma;
28 unsigned int is_osc : 1;
29
30 int (*phy_init)(struct platform_device *pdev, int type);
31 int (*phy_exit)(struct platform_device *pdev, int type);
32};
33
34extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 02:38:53 -0500