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authorRussell King <rmk+kernel@arm.linux.org.uk>2012-03-28 13:30:01 -0400
committerDavid Howells <dhowells@redhat.com>2012-03-28 13:30:01 -0400
commit15d07dc9c59eae51219c40253bdf920f62bb10f2 (patch)
treed830b428bf55526b1ab80139f6b4c24d4b38d627 /arch/arm
parentec2212088c42ff7d1362629ec26dda4f3e8bdad3 (diff)
ARM: move CP15 definitions to separate header file
Avoid namespace conflicts with drivers over the CP15 definitions by moving CP15 related prototypes and definitions to a private header file. Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> [Tegra] Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> [EP93xx] Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: David Howells <dhowells@redhat.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/cp15.h87
-rw-r--r--arch/arm/include/asm/system.h77
-rw-r--r--arch/arm/kernel/fiq.c2
-rw-r--r--arch/arm/kernel/head-nommu.S2
-rw-r--r--arch/arm/kernel/head.S2
-rw-r--r--arch/arm/kernel/setup.c2
-rw-r--r--arch/arm/mach-exynos/hotplug.c1
-rw-r--r--arch/arm/mach-realview/hotplug.c1
-rw-r--r--arch/arm/mach-tegra/hotplug.c1
-rw-r--r--arch/arm/mach-vexpress/hotplug.c2
-rw-r--r--arch/arm/mm/alignment.c2
-rw-r--r--arch/arm/mm/cache-feroceon-l2.c1
-rw-r--r--arch/arm/mm/cache-tauros2.c1
-rw-r--r--arch/arm/mm/cache-xsc3l2.c2
-rw-r--r--arch/arm/mm/ioremap.c1
-rw-r--r--arch/arm/mm/mmu.c1
-rw-r--r--arch/arm/mm/pgd.c1
-rw-r--r--arch/arm/vfp/vfpmodule.c1
18 files changed, 103 insertions, 84 deletions
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
new file mode 100644
index 00000000000..3dabd8dd404
--- /dev/null
+++ b/arch/arm/include/asm/cp15.h
@@ -0,0 +1,87 @@
1#ifndef __ASM_ARM_CP15_H
2#define __ASM_ARM_CP15_H
3
4#include <asm/system.h>
5
6/*
7 * CR1 bits (CP#15 CR1)
8 */
9#define CR_M (1 << 0) /* MMU enable */
10#define CR_A (1 << 1) /* Alignment abort enable */
11#define CR_C (1 << 2) /* Dcache enable */
12#define CR_W (1 << 3) /* Write buffer enable */
13#define CR_P (1 << 4) /* 32-bit exception handler */
14#define CR_D (1 << 5) /* 32-bit data address range */
15#define CR_L (1 << 6) /* Implementation defined */
16#define CR_B (1 << 7) /* Big endian */
17#define CR_S (1 << 8) /* System MMU protection */
18#define CR_R (1 << 9) /* ROM MMU protection */
19#define CR_F (1 << 10) /* Implementation defined */
20#define CR_Z (1 << 11) /* Implementation defined */
21#define CR_I (1 << 12) /* Icache enable */
22#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
23#define CR_RR (1 << 14) /* Round Robin cache replacement */
24#define CR_L4 (1 << 15) /* LDR pc can set T bit */
25#define CR_DT (1 << 16)
26#define CR_IT (1 << 18)
27#define CR_ST (1 << 19)
28#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
29#define CR_U (1 << 22) /* Unaligned access operation */
30#define CR_XP (1 << 23) /* Extended page tables */
31#define CR_VE (1 << 24) /* Vectored interrupts */
32#define CR_EE (1 << 25) /* Exception (Big) Endian */
33#define CR_TRE (1 << 28) /* TEX remap enable */
34#define CR_AFE (1 << 29) /* Access flag enable */
35#define CR_TE (1 << 30) /* Thumb exception enable */
36
37#ifndef __ASSEMBLY__
38
39#if __LINUX_ARM_ARCH__ >= 4
40#define vectors_high() (cr_alignment & CR_V)
41#else
42#define vectors_high() (0)
43#endif
44
45extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
46extern unsigned long cr_alignment; /* defined in entry-armv.S */
47
48static inline unsigned int get_cr(void)
49{
50 unsigned int val;
51 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
52 return val;
53}
54
55static inline void set_cr(unsigned int val)
56{
57 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
58 : : "r" (val) : "cc");
59 isb();
60}
61
62#ifndef CONFIG_SMP
63extern void adjust_cr(unsigned long mask, unsigned long set);
64#endif
65
66#define CPACC_FULL(n) (3 << (n * 2))
67#define CPACC_SVC(n) (1 << (n * 2))
68#define CPACC_DISABLE(n) (0 << (n * 2))
69
70static inline unsigned int get_copro_access(void)
71{
72 unsigned int val;
73 asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
74 : "=r" (val) : : "cc");
75 return val;
76}
77
78static inline void set_copro_access(unsigned int val)
79{
80 asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
81 : : "r" (val) : "cc");
82 isb();
83}
84
85#endif
86
87#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index e4c96cc6ec0..774c41e8add 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -15,37 +15,6 @@
15#define CPU_ARCH_ARMv7 9 15#define CPU_ARCH_ARMv7 9
16 16
17/* 17/*
18 * CR1 bits (CP#15 CR1)
19 */
20#define CR_M (1 << 0) /* MMU enable */
21#define CR_A (1 << 1) /* Alignment abort enable */
22#define CR_C (1 << 2) /* Dcache enable */
23#define CR_W (1 << 3) /* Write buffer enable */
24#define CR_P (1 << 4) /* 32-bit exception handler */
25#define CR_D (1 << 5) /* 32-bit data address range */
26#define CR_L (1 << 6) /* Implementation defined */
27#define CR_B (1 << 7) /* Big endian */
28#define CR_S (1 << 8) /* System MMU protection */
29#define CR_R (1 << 9) /* ROM MMU protection */
30#define CR_F (1 << 10) /* Implementation defined */
31#define CR_Z (1 << 11) /* Implementation defined */
32#define CR_I (1 << 12) /* Icache enable */
33#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
34#define CR_RR (1 << 14) /* Round Robin cache replacement */
35#define CR_L4 (1 << 15) /* LDR pc can set T bit */
36#define CR_DT (1 << 16)
37#define CR_IT (1 << 18)
38#define CR_ST (1 << 19)
39#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
40#define CR_U (1 << 22) /* Unaligned access operation */
41#define CR_XP (1 << 23) /* Extended page tables */
42#define CR_VE (1 << 24) /* Vectored interrupts */
43#define CR_EE (1 << 25) /* Exception (Big) Endian */
44#define CR_TRE (1 << 28) /* TEX remap enable */
45#define CR_AFE (1 << 29) /* Access flag enable */
46#define CR_TE (1 << 30) /* Thumb exception enable */
47
48/*
49 * This is used to ensure the compiler did actually allocate the register we 18 * This is used to ensure the compiler did actually allocate the register we
50 * asked it for some inline assembly sequences. Apparently we can't trust 19 * asked it for some inline assembly sequences. Apparently we can't trust
51 * the compiler from one version to another so a bit of paranoia won't hurt. 20 * the compiler from one version to another so a bit of paranoia won't hurt.
@@ -119,12 +88,6 @@ extern void (*arm_pm_restart)(char str, const char *cmd);
119 88
120extern unsigned int user_debug; 89extern unsigned int user_debug;
121 90
122#if __LINUX_ARM_ARCH__ >= 4
123#define vectors_high() (cr_alignment & CR_V)
124#else
125#define vectors_high() (0)
126#endif
127
128#if __LINUX_ARM_ARCH__ >= 7 || \ 91#if __LINUX_ARM_ARCH__ >= 7 || \
129 (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K)) 92 (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
130#define sev() __asm__ __volatile__ ("sev" : : : "memory") 93#define sev() __asm__ __volatile__ ("sev" : : : "memory")
@@ -185,46 +148,6 @@ extern unsigned int user_debug;
185#define set_mb(var, value) do { var = value; smp_mb(); } while (0) 148#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
186#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); 149#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
187 150
188extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
189extern unsigned long cr_alignment; /* defined in entry-armv.S */
190
191static inline unsigned int get_cr(void)
192{
193 unsigned int val;
194 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
195 return val;
196}
197
198static inline void set_cr(unsigned int val)
199{
200 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
201 : : "r" (val) : "cc");
202 isb();
203}
204
205#ifndef CONFIG_SMP
206extern void adjust_cr(unsigned long mask, unsigned long set);
207#endif
208
209#define CPACC_FULL(n) (3 << (n * 2))
210#define CPACC_SVC(n) (1 << (n * 2))
211#define CPACC_DISABLE(n) (0 << (n * 2))
212
213static inline unsigned int get_copro_access(void)
214{
215 unsigned int val;
216 asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
217 : "=r" (val) : : "cc");
218 return val;
219}
220
221static inline void set_copro_access(unsigned int val)
222{
223 asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
224 : : "r" (val) : "cc");
225 isb();
226}
227
228/* 151/*
229 * switch_mm() may do a full cache flush over the context switch, 152 * switch_mm() may do a full cache flush over the context switch,
230 * so enable interrupts over the context switch to avoid high 153 * so enable interrupts over the context switch to avoid high
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 4c164ece589..c32f8456aa0 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -42,9 +42,9 @@
42#include <linux/seq_file.h> 42#include <linux/seq_file.h>
43 43
44#include <asm/cacheflush.h> 44#include <asm/cacheflush.h>
45#include <asm/cp15.h>
45#include <asm/fiq.h> 46#include <asm/fiq.h>
46#include <asm/irq.h> 47#include <asm/irq.h>
47#include <asm/system.h>
48#include <asm/traps.h> 48#include <asm/traps.h>
49 49
50static unsigned long no_fiq_insn; 50static unsigned long no_fiq_insn;
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index d46f25968be..278cfc144f4 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -17,8 +17,8 @@
17#include <asm/assembler.h> 17#include <asm/assembler.h>
18#include <asm/ptrace.h> 18#include <asm/ptrace.h>
19#include <asm/asm-offsets.h> 19#include <asm/asm-offsets.h>
20#include <asm/cp15.h>
20#include <asm/thread_info.h> 21#include <asm/thread_info.h>
21#include <asm/system.h>
22 22
23/* 23/*
24 * Kernel startup entry point. 24 * Kernel startup entry point.
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 6d579114406..a2e9694a68e 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -15,12 +15,12 @@
15#include <linux/init.h> 15#include <linux/init.h>
16 16
17#include <asm/assembler.h> 17#include <asm/assembler.h>
18#include <asm/cp15.h>
18#include <asm/domain.h> 19#include <asm/domain.h>
19#include <asm/ptrace.h> 20#include <asm/ptrace.h>
20#include <asm/asm-offsets.h> 21#include <asm/asm-offsets.h>
21#include <asm/memory.h> 22#include <asm/memory.h>
22#include <asm/thread_info.h> 23#include <asm/thread_info.h>
23#include <asm/system.h>
24#include <asm/pgtable.h> 24#include <asm/pgtable.h>
25 25
26#ifdef CONFIG_DEBUG_LL 26#ifdef CONFIG_DEBUG_LL
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index a255c39612c..615e992d738 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -33,6 +33,7 @@
33#include <linux/sort.h> 33#include <linux/sort.h>
34 34
35#include <asm/unified.h> 35#include <asm/unified.h>
36#include <asm/cp15.h>
36#include <asm/cpu.h> 37#include <asm/cpu.h>
37#include <asm/cputype.h> 38#include <asm/cputype.h>
38#include <asm/elf.h> 39#include <asm/elf.h>
@@ -44,7 +45,6 @@
44#include <asm/cacheflush.h> 45#include <asm/cacheflush.h>
45#include <asm/cachetype.h> 46#include <asm/cachetype.h>
46#include <asm/tlbflush.h> 47#include <asm/tlbflush.h>
47#include <asm/system.h>
48 48
49#include <asm/prom.h> 49#include <asm/prom.h>
50#include <asm/mach/arch.h> 50#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index dd1ad55524c..9c17a0a4385 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -16,6 +16,7 @@
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/cp15.h>
19#include <asm/smp_plat.h> 20#include <asm/smp_plat.h>
20 21
21#include <mach/regs-pmu.h> 22#include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index eb55f05bef3..57d9efba295 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -13,6 +13,7 @@
13#include <linux/smp.h> 13#include <linux/smp.h>
14 14
15#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
16#include <asm/cp15.h>
16#include <asm/smp_plat.h> 17#include <asm/smp_plat.h>
17 18
18extern volatile int pen_release; 19extern volatile int pen_release;
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index f3294040d35..d8dc9ddd6d1 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -13,6 +13,7 @@
13#include <linux/smp.h> 13#include <linux/smp.h>
14 14
15#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
16#include <asm/cp15.h>
16 17
17static inline void cpu_enter_lowpower(void) 18static inline void cpu_enter_lowpower(void)
18{ 19{
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
index 3034a4dab4a..c504a72b94d 100644
--- a/arch/arm/mach-vexpress/hotplug.c
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -14,7 +14,7 @@
14 14
15#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
16#include <asm/smp_plat.h> 16#include <asm/smp_plat.h>
17#include <asm/system.h> 17#include <asm/cp15.h>
18 18
19extern volatile int pen_release; 19extern volatile int pen_release;
20 20
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index caf14dc059e..78459b8a2a1 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -22,7 +22,7 @@
22#include <linux/sched.h> 22#include <linux/sched.h>
23#include <linux/uaccess.h> 23#include <linux/uaccess.h>
24 24
25#include <asm/system.h> 25#include <asm/cp15.h>
26#include <asm/unaligned.h> 26#include <asm/unaligned.h>
27 27
28#include "fault.h" 28#include "fault.h"
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index e0b0e7a4ec6..dd3d59122cc 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/highmem.h> 16#include <linux/highmem.h>
17#include <asm/cacheflush.h> 17#include <asm/cacheflush.h>
18#include <asm/cp15.h>
18#include <plat/cache-feroceon-l2.h> 19#include <plat/cache-feroceon-l2.h>
19 20
20/* 21/*
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 50868651890..1fbca05fe90 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -16,6 +16,7 @@
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/cp15.h>
19#include <asm/hardware/cache-tauros2.h> 20#include <asm/hardware/cache-tauros2.h>
20 21
21 22
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c
index 5a32020471e..6c3edeb66e7 100644
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -18,7 +18,7 @@
18 */ 18 */
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/highmem.h> 20#include <linux/highmem.h>
21#include <asm/system.h> 21#include <asm/cp15.h>
22#include <asm/cputype.h> 22#include <asm/cputype.h>
23#include <asm/cacheflush.h> 23#include <asm/cacheflush.h>
24 24
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 80632e8d753..66daf17b5e3 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -26,6 +26,7 @@
26#include <linux/vmalloc.h> 26#include <linux/vmalloc.h>
27#include <linux/io.h> 27#include <linux/io.h>
28 28
29#include <asm/cp15.h>
29#include <asm/cputype.h> 30#include <asm/cputype.h>
30#include <asm/cacheflush.h> 31#include <asm/cacheflush.h>
31#include <asm/mmu_context.h> 32#include <asm/mmu_context.h>
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 94c5a0c94f5..163a69af1fb 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -17,6 +17,7 @@
17#include <linux/fs.h> 17#include <linux/fs.h>
18#include <linux/vmalloc.h> 18#include <linux/vmalloc.h>
19 19
20#include <asm/cp15.h>
20#include <asm/cputype.h> 21#include <asm/cputype.h>
21#include <asm/sections.h> 22#include <asm/sections.h>
22#include <asm/cachetype.h> 23#include <asm/cachetype.h>
diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c
index a3e78ccabd6..0acb089d0f7 100644
--- a/arch/arm/mm/pgd.c
+++ b/arch/arm/mm/pgd.c
@@ -12,6 +12,7 @@
12#include <linux/highmem.h> 12#include <linux/highmem.h>
13#include <linux/slab.h> 13#include <linux/slab.h>
14 14
15#include <asm/cp15.h>
15#include <asm/pgalloc.h> 16#include <asm/pgalloc.h>
16#include <asm/page.h> 17#include <asm/page.h>
17#include <asm/tlbflush.h> 18#include <asm/tlbflush.h>
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 8f3ccddbdaf..d89068f6d6e 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -18,6 +18,7 @@
18#include <linux/smp.h> 18#include <linux/smp.h>
19#include <linux/init.h> 19#include <linux/init.h>
20 20
21#include <asm/cp15.h>
21#include <asm/cputype.h> 22#include <asm/cputype.h>
22#include <asm/thread_notify.h> 23#include <asm/thread_notify.h>
23#include <asm/vfp.h> 24#include <asm/vfp.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 15:49:57 -0400