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authorBenoit Cousson <b-cousson@ti.com>2010-09-27 16:02:54 -0400
committerPaul Walmsley <paul@pwsan.com>2010-09-27 16:02:54 -0400
commit0e43327191986e88efdc8717084aeb22db2cc8a9 (patch)
treec13e6d789c7d7104bf16d01508f21de914362d5f /arch/arm
parent76cf52951ac57a31a453610e0ab5cae50b10502d (diff)
OMAP4: clock: Fix clock names and align with hwmod names
The OMAP4 hwmod data introduced the new naming convention for TI IPs (See patch OMAP4: hwmod: Add partial hwmod support for OMAP4430 ES1.0) The leaf clock names are using the same IP name and thus must be modified to match the clock populated in the hwmod data. - Fix some leaf clocks nodes that were using a _iclk instead of the _fclk prefix. - Fix some wrong interface clock name for master IPs connected to interconnect. Please not that due to the fact that nodes are sorted by name, the name change will introduce a quite ugly diff a little bit hard to follow. Timers clock con_id is still using the old gptX_fck name until the gptimer driver is updated to omap_device framework. Timers entries in hwmods DB are still disabled until the migration if timer to platform_driver + omap_hwmod. Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: manually resolved conflicts with Rajendra's clock patch] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c665
1 files changed, 310 insertions, 355 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index f39552bd74b..8296ae04f77 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -26,7 +26,6 @@
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/list.h> 27#include <linux/list.h>
28#include <linux/clk.h> 28#include <linux/clk.h>
29
30#include <plat/control.h> 29#include <plat/control.h>
31#include <plat/clkdev_omap.h> 30#include <plat/clkdev_omap.h>
32 31
@@ -914,6 +913,7 @@ static struct clk usb_hs_clk_div_ck = {
914static struct dpll_data dpll_usb_dd = { 913static struct dpll_data dpll_usb_dd = {
915 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, 914 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
916 .clk_bypass = &usb_hs_clk_div_ck, 915 .clk_bypass = &usb_hs_clk_div_ck,
916 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL,
917 .clk_ref = &sys_clkin_ck, 917 .clk_ref = &sys_clkin_ck,
918 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, 918 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
919 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 919 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -927,7 +927,6 @@ static struct dpll_data dpll_usb_dd = {
927 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 927 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
928 .max_divider = OMAP4430_MAX_DPLL_DIV, 928 .max_divider = OMAP4430_MAX_DPLL_DIV,
929 .min_divider = 1, 929 .min_divider = 1,
930 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL
931}; 930};
932 931
933 932
@@ -1289,16 +1288,6 @@ static struct clk aess_fck = {
1289 .recalc = &followparent_recalc, 1288 .recalc = &followparent_recalc,
1290}; 1289};
1291 1290
1292static struct clk cust_efuse_fck = {
1293 .name = "cust_efuse_fck",
1294 .ops = &clkops_omap2_dflt,
1295 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1296 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1297 .clkdm_name = "l4_cefuse_clkdm",
1298 .parent = &sys_clkin_ck,
1299 .recalc = &followparent_recalc,
1300};
1301
1302static struct clk des3des_fck = { 1291static struct clk des3des_fck = {
1303 .name = "des3des_fck", 1292 .name = "des3des_fck",
1304 .ops = &clkops_omap2_dflt, 1293 .ops = &clkops_omap2_dflt,
@@ -1349,6 +1338,16 @@ static struct clk dmic_fck = {
1349 .clkdm_name = "abe_clkdm", 1338 .clkdm_name = "abe_clkdm",
1350}; 1339};
1351 1340
1341static struct clk dsp_fck = {
1342 .name = "dsp_fck",
1343 .ops = &clkops_omap2_dflt,
1344 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1345 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1346 .clkdm_name = "tesla_clkdm",
1347 .parent = &dpll_iva_m4_ck,
1348 .recalc = &followparent_recalc,
1349};
1350
1352static struct clk dss_fck = { 1351static struct clk dss_fck = {
1353 .name = "dss_fck", 1352 .name = "dss_fck",
1354 .ops = &clkops_omap2_dflt, 1353 .ops = &clkops_omap2_dflt,
@@ -1359,18 +1358,18 @@ static struct clk dss_fck = {
1359 .recalc = &followparent_recalc, 1358 .recalc = &followparent_recalc,
1360}; 1359};
1361 1360
1362static struct clk ducati_ick = { 1361static struct clk efuse_ctrl_cust_fck = {
1363 .name = "ducati_ick", 1362 .name = "efuse_ctrl_cust_fck",
1364 .ops = &clkops_omap2_dflt, 1363 .ops = &clkops_omap2_dflt,
1365 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, 1364 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1366 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1365 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1367 .clkdm_name = "ducati_clkdm", 1366 .clkdm_name = "l4_cefuse_clkdm",
1368 .parent = &ducati_clk_mux_ck, 1367 .parent = &sys_clkin_ck,
1369 .recalc = &followparent_recalc, 1368 .recalc = &followparent_recalc,
1370}; 1369};
1371 1370
1372static struct clk emif1_ick = { 1371static struct clk emif1_fck = {
1373 .name = "emif1_ick", 1372 .name = "emif1_fck",
1374 .ops = &clkops_omap2_dflt, 1373 .ops = &clkops_omap2_dflt,
1375 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, 1374 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1376 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1375 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1380,8 +1379,8 @@ static struct clk emif1_ick = {
1380 .recalc = &followparent_recalc, 1379 .recalc = &followparent_recalc,
1381}; 1380};
1382 1381
1383static struct clk emif2_ick = { 1382static struct clk emif2_fck = {
1384 .name = "emif2_ick", 1383 .name = "emif2_fck",
1385 .ops = &clkops_omap2_dflt, 1384 .ops = &clkops_omap2_dflt,
1386 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, 1385 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1387 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1386 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1412,25 +1411,14 @@ static struct clk fdif_fck = {
1412 .clkdm_name = "iss_clkdm", 1411 .clkdm_name = "iss_clkdm",
1413}; 1412};
1414 1413
1415static const struct clksel sgx_clk_mux_sel[] = { 1414static struct clk fpka_fck = {
1416 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, 1415 .name = "fpka_fck",
1417 { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
1418 { .parent = NULL },
1419};
1420
1421/* Merged sgx_clk_mux into gfx */
1422static struct clk gfx_fck = {
1423 .name = "gfx_fck",
1424 .parent = &dpll_core_m7_ck,
1425 .clksel = sgx_clk_mux_sel,
1426 .init = &omap2_init_clksel_parent,
1427 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1428 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1429 .ops = &clkops_omap2_dflt, 1416 .ops = &clkops_omap2_dflt,
1430 .recalc = &omap2_clksel_recalc, 1417 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1431 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1432 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1418 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1433 .clkdm_name = "l3_gfx_clkdm", 1419 .clkdm_name = "l4_secure_clkdm",
1420 .parent = &l4_div_ck,
1421 .recalc = &followparent_recalc,
1434}; 1422};
1435 1423
1436static struct clk gpio1_ick = { 1424static struct clk gpio1_ick = {
@@ -1503,208 +1491,25 @@ static struct clk gpmc_ick = {
1503 .recalc = &followparent_recalc, 1491 .recalc = &followparent_recalc,
1504}; 1492};
1505 1493
1506/* 1494static const struct clksel sgx_clk_mux_sel[] = {
1507 * Merged dmt1_clk_mux into gptimer1 1495 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1508 * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention 1496 { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
1509 */
1510static struct clk gpt1_fck = {
1511 .name = "gpt1_fck",
1512 .parent = &sys_clkin_ck,
1513 .clksel = abe_dpll_bypass_clk_mux_sel,
1514 .init = &omap2_init_clksel_parent,
1515 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1516 .clksel_mask = OMAP4430_CLKSEL_MASK,
1517 .ops = &clkops_omap2_dflt,
1518 .recalc = &omap2_clksel_recalc,
1519 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1520 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1521 .clkdm_name = "l4_wkup_clkdm",
1522};
1523
1524/*
1525 * Merged cm2_dm10_mux into gptimer10
1526 * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention
1527 */
1528static struct clk gpt10_fck = {
1529 .name = "gpt10_fck",
1530 .parent = &sys_clkin_ck,
1531 .clksel = abe_dpll_bypass_clk_mux_sel,
1532 .init = &omap2_init_clksel_parent,
1533 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1534 .clksel_mask = OMAP4430_CLKSEL_MASK,
1535 .ops = &clkops_omap2_dflt,
1536 .recalc = &omap2_clksel_recalc,
1537 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1538 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1539 .clkdm_name = "l4_per_clkdm",
1540};
1541
1542/*
1543 * Merged cm2_dm11_mux into gptimer11
1544 * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention
1545 */
1546static struct clk gpt11_fck = {
1547 .name = "gpt11_fck",
1548 .parent = &sys_clkin_ck,
1549 .clksel = abe_dpll_bypass_clk_mux_sel,
1550 .init = &omap2_init_clksel_parent,
1551 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1552 .clksel_mask = OMAP4430_CLKSEL_MASK,
1553 .ops = &clkops_omap2_dflt,
1554 .recalc = &omap2_clksel_recalc,
1555 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1556 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1557 .clkdm_name = "l4_per_clkdm",
1558};
1559
1560/*
1561 * Merged cm2_dm2_mux into gptimer2
1562 * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention
1563 */
1564static struct clk gpt2_fck = {
1565 .name = "gpt2_fck",
1566 .parent = &sys_clkin_ck,
1567 .clksel = abe_dpll_bypass_clk_mux_sel,
1568 .init = &omap2_init_clksel_parent,
1569 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1570 .clksel_mask = OMAP4430_CLKSEL_MASK,
1571 .ops = &clkops_omap2_dflt,
1572 .recalc = &omap2_clksel_recalc,
1573 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1574 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1575 .clkdm_name = "l4_per_clkdm",
1576};
1577
1578/*
1579 * Merged cm2_dm3_mux into gptimer3
1580 * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention
1581 */
1582static struct clk gpt3_fck = {
1583 .name = "gpt3_fck",
1584 .parent = &sys_clkin_ck,
1585 .clksel = abe_dpll_bypass_clk_mux_sel,
1586 .init = &omap2_init_clksel_parent,
1587 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1588 .clksel_mask = OMAP4430_CLKSEL_MASK,
1589 .ops = &clkops_omap2_dflt,
1590 .recalc = &omap2_clksel_recalc,
1591 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1592 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1593 .clkdm_name = "l4_per_clkdm",
1594};
1595
1596/*
1597 * Merged cm2_dm4_mux into gptimer4
1598 * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention
1599 */
1600static struct clk gpt4_fck = {
1601 .name = "gpt4_fck",
1602 .parent = &sys_clkin_ck,
1603 .clksel = abe_dpll_bypass_clk_mux_sel,
1604 .init = &omap2_init_clksel_parent,
1605 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1606 .clksel_mask = OMAP4430_CLKSEL_MASK,
1607 .ops = &clkops_omap2_dflt,
1608 .recalc = &omap2_clksel_recalc,
1609 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1610 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1611 .clkdm_name = "l4_per_clkdm",
1612};
1613
1614static const struct clksel timer5_sync_mux_sel[] = {
1615 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1616 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1617 { .parent = NULL }, 1497 { .parent = NULL },
1618}; 1498};
1619 1499
1620/* 1500/* Merged sgx_clk_mux into gpu */
1621 * Merged timer5_sync_mux into gptimer5 1501static struct clk gpu_fck = {
1622 * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention 1502 .name = "gpu_fck",
1623 */ 1503 .parent = &dpll_core_m7_ck,
1624static struct clk gpt5_fck = { 1504 .clksel = sgx_clk_mux_sel,
1625 .name = "gpt5_fck",
1626 .parent = &syc_clk_div_ck,
1627 .clksel = timer5_sync_mux_sel,
1628 .init = &omap2_init_clksel_parent,
1629 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1630 .clksel_mask = OMAP4430_CLKSEL_MASK,
1631 .ops = &clkops_omap2_dflt,
1632 .recalc = &omap2_clksel_recalc,
1633 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1634 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1635 .clkdm_name = "abe_clkdm",
1636};
1637
1638/*
1639 * Merged timer6_sync_mux into gptimer6
1640 * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention
1641 */
1642static struct clk gpt6_fck = {
1643 .name = "gpt6_fck",
1644 .parent = &syc_clk_div_ck,
1645 .clksel = timer5_sync_mux_sel,
1646 .init = &omap2_init_clksel_parent,
1647 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1648 .clksel_mask = OMAP4430_CLKSEL_MASK,
1649 .ops = &clkops_omap2_dflt,
1650 .recalc = &omap2_clksel_recalc,
1651 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1652 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1653 .clkdm_name = "abe_clkdm",
1654};
1655
1656/*
1657 * Merged timer7_sync_mux into gptimer7
1658 * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention
1659 */
1660static struct clk gpt7_fck = {
1661 .name = "gpt7_fck",
1662 .parent = &syc_clk_div_ck,
1663 .clksel = timer5_sync_mux_sel,
1664 .init = &omap2_init_clksel_parent,
1665 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1666 .clksel_mask = OMAP4430_CLKSEL_MASK,
1667 .ops = &clkops_omap2_dflt,
1668 .recalc = &omap2_clksel_recalc,
1669 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1670 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1671 .clkdm_name = "abe_clkdm",
1672};
1673
1674/*
1675 * Merged timer8_sync_mux into gptimer8
1676 * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention
1677 */
1678static struct clk gpt8_fck = {
1679 .name = "gpt8_fck",
1680 .parent = &syc_clk_div_ck,
1681 .clksel = timer5_sync_mux_sel,
1682 .init = &omap2_init_clksel_parent,
1683 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1684 .clksel_mask = OMAP4430_CLKSEL_MASK,
1685 .ops = &clkops_omap2_dflt,
1686 .recalc = &omap2_clksel_recalc,
1687 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1688 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1689 .clkdm_name = "abe_clkdm",
1690};
1691
1692/*
1693 * Merged cm2_dm9_mux into gptimer9
1694 * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention
1695 */
1696static struct clk gpt9_fck = {
1697 .name = "gpt9_fck",
1698 .parent = &sys_clkin_ck,
1699 .clksel = abe_dpll_bypass_clk_mux_sel,
1700 .init = &omap2_init_clksel_parent, 1505 .init = &omap2_init_clksel_parent,
1701 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, 1506 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1702 .clksel_mask = OMAP4430_CLKSEL_MASK, 1507 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1703 .ops = &clkops_omap2_dflt, 1508 .ops = &clkops_omap2_dflt,
1704 .recalc = &omap2_clksel_recalc, 1509 .recalc = &omap2_clksel_recalc,
1705 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, 1510 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1706 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1511 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1707 .clkdm_name = "l4_per_clkdm", 1512 .clkdm_name = "l3_gfx_clkdm",
1708}; 1513};
1709 1514
1710static struct clk hdq1w_fck = { 1515static struct clk hdq1w_fck = {
@@ -1723,8 +1528,8 @@ static const struct clksel hsi_fclk_div[] = {
1723}; 1528};
1724 1529
1725/* Merged hsi_fclk into hsi */ 1530/* Merged hsi_fclk into hsi */
1726static struct clk hsi_ick = { 1531static struct clk hsi_fck = {
1727 .name = "hsi_ick", 1532 .name = "hsi_fck",
1728 .parent = &dpll_per_m2x2_ck, 1533 .parent = &dpll_per_m2x2_ck,
1729 .clksel = hsi_fclk_div, 1534 .clksel = hsi_fclk_div,
1730 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, 1535 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
@@ -1778,6 +1583,16 @@ static struct clk i2c4_fck = {
1778 .recalc = &followparent_recalc, 1583 .recalc = &followparent_recalc,
1779}; 1584};
1780 1585
1586static struct clk ipu_fck = {
1587 .name = "ipu_fck",
1588 .ops = &clkops_omap2_dflt,
1589 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1590 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1591 .clkdm_name = "ducati_clkdm",
1592 .parent = &ducati_clk_mux_ck,
1593 .recalc = &followparent_recalc,
1594};
1595
1781static struct clk iss_fck = { 1596static struct clk iss_fck = {
1782 .name = "iss_fck", 1597 .name = "iss_fck",
1783 .ops = &clkops_omap2_dflt, 1598 .ops = &clkops_omap2_dflt,
@@ -1788,8 +1603,8 @@ static struct clk iss_fck = {
1788 .recalc = &followparent_recalc, 1603 .recalc = &followparent_recalc,
1789}; 1604};
1790 1605
1791static struct clk ivahd_ick = { 1606static struct clk iva_fck = {
1792 .name = "ivahd_ick", 1607 .name = "iva_fck",
1793 .ops = &clkops_omap2_dflt, 1608 .ops = &clkops_omap2_dflt,
1794 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, 1609 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1795 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1610 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1798,8 +1613,8 @@ static struct clk ivahd_ick = {
1798 .recalc = &followparent_recalc, 1613 .recalc = &followparent_recalc,
1799}; 1614};
1800 1615
1801static struct clk keyboard_fck = { 1616static struct clk kbd_fck = {
1802 .name = "keyboard_fck", 1617 .name = "kbd_fck",
1803 .ops = &clkops_omap2_dflt, 1618 .ops = &clkops_omap2_dflt,
1804 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, 1619 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1805 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1620 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1808,8 +1623,8 @@ static struct clk keyboard_fck = {
1808 .recalc = &followparent_recalc, 1623 .recalc = &followparent_recalc,
1809}; 1624};
1810 1625
1811static struct clk l3_instr_interconnect_ick = { 1626static struct clk l3_instr_ick = {
1812 .name = "l3_instr_interconnect_ick", 1627 .name = "l3_instr_ick",
1813 .ops = &clkops_omap2_dflt, 1628 .ops = &clkops_omap2_dflt,
1814 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, 1629 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1815 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1630 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1818,8 +1633,8 @@ static struct clk l3_instr_interconnect_ick = {
1818 .recalc = &followparent_recalc, 1633 .recalc = &followparent_recalc,
1819}; 1634};
1820 1635
1821static struct clk l3_interconnect_3_ick = { 1636static struct clk l3_main_3_ick = {
1822 .name = "l3_interconnect_3_ick", 1637 .name = "l3_main_3_ick",
1823 .ops = &clkops_omap2_dflt, 1638 .ops = &clkops_omap2_dflt,
1824 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 1639 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1825 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1640 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1992,6 +1807,16 @@ static struct clk mcbsp4_fck = {
1992 .clkdm_name = "l4_per_clkdm", 1807 .clkdm_name = "l4_per_clkdm",
1993}; 1808};
1994 1809
1810static struct clk mcpdm_fck = {
1811 .name = "mcpdm_fck",
1812 .ops = &clkops_omap2_dflt,
1813 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
1814 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1815 .clkdm_name = "abe_clkdm",
1816 .parent = &pad_clks_ck,
1817 .recalc = &followparent_recalc,
1818};
1819
1995static struct clk mcspi1_fck = { 1820static struct clk mcspi1_fck = {
1996 .name = "mcspi1_fck", 1821 .name = "mcspi1_fck",
1997 .ops = &clkops_omap2_dflt, 1822 .ops = &clkops_omap2_dflt,
@@ -2092,8 +1917,8 @@ static struct clk mmc5_fck = {
2092 .recalc = &followparent_recalc, 1917 .recalc = &followparent_recalc,
2093}; 1918};
2094 1919
2095static struct clk ocp_wp1_ick = { 1920static struct clk ocp_wp_noc_ick = {
2096 .name = "ocp_wp1_ick", 1921 .name = "ocp_wp_noc_ick",
2097 .ops = &clkops_omap2_dflt, 1922 .ops = &clkops_omap2_dflt,
2098 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, 1923 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2099 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1924 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2102,26 +1927,6 @@ static struct clk ocp_wp1_ick = {
2102 .recalc = &followparent_recalc, 1927 .recalc = &followparent_recalc,
2103}; 1928};
2104 1929
2105static struct clk pdm_fck = {
2106 .name = "pdm_fck",
2107 .ops = &clkops_omap2_dflt,
2108 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2109 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2110 .clkdm_name = "abe_clkdm",
2111 .parent = &pad_clks_ck,
2112 .recalc = &followparent_recalc,
2113};
2114
2115static struct clk pkaeip29_fck = {
2116 .name = "pkaeip29_fck",
2117 .ops = &clkops_omap2_dflt,
2118 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
2119 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2120 .clkdm_name = "l4_secure_clkdm",
2121 .parent = &l4_div_ck,
2122 .recalc = &followparent_recalc,
2123};
2124
2125static struct clk rng_ick = { 1930static struct clk rng_ick = {
2126 .name = "rng_ick", 1931 .name = "rng_ick",
2127 .ops = &clkops_omap2_dflt, 1932 .ops = &clkops_omap2_dflt,
@@ -2132,8 +1937,8 @@ static struct clk rng_ick = {
2132 .recalc = &followparent_recalc, 1937 .recalc = &followparent_recalc,
2133}; 1938};
2134 1939
2135static struct clk sha2md51_fck = { 1940static struct clk sha2md5_fck = {
2136 .name = "sha2md51_fck", 1941 .name = "sha2md5_fck",
2137 .ops = &clkops_omap2_dflt, 1942 .ops = &clkops_omap2_dflt,
2138 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, 1943 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2139 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1944 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2142,8 +1947,8 @@ static struct clk sha2md51_fck = {
2142 .recalc = &followparent_recalc, 1947 .recalc = &followparent_recalc,
2143}; 1948};
2144 1949
2145static struct clk sl2_ick = { 1950static struct clk sl2if_ick = {
2146 .name = "sl2_ick", 1951 .name = "sl2if_ick",
2147 .ops = &clkops_omap2_dflt, 1952 .ops = &clkops_omap2_dflt,
2148 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, 1953 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2149 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1954 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2172,8 +1977,8 @@ static struct clk slimbus2_fck = {
2172 .recalc = &followparent_recalc, 1977 .recalc = &followparent_recalc,
2173}; 1978};
2174 1979
2175static struct clk sr_core_fck = { 1980static struct clk smartreflex_core_fck = {
2176 .name = "sr_core_fck", 1981 .name = "smartreflex_core_fck",
2177 .ops = &clkops_omap2_dflt, 1982 .ops = &clkops_omap2_dflt,
2178 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, 1983 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2179 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1984 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2182,8 +1987,8 @@ static struct clk sr_core_fck = {
2182 .recalc = &followparent_recalc, 1987 .recalc = &followparent_recalc,
2183}; 1988};
2184 1989
2185static struct clk sr_iva_fck = { 1990static struct clk smartreflex_iva_fck = {
2186 .name = "sr_iva_fck", 1991 .name = "smartreflex_iva_fck",
2187 .ops = &clkops_omap2_dflt, 1992 .ops = &clkops_omap2_dflt,
2188 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, 1993 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2189 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1994 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2192,8 +1997,8 @@ static struct clk sr_iva_fck = {
2192 .recalc = &followparent_recalc, 1997 .recalc = &followparent_recalc,
2193}; 1998};
2194 1999
2195static struct clk sr_mpu_fck = { 2000static struct clk smartreflex_mpu_fck = {
2196 .name = "sr_mpu_fck", 2001 .name = "smartreflex_mpu_fck",
2197 .ops = &clkops_omap2_dflt, 2002 .ops = &clkops_omap2_dflt,
2198 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, 2003 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2199 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2004 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2202,14 +2007,175 @@ static struct clk sr_mpu_fck = {
2202 .recalc = &followparent_recalc, 2007 .recalc = &followparent_recalc,
2203}; 2008};
2204 2009
2205static struct clk tesla_ick = { 2010/* Merged dmt1_clk_mux into timer1 */
2206 .name = "tesla_ick", 2011static struct clk timer1_fck = {
2012 .name = "timer1_fck",
2013 .parent = &sys_clkin_ck,
2014 .clksel = abe_dpll_bypass_clk_mux_sel,
2015 .init = &omap2_init_clksel_parent,
2016 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2017 .clksel_mask = OMAP4430_CLKSEL_MASK,
2207 .ops = &clkops_omap2_dflt, 2018 .ops = &clkops_omap2_dflt,
2208 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, 2019 .recalc = &omap2_clksel_recalc,
2209 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2020 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2210 .clkdm_name = "tesla_clkdm", 2021 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2211 .parent = &dpll_iva_m4_ck, 2022 .clkdm_name = "l4_wkup_clkdm",
2212 .recalc = &followparent_recalc, 2023};
2024
2025/* Merged cm2_dm10_mux into timer10 */
2026static struct clk timer10_fck = {
2027 .name = "timer10_fck",
2028 .parent = &sys_clkin_ck,
2029 .clksel = abe_dpll_bypass_clk_mux_sel,
2030 .init = &omap2_init_clksel_parent,
2031 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2032 .clksel_mask = OMAP4430_CLKSEL_MASK,
2033 .ops = &clkops_omap2_dflt,
2034 .recalc = &omap2_clksel_recalc,
2035 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2036 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2037 .clkdm_name = "l4_per_clkdm",
2038};
2039
2040/* Merged cm2_dm11_mux into timer11 */
2041static struct clk timer11_fck = {
2042 .name = "timer11_fck",
2043 .parent = &sys_clkin_ck,
2044 .clksel = abe_dpll_bypass_clk_mux_sel,
2045 .init = &omap2_init_clksel_parent,
2046 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2047 .clksel_mask = OMAP4430_CLKSEL_MASK,
2048 .ops = &clkops_omap2_dflt,
2049 .recalc = &omap2_clksel_recalc,
2050 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2051 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2052 .clkdm_name = "l4_per_clkdm",
2053};
2054
2055/* Merged cm2_dm2_mux into timer2 */
2056static struct clk timer2_fck = {
2057 .name = "timer2_fck",
2058 .parent = &sys_clkin_ck,
2059 .clksel = abe_dpll_bypass_clk_mux_sel,
2060 .init = &omap2_init_clksel_parent,
2061 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2062 .clksel_mask = OMAP4430_CLKSEL_MASK,
2063 .ops = &clkops_omap2_dflt,
2064 .recalc = &omap2_clksel_recalc,
2065 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2066 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2067 .clkdm_name = "l4_per_clkdm",
2068};
2069
2070/* Merged cm2_dm3_mux into timer3 */
2071static struct clk timer3_fck = {
2072 .name = "timer3_fck",
2073 .parent = &sys_clkin_ck,
2074 .clksel = abe_dpll_bypass_clk_mux_sel,
2075 .init = &omap2_init_clksel_parent,
2076 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2077 .clksel_mask = OMAP4430_CLKSEL_MASK,
2078 .ops = &clkops_omap2_dflt,
2079 .recalc = &omap2_clksel_recalc,
2080 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2081 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2082 .clkdm_name = "l4_per_clkdm",
2083};
2084
2085/* Merged cm2_dm4_mux into timer4 */
2086static struct clk timer4_fck = {
2087 .name = "timer4_fck",
2088 .parent = &sys_clkin_ck,
2089 .clksel = abe_dpll_bypass_clk_mux_sel,
2090 .init = &omap2_init_clksel_parent,
2091 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2092 .clksel_mask = OMAP4430_CLKSEL_MASK,
2093 .ops = &clkops_omap2_dflt,
2094 .recalc = &omap2_clksel_recalc,
2095 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2096 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2097 .clkdm_name = "l4_per_clkdm",
2098};
2099
2100static const struct clksel timer5_sync_mux_sel[] = {
2101 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2102 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2103 { .parent = NULL },
2104};
2105
2106/* Merged timer5_sync_mux into timer5 */
2107static struct clk timer5_fck = {
2108 .name = "timer5_fck",
2109 .parent = &syc_clk_div_ck,
2110 .clksel = timer5_sync_mux_sel,
2111 .init = &omap2_init_clksel_parent,
2112 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2113 .clksel_mask = OMAP4430_CLKSEL_MASK,
2114 .ops = &clkops_omap2_dflt,
2115 .recalc = &omap2_clksel_recalc,
2116 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2117 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2118 .clkdm_name = "abe_clkdm",
2119};
2120
2121/* Merged timer6_sync_mux into timer6 */
2122static struct clk timer6_fck = {
2123 .name = "timer6_fck",
2124 .parent = &syc_clk_div_ck,
2125 .clksel = timer5_sync_mux_sel,
2126 .init = &omap2_init_clksel_parent,
2127 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2128 .clksel_mask = OMAP4430_CLKSEL_MASK,
2129 .ops = &clkops_omap2_dflt,
2130 .recalc = &omap2_clksel_recalc,
2131 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2132 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2133 .clkdm_name = "abe_clkdm",
2134};
2135
2136/* Merged timer7_sync_mux into timer7 */
2137static struct clk timer7_fck = {
2138 .name = "timer7_fck",
2139 .parent = &syc_clk_div_ck,
2140 .clksel = timer5_sync_mux_sel,
2141 .init = &omap2_init_clksel_parent,
2142 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2143 .clksel_mask = OMAP4430_CLKSEL_MASK,
2144 .ops = &clkops_omap2_dflt,
2145 .recalc = &omap2_clksel_recalc,
2146 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2147 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2148 .clkdm_name = "abe_clkdm",
2149};
2150
2151/* Merged timer8_sync_mux into timer8 */
2152static struct clk timer8_fck = {
2153 .name = "timer8_fck",
2154 .parent = &syc_clk_div_ck,
2155 .clksel = timer5_sync_mux_sel,
2156 .init = &omap2_init_clksel_parent,
2157 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2158 .clksel_mask = OMAP4430_CLKSEL_MASK,
2159 .ops = &clkops_omap2_dflt,
2160 .recalc = &omap2_clksel_recalc,
2161 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2162 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2163 .clkdm_name = "abe_clkdm",
2164};
2165
2166/* Merged cm2_dm9_mux into timer9 */
2167static struct clk timer9_fck = {
2168 .name = "timer9_fck",
2169 .parent = &sys_clkin_ck,
2170 .clksel = abe_dpll_bypass_clk_mux_sel,
2171 .init = &omap2_init_clksel_parent,
2172 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2173 .clksel_mask = OMAP4430_CLKSEL_MASK,
2174 .ops = &clkops_omap2_dflt,
2175 .recalc = &omap2_clksel_recalc,
2176 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2177 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2178 .clkdm_name = "l4_per_clkdm",
2213}; 2179};
2214 2180
2215static struct clk uart1_fck = { 2181static struct clk uart1_fck = {
@@ -2252,18 +2218,18 @@ static struct clk uart4_fck = {
2252 .recalc = &followparent_recalc, 2218 .recalc = &followparent_recalc,
2253}; 2219};
2254 2220
2255static struct clk unipro1_fck = { 2221static struct clk usb_host_fs_fck = {
2256 .name = "unipro1_fck", 2222 .name = "usb_host_fs_fck",
2257 .ops = &clkops_omap2_dflt, 2223 .ops = &clkops_omap2_dflt,
2258 .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, 2224 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2259 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2225 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2260 .clkdm_name = "l3_init_clkdm", 2226 .clkdm_name = "l3_init_clkdm",
2261 .parent = &func_96m_fclk, 2227 .parent = &func_48mc_fclk,
2262 .recalc = &followparent_recalc, 2228 .recalc = &followparent_recalc,
2263}; 2229};
2264 2230
2265static struct clk usb_host_fck = { 2231static struct clk usb_host_hs_fck = {
2266 .name = "usb_host_fck", 2232 .name = "usb_host_hs_fck",
2267 .ops = &clkops_omap2_dflt, 2233 .ops = &clkops_omap2_dflt,
2268 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2234 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2269 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2235 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2272,18 +2238,8 @@ static struct clk usb_host_fck = {
2272 .recalc = &followparent_recalc, 2238 .recalc = &followparent_recalc,
2273}; 2239};
2274 2240
2275static struct clk usb_host_fs_fck = { 2241static struct clk usb_otg_hs_ick = {
2276 .name = "usb_host_fs_fck", 2242 .name = "usb_otg_hs_ick",
2277 .ops = &clkops_omap2_dflt,
2278 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2279 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2280 .clkdm_name = "l3_init_clkdm",
2281 .parent = &func_48mc_fclk,
2282 .recalc = &followparent_recalc,
2283};
2284
2285static struct clk usb_otg_ick = {
2286 .name = "usb_otg_ick",
2287 .ops = &clkops_omap2_dflt, 2243 .ops = &clkops_omap2_dflt,
2288 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, 2244 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2289 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2245 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2292,8 +2248,8 @@ static struct clk usb_otg_ick = {
2292 .recalc = &followparent_recalc, 2248 .recalc = &followparent_recalc,
2293}; 2249};
2294 2250
2295static struct clk usb_tll_ick = { 2251static struct clk usb_tll_hs_ick = {
2296 .name = "usb_tll_ick", 2252 .name = "usb_tll_hs_ick",
2297 .ops = &clkops_omap2_dflt, 2253 .ops = &clkops_omap2_dflt,
2298 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, 2254 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2299 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2255 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2302,8 +2258,8 @@ static struct clk usb_tll_ick = {
2302 .recalc = &followparent_recalc, 2258 .recalc = &followparent_recalc,
2303}; 2259};
2304 2260
2305static struct clk usim_ick = { 2261static struct clk usim_fck = {
2306 .name = "usim_ick", 2262 .name = "usim_fck",
2307 .ops = &clkops_omap2_dflt, 2263 .ops = &clkops_omap2_dflt,
2308 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, 2264 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2309 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2265 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2312,8 +2268,8 @@ static struct clk usim_ick = {
2312 .recalc = &followparent_recalc, 2268 .recalc = &followparent_recalc,
2313}; 2269};
2314 2270
2315static struct clk wdt2_fck = { 2271static struct clk wd_timer2_fck = {
2316 .name = "wdt2_fck", 2272 .name = "wd_timer2_fck",
2317 .ops = &clkops_omap2_dflt, 2273 .ops = &clkops_omap2_dflt,
2318 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, 2274 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2319 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2275 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2322,8 +2278,8 @@ static struct clk wdt2_fck = {
2322 .recalc = &followparent_recalc, 2278 .recalc = &followparent_recalc,
2323}; 2279};
2324 2280
2325static struct clk wdt3_fck = { 2281static struct clk wd_timer3_fck = {
2326 .name = "wdt3_fck", 2282 .name = "wd_timer3_fck",
2327 .ops = &clkops_omap2_dflt, 2283 .ops = &clkops_omap2_dflt,
2328 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, 2284 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2329 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2285 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2535,16 +2491,16 @@ static struct omap_clk omap44xx_clks[] = {
2535 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), 2491 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
2536 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 2492 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
2537 CLK(NULL, "aess_fck", &aess_fck, CK_443X), 2493 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
2538 CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X),
2539 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), 2494 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
2540 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 2495 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
2541 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), 2496 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
2497 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
2542 CLK(NULL, "dss_fck", &dss_fck, CK_443X), 2498 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
2543 CLK(NULL, "ducati_ick", &ducati_ick, CK_443X), 2499 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
2544 CLK(NULL, "emif1_ick", &emif1_ick, CK_443X), 2500 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
2545 CLK(NULL, "emif2_ick", &emif2_ick, CK_443X), 2501 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
2546 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), 2502 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
2547 CLK(NULL, "gfx_fck", &gfx_fck, CK_443X), 2503 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
2548 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), 2504 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
2549 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), 2505 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
2550 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), 2506 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
@@ -2552,28 +2508,19 @@ static struct omap_clk omap44xx_clks[] = {
2552 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), 2508 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
2553 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), 2509 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
2554 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), 2510 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
2555 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X), 2511 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
2556 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X),
2557 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X),
2558 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X),
2559 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X),
2560 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X),
2561 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X),
2562 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X),
2563 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X),
2564 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X),
2565 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X),
2566 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), 2512 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
2567 CLK(NULL, "hsi_ick", &hsi_ick, CK_443X), 2513 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
2568 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), 2514 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X),
2569 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X), 2515 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X),
2570 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), 2516 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X),
2571 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), 2517 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X),
2518 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
2572 CLK(NULL, "iss_fck", &iss_fck, CK_443X), 2519 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
2573 CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X), 2520 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
2574 CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X), 2521 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
2575 CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X), 2522 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
2576 CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X), 2523 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
2577 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 2524 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
2578 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), 2525 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
2579 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 2526 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
@@ -2584,6 +2531,7 @@ static struct omap_clk omap44xx_clks[] = {
2584 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), 2531 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
2585 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 2532 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
2586 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), 2533 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
2534 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
2587 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), 2535 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
2588 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), 2536 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
2589 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), 2537 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
@@ -2593,30 +2541,37 @@ static struct omap_clk omap44xx_clks[] = {
2593 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), 2541 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
2594 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), 2542 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
2595 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), 2543 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
2596 CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X), 2544 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
2597 CLK(NULL, "pdm_fck", &pdm_fck, CK_443X),
2598 CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X),
2599 CLK("omap_rng", "ick", &rng_ick, CK_443X), 2545 CLK("omap_rng", "ick", &rng_ick, CK_443X),
2600 CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X), 2546 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
2601 CLK(NULL, "sl2_ick", &sl2_ick, CK_443X), 2547 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
2602 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), 2548 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
2603 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), 2549 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
2604 CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X), 2550 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
2605 CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X), 2551 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
2606 CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X), 2552 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
2607 CLK(NULL, "tesla_ick", &tesla_ick, CK_443X), 2553 CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
2554 CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X),
2555 CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X),
2556 CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X),
2557 CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X),
2558 CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X),
2559 CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X),
2560 CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X),
2561 CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X),
2562 CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X),
2563 CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X),
2608 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), 2564 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
2609 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), 2565 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
2610 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), 2566 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
2611 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), 2567 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
2612 CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X),
2613 CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X),
2614 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), 2568 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
2615 CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X), 2569 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
2616 CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X), 2570 CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X),
2617 CLK(NULL, "usim_ick", &usim_ick, CK_443X), 2571 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
2618 CLK("omap_wdt", "fck", &wdt2_fck, CK_443X), 2572 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
2619 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X), 2573 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
2574 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
2620 CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), 2575 CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X),
2621 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 2576 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
2622 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 2577 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
@@ -2645,19 +2600,19 @@ static struct omap_clk omap44xx_clks[] = {
2645 CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X), 2600 CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X),
2646 CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X), 2601 CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X),
2647 CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X), 2602 CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X),
2603 CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
2604 CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
2605 CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
2606 CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
2607 CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
2648 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), 2608 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
2649 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), 2609 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
2650 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), 2610 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
2651 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), 2611 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
2652 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), 2612 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
2653 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), 2613 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
2654 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), 2614 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
2655 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), 2615 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
2656 CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
2657 CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
2658 CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
2659 CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
2660 CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
2661 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), 2616 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
2662 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), 2617 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
2663 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), 2618 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 02:29:21 -0400