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authorTakashi Ohmasa <ohmasa.takashi@jp.panasonic.com>2007-10-19 08:59:15 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-10-20 18:42:22 -0400
commitb9a5ce3cae2f6d04c521204004a36be46656ec7b (patch)
tree6aae53d24599dbd279fc00196e3db2c33bc8ddd1 /arch/arm/vfp
parent67f18f34583c9dda0dbcd4088df9070926f7e611 (diff)
[ARM] 4630/1: Fix the vector stride of the double vector instruction.
The vector stride of the double-precision vector instructions must be changed to 1-2 from even 2-4, because the double registers numbering has been changed to 0-15 from even 0-30 by 1356c1948da967bc1d4c663762bfe21dfcec4b2f commit. Signed-off-by: Takashi Ohmasa <ohmasa.takashi@jp.panasonic.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/vfp')
-rw-r--r--arch/arm/vfp/vfpdouble.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/vfp/vfpdouble.c b/arch/arm/vfp/vfpdouble.c
index 74e89f8fb3a..190a09ad18e 100644
--- a/arch/arm/vfp/vfpdouble.c
+++ b/arch/arm/vfp/vfpdouble.c
@@ -1132,7 +1132,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
1132 unsigned int vecitr, veclen, vecstride; 1132 unsigned int vecitr, veclen, vecstride;
1133 struct op *fop; 1133 struct op *fop;
1134 1134
1135 vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2; 1135 vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK));
1136 1136
1137 fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)]; 1137 fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
1138 1138
@@ -1184,10 +1184,10 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
1184 * CHECK: It appears to be undefined whether we stop when 1184 * CHECK: It appears to be undefined whether we stop when
1185 * we encounter an exception. We continue. 1185 * we encounter an exception. We continue.
1186 */ 1186 */
1187 dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6); 1187 dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 3);
1188 dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6); 1188 dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 3);
1189 if (FREG_BANK(dm) != 0) 1189 if (FREG_BANK(dm) != 0)
1190 dm = FREG_BANK(dm) + ((FREG_IDX(dm) + vecstride) & 6); 1190 dm = FREG_BANK(dm) + ((FREG_IDX(dm) + vecstride) & 3);
1191 } 1191 }
1192 return exceptions; 1192 return exceptions;
1193 1193