Added missing tegra files.HEADmaster

10 files changed, 704 insertions, 0 deletions

diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
new file mode 100644
index 00000000000..0062bafef12
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -0,0 +1,249 @@
+/*
+ * arch/arm/plat-spear/include/plat/clock.h
+ *
+ * Clock framework definitions for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_CLOCK_H
+#define __PLAT_CLOCK_H
+
+#include <linux/list.h>
+#include <linux/clkdev.h>
+#include <linux/types.h>
+
+/* clk structure flags */
+#define ALWAYS_ENABLED          (1 << 0) /* clock always enabled */
+#define RESET_TO_ENABLE         (1 << 1) /* reset register bit to enable clk */
+#define ENABLED_ON_INIT         (1 << 2) /* clocks enabled at init */
+
+/**
+ * struct clkops - clock operations
+ * @enable: pointer to clock enable function
+ * @disable: pointer to clock disable function
+ */
+struct clkops {
+        int (*enable) (struct clk *);
+        void (*disable) (struct clk *);
+};
+
+/**
+ * struct pclk_info - parents info
+ * @pclk: pointer to parent clk
+ * @pclk_val: value to be written for selecting this parent
+ */
+struct pclk_info {
+        struct clk *pclk;
+        u8 pclk_val;
+};
+
+/**
+ * struct pclk_sel - parents selection configuration
+ * @pclk_info: pointer to array of parent clock info
+ * @pclk_count: number of parents
+ * @pclk_sel_reg: register for selecting a parent
+ * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also)
+ */
+struct pclk_sel {
+        struct pclk_info *pclk_info;
+        u8 pclk_count;
+        void __iomem *pclk_sel_reg;
+        unsigned int pclk_sel_mask;
+};
+
+/**
+ * struct rate_config - clk rate configurations
+ * @tbls: array of device specific clk rate tables, in ascending order of rates
+ * @count: size of tbls array
+ * @default_index: default setting when originally disabled
+ */
+struct rate_config {
+        void *tbls;
+        u8 count;
+        u8 default_index;
+};
+
+/**
+ * struct clk - clock structure
+ * @usage_count: num of users who enabled this clock
+ * @flags: flags for clock properties
+ * @rate: programmed clock rate in Hz
+ * @en_reg: clk enable/disable reg
+ * @en_reg_bit: clk enable/disable bit
+ * @ops: clk enable/disable ops - generic_clkops selected if NULL
+ * @recalc: pointer to clock rate recalculate function
+ * @set_rate: pointer to clock set rate function
+ * @calc_rate: pointer to clock get rate function for index
+ * @rate_config: rate configuration information, used by set_rate
+ * @div_factor: division factor to parent clock.
+ * @pclk: current parent clk
+ * @pclk_sel: pointer to parent selection structure
+ * @pclk_sel_shift: register shift for selecting parent of this clock
+ * @children: list for childrens or this clock
+ * @sibling: node for list of clocks having same parents
+ * @private_data: clock specific private data
+ * @node: list to maintain clocks linearly
+ * @cl: clocklook up associated with this clock
+ * @dent: object for debugfs
+ */
+struct clk {
+        unsigned int usage_count;
+        unsigned int flags;
+        unsigned long rate;
+        void __iomem *en_reg;
+        u8 en_reg_bit;
+        const struct clkops *ops;
+        int (*recalc) (struct clk *);
+        int (*set_rate) (struct clk *, unsigned long rate);
+        unsigned long (*calc_rate)(struct clk *, int index);
+        struct rate_config rate_config;
+        unsigned int div_factor;
+
+        struct clk *pclk;
+        struct pclk_sel *pclk_sel;
+        unsigned int pclk_sel_shift;
+
+        struct list_head children;
+        struct list_head sibling;
+        void *private_data;
+#ifdef CONFIG_DEBUG_FS
+        struct list_head node;
+        struct clk_lookup *cl;
+        struct dentry *dent;
+#endif
+};
+
+/* pll configuration structure */
+struct pll_clk_masks {
+        u32 mode_mask;
+        u32 mode_shift;
+
+        u32 norm_fdbk_m_mask;
+        u32 norm_fdbk_m_shift;
+        u32 dith_fdbk_m_mask;
+        u32 dith_fdbk_m_shift;
+        u32 div_p_mask;
+        u32 div_p_shift;
+        u32 div_n_mask;
+        u32 div_n_shift;
+};
+
+struct pll_clk_config {
+        void __iomem *mode_reg;
+        void __iomem *cfg_reg;
+        struct pll_clk_masks *masks;
+};
+
+/* pll clk rate config structure */
+struct pll_rate_tbl {
+        u8 mode;
+        u16 m;
+        u8 n;
+        u8 p;
+};
+
+/* ahb and apb bus configuration structure */
+struct bus_clk_masks {
+        u32 mask;
+        u32 shift;
+};
+
+struct bus_clk_config {
+        void __iomem *reg;
+        struct bus_clk_masks *masks;
+};
+
+/* ahb and apb clk bus rate config structure */
+struct bus_rate_tbl {
+        u8 div;
+};
+
+/* Aux clk configuration structure: applicable to UART and FIRDA */
+struct aux_clk_masks {
+        u32 eq_sel_mask;
+        u32 eq_sel_shift;
+        u32 eq1_mask;
+        u32 eq2_mask;
+        u32 xscale_sel_mask;
+        u32 xscale_sel_shift;
+        u32 yscale_sel_mask;
+        u32 yscale_sel_shift;
+};
+
+struct aux_clk_config {
+        void __iomem *synth_reg;
+        struct aux_clk_masks *masks;
+};
+
+/* aux clk rate config structure */
+struct aux_rate_tbl {
+        u16 xscale;
+        u16 yscale;
+        u8 eq;
+};
+
+/* GPT clk configuration structure */
+struct gpt_clk_masks {
+        u32 mscale_sel_mask;
+        u32 mscale_sel_shift;
+        u32 nscale_sel_mask;
+        u32 nscale_sel_shift;
+};
+
+struct gpt_clk_config {
+        void __iomem *synth_reg;
+        struct gpt_clk_masks *masks;
+};
+
+/* gpt clk rate config structure */
+struct gpt_rate_tbl {
+        u16 mscale;
+        u16 nscale;
+};
+
+/* clcd clk configuration structure */
+struct clcd_synth_masks {
+        u32 div_factor_mask;
+        u32 div_factor_shift;
+};
+
+struct clcd_clk_config {
+        void __iomem *synth_reg;
+        struct clcd_synth_masks *masks;
+};
+
+/* clcd clk rate config structure */
+struct clcd_rate_tbl {
+        u16 div;
+};
+
+/* platform specific clock functions */
+void __init clk_init(void);
+void clk_register(struct clk_lookup *cl);
+void recalc_root_clocks(void);
+
+/* clock recalc & set rate functions */
+int follow_parent(struct clk *clk);
+unsigned long pll_calc_rate(struct clk *clk, int index);
+int pll_clk_recalc(struct clk *clk);
+int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate);
+unsigned long bus_calc_rate(struct clk *clk, int index);
+int bus_clk_recalc(struct clk *clk);
+int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate);
+unsigned long gpt_calc_rate(struct clk *clk, int index);
+int gpt_clk_recalc(struct clk *clk);
+int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate);
+unsigned long aux_calc_rate(struct clk *clk, int index);
+int aux_clk_recalc(struct clk *clk);
+int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
+unsigned long clcd_calc_rate(struct clk *clk, int index);
+int clcd_clk_recalc(struct clk *clk);
+int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
+
+#endif /* __PLAT_CLOCK_H */
diff --git a/arch/arm/plat-spear/include/plat/gpio.h b/arch/arm/plat-spear/include/plat/gpio.h
new file mode 100644
index 00000000000..b857c91257d
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/gpio.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/plat-spear/include/plat/gpio.h
+ *
+ * GPIO macros for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_GPIO_H
+#define __PLAT_GPIO_H
+
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
+#endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h
new file mode 100644
index 00000000000..66d677225d1
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/hardware.h
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/plat-spear/include/plat/hardware.h
+ *
+ * Hardware definitions for SPEAr
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_HARDWARE_H
+#define __PLAT_HARDWARE_H
+
+#ifndef __ASSEMBLY__
+#define IOMEM(x)        ((void __iomem __force *)(x))
+#else
+#define IOMEM(x)        (x)
+#endif
+
+#endif /* __PLAT_HARDWARE_H */
diff --git a/arch/arm/plat-spear/include/plat/io.h b/arch/arm/plat-spear/include/plat/io.h
new file mode 100644
index 00000000000..4d4ba822b3e
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/io.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/plat-spear/include/plat/io.h
+ *
+ * IO definitions for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_IO_H
+#define __PLAT_IO_H
+
+#define IO_SPACE_LIMIT          0xFFFFFFFF
+
+#define __io(a)                 __typesafe_io(a)
+#define __mem_pci(a)            (a)
+
+#endif /* __PLAT_IO_H */
diff --git a/arch/arm/plat-spear/include/plat/keyboard.h b/arch/arm/plat-spear/include/plat/keyboard.h
new file mode 100644
index 00000000000..68b5394fc58
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/keyboard.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2010 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_KEYBOARD_H
+#define __PLAT_KEYBOARD_H
+
+#include <linux/bitops.h>
+#include <linux/input.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/types.h>
+
+#define DECLARE_KEYMAP(_name) \
+int _name[] = { \
+        KEY(0, 0, KEY_ESC), \
+        KEY(0, 1, KEY_1), \
+        KEY(0, 2, KEY_2), \
+        KEY(0, 3, KEY_3), \
+        KEY(0, 4, KEY_4), \
+        KEY(0, 5, KEY_5), \
+        KEY(0, 6, KEY_6), \
+        KEY(0, 7, KEY_7), \
+        KEY(0, 8, KEY_8), \
+        KEY(1, 0, KEY_9), \
+        KEY(1, 1, KEY_MINUS), \
+        KEY(1, 2, KEY_EQUAL), \
+        KEY(1, 3, KEY_BACKSPACE), \
+        KEY(1, 4, KEY_TAB), \
+        KEY(1, 5, KEY_Q), \
+        KEY(1, 6, KEY_W), \
+        KEY(1, 7, KEY_E), \
+        KEY(1, 8, KEY_R), \
+        KEY(2, 0, KEY_T), \
+        KEY(2, 1, KEY_Y), \
+        KEY(2, 2, KEY_U), \
+        KEY(2, 3, KEY_I), \
+        KEY(2, 4, KEY_O), \
+        KEY(2, 5, KEY_P), \
+        KEY(2, 6, KEY_LEFTBRACE), \
+        KEY(2, 7, KEY_RIGHTBRACE), \
+        KEY(2, 8, KEY_ENTER), \
+        KEY(3, 0, KEY_LEFTCTRL), \
+        KEY(3, 1, KEY_A), \
+        KEY(3, 2, KEY_S), \
+        KEY(3, 3, KEY_D), \
+        KEY(3, 4, KEY_F), \
+        KEY(3, 5, KEY_G), \
+        KEY(3, 6, KEY_H), \
+        KEY(3, 7, KEY_J), \
+        KEY(3, 8, KEY_K), \
+        KEY(4, 0, KEY_L), \
+        KEY(4, 1, KEY_SEMICOLON), \
+        KEY(4, 2, KEY_APOSTROPHE), \
+        KEY(4, 3, KEY_GRAVE), \
+        KEY(4, 4, KEY_LEFTSHIFT), \
+        KEY(4, 5, KEY_BACKSLASH), \
+        KEY(4, 6, KEY_Z), \
+        KEY(4, 7, KEY_X), \
+        KEY(4, 8, KEY_C), \
+        KEY(4, 0, KEY_L), \
+        KEY(4, 1, KEY_SEMICOLON), \
+        KEY(4, 2, KEY_APOSTROPHE), \
+        KEY(4, 3, KEY_GRAVE), \
+        KEY(4, 4, KEY_LEFTSHIFT), \
+        KEY(4, 5, KEY_BACKSLASH), \
+        KEY(4, 6, KEY_Z), \
+        KEY(4, 7, KEY_X), \
+        KEY(4, 8, KEY_C), \
+        KEY(4, 0, KEY_L), \
+        KEY(4, 1, KEY_SEMICOLON), \
+        KEY(4, 2, KEY_APOSTROPHE), \
+        KEY(4, 3, KEY_GRAVE), \
+        KEY(4, 4, KEY_LEFTSHIFT), \
+        KEY(4, 5, KEY_BACKSLASH), \
+        KEY(4, 6, KEY_Z), \
+        KEY(4, 7, KEY_X), \
+        KEY(4, 8, KEY_C), \
+        KEY(5, 0, KEY_V), \
+        KEY(5, 1, KEY_B), \
+        KEY(5, 2, KEY_N), \
+        KEY(5, 3, KEY_M), \
+        KEY(5, 4, KEY_COMMA), \
+        KEY(5, 5, KEY_DOT), \
+        KEY(5, 6, KEY_SLASH), \
+        KEY(5, 7, KEY_RIGHTSHIFT), \
+        KEY(5, 8, KEY_KPASTERISK), \
+        KEY(6, 0, KEY_LEFTALT), \
+        KEY(6, 1, KEY_SPACE), \
+        KEY(6, 2, KEY_CAPSLOCK), \
+        KEY(6, 3, KEY_F1), \
+        KEY(6, 4, KEY_F2), \
+        KEY(6, 5, KEY_F3), \
+        KEY(6, 6, KEY_F4), \
+        KEY(6, 7, KEY_F5), \
+        KEY(6, 8, KEY_F6), \
+        KEY(7, 0, KEY_F7), \
+        KEY(7, 1, KEY_F8), \
+        KEY(7, 2, KEY_F9), \
+        KEY(7, 3, KEY_F10), \
+        KEY(7, 4, KEY_NUMLOCK), \
+        KEY(7, 5, KEY_SCROLLLOCK), \
+        KEY(7, 6, KEY_KP7), \
+        KEY(7, 7, KEY_KP8), \
+        KEY(7, 8, KEY_KP9), \
+        KEY(8, 0, KEY_KPMINUS), \
+        KEY(8, 1, KEY_KP4), \
+        KEY(8, 2, KEY_KP5), \
+        KEY(8, 3, KEY_KP6), \
+        KEY(8, 4, KEY_KPPLUS), \
+        KEY(8, 5, KEY_KP1), \
+        KEY(8, 6, KEY_KP2), \
+        KEY(8, 7, KEY_KP3), \
+        KEY(8, 8, KEY_KP0), \
+}
+
+/**
+ * struct kbd_platform_data - spear keyboard platform data
+ * keymap: pointer to keymap data (table and size)
+ * rep: enables key autorepeat
+ *
+ * This structure is supposed to be used by platform code to supply
+ * keymaps to drivers that implement keyboards.
+ */
+struct kbd_platform_data {
+        const struct matrix_keymap_data *keymap;
+        bool rep;
+};
+
+/* This function is used to set platform data field of pdev->dev */
+static inline void
+kbd_set_plat_data(struct platform_device *pdev, struct kbd_platform_data *data)
+{
+        pdev->dev.platform_data = data;
+}
+
+#endif /* __PLAT_KEYBOARD_H */
diff --git a/arch/arm/plat-spear/include/plat/memory.h b/arch/arm/plat-spear/include/plat/memory.h
new file mode 100644
index 00000000000..7e3599e1104
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/memory.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-spear/include/plat/memory.h
+ *
+ * Memory map for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_MEMORY_H
+#define __PLAT_MEMORY_H
+
+/* Physical DRAM offset */
+#define PLAT_PHYS_OFFSET                UL(0x00000000)
+
+#endif /* __PLAT_MEMORY_H */
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
new file mode 100644
index 00000000000..877f3adcf61
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/padmux.h
@@ -0,0 +1,92 @@
+/*
+ * arch/arm/plat-spear/include/plat/padmux.h
+ *
+ * SPEAr platform specific gpio pads muxing file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_PADMUX_H
+#define __PLAT_PADMUX_H
+
+#include <linux/types.h>
+
+/*
+ * struct pmx_reg: configuration structure for mode reg and mux reg
+ *
+ * offset: offset of mode reg
+ * mask: mask of mode reg
+ */
+struct pmx_reg {
+        u32 offset;
+        u32 mask;
+};
+
+/*
+ * struct pmx_dev_mode: configuration structure every group of modes of a device
+ *
+ * ids: all modes for this configuration
+ * mask: mask for supported mode
+ */
+struct pmx_dev_mode {
+        u32 ids;
+        u32 mask;
+};
+
+/*
+ * struct pmx_mode: mode definition structure
+ *
+ * name: mode name
+ * mask: mode mask
+ */
+struct pmx_mode {
+        char *name;
+        u32 id;
+        u32 mask;
+};
+
+/*
+ * struct pmx_dev: device definition structure
+ *
+ * name: device name
+ * modes: device configuration array for different modes supported
+ * mode_count: size of modes array
+ * is_active: is peripheral active/enabled
+ * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
+ */
+struct pmx_dev {
+        char *name;
+        struct pmx_dev_mode *modes;
+        u8 mode_count;
+        bool is_active;
+        bool enb_on_reset;
+};
+
+/*
+ * struct pmx_driver: driver definition structure
+ *
+ * mode: mode to be set
+ * devs: array of pointer to pmx devices
+ * devs_count: ARRAY_SIZE of devs
+ * base: base address of soc config registers
+ * mode_reg: structure of mode config register
+ * mux_reg: structure of device mux config register
+ */
+struct pmx_driver {
+        struct pmx_mode *mode;
+        struct pmx_dev **devs;
+        u8 devs_count;
+        u32 *base;
+        struct pmx_reg mode_reg;
+        struct pmx_reg mux_reg;
+};
+
+/* pmx functions */
+int pmx_register(struct pmx_driver *driver);
+
+#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/include/plat/shirq.h b/arch/arm/plat-spear/include/plat/shirq.h
new file mode 100644
index 00000000000..03ed8b585dc
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/shirq.h
@@ -0,0 +1,73 @@
+/*
+ * arch/arm/plat-spear/include/plat/shirq.h
+ *
+ * SPEAr platform shared irq layer header file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_SHIRQ_H
+#define __PLAT_SHIRQ_H
+
+#include <linux/irq.h>
+#include <linux/types.h>
+
+/*
+ * struct shirq_dev_config: shared irq device configuration
+ *
+ * virq: virtual irq number of device
+ * enb_mask: enable mask of device
+ * status_mask: status mask of device
+ * clear_mask: clear mask of device
+ */
+struct shirq_dev_config {
+        u32 virq;
+        u32 enb_mask;
+        u32 status_mask;
+        u32 clear_mask;
+};
+
+/*
+ * struct shirq_regs: shared irq register configuration
+ *
+ * base: base address of shared irq register
+ * enb_reg: enable register offset
+ * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
+ * status_reg: status register offset
+ * status_reg_mask: status register valid mask
+ * clear_reg: clear register offset
+ * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
+ */
+struct shirq_regs {
+        void __iomem *base;
+        u32 enb_reg;
+        u32 reset_to_enb;
+        u32 status_reg;
+        u32 status_reg_mask;
+        u32 clear_reg;
+        u32 reset_to_clear;
+};
+
+/*
+ * struct spear_shirq: shared irq structure
+ *
+ * irq: hardware irq number
+ * dev_config: array of device config structures which are using "irq" line
+ * dev_count: size of dev_config array
+ * regs: register configuration for shared irq block
+ */
+struct spear_shirq {
+        u32 irq;
+        struct shirq_dev_config *dev_config;
+        u32 dev_count;
+        struct shirq_regs regs;
+};
+
+int spear_shirq_register(struct spear_shirq *shirq);
+
+#endif /* __PLAT_SHIRQ_H */
diff --git a/arch/arm/plat-spear/include/plat/system.h b/arch/arm/plat-spear/include/plat/system.h
new file mode 100644
index 00000000000..a235fa0ca77
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/system.h
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/plat-spear/include/plat/system.h
+ *
+ * SPEAr platform specific architecture functions
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_SYSTEM_H
+#define __PLAT_SYSTEM_H
+
+#include <linux/io.h>
+#include <asm/hardware/sp810.h>
+#include <mach/hardware.h>
+
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+        if (mode == 's') {
+                /* software reset, Jump into ROM at address 0 */
+                cpu_reset(0);
+        } else {
+                /* hardware reset, Use on-chip reset capability */
+                sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
+        }
+}
+
+#endif /* __PLAT_SYSTEM_H */
diff --git a/arch/arm/plat-spear/include/plat/vmalloc.h b/arch/arm/plat-spear/include/plat/vmalloc.h
new file mode 100644
index 00000000000..8c8b24d0704
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/vmalloc.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/plat-spear/include/plat/vmalloc.h
+ *
+ * Defining Vmalloc area for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_VMALLOC_H
+#define __PLAT_VMALLOC_H
+
+#define VMALLOC_END             0xF0000000UL
+
+#endif /* __PLAT_VMALLOC_H */