aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-samsung
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-05 21:18:05 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-05 21:18:05 -0400
commit7abec10c623d9e0416dab6919a0ea22e6283516b (patch)
tree83aa79c369e99c4fc60eea91ebd399b7689b312e /arch/arm/plat-samsung
parent0de9adf284ec20454ecf37ffd98e7e98ba7292d6 (diff)
parentcfaf8fc5b59527281e9ddc2e0e04e1127936e17f (diff)
Merge branch 'next/cleanup3' of git://git.linaro.org/people/arnd/arm-soc
* 'next/cleanup3' of git://git.linaro.org/people/arnd/arm-soc: (79 commits) ARM: SAMSUNG: Move fimc plat. device from board files to plat-samsung ARM: SAMSUNG: Cleanup resources by using macro ARM: SAMSUNG: Cleanup plat-samsung/devs.c and devs.h ARM: S5P: To merge devs.c files to one devs.c ARM: S3C64XX: To merge devs.c files to one devs.c ARM: S3C24XX: To merge s3c24xx devs.c files to one devs.c ARM: S5P64X0: Add Power Management support ARM: S5P: Make the sleep code common for S5P series SoCs ARM: S5P: Make the common S5P PM code conditionally compile ARM: SAMSUNG: Move S5P header files to plat-samsung ARM: SAMSUNG: Move S3C24XX header files to plat-samsung ARM: SAMSUNG: Moving each SoC support header files ARM: SAMSUNG: Consolidate plat/pll.h ARM: SAMSUNG: Consolidate plat/pwm-clock.h ARM: SAMSUNG: Cleanup mach/clkdev.h ARM: SAMSUNG: remove sdhci default configuration setup platform helper ARM: EXYNOS4: Add FIMC device on SMDKV310 board ARM: EXYNOS4: Add header file protection macros ARM: EXYNOS4: Add usb ehci device to the SMDKV310 ARM: S3C2443: Add hsspi-clock from pclk and rename S3C2443 hsspi sclk ... Fix up conflicts in - arch/arm/mach-exynos4/{Kconfig,clock.c} ARM_CPU_SUSPEND, various random device tables (gah!) - drivers/gpio/Makefile sa1100 gpio added, samsung gpio drivers merged
Diffstat (limited to 'arch/arm/plat-samsung')
-rw-r--r--arch/arm/plat-samsung/Kconfig27
-rw-r--r--arch/arm/plat-samsung/Makefile33
-rw-r--r--arch/arm/plat-samsung/dev-adc.c46
-rw-r--r--arch/arm/plat-samsung/dev-asocdma.c35
-rw-r--r--arch/arm/plat-samsung/dev-fb.c63
-rw-r--r--arch/arm/plat-samsung/dev-hsmmc.c62
-rw-r--r--arch/arm/plat-samsung/dev-hsmmc1.c62
-rw-r--r--arch/arm/plat-samsung/dev-hsmmc2.c63
-rw-r--r--arch/arm/plat-samsung/dev-hsmmc3.c66
-rw-r--r--arch/arm/plat-samsung/dev-hwmon.c32
-rw-r--r--arch/arm/plat-samsung/dev-i2c0.c70
-rw-r--r--arch/arm/plat-samsung/dev-i2c1.c61
-rw-r--r--arch/arm/plat-samsung/dev-i2c2.c62
-rw-r--r--arch/arm/plat-samsung/dev-i2c3.c60
-rw-r--r--arch/arm/plat-samsung/dev-i2c4.c60
-rw-r--r--arch/arm/plat-samsung/dev-i2c5.c60
-rw-r--r--arch/arm/plat-samsung/dev-i2c6.c60
-rw-r--r--arch/arm/plat-samsung/dev-i2c7.c60
-rw-r--r--arch/arm/plat-samsung/dev-ide.c44
-rw-r--r--arch/arm/plat-samsung/dev-keypad.c50
-rw-r--r--arch/arm/plat-samsung/dev-nand.c125
-rw-r--r--arch/arm/plat-samsung/dev-onenand.c43
-rw-r--r--arch/arm/plat-samsung/dev-pwm.c53
-rw-r--r--arch/arm/plat-samsung/dev-rtc.c43
-rw-r--r--arch/arm/plat-samsung/dev-ts.c59
-rw-r--r--arch/arm/plat-samsung/dev-usb-hsotg.c48
-rw-r--r--arch/arm/plat-samsung/dev-usb.c65
-rw-r--r--arch/arm/plat-samsung/dev-wdt.c40
-rw-r--r--arch/arm/plat-samsung/devs.c1463
-rw-r--r--arch/arm/plat-samsung/gpio-config.c431
-rw-r--r--arch/arm/plat-samsung/gpio.c167
-rw-r--r--arch/arm/plat-samsung/include/plat/audio-simtec.h37
-rw-r--r--arch/arm/plat-samsung/include/plat/camport.h28
-rw-r--r--arch/arm/plat-samsung/include/plat/common-smdk.h15
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu-freq-core.h288
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h151
-rw-r--r--arch/arm/plat-samsung/include/plat/ehci.h21
-rw-r--r--arch/arm/plat-samsung/include/plat/exynos4.h35
-rw-r--r--arch/arm/plat-samsung/include/plat/fb-s3c2410.h72
-rw-r--r--arch/arm/plat-samsung/include/plat/fb.h7
-rw-r--r--arch/arm/plat-samsung/include/plat/fiq.h13
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h172
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg.h34
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-core.h97
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-fns.h98
-rw-r--r--arch/arm/plat-samsung/include/plat/iic.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/irq.h116
-rw-r--r--arch/arm/plat-samsung/include/plat/irqs.h80
-rw-r--r--arch/arm/plat-samsung/include/plat/mci.h52
-rw-r--r--arch/arm/plat-samsung/include/plat/mfc.h27
-rw-r--r--arch/arm/plat-samsung/include/plat/mipi_csis.h43
-rw-r--r--arch/arm/plat-samsung/include/plat/pll.h323
-rw-r--r--arch/arm/plat-samsung/include/plat/pll6553x.h51
-rw-r--r--arch/arm/plat-samsung/include/plat/pm.h10
-rw-r--r--arch/arm/plat-samsung/include/plat/pwm-clock.h81
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-dma.h151
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-iis.h70
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-spi.h48
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-srom.h54
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-udc.h151
-rw-r--r--arch/arm/plat-samsung/include/plat/reset.h16
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c2410.h33
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c2412.h29
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c2416.h31
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c2443.h51
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c244x.h42
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c6400.h36
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c6410.h29
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-clock.h55
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-time.h40
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p6440.h36
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p6450.h36
-rw-r--r--arch/arm/plat-samsung/include/plat/s5pc100.h33
-rw-r--r--arch/arm/plat-samsung/include/plat/s5pv210.h33
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h57
-rw-r--r--arch/arm/plat-samsung/include/plat/sysmmu.h95
-rw-r--r--arch/arm/plat-samsung/include/plat/system-reset.h31
-rw-r--r--arch/arm/plat-samsung/include/plat/tv-core.h44
-rw-r--r--arch/arm/plat-samsung/include/plat/udc.h57
-rw-r--r--arch/arm/plat-samsung/include/plat/usb-phy.h22
-rw-r--r--arch/arm/plat-samsung/platformdata.c2
-rw-r--r--arch/arm/plat-samsung/pm-gpio.c72
-rw-r--r--arch/arm/plat-samsung/pm.c6
-rw-r--r--arch/arm/plat-samsung/pwm-clock.c13
84 files changed, 4236 insertions, 2602 deletions
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 7a96198e3a7..313eb26cfa6 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -74,39 +74,12 @@ config SAMSUNG_GPIOLIB_4BIT
74 configuration. GPIOlib shall be compiled only for S3C64XX and S5P 74 configuration. GPIOlib shall be compiled only for S3C64XX and S5P
75 series of processors. 75 series of processors.
76 76
77config S3C_GPIO_CFG_S3C24XX
78 bool
79 help
80 Internal configuration to enable S3C24XX style GPIO configuration
81 functions.
82
83config S3C_GPIO_CFG_S3C64XX 77config S3C_GPIO_CFG_S3C64XX
84 bool 78 bool
85 help 79 help
86 Internal configuration to enable S3C64XX style GPIO configuration 80 Internal configuration to enable S3C64XX style GPIO configuration
87 functions. 81 functions.
88 82
89config S3C_GPIO_PULL_UPDOWN
90 bool
91 help
92 Internal configuration to enable the correct GPIO pull helper
93
94config S3C_GPIO_PULL_S3C2443
95 bool
96 select S3C_GPIO_PULL_UPDOWN
97 help
98 Internal configuration to enable the correct GPIO pull helper for S3C2443-style GPIO
99
100config S3C_GPIO_PULL_DOWN
101 bool
102 help
103 Internal configuration to enable the correct GPIO pull helper
104
105config S3C_GPIO_PULL_UP
106 bool
107 help
108 Internal configuration to enable the correct GPIO pull helper
109
110config S5P_GPIO_DRVSTR 83config S5P_GPIO_DRVSTR
111 bool 84 bool
112 help 85 help
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 3dd5dbad55c..6012366f33c 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -1,4 +1,4 @@
1# arch/arm/plat-s3c64xx/Makefile 1# arch/arm/plat-samsung/Makefile
2# 2#
3# Copyright 2009 Simtec Electronics 3# Copyright 2009 Simtec Electronics
4# 4#
@@ -15,9 +15,6 @@ obj-y += init.o cpu.o
15obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o 15obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o
16obj-y += clock.o 16obj-y += clock.o
17obj-y += pwm-clock.o 17obj-y += pwm-clock.o
18obj-y += gpio.o
19obj-y += gpio-config.o
20obj-y += dev-asocdma.o
21 18
22obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o 19obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
23 20
@@ -31,33 +28,9 @@ obj-$(CONFIG_S3C_ADC) += adc.o
31 28
32obj-y += platformdata.o 29obj-y += platformdata.o
33 30
34obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o 31obj-y += devs.o
35obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
36obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o
37obj-$(CONFIG_S3C_DEV_HSMMC3) += dev-hsmmc3.o
38obj-$(CONFIG_S3C_DEV_HWMON) += dev-hwmon.o
39obj-y += dev-i2c0.o
40obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
41obj-$(CONFIG_S3C_DEV_I2C2) += dev-i2c2.o
42obj-$(CONFIG_S3C_DEV_I2C3) += dev-i2c3.o
43obj-$(CONFIG_S3C_DEV_I2C4) += dev-i2c4.o
44obj-$(CONFIG_S3C_DEV_I2C5) += dev-i2c5.o
45obj-$(CONFIG_S3C_DEV_I2C6) += dev-i2c6.o
46obj-$(CONFIG_S3C_DEV_I2C7) += dev-i2c7.o
47obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
48obj-y += dev-uart.o 32obj-y += dev-uart.o
49obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o 33
50obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
51obj-$(CONFIG_S3C_DEV_WDT) += dev-wdt.o
52obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o
53obj-$(CONFIG_S3C_DEV_ONENAND) += dev-onenand.o
54obj-$(CONFIG_S3C_DEV_RTC) += dev-rtc.o
55
56obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o
57obj-$(CONFIG_SAMSUNG_DEV_IDE) += dev-ide.o
58obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o
59obj-$(CONFIG_SAMSUNG_DEV_KEYPAD) += dev-keypad.o
60obj-$(CONFIG_SAMSUNG_DEV_PWM) += dev-pwm.o
61obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o 34obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o
62 35
63# DMA support 36# DMA support
diff --git a/arch/arm/plat-samsung/dev-adc.c b/arch/arm/plat-samsung/dev-adc.c
deleted file mode 100644
index 9d903d4095e..00000000000
--- a/arch/arm/plat-samsung/dev-adc.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-adc.c
2 *
3 * Copyright 2010 Maurus Cuelenaere
4 *
5 * S3C64xx series device definition for ADC device
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/platform_device.h>
15
16#include <mach/irqs.h>
17#include <mach/map.h>
18
19#include <plat/adc.h>
20#include <plat/devs.h>
21#include <plat/cpu.h>
22
23static struct resource s3c_adc_resource[] = {
24 [0] = {
25 .start = SAMSUNG_PA_ADC,
26 .end = SAMSUNG_PA_ADC + SZ_256 - 1,
27 .flags = IORESOURCE_MEM,
28 },
29 [1] = {
30 .start = IRQ_TC,
31 .end = IRQ_TC,
32 .flags = IORESOURCE_IRQ,
33 },
34 [2] = {
35 .start = IRQ_ADC,
36 .end = IRQ_ADC,
37 .flags = IORESOURCE_IRQ,
38 },
39};
40
41struct platform_device s3c_device_adc = {
42 .name = "samsung-adc",
43 .id = -1,
44 .num_resources = ARRAY_SIZE(s3c_adc_resource),
45 .resource = s3c_adc_resource,
46};
diff --git a/arch/arm/plat-samsung/dev-asocdma.c b/arch/arm/plat-samsung/dev-asocdma.c
deleted file mode 100644
index 97e35d3c064..00000000000
--- a/arch/arm/plat-samsung/dev-asocdma.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-asocdma.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <plat/devs.h>
14
15static u64 audio_dmamask = DMA_BIT_MASK(32);
16
17struct platform_device samsung_asoc_dma = {
18 .name = "samsung-audio",
19 .id = -1,
20 .dev = {
21 .dma_mask = &audio_dmamask,
22 .coherent_dma_mask = DMA_BIT_MASK(32),
23 }
24};
25EXPORT_SYMBOL(samsung_asoc_dma);
26
27struct platform_device samsung_asoc_idma = {
28 .name = "samsung-idma",
29 .id = -1,
30 .dev = {
31 .dma_mask = &audio_dmamask,
32 .coherent_dma_mask = DMA_BIT_MASK(32),
33 }
34};
35EXPORT_SYMBOL(samsung_asoc_idma);
diff --git a/arch/arm/plat-samsung/dev-fb.c b/arch/arm/plat-samsung/dev-fb.c
deleted file mode 100644
index 49a1362fd25..00000000000
--- a/arch/arm/plat-samsung/dev-fb.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/* linux/arch/arm/plat-s3c/dev-fb.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for framebuffer device
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17#include <linux/fb.h>
18#include <linux/gfp.h>
19
20#include <mach/irqs.h>
21#include <mach/map.h>
22
23#include <plat/fb.h>
24#include <plat/devs.h>
25#include <plat/cpu.h>
26
27static struct resource s3c_fb_resource[] = {
28 [0] = {
29 .start = S3C_PA_FB,
30 .end = S3C_PA_FB + SZ_16K - 1,
31 .flags = IORESOURCE_MEM,
32 },
33 [1] = {
34 .start = IRQ_LCD_VSYNC,
35 .end = IRQ_LCD_VSYNC,
36 .flags = IORESOURCE_IRQ,
37 },
38 [2] = {
39 .start = IRQ_LCD_FIFO,
40 .end = IRQ_LCD_FIFO,
41 .flags = IORESOURCE_IRQ,
42 },
43 [3] = {
44 .start = IRQ_LCD_SYSTEM,
45 .end = IRQ_LCD_SYSTEM,
46 .flags = IORESOURCE_IRQ,
47 },
48};
49
50struct platform_device s3c_device_fb = {
51 .name = "s3c-fb",
52 .id = -1,
53 .num_resources = ARRAY_SIZE(s3c_fb_resource),
54 .resource = s3c_fb_resource,
55 .dev.dma_mask = &s3c_device_fb.dev.coherent_dma_mask,
56 .dev.coherent_dma_mask = 0xffffffffUL,
57};
58
59void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
60{
61 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
62 &s3c_device_fb);
63}
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
deleted file mode 100644
index 06825c4276d..00000000000
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/* linux/arch/arm/plat-s3c/dev-hsmmc.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for hsmmc devices
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/mmc/host.h>
17
18#include <mach/map.h>
19#include <plat/sdhci.h>
20#include <plat/devs.h>
21#include <plat/cpu.h>
22
23#define S3C_SZ_HSMMC (0x1000)
24
25static struct resource s3c_hsmmc_resource[] = {
26 [0] = {
27 .start = S3C_PA_HSMMC0,
28 .end = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1,
29 .flags = IORESOURCE_MEM,
30 },
31 [1] = {
32 .start = IRQ_HSMMC0,
33 .end = IRQ_HSMMC0,
34 .flags = IORESOURCE_IRQ,
35 }
36};
37
38static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
39
40struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
41 .max_width = 4,
42 .host_caps = (MMC_CAP_4_BIT_DATA |
43 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
44 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
45};
46
47struct platform_device s3c_device_hsmmc0 = {
48 .name = "s3c-sdhci",
49 .id = 0,
50 .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
51 .resource = s3c_hsmmc_resource,
52 .dev = {
53 .dma_mask = &s3c_device_hsmmc_dmamask,
54 .coherent_dma_mask = 0xffffffffUL,
55 .platform_data = &s3c_hsmmc0_def_platdata,
56 },
57};
58
59void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
60{
61 s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
62}
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
deleted file mode 100644
index 4524ef44001..00000000000
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/* linux/arch/arm/plat-s3c/dev-hsmmc1.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for hsmmc device 1
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/mmc/host.h>
17
18#include <mach/map.h>
19#include <plat/sdhci.h>
20#include <plat/devs.h>
21#include <plat/cpu.h>
22
23#define S3C_SZ_HSMMC (0x1000)
24
25static struct resource s3c_hsmmc1_resource[] = {
26 [0] = {
27 .start = S3C_PA_HSMMC1,
28 .end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
29 .flags = IORESOURCE_MEM,
30 },
31 [1] = {
32 .start = IRQ_HSMMC1,
33 .end = IRQ_HSMMC1,
34 .flags = IORESOURCE_IRQ,
35 }
36};
37
38static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL;
39
40struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
41 .max_width = 4,
42 .host_caps = (MMC_CAP_4_BIT_DATA |
43 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
44 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
45};
46
47struct platform_device s3c_device_hsmmc1 = {
48 .name = "s3c-sdhci",
49 .id = 1,
50 .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
51 .resource = s3c_hsmmc1_resource,
52 .dev = {
53 .dma_mask = &s3c_device_hsmmc1_dmamask,
54 .coherent_dma_mask = 0xffffffffUL,
55 .platform_data = &s3c_hsmmc1_def_platdata,
56 },
57};
58
59void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
60{
61 s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
62}
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
deleted file mode 100644
index 9cede9615e4..00000000000
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/* linux/arch/arm/plat-s3c/dev-hsmmc2.c
2 *
3 * Copyright (c) 2009 Samsung Electronics
4 * Copyright (c) 2009 Maurus Cuelenaere
5 *
6 * Based on arch/arm/plat-s3c/dev-hsmmc1.c
7 * original file Copyright (c) 2008 Simtec Electronics
8 *
9 * S3C series device definition for hsmmc device 2
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18#include <linux/mmc/host.h>
19
20#include <mach/map.h>
21#include <plat/sdhci.h>
22#include <plat/devs.h>
23
24#define S3C_SZ_HSMMC (0x1000)
25
26static struct resource s3c_hsmmc2_resource[] = {
27 [0] = {
28 .start = S3C_PA_HSMMC2,
29 .end = S3C_PA_HSMMC2 + S3C_SZ_HSMMC - 1,
30 .flags = IORESOURCE_MEM,
31 },
32 [1] = {
33 .start = IRQ_HSMMC2,
34 .end = IRQ_HSMMC2,
35 .flags = IORESOURCE_IRQ,
36 }
37};
38
39static u64 s3c_device_hsmmc2_dmamask = 0xffffffffUL;
40
41struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
42 .max_width = 4,
43 .host_caps = (MMC_CAP_4_BIT_DATA |
44 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
45 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
46};
47
48struct platform_device s3c_device_hsmmc2 = {
49 .name = "s3c-sdhci",
50 .id = 2,
51 .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
52 .resource = s3c_hsmmc2_resource,
53 .dev = {
54 .dma_mask = &s3c_device_hsmmc2_dmamask,
55 .coherent_dma_mask = 0xffffffffUL,
56 .platform_data = &s3c_hsmmc2_def_platdata,
57 },
58};
59
60void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
61{
62 s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
63}
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c
deleted file mode 100644
index 0358ef4a8f6..00000000000
--- a/arch/arm/plat-samsung/dev-hsmmc3.c
+++ /dev/null
@@ -1,66 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-hsmmc3.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (c) 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * Based on arch/arm/plat-samsung/dev-hsmmc1.c
11 *
12 * Samsung device definition for hsmmc device 3
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17*/
18
19#include <linux/kernel.h>
20#include <linux/platform_device.h>
21#include <linux/mmc/host.h>
22
23#include <mach/map.h>
24#include <plat/sdhci.h>
25#include <plat/devs.h>
26
27#define S3C_SZ_HSMMC (0x1000)
28
29static struct resource s3c_hsmmc3_resource[] = {
30 [0] = {
31 .start = S3C_PA_HSMMC3,
32 .end = S3C_PA_HSMMC3 + S3C_SZ_HSMMC - 1,
33 .flags = IORESOURCE_MEM,
34 },
35 [1] = {
36 .start = IRQ_HSMMC3,
37 .end = IRQ_HSMMC3,
38 .flags = IORESOURCE_IRQ,
39 }
40};
41
42static u64 s3c_device_hsmmc3_dmamask = 0xffffffffUL;
43
44struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
45 .max_width = 4,
46 .host_caps = (MMC_CAP_4_BIT_DATA |
47 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
48 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
49};
50
51struct platform_device s3c_device_hsmmc3 = {
52 .name = "s3c-sdhci",
53 .id = 3,
54 .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
55 .resource = s3c_hsmmc3_resource,
56 .dev = {
57 .dma_mask = &s3c_device_hsmmc3_dmamask,
58 .coherent_dma_mask = 0xffffffffUL,
59 .platform_data = &s3c_hsmmc3_def_platdata,
60 },
61};
62
63void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
64{
65 s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
66}
diff --git a/arch/arm/plat-samsung/dev-hwmon.c b/arch/arm/plat-samsung/dev-hwmon.c
deleted file mode 100644
index c91a79ce8f3..00000000000
--- a/arch/arm/plat-samsung/dev-hwmon.c
+++ /dev/null
@@ -1,32 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-hwmon.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * Adapted for HWMON by Maurus Cuelenaere
8 *
9 * Samsung series device definition for HWMON
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18
19#include <plat/devs.h>
20#include <plat/hwmon.h>
21
22struct platform_device s3c_device_hwmon = {
23 .name = "s3c-hwmon",
24 .id = -1,
25 .dev.parent = &s3c_device_adc.dev,
26};
27
28void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
29{
30 s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
31 &s3c_device_hwmon);
32}
diff --git a/arch/arm/plat-samsung/dev-i2c0.c b/arch/arm/plat-samsung/dev-i2c0.c
deleted file mode 100644
index f8251f5098b..00000000000
--- a/arch/arm/plat-samsung/dev-i2c0.c
+++ /dev/null
@@ -1,70 +0,0 @@
1/* linux/arch/arm/plat-s3c/dev-i2c0.c
2 *
3 * Copyright 2008-2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for i2c device 0
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/gfp.h>
15#include <linux/kernel.h>
16#include <linux/string.h>
17#include <linux/platform_device.h>
18
19#include <mach/irqs.h>
20#include <mach/map.h>
21
22#include <plat/regs-iic.h>
23#include <plat/iic.h>
24#include <plat/devs.h>
25#include <plat/cpu.h>
26
27static struct resource s3c_i2c_resource[] = {
28 [0] = {
29 .start = S3C_PA_IIC,
30 .end = S3C_PA_IIC + SZ_4K - 1,
31 .flags = IORESOURCE_MEM,
32 },
33 [1] = {
34 .start = IRQ_IIC,
35 .end = IRQ_IIC,
36 .flags = IORESOURCE_IRQ,
37 },
38};
39
40struct platform_device s3c_device_i2c0 = {
41 .name = "s3c2410-i2c",
42#ifdef CONFIG_S3C_DEV_I2C1
43 .id = 0,
44#else
45 .id = -1,
46#endif
47 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
48 .resource = s3c_i2c_resource,
49};
50
51struct s3c2410_platform_i2c default_i2c_data __initdata = {
52 .flags = 0,
53 .slave_addr = 0x10,
54 .frequency = 100*1000,
55 .sda_delay = 100,
56};
57
58void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
59{
60 struct s3c2410_platform_i2c *npd;
61
62 if (!pd)
63 pd = &default_i2c_data;
64
65 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
66 &s3c_device_i2c0);
67
68 if (!npd->cfg_gpio)
69 npd->cfg_gpio = s3c_i2c0_cfg_gpio;
70}
diff --git a/arch/arm/plat-samsung/dev-i2c1.c b/arch/arm/plat-samsung/dev-i2c1.c
deleted file mode 100644
index 3b7c7bec1cf..00000000000
--- a/arch/arm/plat-samsung/dev-i2c1.c
+++ /dev/null
@@ -1,61 +0,0 @@
1/* linux/arch/arm/plat-s3c/dev-i2c1.c
2 *
3 * Copyright 2008-2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for i2c device 1
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/gfp.h>
15#include <linux/kernel.h>
16#include <linux/string.h>
17#include <linux/platform_device.h>
18
19#include <mach/irqs.h>
20#include <mach/map.h>
21
22#include <plat/regs-iic.h>
23#include <plat/iic.h>
24#include <plat/devs.h>
25#include <plat/cpu.h>
26
27static struct resource s3c_i2c_resource[] = {
28 [0] = {
29 .start = S3C_PA_IIC1,
30 .end = S3C_PA_IIC1 + SZ_4K - 1,
31 .flags = IORESOURCE_MEM,
32 },
33 [1] = {
34 .start = IRQ_IIC1,
35 .end = IRQ_IIC1,
36 .flags = IORESOURCE_IRQ,
37 },
38};
39
40struct platform_device s3c_device_i2c1 = {
41 .name = "s3c2410-i2c",
42 .id = 1,
43 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
44 .resource = s3c_i2c_resource,
45};
46
47void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
48{
49 struct s3c2410_platform_i2c *npd;
50
51 if (!pd) {
52 pd = &default_i2c_data;
53 pd->bus_num = 1;
54 }
55
56 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
57 &s3c_device_i2c1);
58
59 if (!npd->cfg_gpio)
60 npd->cfg_gpio = s3c_i2c1_cfg_gpio;
61}
diff --git a/arch/arm/plat-samsung/dev-i2c2.c b/arch/arm/plat-samsung/dev-i2c2.c
deleted file mode 100644
index 07e9fd0b1b8..00000000000
--- a/arch/arm/plat-samsung/dev-i2c2.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/* linux/arch/arm/plat-s3c/dev-i2c2.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S3C series device definition for i2c device 2
7 *
8 * Based on plat-samsung/dev-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/gfp.h>
16#include <linux/kernel.h>
17#include <linux/string.h>
18#include <linux/platform_device.h>
19
20#include <mach/irqs.h>
21#include <mach/map.h>
22
23#include <plat/regs-iic.h>
24#include <plat/iic.h>
25#include <plat/devs.h>
26#include <plat/cpu.h>
27
28static struct resource s3c_i2c_resource[] = {
29 [0] = {
30 .start = S3C_PA_IIC2,
31 .end = S3C_PA_IIC2 + SZ_4K - 1,
32 .flags = IORESOURCE_MEM,
33 },
34 [1] = {
35 .start = IRQ_IIC2,
36 .end = IRQ_IIC2,
37 .flags = IORESOURCE_IRQ,
38 },
39};
40
41struct platform_device s3c_device_i2c2 = {
42 .name = "s3c2410-i2c",
43 .id = 2,
44 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
45 .resource = s3c_i2c_resource,
46};
47
48void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
49{
50 struct s3c2410_platform_i2c *npd;
51
52 if (!pd) {
53 pd = &default_i2c_data;
54 pd->bus_num = 2;
55 }
56
57 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
58 &s3c_device_i2c2);
59
60 if (!npd->cfg_gpio)
61 npd->cfg_gpio = s3c_i2c2_cfg_gpio;
62}
diff --git a/arch/arm/plat-samsung/dev-i2c3.c b/arch/arm/plat-samsung/dev-i2c3.c
deleted file mode 100644
index d48efa93c6e..00000000000
--- a/arch/arm/plat-samsung/dev-i2c3.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-i2c3.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P series device definition for i2c device 3
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/gfp.h>
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17
18#include <mach/irqs.h>
19#include <mach/map.h>
20
21#include <plat/regs-iic.h>
22#include <plat/iic.h>
23#include <plat/devs.h>
24#include <plat/cpu.h>
25
26static struct resource s3c_i2c_resource[] = {
27 [0] = {
28 .start = S3C_PA_IIC3,
29 .end = S3C_PA_IIC3 + SZ_4K - 1,
30 .flags = IORESOURCE_MEM,
31 },
32 [1] = {
33 .start = IRQ_IIC3,
34 .end = IRQ_IIC3,
35 .flags = IORESOURCE_IRQ,
36 },
37};
38
39struct platform_device s3c_device_i2c3 = {
40 .name = "s3c2440-i2c",
41 .id = 3,
42 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
43 .resource = s3c_i2c_resource,
44};
45
46void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
47{
48 struct s3c2410_platform_i2c *npd;
49
50 if (!pd) {
51 pd = &default_i2c_data;
52 pd->bus_num = 3;
53 }
54
55 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
56 &s3c_device_i2c3);
57
58 if (!npd->cfg_gpio)
59 npd->cfg_gpio = s3c_i2c3_cfg_gpio;
60}
diff --git a/arch/arm/plat-samsung/dev-i2c4.c b/arch/arm/plat-samsung/dev-i2c4.c
deleted file mode 100644
index 07e26444efe..00000000000
--- a/arch/arm/plat-samsung/dev-i2c4.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-i2c4.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P series device definition for i2c device 3
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/gfp.h>
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17
18#include <mach/irqs.h>
19#include <mach/map.h>
20
21#include <plat/regs-iic.h>
22#include <plat/iic.h>
23#include <plat/devs.h>
24#include <plat/cpu.h>
25
26static struct resource s3c_i2c_resource[] = {
27 [0] = {
28 .start = S3C_PA_IIC4,
29 .end = S3C_PA_IIC4 + SZ_4K - 1,
30 .flags = IORESOURCE_MEM,
31 },
32 [1] = {
33 .start = IRQ_IIC4,
34 .end = IRQ_IIC4,
35 .flags = IORESOURCE_IRQ,
36 },
37};
38
39struct platform_device s3c_device_i2c4 = {
40 .name = "s3c2440-i2c",
41 .id = 4,
42 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
43 .resource = s3c_i2c_resource,
44};
45
46void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
47{
48 struct s3c2410_platform_i2c *npd;
49
50 if (!pd) {
51 pd = &default_i2c_data;
52 pd->bus_num = 4;
53 }
54
55 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
56 &s3c_device_i2c4);
57
58 if (!npd->cfg_gpio)
59 npd->cfg_gpio = s3c_i2c4_cfg_gpio;
60}
diff --git a/arch/arm/plat-samsung/dev-i2c5.c b/arch/arm/plat-samsung/dev-i2c5.c
deleted file mode 100644
index f4965578456..00000000000
--- a/arch/arm/plat-samsung/dev-i2c5.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-i2c3.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P series device definition for i2c device 3
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/gfp.h>
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17
18#include <mach/irqs.h>
19#include <mach/map.h>
20
21#include <plat/regs-iic.h>
22#include <plat/iic.h>
23#include <plat/devs.h>
24#include <plat/cpu.h>
25
26static struct resource s3c_i2c_resource[] = {
27 [0] = {
28 .start = S3C_PA_IIC5,
29 .end = S3C_PA_IIC5 + SZ_4K - 1,
30 .flags = IORESOURCE_MEM,
31 },
32 [1] = {
33 .start = IRQ_IIC5,
34 .end = IRQ_IIC5,
35 .flags = IORESOURCE_IRQ,
36 },
37};
38
39struct platform_device s3c_device_i2c5 = {
40 .name = "s3c2440-i2c",
41 .id = 5,
42 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
43 .resource = s3c_i2c_resource,
44};
45
46void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
47{
48 struct s3c2410_platform_i2c *npd;
49
50 if (!pd) {
51 pd = &default_i2c_data;
52 pd->bus_num = 5;
53 }
54
55 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
56 &s3c_device_i2c5);
57
58 if (!npd->cfg_gpio)
59 npd->cfg_gpio = s3c_i2c5_cfg_gpio;
60}
diff --git a/arch/arm/plat-samsung/dev-i2c6.c b/arch/arm/plat-samsung/dev-i2c6.c
deleted file mode 100644
index 141d799944e..00000000000
--- a/arch/arm/plat-samsung/dev-i2c6.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-i2c6.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P series device definition for i2c device 6
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/gfp.h>
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17
18#include <mach/irqs.h>
19#include <mach/map.h>
20
21#include <plat/regs-iic.h>
22#include <plat/iic.h>
23#include <plat/devs.h>
24#include <plat/cpu.h>
25
26static struct resource s3c_i2c_resource[] = {
27 [0] = {
28 .start = S3C_PA_IIC6,
29 .end = S3C_PA_IIC6 + SZ_4K - 1,
30 .flags = IORESOURCE_MEM,
31 },
32 [1] = {
33 .start = IRQ_IIC6,
34 .end = IRQ_IIC6,
35 .flags = IORESOURCE_IRQ,
36 },
37};
38
39struct platform_device s3c_device_i2c6 = {
40 .name = "s3c2440-i2c",
41 .id = 6,
42 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
43 .resource = s3c_i2c_resource,
44};
45
46void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
47{
48 struct s3c2410_platform_i2c *npd;
49
50 if (!pd) {
51 pd = &default_i2c_data;
52 pd->bus_num = 6;
53 }
54
55 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
56 &s3c_device_i2c6);
57
58 if (!npd->cfg_gpio)
59 npd->cfg_gpio = s3c_i2c6_cfg_gpio;
60}
diff --git a/arch/arm/plat-samsung/dev-i2c7.c b/arch/arm/plat-samsung/dev-i2c7.c
deleted file mode 100644
index 9dddcd1665b..00000000000
--- a/arch/arm/plat-samsung/dev-i2c7.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-i2c7.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P series device definition for i2c device 7
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/gfp.h>
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17
18#include <mach/irqs.h>
19#include <mach/map.h>
20
21#include <plat/regs-iic.h>
22#include <plat/iic.h>
23#include <plat/devs.h>
24#include <plat/cpu.h>
25
26static struct resource s3c_i2c_resource[] = {
27 [0] = {
28 .start = S3C_PA_IIC7,
29 .end = S3C_PA_IIC7 + SZ_4K - 1,
30 .flags = IORESOURCE_MEM,
31 },
32 [1] = {
33 .start = IRQ_IIC7,
34 .end = IRQ_IIC7,
35 .flags = IORESOURCE_IRQ,
36 },
37};
38
39struct platform_device s3c_device_i2c7 = {
40 .name = "s3c2440-i2c",
41 .id = 7,
42 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
43 .resource = s3c_i2c_resource,
44};
45
46void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
47{
48 struct s3c2410_platform_i2c *npd;
49
50 if (!pd) {
51 pd = &default_i2c_data;
52 pd->bus_num = 7;
53 }
54
55 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
56 &s3c_device_i2c7);
57
58 if (!npd->cfg_gpio)
59 npd->cfg_gpio = s3c_i2c7_cfg_gpio;
60}
diff --git a/arch/arm/plat-samsung/dev-ide.c b/arch/arm/plat-samsung/dev-ide.c
deleted file mode 100644
index b497982795a..00000000000
--- a/arch/arm/plat-samsung/dev-ide.c
+++ /dev/null
@@ -1,44 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-ide.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung CF-ATA device definition.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16
17#include <mach/map.h>
18#include <plat/ata.h>
19#include <plat/devs.h>
20
21static struct resource s3c_cfcon_resource[] = {
22 [0] = {
23 .start = SAMSUNG_PA_CFCON,
24 .end = SAMSUNG_PA_CFCON + SZ_16K - 1,
25 .flags = IORESOURCE_MEM,
26 },
27 [1] = {
28 .start = IRQ_CFCON,
29 .end = IRQ_CFCON,
30 .flags = IORESOURCE_IRQ,
31 },
32};
33
34struct platform_device s3c_device_cfcon = {
35 .id = 0,
36 .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
37 .resource = s3c_cfcon_resource,
38};
39
40void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
41{
42 s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
43 &s3c_device_cfcon);
44}
diff --git a/arch/arm/plat-samsung/dev-keypad.c b/arch/arm/plat-samsung/dev-keypad.c
deleted file mode 100644
index 677c2d731b6..00000000000
--- a/arch/arm/plat-samsung/dev-keypad.c
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * linux/arch/arm/plat-samsung/dev-keypad.c
3 *
4 * Copyright (C) 2010 Samsung Electronics Co.Ltd
5 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/platform_device.h>
15#include <mach/irqs.h>
16#include <mach/map.h>
17#include <plat/cpu.h>
18#include <plat/devs.h>
19#include <plat/keypad.h>
20
21static struct resource samsung_keypad_resources[] = {
22 [0] = {
23 .start = SAMSUNG_PA_KEYPAD,
24 .end = SAMSUNG_PA_KEYPAD + 0x20 - 1,
25 .flags = IORESOURCE_MEM,
26 },
27 [1] = {
28 .start = IRQ_KEYPAD,
29 .end = IRQ_KEYPAD,
30 .flags = IORESOURCE_IRQ,
31 },
32};
33
34struct platform_device samsung_device_keypad = {
35 .name = "samsung-keypad",
36 .id = -1,
37 .num_resources = ARRAY_SIZE(samsung_keypad_resources),
38 .resource = samsung_keypad_resources,
39};
40
41void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
42{
43 struct samsung_keypad_platdata *npd;
44
45 npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
46 &samsung_device_keypad);
47
48 if (!npd->cfg_gpio)
49 npd->cfg_gpio = samsung_keypad_cfg_gpio;
50}
diff --git a/arch/arm/plat-samsung/dev-nand.c b/arch/arm/plat-samsung/dev-nand.c
deleted file mode 100644
index b8e30ec6ac2..00000000000
--- a/arch/arm/plat-samsung/dev-nand.c
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * S3C series device definition for nand device
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7*/
8
9#include <linux/gfp.h>
10#include <linux/kernel.h>
11#include <linux/platform_device.h>
12
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/partitions.h>
15
16#include <mach/map.h>
17#include <plat/devs.h>
18#include <plat/nand.h>
19
20static struct resource s3c_nand_resource[] = {
21 [0] = {
22 .start = S3C_PA_NAND,
23 .end = S3C_PA_NAND + SZ_1M,
24 .flags = IORESOURCE_MEM,
25 }
26};
27
28struct platform_device s3c_device_nand = {
29 .name = "s3c2410-nand",
30 .id = -1,
31 .num_resources = ARRAY_SIZE(s3c_nand_resource),
32 .resource = s3c_nand_resource,
33};
34
35EXPORT_SYMBOL(s3c_device_nand);
36
37/**
38 * s3c_nand_copy_set() - copy nand set data
39 * @set: The new structure, directly copied from the old.
40 *
41 * Copy all the fields from the NAND set field from what is probably __initdata
42 * to new kernel memory. The code returns 0 if the copy happened correctly or
43 * an error code for the calling function to display.
44 *
45 * Note, we currently do not try and look to see if we've already copied the
46 * data in a previous set.
47 */
48static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
49{
50 void *ptr;
51 int size;
52
53 size = sizeof(struct mtd_partition) * set->nr_partitions;
54 if (size) {
55 ptr = kmemdup(set->partitions, size, GFP_KERNEL);
56 set->partitions = ptr;
57
58 if (!ptr)
59 return -ENOMEM;
60 }
61
62 if (set->nr_map && set->nr_chips) {
63 size = sizeof(int) * set->nr_chips;
64 ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
65 set->nr_map = ptr;
66
67 if (!ptr)
68 return -ENOMEM;
69 }
70
71 if (set->ecc_layout) {
72 ptr = kmemdup(set->ecc_layout,
73 sizeof(struct nand_ecclayout), GFP_KERNEL);
74 set->ecc_layout = ptr;
75
76 if (!ptr)
77 return -ENOMEM;
78 }
79
80 return 0;
81}
82
83void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
84{
85 struct s3c2410_platform_nand *npd;
86 int size;
87 int ret;
88
89 /* note, if we get a failure in allocation, we simply drop out of the
90 * function. If there is so little memory available at initialisation
91 * time then there is little chance the system is going to run.
92 */
93
94 npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
95 &s3c_device_nand);
96 if (!npd)
97 return;
98
99 /* now see if we need to copy any of the nand set data */
100
101 size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
102 if (size) {
103 struct s3c2410_nand_set *from = npd->sets;
104 struct s3c2410_nand_set *to;
105 int i;
106
107 to = kmemdup(from, size, GFP_KERNEL);
108 npd->sets = to; /* set, even if we failed */
109
110 if (!to) {
111 printk(KERN_ERR "%s: no memory for sets\n", __func__);
112 return;
113 }
114
115 for (i = 0; i < npd->nr_sets; i++) {
116 ret = s3c_nand_copy_set(to);
117 if (ret) {
118 printk(KERN_ERR "%s: failed to copy set %d\n",
119 __func__, i);
120 return;
121 }
122 to++;
123 }
124 }
125}
diff --git a/arch/arm/plat-samsung/dev-onenand.c b/arch/arm/plat-samsung/dev-onenand.c
deleted file mode 100644
index f54ae71f0cd..00000000000
--- a/arch/arm/plat-samsung/dev-onenand.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * linux/arch/arm/plat-samsung/dev-onenand.c
3 *
4 * Copyright (c) 2008-2010 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * S3C64XX/S5PC100 series device definition for OneNAND devices
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16
17#include <mach/irqs.h>
18#include <mach/map.h>
19
20static struct resource s3c_onenand_resources[] = {
21 [0] = {
22 .start = S3C_PA_ONENAND,
23 .end = S3C_PA_ONENAND + 0x400 - 1,
24 .flags = IORESOURCE_MEM,
25 },
26 [1] = {
27 .start = S3C_PA_ONENAND_BUF,
28 .end = S3C_PA_ONENAND_BUF + S3C_SZ_ONENAND_BUF - 1,
29 .flags = IORESOURCE_MEM,
30 },
31 [2] = {
32 .start = IRQ_ONENAND,
33 .end = IRQ_ONENAND,
34 .flags = IORESOURCE_IRQ,
35 },
36};
37
38struct platform_device s3c_device_onenand = {
39 .name = "samsung-onenand",
40 .id = 0,
41 .num_resources = ARRAY_SIZE(s3c_onenand_resources),
42 .resource = s3c_onenand_resources,
43};
diff --git a/arch/arm/plat-samsung/dev-pwm.c b/arch/arm/plat-samsung/dev-pwm.c
deleted file mode 100644
index dab47b0e190..00000000000
--- a/arch/arm/plat-samsung/dev-pwm.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-pwm.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (c) 2007 Ben Dooks
7 * Copyright (c) 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
9 *
10 * S3C series device definition for the PWM timer
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/platform_device.h>
19
20#include <mach/irqs.h>
21
22#include <plat/devs.h>
23
24#define TIMER_RESOURCE_SIZE (1)
25
26#define TIMER_RESOURCE(_tmr, _irq) \
27 (struct resource [TIMER_RESOURCE_SIZE]) { \
28 [0] = { \
29 .start = _irq, \
30 .end = _irq, \
31 .flags = IORESOURCE_IRQ \
32 } \
33 }
34
35#define DEFINE_S3C_TIMER(_tmr_no, _irq) \
36 .name = "s3c24xx-pwm", \
37 .id = _tmr_no, \
38 .num_resources = TIMER_RESOURCE_SIZE, \
39 .resource = TIMER_RESOURCE(_tmr_no, _irq), \
40
41/*
42 * since we already have an static mapping for the timer,
43 * we do not bother setting any IO resource for the base.
44 */
45
46struct platform_device s3c_device_timer[] = {
47 [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
48 [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
49 [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
50 [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
51 [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
52};
53EXPORT_SYMBOL(s3c_device_timer);
diff --git a/arch/arm/plat-samsung/dev-rtc.c b/arch/arm/plat-samsung/dev-rtc.c
deleted file mode 100644
index bf4e2267333..00000000000
--- a/arch/arm/plat-samsung/dev-rtc.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-rtc.c
2 *
3 * Copyright 2009 by Maurus Cuelenaere <mcuelenaere@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/kernel.h>
11#include <linux/string.h>
12#include <linux/platform_device.h>
13
14#include <mach/irqs.h>
15#include <mach/map.h>
16
17#include <plat/devs.h>
18
19static struct resource s3c_rtc_resource[] = {
20 [0] = {
21 .start = S3C_PA_RTC,
22 .end = S3C_PA_RTC + 0xff,
23 .flags = IORESOURCE_MEM,
24 },
25 [1] = {
26 .start = IRQ_RTC_ALARM,
27 .end = IRQ_RTC_ALARM,
28 .flags = IORESOURCE_IRQ,
29 },
30 [2] = {
31 .start = IRQ_RTC_TIC,
32 .end = IRQ_RTC_TIC,
33 .flags = IORESOURCE_IRQ
34 }
35};
36
37struct platform_device s3c_device_rtc = {
38 .name = "s3c64xx-rtc",
39 .id = -1,
40 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
41 .resource = s3c_rtc_resource,
42};
43EXPORT_SYMBOL(s3c_device_rtc);
diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c
deleted file mode 100644
index 5f3d46a9bd8..00000000000
--- a/arch/arm/plat-samsung/dev-ts.c
+++ /dev/null
@@ -1,59 +0,0 @@
1/* linux/arch/arm/mach-s3c64xx/dev-ts.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
6 *
7 * Adapted by Maurus Cuelenaere for s3c64xx
8 *
9 * S3C64XX series device definition for touchscreen device
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/kernel.h>
17#include <linux/string.h>
18#include <linux/platform_device.h>
19
20#include <mach/irqs.h>
21#include <mach/map.h>
22
23#include <plat/devs.h>
24#include <plat/ts.h>
25
26static struct resource s3c_ts_resource[] = {
27 [0] = {
28 .start = SAMSUNG_PA_ADC,
29 .end = SAMSUNG_PA_ADC + SZ_256 - 1,
30 .flags = IORESOURCE_MEM,
31 },
32 [1] = {
33 .start = IRQ_TC,
34 .end = IRQ_TC,
35 .flags = IORESOURCE_IRQ,
36 },
37};
38
39struct platform_device s3c_device_ts = {
40 .name = "s3c64xx-ts",
41 .id = -1,
42 .num_resources = ARRAY_SIZE(s3c_ts_resource),
43 .resource = s3c_ts_resource,
44};
45
46static struct s3c2410_ts_mach_info default_ts_data __initdata = {
47 .delay = 10000,
48 .presc = 49,
49 .oversampling_shift = 2,
50};
51
52void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
53{
54 if (!pd)
55 pd = &default_ts_data;
56
57 s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
58 &s3c_device_ts);
59}
diff --git a/arch/arm/plat-samsung/dev-usb-hsotg.c b/arch/arm/plat-samsung/dev-usb-hsotg.c
deleted file mode 100644
index 33a844ab691..00000000000
--- a/arch/arm/plat-samsung/dev-usb-hsotg.c
+++ /dev/null
@@ -1,48 +0,0 @@
1/* linux/arch/arm/plat-s3c/dev-usb-hsotg.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for USB high-speed UDC/OtG block
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17#include <linux/dma-mapping.h>
18
19#include <mach/irqs.h>
20#include <mach/map.h>
21
22#include <plat/devs.h>
23
24static struct resource s3c_usb_hsotg_resources[] = {
25 [0] = {
26 .start = S3C_PA_USB_HSOTG,
27 .end = S3C_PA_USB_HSOTG + 0x10000 - 1,
28 .flags = IORESOURCE_MEM,
29 },
30 [1] = {
31 .start = IRQ_OTG,
32 .end = IRQ_OTG,
33 .flags = IORESOURCE_IRQ,
34 },
35};
36
37static u64 s3c_hsotg_dmamask = DMA_BIT_MASK(32);
38
39struct platform_device s3c_device_usb_hsotg = {
40 .name = "s3c-hsotg",
41 .id = -1,
42 .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
43 .resource = s3c_usb_hsotg_resources,
44 .dev = {
45 .dma_mask = &s3c_hsotg_dmamask,
46 .coherent_dma_mask = DMA_BIT_MASK(32),
47 },
48};
diff --git a/arch/arm/plat-samsung/dev-usb.c b/arch/arm/plat-samsung/dev-usb.c
deleted file mode 100644
index 33fbaa96770..00000000000
--- a/arch/arm/plat-samsung/dev-usb.c
+++ /dev/null
@@ -1,65 +0,0 @@
1/* linux/arch/arm/plat-s3c/dev-usb.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for USB host
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/gfp.h>
15#include <linux/kernel.h>
16#include <linux/string.h>
17#include <linux/platform_device.h>
18
19#include <mach/irqs.h>
20#include <mach/map.h>
21
22#include <plat/devs.h>
23#include <plat/usb-control.h>
24
25static struct resource s3c_usb_resource[] = {
26 [0] = {
27 .start = S3C_PA_USBHOST,
28 .end = S3C_PA_USBHOST + 0x100 - 1,
29 .flags = IORESOURCE_MEM,
30 },
31 [1] = {
32 .start = IRQ_USBH,
33 .end = IRQ_USBH,
34 .flags = IORESOURCE_IRQ,
35 }
36};
37
38static u64 s3c_device_usb_dmamask = 0xffffffffUL;
39
40struct platform_device s3c_device_ohci = {
41 .name = "s3c2410-ohci",
42 .id = -1,
43 .num_resources = ARRAY_SIZE(s3c_usb_resource),
44 .resource = s3c_usb_resource,
45 .dev = {
46 .dma_mask = &s3c_device_usb_dmamask,
47 .coherent_dma_mask = 0xffffffffUL
48 }
49};
50
51EXPORT_SYMBOL(s3c_device_ohci);
52
53/**
54 * s3c_ohci_set_platdata - initialise OHCI device platform data
55 * @info: The platform data.
56 *
57 * This call copies the @info passed in and sets the device .platform_data
58 * field to that copy. The @info is copied so that the original can be marked
59 * __initdata.
60 */
61void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
62{
63 s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
64 &s3c_device_ohci);
65}
diff --git a/arch/arm/plat-samsung/dev-wdt.c b/arch/arm/plat-samsung/dev-wdt.c
deleted file mode 100644
index 019b5b8cf14..00000000000
--- a/arch/arm/plat-samsung/dev-wdt.c
+++ /dev/null
@@ -1,40 +0,0 @@
1/* linux/arch/arm/plat-samsung/dev-wdt.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C series device definition for the watchdog timer
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15
16#include <mach/irqs.h>
17#include <mach/map.h>
18
19#include <plat/devs.h>
20
21static struct resource s3c_wdt_resource[] = {
22 [0] = {
23 .start = S3C_PA_WDT,
24 .end = S3C_PA_WDT + SZ_1K,
25 .flags = IORESOURCE_MEM,
26 },
27 [1] = {
28 .start = IRQ_WDT,
29 .end = IRQ_WDT,
30 .flags = IORESOURCE_IRQ,
31 }
32};
33
34struct platform_device s3c_device_wdt = {
35 .name = "s3c2410-wdt",
36 .id = -1,
37 .num_resources = ARRAY_SIZE(s3c_wdt_resource),
38 .resource = s3c_wdt_resource,
39};
40EXPORT_SYMBOL(s3c_device_wdt);
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
new file mode 100644
index 00000000000..4ca8b571f97
--- /dev/null
+++ b/arch/arm/plat-samsung/devs.c
@@ -0,0 +1,1463 @@
1/* linux/arch/arm/plat-samsung/devs.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Base SAMSUNG platform device definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/string.h>
24#include <linux/dma-mapping.h>
25#include <linux/fb.h>
26#include <linux/gfp.h>
27#include <linux/mtd/mtd.h>
28#include <linux/mtd/onenand.h>
29#include <linux/mtd/partitions.h>
30#include <linux/mmc/host.h>
31#include <linux/ioport.h>
32
33#include <asm/irq.h>
34#include <asm/pmu.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/irq.h>
38
39#include <mach/hardware.h>
40#include <mach/dma.h>
41#include <mach/irqs.h>
42#include <mach/map.h>
43
44#include <plat/cpu.h>
45#include <plat/devs.h>
46#include <plat/adc.h>
47#include <plat/ata.h>
48#include <plat/ehci.h>
49#include <plat/fb.h>
50#include <plat/fb-s3c2410.h>
51#include <plat/hwmon.h>
52#include <plat/iic.h>
53#include <plat/keypad.h>
54#include <plat/mci.h>
55#include <plat/nand.h>
56#include <plat/sdhci.h>
57#include <plat/ts.h>
58#include <plat/udc.h>
59#include <plat/usb-control.h>
60#include <plat/usb-phy.h>
61#include <plat/regs-iic.h>
62#include <plat/regs-serial.h>
63#include <plat/regs-spi.h>
64
65static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
66
67/* AC97 */
68#ifdef CONFIG_CPU_S3C2440
69static struct resource s3c_ac97_resource[] = {
70 [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
71 [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
72 [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
73 [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
74 [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
75};
76
77struct platform_device s3c_device_ac97 = {
78 .name = "samsung-ac97",
79 .id = -1,
80 .num_resources = ARRAY_SIZE(s3c_ac97_resource),
81 .resource = s3c_ac97_resource,
82 .dev = {
83 .dma_mask = &samsung_device_dma_mask,
84 .coherent_dma_mask = DMA_BIT_MASK(32),
85 }
86};
87#endif /* CONFIG_CPU_S3C2440 */
88
89/* ADC */
90
91#ifdef CONFIG_PLAT_S3C24XX
92static struct resource s3c_adc_resource[] = {
93 [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
94 [1] = DEFINE_RES_IRQ(IRQ_TC),
95 [2] = DEFINE_RES_IRQ(IRQ_ADC),
96};
97
98struct platform_device s3c_device_adc = {
99 .name = "s3c24xx-adc",
100 .id = -1,
101 .num_resources = ARRAY_SIZE(s3c_adc_resource),
102 .resource = s3c_adc_resource,
103};
104#endif /* CONFIG_PLAT_S3C24XX */
105
106#if defined(CONFIG_SAMSUNG_DEV_ADC)
107static struct resource s3c_adc_resource[] = {
108 [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
109 [1] = DEFINE_RES_IRQ(IRQ_TC),
110 [2] = DEFINE_RES_IRQ(IRQ_ADC),
111};
112
113struct platform_device s3c_device_adc = {
114 .name = "samsung-adc",
115 .id = -1,
116 .num_resources = ARRAY_SIZE(s3c_adc_resource),
117 .resource = s3c_adc_resource,
118};
119#endif /* CONFIG_SAMSUNG_DEV_ADC */
120
121/* Camif Controller */
122
123#ifdef CONFIG_CPU_S3C2440
124static struct resource s3c_camif_resource[] = {
125 [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
126 [1] = DEFINE_RES_IRQ(IRQ_CAM),
127};
128
129struct platform_device s3c_device_camif = {
130 .name = "s3c2440-camif",
131 .id = -1,
132 .num_resources = ARRAY_SIZE(s3c_camif_resource),
133 .resource = s3c_camif_resource,
134 .dev = {
135 .dma_mask = &samsung_device_dma_mask,
136 .coherent_dma_mask = DMA_BIT_MASK(32),
137 }
138};
139#endif /* CONFIG_CPU_S3C2440 */
140
141/* ASOC DMA */
142
143struct platform_device samsung_asoc_dma = {
144 .name = "samsung-audio",
145 .id = -1,
146 .dev = {
147 .dma_mask = &samsung_device_dma_mask,
148 .coherent_dma_mask = DMA_BIT_MASK(32),
149 }
150};
151
152struct platform_device samsung_asoc_idma = {
153 .name = "samsung-idma",
154 .id = -1,
155 .dev = {
156 .dma_mask = &samsung_device_dma_mask,
157 .coherent_dma_mask = DMA_BIT_MASK(32),
158 }
159};
160
161/* FB */
162
163#ifdef CONFIG_S3C_DEV_FB
164static struct resource s3c_fb_resource[] = {
165 [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
166 [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
167 [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
168 [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
169};
170
171struct platform_device s3c_device_fb = {
172 .name = "s3c-fb",
173 .id = -1,
174 .num_resources = ARRAY_SIZE(s3c_fb_resource),
175 .resource = s3c_fb_resource,
176 .dev = {
177 .dma_mask = &samsung_device_dma_mask,
178 .coherent_dma_mask = DMA_BIT_MASK(32),
179 },
180};
181
182void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
183{
184 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
185 &s3c_device_fb);
186}
187#endif /* CONFIG_S3C_DEV_FB */
188
189/* FIMC */
190
191#ifdef CONFIG_S5P_DEV_FIMC0
192static struct resource s5p_fimc0_resource[] = {
193 [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
194 [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
195};
196
197struct platform_device s5p_device_fimc0 = {
198 .name = "s5p-fimc",
199 .id = 0,
200 .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
201 .resource = s5p_fimc0_resource,
202 .dev = {
203 .dma_mask = &samsung_device_dma_mask,
204 .coherent_dma_mask = DMA_BIT_MASK(32),
205 },
206};
207
208struct platform_device s5p_device_fimc_md = {
209 .name = "s5p-fimc-md",
210 .id = -1,
211};
212#endif /* CONFIG_S5P_DEV_FIMC0 */
213
214#ifdef CONFIG_S5P_DEV_FIMC1
215static struct resource s5p_fimc1_resource[] = {
216 [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
217 [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
218};
219
220struct platform_device s5p_device_fimc1 = {
221 .name = "s5p-fimc",
222 .id = 1,
223 .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
224 .resource = s5p_fimc1_resource,
225 .dev = {
226 .dma_mask = &samsung_device_dma_mask,
227 .coherent_dma_mask = DMA_BIT_MASK(32),
228 },
229};
230#endif /* CONFIG_S5P_DEV_FIMC1 */
231
232#ifdef CONFIG_S5P_DEV_FIMC2
233static struct resource s5p_fimc2_resource[] = {
234 [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
235 [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
236};
237
238struct platform_device s5p_device_fimc2 = {
239 .name = "s5p-fimc",
240 .id = 2,
241 .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
242 .resource = s5p_fimc2_resource,
243 .dev = {
244 .dma_mask = &samsung_device_dma_mask,
245 .coherent_dma_mask = DMA_BIT_MASK(32),
246 },
247};
248#endif /* CONFIG_S5P_DEV_FIMC2 */
249
250#ifdef CONFIG_S5P_DEV_FIMC3
251static struct resource s5p_fimc3_resource[] = {
252 [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
253 [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
254};
255
256struct platform_device s5p_device_fimc3 = {
257 .name = "s5p-fimc",
258 .id = 3,
259 .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
260 .resource = s5p_fimc3_resource,
261 .dev = {
262 .dma_mask = &samsung_device_dma_mask,
263 .coherent_dma_mask = DMA_BIT_MASK(32),
264 },
265};
266#endif /* CONFIG_S5P_DEV_FIMC3 */
267
268/* FIMD0 */
269
270#ifdef CONFIG_S5P_DEV_FIMD0
271static struct resource s5p_fimd0_resource[] = {
272 [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
273 [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
274 [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
275 [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
276};
277
278struct platform_device s5p_device_fimd0 = {
279 .name = "s5p-fb",
280 .id = 0,
281 .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
282 .resource = s5p_fimd0_resource,
283 .dev = {
284 .dma_mask = &samsung_device_dma_mask,
285 .coherent_dma_mask = DMA_BIT_MASK(32),
286 },
287};
288
289void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
290{
291 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
292 &s5p_device_fimd0);
293}
294#endif /* CONFIG_S5P_DEV_FIMD0 */
295
296/* HWMON */
297
298#ifdef CONFIG_S3C_DEV_HWMON
299struct platform_device s3c_device_hwmon = {
300 .name = "s3c-hwmon",
301 .id = -1,
302 .dev.parent = &s3c_device_adc.dev,
303};
304
305void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
306{
307 s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
308 &s3c_device_hwmon);
309}
310#endif /* CONFIG_S3C_DEV_HWMON */
311
312/* HSMMC */
313
314#ifdef CONFIG_S3C_DEV_HSMMC
315static struct resource s3c_hsmmc_resource[] = {
316 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
317 [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
318};
319
320struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
321 .max_width = 4,
322 .host_caps = (MMC_CAP_4_BIT_DATA |
323 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
324 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
325};
326
327struct platform_device s3c_device_hsmmc0 = {
328 .name = "s3c-sdhci",
329 .id = 0,
330 .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
331 .resource = s3c_hsmmc_resource,
332 .dev = {
333 .dma_mask = &samsung_device_dma_mask,
334 .coherent_dma_mask = DMA_BIT_MASK(32),
335 .platform_data = &s3c_hsmmc0_def_platdata,
336 },
337};
338
339void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
340{
341 s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
342}
343#endif /* CONFIG_S3C_DEV_HSMMC */
344
345#ifdef CONFIG_S3C_DEV_HSMMC1
346static struct resource s3c_hsmmc1_resource[] = {
347 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
348 [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
349};
350
351struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
352 .max_width = 4,
353 .host_caps = (MMC_CAP_4_BIT_DATA |
354 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
355 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
356};
357
358struct platform_device s3c_device_hsmmc1 = {
359 .name = "s3c-sdhci",
360 .id = 1,
361 .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
362 .resource = s3c_hsmmc1_resource,
363 .dev = {
364 .dma_mask = &samsung_device_dma_mask,
365 .coherent_dma_mask = DMA_BIT_MASK(32),
366 .platform_data = &s3c_hsmmc1_def_platdata,
367 },
368};
369
370void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
371{
372 s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
373}
374#endif /* CONFIG_S3C_DEV_HSMMC1 */
375
376/* HSMMC2 */
377
378#ifdef CONFIG_S3C_DEV_HSMMC2
379static struct resource s3c_hsmmc2_resource[] = {
380 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
381 [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
382};
383
384struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
385 .max_width = 4,
386 .host_caps = (MMC_CAP_4_BIT_DATA |
387 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
388 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
389};
390
391struct platform_device s3c_device_hsmmc2 = {
392 .name = "s3c-sdhci",
393 .id = 2,
394 .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
395 .resource = s3c_hsmmc2_resource,
396 .dev = {
397 .dma_mask = &samsung_device_dma_mask,
398 .coherent_dma_mask = DMA_BIT_MASK(32),
399 .platform_data = &s3c_hsmmc2_def_platdata,
400 },
401};
402
403void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
404{
405 s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
406}
407#endif /* CONFIG_S3C_DEV_HSMMC2 */
408
409#ifdef CONFIG_S3C_DEV_HSMMC3
410static struct resource s3c_hsmmc3_resource[] = {
411 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
412 [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
413};
414
415struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
416 .max_width = 4,
417 .host_caps = (MMC_CAP_4_BIT_DATA |
418 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
419 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
420};
421
422struct platform_device s3c_device_hsmmc3 = {
423 .name = "s3c-sdhci",
424 .id = 3,
425 .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
426 .resource = s3c_hsmmc3_resource,
427 .dev = {
428 .dma_mask = &samsung_device_dma_mask,
429 .coherent_dma_mask = DMA_BIT_MASK(32),
430 .platform_data = &s3c_hsmmc3_def_platdata,
431 },
432};
433
434void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
435{
436 s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
437}
438#endif /* CONFIG_S3C_DEV_HSMMC3 */
439
440/* I2C */
441
442static struct resource s3c_i2c0_resource[] = {
443 [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
444 [1] = DEFINE_RES_IRQ(IRQ_IIC),
445};
446
447struct platform_device s3c_device_i2c0 = {
448 .name = "s3c2410-i2c",
449#ifdef CONFIG_S3C_DEV_I2C1
450 .id = 0,
451#else
452 .id = -1,
453#endif
454 .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
455 .resource = s3c_i2c0_resource,
456};
457
458struct s3c2410_platform_i2c default_i2c_data __initdata = {
459 .flags = 0,
460 .slave_addr = 0x10,
461 .frequency = 100*1000,
462 .sda_delay = 100,
463};
464
465void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
466{
467 struct s3c2410_platform_i2c *npd;
468
469 if (!pd)
470 pd = &default_i2c_data;
471
472 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
473 &s3c_device_i2c0);
474
475 if (!npd->cfg_gpio)
476 npd->cfg_gpio = s3c_i2c0_cfg_gpio;
477}
478
479#ifdef CONFIG_S3C_DEV_I2C1
480static struct resource s3c_i2c1_resource[] = {
481 [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
482 [1] = DEFINE_RES_IRQ(IRQ_IIC1),
483};
484
485struct platform_device s3c_device_i2c1 = {
486 .name = "s3c2410-i2c",
487 .id = 1,
488 .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
489 .resource = s3c_i2c1_resource,
490};
491
492void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
493{
494 struct s3c2410_platform_i2c *npd;
495
496 if (!pd) {
497 pd = &default_i2c_data;
498 pd->bus_num = 1;
499 }
500
501 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
502 &s3c_device_i2c1);
503
504 if (!npd->cfg_gpio)
505 npd->cfg_gpio = s3c_i2c1_cfg_gpio;
506}
507#endif /* CONFIG_S3C_DEV_I2C1 */
508
509#ifdef CONFIG_S3C_DEV_I2C2
510static struct resource s3c_i2c2_resource[] = {
511 [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
512 [1] = DEFINE_RES_IRQ(IRQ_IIC2),
513};
514
515struct platform_device s3c_device_i2c2 = {
516 .name = "s3c2410-i2c",
517 .id = 2,
518 .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
519 .resource = s3c_i2c2_resource,
520};
521
522void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
523{
524 struct s3c2410_platform_i2c *npd;
525
526 if (!pd) {
527 pd = &default_i2c_data;
528 pd->bus_num = 2;
529 }
530
531 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
532 &s3c_device_i2c2);
533
534 if (!npd->cfg_gpio)
535 npd->cfg_gpio = s3c_i2c2_cfg_gpio;
536}
537#endif /* CONFIG_S3C_DEV_I2C2 */
538
539#ifdef CONFIG_S3C_DEV_I2C3
540static struct resource s3c_i2c3_resource[] = {
541 [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
542 [1] = DEFINE_RES_IRQ(IRQ_IIC3),
543};
544
545struct platform_device s3c_device_i2c3 = {
546 .name = "s3c2440-i2c",
547 .id = 3,
548 .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
549 .resource = s3c_i2c3_resource,
550};
551
552void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
553{
554 struct s3c2410_platform_i2c *npd;
555
556 if (!pd) {
557 pd = &default_i2c_data;
558 pd->bus_num = 3;
559 }
560
561 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
562 &s3c_device_i2c3);
563
564 if (!npd->cfg_gpio)
565 npd->cfg_gpio = s3c_i2c3_cfg_gpio;
566}
567#endif /*CONFIG_S3C_DEV_I2C3 */
568
569#ifdef CONFIG_S3C_DEV_I2C4
570static struct resource s3c_i2c4_resource[] = {
571 [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
572 [1] = DEFINE_RES_IRQ(IRQ_IIC4),
573};
574
575struct platform_device s3c_device_i2c4 = {
576 .name = "s3c2440-i2c",
577 .id = 4,
578 .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
579 .resource = s3c_i2c4_resource,
580};
581
582void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
583{
584 struct s3c2410_platform_i2c *npd;
585
586 if (!pd) {
587 pd = &default_i2c_data;
588 pd->bus_num = 4;
589 }
590
591 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
592 &s3c_device_i2c4);
593
594 if (!npd->cfg_gpio)
595 npd->cfg_gpio = s3c_i2c4_cfg_gpio;
596}
597#endif /*CONFIG_S3C_DEV_I2C4 */
598
599#ifdef CONFIG_S3C_DEV_I2C5
600static struct resource s3c_i2c5_resource[] = {
601 [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
602 [1] = DEFINE_RES_IRQ(IRQ_IIC5),
603};
604
605struct platform_device s3c_device_i2c5 = {
606 .name = "s3c2440-i2c",
607 .id = 5,
608 .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
609 .resource = s3c_i2c5_resource,
610};
611
612void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
613{
614 struct s3c2410_platform_i2c *npd;
615
616 if (!pd) {
617 pd = &default_i2c_data;
618 pd->bus_num = 5;
619 }
620
621 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
622 &s3c_device_i2c5);
623
624 if (!npd->cfg_gpio)
625 npd->cfg_gpio = s3c_i2c5_cfg_gpio;
626}
627#endif /*CONFIG_S3C_DEV_I2C5 */
628
629#ifdef CONFIG_S3C_DEV_I2C6
630static struct resource s3c_i2c6_resource[] = {
631 [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
632 [1] = DEFINE_RES_IRQ(IRQ_IIC6),
633};
634
635struct platform_device s3c_device_i2c6 = {
636 .name = "s3c2440-i2c",
637 .id = 6,
638 .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
639 .resource = s3c_i2c6_resource,
640};
641
642void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
643{
644 struct s3c2410_platform_i2c *npd;
645
646 if (!pd) {
647 pd = &default_i2c_data;
648 pd->bus_num = 6;
649 }
650
651 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
652 &s3c_device_i2c6);
653
654 if (!npd->cfg_gpio)
655 npd->cfg_gpio = s3c_i2c6_cfg_gpio;
656}
657#endif /* CONFIG_S3C_DEV_I2C6 */
658
659#ifdef CONFIG_S3C_DEV_I2C7
660static struct resource s3c_i2c7_resource[] = {
661 [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
662 [1] = DEFINE_RES_IRQ(IRQ_IIC7),
663};
664
665struct platform_device s3c_device_i2c7 = {
666 .name = "s3c2440-i2c",
667 .id = 7,
668 .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
669 .resource = s3c_i2c7_resource,
670};
671
672void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
673{
674 struct s3c2410_platform_i2c *npd;
675
676 if (!pd) {
677 pd = &default_i2c_data;
678 pd->bus_num = 7;
679 }
680
681 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
682 &s3c_device_i2c7);
683
684 if (!npd->cfg_gpio)
685 npd->cfg_gpio = s3c_i2c7_cfg_gpio;
686}
687#endif /* CONFIG_S3C_DEV_I2C7 */
688
689/* I2C HDMIPHY */
690
691#ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
692static struct resource s5p_i2c_resource[] = {
693 [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
694 [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
695};
696
697struct platform_device s5p_device_i2c_hdmiphy = {
698 .name = "s3c2440-hdmiphy-i2c",
699 .id = -1,
700 .num_resources = ARRAY_SIZE(s5p_i2c_resource),
701 .resource = s5p_i2c_resource,
702};
703
704void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
705{
706 struct s3c2410_platform_i2c *npd;
707
708 if (!pd) {
709 pd = &default_i2c_data;
710
711 if (soc_is_exynos4210())
712 pd->bus_num = 8;
713 else if (soc_is_s5pv210())
714 pd->bus_num = 3;
715 else
716 pd->bus_num = 0;
717 }
718
719 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
720 &s5p_device_i2c_hdmiphy);
721}
722#endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
723
724/* I2S */
725
726#ifdef CONFIG_PLAT_S3C24XX
727static struct resource s3c_iis_resource[] = {
728 [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
729};
730
731struct platform_device s3c_device_iis = {
732 .name = "s3c24xx-iis",
733 .id = -1,
734 .num_resources = ARRAY_SIZE(s3c_iis_resource),
735 .resource = s3c_iis_resource,
736 .dev = {
737 .dma_mask = &samsung_device_dma_mask,
738 .coherent_dma_mask = DMA_BIT_MASK(32),
739 }
740};
741#endif /* CONFIG_PLAT_S3C24XX */
742
743#ifdef CONFIG_CPU_S3C2440
744struct platform_device s3c2412_device_iis = {
745 .name = "s3c2412-iis",
746 .id = -1,
747 .dev = {
748 .dma_mask = &samsung_device_dma_mask,
749 .coherent_dma_mask = DMA_BIT_MASK(32),
750 }
751};
752#endif /* CONFIG_CPU_S3C2440 */
753
754/* IDE CFCON */
755
756#ifdef CONFIG_SAMSUNG_DEV_IDE
757static struct resource s3c_cfcon_resource[] = {
758 [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
759 [1] = DEFINE_RES_IRQ(IRQ_CFCON),
760};
761
762struct platform_device s3c_device_cfcon = {
763 .id = 0,
764 .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
765 .resource = s3c_cfcon_resource,
766};
767
768void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
769{
770 s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
771 &s3c_device_cfcon);
772}
773#endif /* CONFIG_SAMSUNG_DEV_IDE */
774
775/* KEYPAD */
776
777#ifdef CONFIG_SAMSUNG_DEV_KEYPAD
778static struct resource samsung_keypad_resources[] = {
779 [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
780 [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
781};
782
783struct platform_device samsung_device_keypad = {
784 .name = "samsung-keypad",
785 .id = -1,
786 .num_resources = ARRAY_SIZE(samsung_keypad_resources),
787 .resource = samsung_keypad_resources,
788};
789
790void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
791{
792 struct samsung_keypad_platdata *npd;
793
794 npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
795 &samsung_device_keypad);
796
797 if (!npd->cfg_gpio)
798 npd->cfg_gpio = samsung_keypad_cfg_gpio;
799}
800#endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
801
802/* LCD Controller */
803
804#ifdef CONFIG_PLAT_S3C24XX
805static struct resource s3c_lcd_resource[] = {
806 [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
807 [1] = DEFINE_RES_IRQ(IRQ_LCD),
808};
809
810struct platform_device s3c_device_lcd = {
811 .name = "s3c2410-lcd",
812 .id = -1,
813 .num_resources = ARRAY_SIZE(s3c_lcd_resource),
814 .resource = s3c_lcd_resource,
815 .dev = {
816 .dma_mask = &samsung_device_dma_mask,
817 .coherent_dma_mask = DMA_BIT_MASK(32),
818 }
819};
820
821void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
822{
823 struct s3c2410fb_mach_info *npd;
824
825 npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
826 if (npd) {
827 npd->displays = kmemdup(pd->displays,
828 sizeof(struct s3c2410fb_display) * npd->num_displays,
829 GFP_KERNEL);
830 if (!npd->displays)
831 printk(KERN_ERR "no memory for LCD display data\n");
832 } else {
833 printk(KERN_ERR "no memory for LCD platform data\n");
834 }
835}
836#endif /* CONFIG_PLAT_S3C24XX */
837
838/* MFC */
839
840#ifdef CONFIG_S5P_DEV_MFC
841static struct resource s5p_mfc_resource[] = {
842 [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
843 [1] = DEFINE_RES_IRQ(IRQ_MFC),
844};
845
846struct platform_device s5p_device_mfc = {
847 .name = "s5p-mfc",
848 .id = -1,
849 .num_resources = ARRAY_SIZE(s5p_mfc_resource),
850 .resource = s5p_mfc_resource,
851};
852
853/*
854 * MFC hardware has 2 memory interfaces which are modelled as two separate
855 * platform devices to let dma-mapping distinguish between them.
856 *
857 * MFC parent device (s5p_device_mfc) must be registered before memory
858 * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
859 */
860
861struct platform_device s5p_device_mfc_l = {
862 .name = "s5p-mfc-l",
863 .id = -1,
864 .dev = {
865 .parent = &s5p_device_mfc.dev,
866 .dma_mask = &samsung_device_dma_mask,
867 .coherent_dma_mask = DMA_BIT_MASK(32),
868 },
869};
870
871struct platform_device s5p_device_mfc_r = {
872 .name = "s5p-mfc-r",
873 .id = -1,
874 .dev = {
875 .parent = &s5p_device_mfc.dev,
876 .dma_mask = &samsung_device_dma_mask,
877 .coherent_dma_mask = DMA_BIT_MASK(32),
878 },
879};
880#endif /* CONFIG_S5P_DEV_MFC */
881
882/* MIPI CSIS */
883
884#ifdef CONFIG_S5P_DEV_CSIS0
885static struct resource s5p_mipi_csis0_resource[] = {
886 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_4K),
887 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
888};
889
890struct platform_device s5p_device_mipi_csis0 = {
891 .name = "s5p-mipi-csis",
892 .id = 0,
893 .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
894 .resource = s5p_mipi_csis0_resource,
895};
896#endif /* CONFIG_S5P_DEV_CSIS0 */
897
898#ifdef CONFIG_S5P_DEV_CSIS1
899static struct resource s5p_mipi_csis1_resource[] = {
900 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_4K),
901 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
902};
903
904struct platform_device s5p_device_mipi_csis1 = {
905 .name = "s5p-mipi-csis",
906 .id = 1,
907 .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
908 .resource = s5p_mipi_csis1_resource,
909};
910#endif
911
912/* NAND */
913
914#ifdef CONFIG_S3C_DEV_NAND
915static struct resource s3c_nand_resource[] = {
916 [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
917};
918
919struct platform_device s3c_device_nand = {
920 .name = "s3c2410-nand",
921 .id = -1,
922 .num_resources = ARRAY_SIZE(s3c_nand_resource),
923 .resource = s3c_nand_resource,
924};
925
926/*
927 * s3c_nand_copy_set() - copy nand set data
928 * @set: The new structure, directly copied from the old.
929 *
930 * Copy all the fields from the NAND set field from what is probably __initdata
931 * to new kernel memory. The code returns 0 if the copy happened correctly or
932 * an error code for the calling function to display.
933 *
934 * Note, we currently do not try and look to see if we've already copied the
935 * data in a previous set.
936 */
937static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
938{
939 void *ptr;
940 int size;
941
942 size = sizeof(struct mtd_partition) * set->nr_partitions;
943 if (size) {
944 ptr = kmemdup(set->partitions, size, GFP_KERNEL);
945 set->partitions = ptr;
946
947 if (!ptr)
948 return -ENOMEM;
949 }
950
951 if (set->nr_map && set->nr_chips) {
952 size = sizeof(int) * set->nr_chips;
953 ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
954 set->nr_map = ptr;
955
956 if (!ptr)
957 return -ENOMEM;
958 }
959
960 if (set->ecc_layout) {
961 ptr = kmemdup(set->ecc_layout,
962 sizeof(struct nand_ecclayout), GFP_KERNEL);
963 set->ecc_layout = ptr;
964
965 if (!ptr)
966 return -ENOMEM;
967 }
968
969 return 0;
970}
971
972void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
973{
974 struct s3c2410_platform_nand *npd;
975 int size;
976 int ret;
977
978 /* note, if we get a failure in allocation, we simply drop out of the
979 * function. If there is so little memory available at initialisation
980 * time then there is little chance the system is going to run.
981 */
982
983 npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
984 &s3c_device_nand);
985 if (!npd)
986 return;
987
988 /* now see if we need to copy any of the nand set data */
989
990 size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
991 if (size) {
992 struct s3c2410_nand_set *from = npd->sets;
993 struct s3c2410_nand_set *to;
994 int i;
995
996 to = kmemdup(from, size, GFP_KERNEL);
997 npd->sets = to; /* set, even if we failed */
998
999 if (!to) {
1000 printk(KERN_ERR "%s: no memory for sets\n", __func__);
1001 return;
1002 }
1003
1004 for (i = 0; i < npd->nr_sets; i++) {
1005 ret = s3c_nand_copy_set(to);
1006 if (ret) {
1007 printk(KERN_ERR "%s: failed to copy set %d\n",
1008 __func__, i);
1009 return;
1010 }
1011 to++;
1012 }
1013 }
1014}
1015#endif /* CONFIG_S3C_DEV_NAND */
1016
1017/* ONENAND */
1018
1019#ifdef CONFIG_S3C_DEV_ONENAND
1020static struct resource s3c_onenand_resources[] = {
1021 [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
1022 [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
1023 [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
1024};
1025
1026struct platform_device s3c_device_onenand = {
1027 .name = "samsung-onenand",
1028 .id = 0,
1029 .num_resources = ARRAY_SIZE(s3c_onenand_resources),
1030 .resource = s3c_onenand_resources,
1031};
1032#endif /* CONFIG_S3C_DEV_ONENAND */
1033
1034#ifdef CONFIG_S3C64XX_DEV_ONENAND1
1035static struct resource s3c64xx_onenand1_resources[] = {
1036 [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
1037 [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
1038 [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
1039};
1040
1041struct platform_device s3c64xx_device_onenand1 = {
1042 .name = "samsung-onenand",
1043 .id = 1,
1044 .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
1045 .resource = s3c64xx_onenand1_resources,
1046};
1047
1048void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
1049{
1050 s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
1051 &s3c64xx_device_onenand1);
1052}
1053#endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
1054
1055#ifdef CONFIG_S5P_DEV_ONENAND
1056static struct resource s5p_onenand_resources[] = {
1057 [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
1058 [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
1059 [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
1060};
1061
1062struct platform_device s5p_device_onenand = {
1063 .name = "s5pc110-onenand",
1064 .id = -1,
1065 .num_resources = ARRAY_SIZE(s5p_onenand_resources),
1066 .resource = s5p_onenand_resources,
1067};
1068#endif /* CONFIG_S5P_DEV_ONENAND */
1069
1070/* PMU */
1071
1072#ifdef CONFIG_PLAT_S5P
1073static struct resource s5p_pmu_resource[] = {
1074 DEFINE_RES_IRQ(IRQ_PMU)
1075};
1076
1077struct platform_device s5p_device_pmu = {
1078 .name = "arm-pmu",
1079 .id = ARM_PMU_DEVICE_CPU,
1080 .num_resources = ARRAY_SIZE(s5p_pmu_resource),
1081 .resource = s5p_pmu_resource,
1082};
1083
1084static int __init s5p_pmu_init(void)
1085{
1086 platform_device_register(&s5p_device_pmu);
1087 return 0;
1088}
1089arch_initcall(s5p_pmu_init);
1090#endif /* CONFIG_PLAT_S5P */
1091
1092/* PWM Timer */
1093
1094#ifdef CONFIG_SAMSUNG_DEV_PWM
1095
1096#define TIMER_RESOURCE_SIZE (1)
1097
1098#define TIMER_RESOURCE(_tmr, _irq) \
1099 (struct resource [TIMER_RESOURCE_SIZE]) { \
1100 [0] = { \
1101 .start = _irq, \
1102 .end = _irq, \
1103 .flags = IORESOURCE_IRQ \
1104 } \
1105 }
1106
1107#define DEFINE_S3C_TIMER(_tmr_no, _irq) \
1108 .name = "s3c24xx-pwm", \
1109 .id = _tmr_no, \
1110 .num_resources = TIMER_RESOURCE_SIZE, \
1111 .resource = TIMER_RESOURCE(_tmr_no, _irq), \
1112
1113/*
1114 * since we already have an static mapping for the timer,
1115 * we do not bother setting any IO resource for the base.
1116 */
1117
1118struct platform_device s3c_device_timer[] = {
1119 [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
1120 [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
1121 [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
1122 [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
1123 [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
1124};
1125#endif /* CONFIG_SAMSUNG_DEV_PWM */
1126
1127/* RTC */
1128
1129#ifdef CONFIG_PLAT_S3C24XX
1130static struct resource s3c_rtc_resource[] = {
1131 [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
1132 [1] = DEFINE_RES_IRQ(IRQ_RTC),
1133 [2] = DEFINE_RES_IRQ(IRQ_TICK),
1134};
1135
1136struct platform_device s3c_device_rtc = {
1137 .name = "s3c2410-rtc",
1138 .id = -1,
1139 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
1140 .resource = s3c_rtc_resource,
1141};
1142#endif /* CONFIG_PLAT_S3C24XX */
1143
1144#ifdef CONFIG_S3C_DEV_RTC
1145static struct resource s3c_rtc_resource[] = {
1146 [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
1147 [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
1148 [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
1149};
1150
1151struct platform_device s3c_device_rtc = {
1152 .name = "s3c64xx-rtc",
1153 .id = -1,
1154 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
1155 .resource = s3c_rtc_resource,
1156};
1157#endif /* CONFIG_S3C_DEV_RTC */
1158
1159/* SDI */
1160
1161#ifdef CONFIG_PLAT_S3C24XX
1162static struct resource s3c_sdi_resource[] = {
1163 [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
1164 [1] = DEFINE_RES_IRQ(IRQ_SDI),
1165};
1166
1167struct platform_device s3c_device_sdi = {
1168 .name = "s3c2410-sdi",
1169 .id = -1,
1170 .num_resources = ARRAY_SIZE(s3c_sdi_resource),
1171 .resource = s3c_sdi_resource,
1172};
1173
1174void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
1175{
1176 s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
1177 &s3c_device_sdi);
1178}
1179#endif /* CONFIG_PLAT_S3C24XX */
1180
1181/* SPI */
1182
1183#ifdef CONFIG_PLAT_S3C24XX
1184static struct resource s3c_spi0_resource[] = {
1185 [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
1186 [1] = DEFINE_RES_IRQ(IRQ_SPI0),
1187};
1188
1189struct platform_device s3c_device_spi0 = {
1190 .name = "s3c2410-spi",
1191 .id = 0,
1192 .num_resources = ARRAY_SIZE(s3c_spi0_resource),
1193 .resource = s3c_spi0_resource,
1194 .dev = {
1195 .dma_mask = &samsung_device_dma_mask,
1196 .coherent_dma_mask = DMA_BIT_MASK(32),
1197 }
1198};
1199
1200static struct resource s3c_spi1_resource[] = {
1201 [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
1202 [1] = DEFINE_RES_IRQ(IRQ_SPI1),
1203};
1204
1205struct platform_device s3c_device_spi1 = {
1206 .name = "s3c2410-spi",
1207 .id = 1,
1208 .num_resources = ARRAY_SIZE(s3c_spi1_resource),
1209 .resource = s3c_spi1_resource,
1210 .dev = {
1211 .dma_mask = &samsung_device_dma_mask,
1212 .coherent_dma_mask = DMA_BIT_MASK(32),
1213 }
1214};
1215#endif /* CONFIG_PLAT_S3C24XX */
1216
1217/* Touchscreen */
1218
1219#ifdef CONFIG_PLAT_S3C24XX
1220static struct resource s3c_ts_resource[] = {
1221 [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
1222 [1] = DEFINE_RES_IRQ(IRQ_TC),
1223};
1224
1225struct platform_device s3c_device_ts = {
1226 .name = "s3c2410-ts",
1227 .id = -1,
1228 .dev.parent = &s3c_device_adc.dev,
1229 .num_resources = ARRAY_SIZE(s3c_ts_resource),
1230 .resource = s3c_ts_resource,
1231};
1232
1233void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
1234{
1235 s3c_set_platdata(hard_s3c2410ts_info,
1236 sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
1237}
1238#endif /* CONFIG_PLAT_S3C24XX */
1239
1240#ifdef CONFIG_SAMSUNG_DEV_TS
1241static struct resource s3c_ts_resource[] = {
1242 [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
1243 [1] = DEFINE_RES_IRQ(IRQ_TC),
1244};
1245
1246static struct s3c2410_ts_mach_info default_ts_data __initdata = {
1247 .delay = 10000,
1248 .presc = 49,
1249 .oversampling_shift = 2,
1250};
1251
1252struct platform_device s3c_device_ts = {
1253 .name = "s3c64xx-ts",
1254 .id = -1,
1255 .num_resources = ARRAY_SIZE(s3c_ts_resource),
1256 .resource = s3c_ts_resource,
1257};
1258
1259void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
1260{
1261 if (!pd)
1262 pd = &default_ts_data;
1263
1264 s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
1265 &s3c_device_ts);
1266}
1267#endif /* CONFIG_SAMSUNG_DEV_TS */
1268
1269/* TV */
1270
1271#ifdef CONFIG_S5P_DEV_TV
1272
1273static struct resource s5p_hdmi_resources[] = {
1274 [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
1275 [1] = DEFINE_RES_IRQ(IRQ_HDMI),
1276};
1277
1278struct platform_device s5p_device_hdmi = {
1279 .name = "s5p-hdmi",
1280 .id = -1,
1281 .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
1282 .resource = s5p_hdmi_resources,
1283};
1284
1285static struct resource s5p_sdo_resources[] = {
1286 [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
1287 [1] = DEFINE_RES_IRQ(IRQ_SDO),
1288};
1289
1290struct platform_device s5p_device_sdo = {
1291 .name = "s5p-sdo",
1292 .id = -1,
1293 .num_resources = ARRAY_SIZE(s5p_sdo_resources),
1294 .resource = s5p_sdo_resources,
1295};
1296
1297static struct resource s5p_mixer_resources[] = {
1298 [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
1299 [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
1300 [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
1301};
1302
1303struct platform_device s5p_device_mixer = {
1304 .name = "s5p-mixer",
1305 .id = -1,
1306 .num_resources = ARRAY_SIZE(s5p_mixer_resources),
1307 .resource = s5p_mixer_resources,
1308 .dev = {
1309 .dma_mask = &samsung_device_dma_mask,
1310 .coherent_dma_mask = DMA_BIT_MASK(32),
1311 }
1312};
1313#endif /* CONFIG_S5P_DEV_TV */
1314
1315/* USB */
1316
1317#ifdef CONFIG_S3C_DEV_USB_HOST
1318static struct resource s3c_usb_resource[] = {
1319 [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
1320 [1] = DEFINE_RES_IRQ(IRQ_USBH),
1321};
1322
1323struct platform_device s3c_device_ohci = {
1324 .name = "s3c2410-ohci",
1325 .id = -1,
1326 .num_resources = ARRAY_SIZE(s3c_usb_resource),
1327 .resource = s3c_usb_resource,
1328 .dev = {
1329 .dma_mask = &samsung_device_dma_mask,
1330 .coherent_dma_mask = DMA_BIT_MASK(32),
1331 }
1332};
1333
1334/*
1335 * s3c_ohci_set_platdata - initialise OHCI device platform data
1336 * @info: The platform data.
1337 *
1338 * This call copies the @info passed in and sets the device .platform_data
1339 * field to that copy. The @info is copied so that the original can be marked
1340 * __initdata.
1341 */
1342
1343void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
1344{
1345 s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
1346 &s3c_device_ohci);
1347}
1348#endif /* CONFIG_S3C_DEV_USB_HOST */
1349
1350/* USB Device (Gadget) */
1351
1352#ifdef CONFIG_PLAT_S3C24XX
1353static struct resource s3c_usbgadget_resource[] = {
1354 [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
1355 [1] = DEFINE_RES_IRQ(IRQ_USBD),
1356};
1357
1358struct platform_device s3c_device_usbgadget = {
1359 .name = "s3c2410-usbgadget",
1360 .id = -1,
1361 .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
1362 .resource = s3c_usbgadget_resource,
1363};
1364
1365void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
1366{
1367 s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
1368}
1369#endif /* CONFIG_PLAT_S3C24XX */
1370
1371/* USB EHCI Host Controller */
1372
1373#ifdef CONFIG_S5P_DEV_USB_EHCI
1374static struct resource s5p_ehci_resource[] = {
1375 [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
1376 [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
1377};
1378
1379struct platform_device s5p_device_ehci = {
1380 .name = "s5p-ehci",
1381 .id = -1,
1382 .num_resources = ARRAY_SIZE(s5p_ehci_resource),
1383 .resource = s5p_ehci_resource,
1384 .dev = {
1385 .dma_mask = &samsung_device_dma_mask,
1386 .coherent_dma_mask = DMA_BIT_MASK(32),
1387 }
1388};
1389
1390void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
1391{
1392 struct s5p_ehci_platdata *npd;
1393
1394 npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
1395 &s5p_device_ehci);
1396
1397 if (!npd->phy_init)
1398 npd->phy_init = s5p_usb_phy_init;
1399 if (!npd->phy_exit)
1400 npd->phy_exit = s5p_usb_phy_exit;
1401}
1402#endif /* CONFIG_S5P_DEV_USB_EHCI */
1403
1404/* USB HSOTG */
1405
1406#ifdef CONFIG_S3C_DEV_USB_HSOTG
1407static struct resource s3c_usb_hsotg_resources[] = {
1408 [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_16K),
1409 [1] = DEFINE_RES_IRQ(IRQ_OTG),
1410};
1411
1412struct platform_device s3c_device_usb_hsotg = {
1413 .name = "s3c-hsotg",
1414 .id = -1,
1415 .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
1416 .resource = s3c_usb_hsotg_resources,
1417 .dev = {
1418 .dma_mask = &samsung_device_dma_mask,
1419 .coherent_dma_mask = DMA_BIT_MASK(32),
1420 },
1421};
1422#endif /* CONFIG_S3C_DEV_USB_HSOTG */
1423
1424/* USB High Spped 2.0 Device (Gadget) */
1425
1426#ifdef CONFIG_PLAT_S3C24XX
1427static struct resource s3c_hsudc_resource[] = {
1428 [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
1429 [1] = DEFINE_RES_IRQ(IRQ_USBD),
1430};
1431
1432struct platform_device s3c_device_usb_hsudc = {
1433 .name = "s3c-hsudc",
1434 .id = -1,
1435 .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
1436 .resource = s3c_hsudc_resource,
1437 .dev = {
1438 .dma_mask = &samsung_device_dma_mask,
1439 .coherent_dma_mask = DMA_BIT_MASK(32),
1440 },
1441};
1442
1443void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
1444{
1445 s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
1446}
1447#endif /* CONFIG_PLAT_S3C24XX */
1448
1449/* WDT */
1450
1451#ifdef CONFIG_S3C_DEV_WDT
1452static struct resource s3c_wdt_resource[] = {
1453 [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
1454 [1] = DEFINE_RES_IRQ(IRQ_WDT),
1455};
1456
1457struct platform_device s3c_device_wdt = {
1458 .name = "s3c2410-wdt",
1459 .id = -1,
1460 .num_resources = ARRAY_SIZE(s3c_wdt_resource),
1461 .resource = s3c_wdt_resource,
1462};
1463#endif /* CONFIG_S3C_DEV_WDT */
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
deleted file mode 100644
index 1c0b0401594..00000000000
--- a/arch/arm/plat-samsung/gpio-config.c
+++ /dev/null
@@ -1,431 +0,0 @@
1/* linux/arch/arm/plat-s3c/gpio-config.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008-2010 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C series GPIO configuration core
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/gpio.h>
18#include <linux/io.h>
19
20#include <plat/gpio-core.h>
21#include <plat/gpio-cfg.h>
22#include <plat/gpio-cfg-helpers.h>
23
24int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
25{
26 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
27 unsigned long flags;
28 int offset;
29 int ret;
30
31 if (!chip)
32 return -EINVAL;
33
34 offset = pin - chip->chip.base;
35
36 s3c_gpio_lock(chip, flags);
37 ret = s3c_gpio_do_setcfg(chip, offset, config);
38 s3c_gpio_unlock(chip, flags);
39
40 return ret;
41}
42EXPORT_SYMBOL(s3c_gpio_cfgpin);
43
44int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
45 unsigned int cfg)
46{
47 int ret;
48
49 for (; nr > 0; nr--, start++) {
50 ret = s3c_gpio_cfgpin(start, cfg);
51 if (ret != 0)
52 return ret;
53 }
54
55 return 0;
56}
57EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
58
59int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
60 unsigned int cfg, s3c_gpio_pull_t pull)
61{
62 int ret;
63
64 for (; nr > 0; nr--, start++) {
65 s3c_gpio_setpull(start, pull);
66 ret = s3c_gpio_cfgpin(start, cfg);
67 if (ret != 0)
68 return ret;
69 }
70
71 return 0;
72}
73EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
74
75unsigned s3c_gpio_getcfg(unsigned int pin)
76{
77 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
78 unsigned long flags;
79 unsigned ret = 0;
80 int offset;
81
82 if (chip) {
83 offset = pin - chip->chip.base;
84
85 s3c_gpio_lock(chip, flags);
86 ret = s3c_gpio_do_getcfg(chip, offset);
87 s3c_gpio_unlock(chip, flags);
88 }
89
90 return ret;
91}
92EXPORT_SYMBOL(s3c_gpio_getcfg);
93
94
95int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
96{
97 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
98 unsigned long flags;
99 int offset, ret;
100
101 if (!chip)
102 return -EINVAL;
103
104 offset = pin - chip->chip.base;
105
106 s3c_gpio_lock(chip, flags);
107 ret = s3c_gpio_do_setpull(chip, offset, pull);
108 s3c_gpio_unlock(chip, flags);
109
110 return ret;
111}
112EXPORT_SYMBOL(s3c_gpio_setpull);
113
114s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
115{
116 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
117 unsigned long flags;
118 int offset;
119 u32 pup = 0;
120
121 if (chip) {
122 offset = pin - chip->chip.base;
123
124 s3c_gpio_lock(chip, flags);
125 pup = s3c_gpio_do_getpull(chip, offset);
126 s3c_gpio_unlock(chip, flags);
127 }
128
129 return (__force s3c_gpio_pull_t)pup;
130}
131EXPORT_SYMBOL(s3c_gpio_getpull);
132
133#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
134int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
135 unsigned int off, unsigned int cfg)
136{
137 void __iomem *reg = chip->base;
138 unsigned int shift = off;
139 u32 con;
140
141 if (s3c_gpio_is_cfg_special(cfg)) {
142 cfg &= 0xf;
143
144 /* Map output to 0, and SFN2 to 1 */
145 cfg -= 1;
146 if (cfg > 1)
147 return -EINVAL;
148
149 cfg <<= shift;
150 }
151
152 con = __raw_readl(reg);
153 con &= ~(0x1 << shift);
154 con |= cfg;
155 __raw_writel(con, reg);
156
157 return 0;
158}
159
160unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
161 unsigned int off)
162{
163 u32 con;
164
165 con = __raw_readl(chip->base);
166 con >>= off;
167 con &= 1;
168 con++;
169
170 return S3C_GPIO_SFN(con);
171}
172
173int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
174 unsigned int off, unsigned int cfg)
175{
176 void __iomem *reg = chip->base;
177 unsigned int shift = off * 2;
178 u32 con;
179
180 if (s3c_gpio_is_cfg_special(cfg)) {
181 cfg &= 0xf;
182 if (cfg > 3)
183 return -EINVAL;
184
185 cfg <<= shift;
186 }
187
188 con = __raw_readl(reg);
189 con &= ~(0x3 << shift);
190 con |= cfg;
191 __raw_writel(con, reg);
192
193 return 0;
194}
195
196unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
197 unsigned int off)
198{
199 u32 con;
200
201 con = __raw_readl(chip->base);
202 con >>= off * 2;
203 con &= 3;
204
205 /* this conversion works for IN and OUT as well as special mode */
206 return S3C_GPIO_SPECIAL(con);
207}
208#endif
209
210#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
211int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
212 unsigned int off, unsigned int cfg)
213{
214 void __iomem *reg = chip->base;
215 unsigned int shift = (off & 7) * 4;
216 u32 con;
217
218 if (off < 8 && chip->chip.ngpio > 8)
219 reg -= 4;
220
221 if (s3c_gpio_is_cfg_special(cfg)) {
222 cfg &= 0xf;
223 cfg <<= shift;
224 }
225
226 con = __raw_readl(reg);
227 con &= ~(0xf << shift);
228 con |= cfg;
229 __raw_writel(con, reg);
230
231 return 0;
232}
233
234unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
235 unsigned int off)
236{
237 void __iomem *reg = chip->base;
238 unsigned int shift = (off & 7) * 4;
239 u32 con;
240
241 if (off < 8 && chip->chip.ngpio > 8)
242 reg -= 4;
243
244 con = __raw_readl(reg);
245 con >>= shift;
246 con &= 0xf;
247
248 /* this conversion works for IN and OUT as well as special mode */
249 return S3C_GPIO_SPECIAL(con);
250}
251
252#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
253
254#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
255int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
256 unsigned int off, s3c_gpio_pull_t pull)
257{
258 void __iomem *reg = chip->base + 0x08;
259 int shift = off * 2;
260 u32 pup;
261
262 pup = __raw_readl(reg);
263 pup &= ~(3 << shift);
264 pup |= pull << shift;
265 __raw_writel(pup, reg);
266
267 return 0;
268}
269
270s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
271 unsigned int off)
272{
273 void __iomem *reg = chip->base + 0x08;
274 int shift = off * 2;
275 u32 pup = __raw_readl(reg);
276
277 pup >>= shift;
278 pup &= 0x3;
279 return (__force s3c_gpio_pull_t)pup;
280}
281
282#ifdef CONFIG_S3C_GPIO_PULL_S3C2443
283int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
284 unsigned int off, s3c_gpio_pull_t pull)
285{
286 switch (pull) {
287 case S3C_GPIO_PULL_NONE:
288 pull = 0x01;
289 break;
290 case S3C_GPIO_PULL_UP:
291 pull = 0x00;
292 break;
293 case S3C_GPIO_PULL_DOWN:
294 pull = 0x02;
295 break;
296 }
297 return s3c_gpio_setpull_updown(chip, off, pull);
298}
299
300s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip,
301 unsigned int off)
302{
303 s3c_gpio_pull_t pull;
304
305 pull = s3c_gpio_getpull_updown(chip, off);
306
307 switch (pull) {
308 case 0x00:
309 pull = S3C_GPIO_PULL_UP;
310 break;
311 case 0x01:
312 case 0x03:
313 pull = S3C_GPIO_PULL_NONE;
314 break;
315 case 0x02:
316 pull = S3C_GPIO_PULL_DOWN;
317 break;
318 }
319
320 return pull;
321}
322#endif
323#endif
324
325#if defined(CONFIG_S3C_GPIO_PULL_UP) || defined(CONFIG_S3C_GPIO_PULL_DOWN)
326static int s3c_gpio_setpull_1(struct s3c_gpio_chip *chip,
327 unsigned int off, s3c_gpio_pull_t pull,
328 s3c_gpio_pull_t updown)
329{
330 void __iomem *reg = chip->base + 0x08;
331 u32 pup = __raw_readl(reg);
332
333 if (pull == updown)
334 pup &= ~(1 << off);
335 else if (pull == S3C_GPIO_PULL_NONE)
336 pup |= (1 << off);
337 else
338 return -EINVAL;
339
340 __raw_writel(pup, reg);
341 return 0;
342}
343
344static s3c_gpio_pull_t s3c_gpio_getpull_1(struct s3c_gpio_chip *chip,
345 unsigned int off, s3c_gpio_pull_t updown)
346{
347 void __iomem *reg = chip->base + 0x08;
348 u32 pup = __raw_readl(reg);
349
350 pup &= (1 << off);
351 return pup ? S3C_GPIO_PULL_NONE : updown;
352}
353#endif /* CONFIG_S3C_GPIO_PULL_UP || CONFIG_S3C_GPIO_PULL_DOWN */
354
355#ifdef CONFIG_S3C_GPIO_PULL_UP
356s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
357 unsigned int off)
358{
359 return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
360}
361
362int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
363 unsigned int off, s3c_gpio_pull_t pull)
364{
365 return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
366}
367#endif /* CONFIG_S3C_GPIO_PULL_UP */
368
369#ifdef CONFIG_S3C_GPIO_PULL_DOWN
370s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip,
371 unsigned int off)
372{
373 return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
374}
375
376int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
377 unsigned int off, s3c_gpio_pull_t pull)
378{
379 return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
380}
381#endif /* CONFIG_S3C_GPIO_PULL_DOWN */
382
383#ifdef CONFIG_S5P_GPIO_DRVSTR
384s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
385{
386 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
387 unsigned int off;
388 void __iomem *reg;
389 int shift;
390 u32 drvstr;
391
392 if (!chip)
393 return -EINVAL;
394
395 off = pin - chip->chip.base;
396 shift = off * 2;
397 reg = chip->base + 0x0C;
398
399 drvstr = __raw_readl(reg);
400 drvstr = drvstr >> shift;
401 drvstr &= 0x3;
402
403 return (__force s5p_gpio_drvstr_t)drvstr;
404}
405EXPORT_SYMBOL(s5p_gpio_get_drvstr);
406
407int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
408{
409 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
410 unsigned int off;
411 void __iomem *reg;
412 int shift;
413 u32 tmp;
414
415 if (!chip)
416 return -EINVAL;
417
418 off = pin - chip->chip.base;
419 shift = off * 2;
420 reg = chip->base + 0x0C;
421
422 tmp = __raw_readl(reg);
423 tmp &= ~(0x3 << shift);
424 tmp |= drvstr << shift;
425
426 __raw_writel(tmp, reg);
427
428 return 0;
429}
430EXPORT_SYMBOL(s5p_gpio_set_drvstr);
431#endif /* CONFIG_S5P_GPIO_DRVSTR */
diff --git a/arch/arm/plat-samsung/gpio.c b/arch/arm/plat-samsung/gpio.c
deleted file mode 100644
index 7743c4b8b2f..00000000000
--- a/arch/arm/plat-samsung/gpio.c
+++ /dev/null
@@ -1,167 +0,0 @@
1/* linux/arch/arm/plat-s3c/gpio.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series GPIO core
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/spinlock.h>
19
20#include <plat/gpio-core.h>
21
22#ifdef CONFIG_S3C_GPIO_TRACK
23struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
24
25static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip)
26{
27 unsigned int gpn;
28 int i;
29
30 gpn = chip->chip.base;
31 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
32 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
33 s3c_gpios[gpn] = chip;
34 }
35}
36#endif /* CONFIG_S3C_GPIO_TRACK */
37
38/* Default routines for controlling GPIO, based on the original S3C24XX
39 * GPIO functions which deal with the case where each gpio bank of the
40 * chip is as following:
41 *
42 * base + 0x00: Control register, 2 bits per gpio
43 * gpio n: 2 bits starting at (2*n)
44 * 00 = input, 01 = output, others mean special-function
45 * base + 0x04: Data register, 1 bit per gpio
46 * bit n: data bit n
47*/
48
49static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
50{
51 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
52 void __iomem *base = ourchip->base;
53 unsigned long flags;
54 unsigned long con;
55
56 s3c_gpio_lock(ourchip, flags);
57
58 con = __raw_readl(base + 0x00);
59 con &= ~(3 << (offset * 2));
60
61 __raw_writel(con, base + 0x00);
62
63 s3c_gpio_unlock(ourchip, flags);
64 return 0;
65}
66
67static int s3c_gpiolib_output(struct gpio_chip *chip,
68 unsigned offset, int value)
69{
70 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
71 void __iomem *base = ourchip->base;
72 unsigned long flags;
73 unsigned long dat;
74 unsigned long con;
75
76 s3c_gpio_lock(ourchip, flags);
77
78 dat = __raw_readl(base + 0x04);
79 dat &= ~(1 << offset);
80 if (value)
81 dat |= 1 << offset;
82 __raw_writel(dat, base + 0x04);
83
84 con = __raw_readl(base + 0x00);
85 con &= ~(3 << (offset * 2));
86 con |= 1 << (offset * 2);
87
88 __raw_writel(con, base + 0x00);
89 __raw_writel(dat, base + 0x04);
90
91 s3c_gpio_unlock(ourchip, flags);
92 return 0;
93}
94
95static void s3c_gpiolib_set(struct gpio_chip *chip,
96 unsigned offset, int value)
97{
98 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
99 void __iomem *base = ourchip->base;
100 unsigned long flags;
101 unsigned long dat;
102
103 s3c_gpio_lock(ourchip, flags);
104
105 dat = __raw_readl(base + 0x04);
106 dat &= ~(1 << offset);
107 if (value)
108 dat |= 1 << offset;
109 __raw_writel(dat, base + 0x04);
110
111 s3c_gpio_unlock(ourchip, flags);
112}
113
114static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
115{
116 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
117 unsigned long val;
118
119 val = __raw_readl(ourchip->base + 0x04);
120 val >>= offset;
121 val &= 1;
122
123 return val;
124}
125
126__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
127{
128 struct gpio_chip *gc = &chip->chip;
129 int ret;
130
131 BUG_ON(!chip->base);
132 BUG_ON(!gc->label);
133 BUG_ON(!gc->ngpio);
134
135 spin_lock_init(&chip->lock);
136
137 if (!gc->direction_input)
138 gc->direction_input = s3c_gpiolib_input;
139 if (!gc->direction_output)
140 gc->direction_output = s3c_gpiolib_output;
141 if (!gc->set)
142 gc->set = s3c_gpiolib_set;
143 if (!gc->get)
144 gc->get = s3c_gpiolib_get;
145
146#ifdef CONFIG_PM
147 if (chip->pm != NULL) {
148 if (!chip->pm->save || !chip->pm->resume)
149 printk(KERN_ERR "gpio: %s has missing PM functions\n",
150 gc->label);
151 } else
152 printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
153#endif
154
155 /* gpiochip_add() prints own failure message on error. */
156 ret = gpiochip_add(gc);
157 if (ret >= 0)
158 s3c_gpiolib_track(chip);
159}
160
161int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
162{
163 struct s3c_gpio_chip *s3c_chip = container_of(chip,
164 struct s3c_gpio_chip, chip);
165
166 return s3c_chip->irq_base + offset;
167}
diff --git a/arch/arm/plat-samsung/include/plat/audio-simtec.h b/arch/arm/plat-samsung/include/plat/audio-simtec.h
new file mode 100644
index 00000000000..5345364e742
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/audio-simtec.h
@@ -0,0 +1,37 @@
1/* arch/arm/plat-samsung/include/plat/audio-simtec.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Simtec Audio support.
12*/
13
14/**
15 * struct s3c24xx_audio_simtec_pdata - platform data for simtec audio
16 * @use_mpllin: Select codec clock from MPLLin
17 * @output_cdclk: Need to output CDCLK to the codec
18 * @have_mic: Set if we have a MIC socket
19 * @have_lout: Set if we have a LineOut socket
20 * @amp_gpio: GPIO pin to enable the AMP
21 * @amp_gain: Option GPIO to control AMP gain
22 */
23struct s3c24xx_audio_simtec_pdata {
24 unsigned int use_mpllin:1;
25 unsigned int output_cdclk:1;
26
27 unsigned int have_mic:1;
28 unsigned int have_lout:1;
29
30 int amp_gpio;
31 int amp_gain[2];
32
33 void (*startup)(void);
34};
35
36extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
37 struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/plat-samsung/include/plat/camport.h b/arch/arm/plat-samsung/include/plat/camport.h
new file mode 100644
index 00000000000..a5708bf84b3
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/camport.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * S5P series camera interface helper functions
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __PLAT_SAMSUNG_CAMPORT_H_
12#define __PLAT_SAMSUNG_CAMPORT_H_ __FILE__
13
14enum s5p_camport_id {
15 S5P_CAMPORT_A,
16 S5P_CAMPORT_B,
17};
18
19/*
20 * The helper functions to configure GPIO for the camera parallel bus.
21 * The camera port can be multiplexed with any FIMC entity, even multiple
22 * FIMC entities are allowed to be attached to a single port simultaneously.
23 * These functions are to be used in the board setup code.
24 */
25int s5pv210_fimc_setup_gpio(enum s5p_camport_id id);
26int exynos4_fimc_setup_gpio(enum s5p_camport_id id);
27
28#endif /* __PLAT_SAMSUNG_CAMPORT_H */
diff --git a/arch/arm/plat-samsung/include/plat/common-smdk.h b/arch/arm/plat-samsung/include/plat/common-smdk.h
new file mode 100644
index 00000000000..ba028f1ed30
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/common-smdk.h
@@ -0,0 +1,15 @@
1/* linux/arch/arm/plat-samsung/include/plat/common-smdk.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Common code for SMDK2410 and SMDK2440 boards
7 *
8 * http://www.fluff.org/ben/smdk2440/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern void smdk_machine_init(void);
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
new file mode 100644
index 00000000000..dac4760c0f0
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -0,0 +1,288 @@
1/* arch/arm/plat-samsung/include/plat/cpu-freq-core.h
2 *
3 * Copyright (c) 2006-2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C CPU frequency scaling support - core support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <plat/cpu-freq.h>
15
16struct seq_file;
17
18#define MAX_BANKS (8)
19#define S3C2412_MAX_IO (8)
20
21/**
22 * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
23 * @bankcon: The cached version of settings in this structure.
24 * @tacp:
25 * @tacs: Time from address valid to nCS asserted.
26 * @tcos: Time from nCS asserted to nOE or nWE asserted.
27 * @tacc: Time that nOE or nWE is asserted.
28 * @tcoh: Time nCS is held after nOE or nWE are released.
29 * @tcah: Time address is held for after
30 * @nwait_en: Whether nWAIT is enabled for this bank.
31 *
32 * This structure represents the IO timings for a S3C2410 style IO bank
33 * used by the CPU frequency support if it needs to change the settings
34 * of the IO.
35 */
36struct s3c2410_iobank_timing {
37 unsigned long bankcon;
38 unsigned int tacp;
39 unsigned int tacs;
40 unsigned int tcos;
41 unsigned int tacc;
42 unsigned int tcoh; /* nCS hold afrer nOE/nWE */
43 unsigned int tcah; /* Address hold after nCS */
44 unsigned char nwait_en; /* nWait enabled for bank. */
45};
46
47/**
48 * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
49 * @idcy: The idle cycle time between transactions.
50 * @wstrd: nCS release to end of read cycle.
51 * @wstwr: nCS release to end of write cycle.
52 * @wstoen: nCS assertion to nOE assertion time.
53 * @wstwen: nCS assertion to nWE assertion time.
54 * @wstbrd: Burst ready delay.
55 * @smbidcyr: Register cache for smbidcyr value.
56 * @smbwstrd: Register cache for smbwstrd value.
57 * @smbwstwr: Register cache for smbwstwr value.
58 * @smbwstoen: Register cache for smbwstoen value.
59 * @smbwstwen: Register cache for smbwstwen value.
60 * @smbwstbrd: Register cache for smbwstbrd value.
61 *
62 * Timing information for a IO bank on an S3C2412 or similar system which
63 * uses a PL093 block.
64 */
65struct s3c2412_iobank_timing {
66 unsigned int idcy;
67 unsigned int wstrd;
68 unsigned int wstwr;
69 unsigned int wstoen;
70 unsigned int wstwen;
71 unsigned int wstbrd;
72
73 /* register cache */
74 unsigned char smbidcyr;
75 unsigned char smbwstrd;
76 unsigned char smbwstwr;
77 unsigned char smbwstoen;
78 unsigned char smbwstwen;
79 unsigned char smbwstbrd;
80};
81
82union s3c_iobank {
83 struct s3c2410_iobank_timing *io_2410;
84 struct s3c2412_iobank_timing *io_2412;
85};
86
87/**
88 * struct s3c_iotimings - Chip IO timings holder
89 * @bank: The timings for each IO bank.
90 */
91struct s3c_iotimings {
92 union s3c_iobank bank[MAX_BANKS];
93};
94
95/**
96 * struct s3c_plltab - PLL table information.
97 * @vals: List of PLL values.
98 * @size: Size of the PLL table @vals.
99 */
100struct s3c_plltab {
101 struct s3c_pllval *vals;
102 int size;
103};
104
105/**
106 * struct s3c_cpufreq_config - current cpu frequency configuration
107 * @freq: The current settings for the core clocks.
108 * @max: Maxium settings, derived from core, board and user settings.
109 * @pll: The PLL table entry for the current PLL settings.
110 * @divs: The divisor settings for the core clocks.
111 * @info: The current core driver information.
112 * @board: The information for the board we are running on.
113 * @lock_pll: Set if the PLL settings cannot be changed.
114 *
115 * This is for the core drivers that need to know information about
116 * the current settings and values. It should not be needed by any
117 * device drivers.
118*/
119struct s3c_cpufreq_config {
120 struct s3c_freq freq;
121 struct s3c_freq max;
122 struct cpufreq_frequency_table pll;
123 struct s3c_clkdivs divs;
124 struct s3c_cpufreq_info *info; /* for core, not drivers */
125 struct s3c_cpufreq_board *board;
126
127 unsigned int lock_pll:1;
128};
129
130/**
131 * struct s3c_cpufreq_info - Information for the CPU frequency driver.
132 * @name: The name of this implementation.
133 * @max: The maximum frequencies for the system.
134 * @latency: Transition latency to give to cpufreq.
135 * @locktime_m: The lock-time in uS for the MPLL.
136 * @locktime_u: The lock-time in uS for the UPLL.
137 * @locttime_bits: The number of bits each LOCKTIME field.
138 * @need_pll: Set if this driver needs to change the PLL values to achieve
139 * any frequency changes. This is really only need by devices like the
140 * S3C2410 where there is no or limited divider between the PLL and the
141 * ARMCLK.
142 * @resume_clocks: Update the clocks on resume.
143 * @get_iotiming: Get the current IO timing data, mainly for use at start.
144 * @set_iotiming: Update the IO timings from the cached copies calculated
145 * from the @calc_iotiming entry when changing the frequency.
146 * @calc_iotiming: Calculate and update the cached copies of the IO timings
147 * from the newly calculated frequencies.
148 * @calc_freqtable: Calculate (fill in) the given frequency table from the
149 * current frequency configuration. If the table passed in is NULL,
150 * then the return is the number of elements to be filled for allocation
151 * of the table.
152 * @set_refresh: Set the memory refresh configuration.
153 * @set_fvco: Set the PLL frequencies.
154 * @set_divs: Update the clock divisors.
155 * @calc_divs: Calculate the clock divisors.
156 */
157struct s3c_cpufreq_info {
158 const char *name;
159 struct s3c_freq max;
160
161 unsigned int latency;
162
163 unsigned int locktime_m;
164 unsigned int locktime_u;
165 unsigned char locktime_bits;
166
167 unsigned int need_pll:1;
168
169 /* driver routines */
170
171 void (*resume_clocks)(void);
172
173 int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
174 struct s3c_iotimings *timings);
175
176 void (*set_iotiming)(struct s3c_cpufreq_config *cfg,
177 struct s3c_iotimings *timings);
178
179 int (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
180 struct s3c_iotimings *timings);
181
182 int (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
183 struct cpufreq_frequency_table *t,
184 size_t table_size);
185
186 void (*debug_io_show)(struct seq_file *seq,
187 struct s3c_cpufreq_config *cfg,
188 union s3c_iobank *iob);
189
190 void (*set_refresh)(struct s3c_cpufreq_config *cfg);
191 void (*set_fvco)(struct s3c_cpufreq_config *cfg);
192 void (*set_divs)(struct s3c_cpufreq_config *cfg);
193 int (*calc_divs)(struct s3c_cpufreq_config *cfg);
194};
195
196extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
197
198extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
199 unsigned int plls_no);
200
201/* exports and utilities for debugfs */
202extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
203extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
204
205extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
206 struct s3c_cpufreq_config *cfg,
207 union s3c_iobank *iob);
208
209extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
210 struct s3c_cpufreq_config *cfg,
211 union s3c_iobank *iob);
212
213#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
214#define s3c_cpufreq_debugfs_call(x) x
215#else
216#define s3c_cpufreq_debugfs_call(x) NULL
217#endif
218
219/* Useful utility functions. */
220
221extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
222
223/* S3C2410 and compatible exported functions */
224
225extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
226extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
227
228#ifdef CONFIG_S3C2410_IOTIMING
229extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
230 struct s3c_iotimings *iot);
231
232extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
233 struct s3c_iotimings *timings);
234
235extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
236 struct s3c_iotimings *iot);
237#else
238#define s3c2410_iotiming_calc NULL
239#define s3c2410_iotiming_get NULL
240#define s3c2410_iotiming_set NULL
241#endif /* CONFIG_S3C2410_IOTIMING */
242
243/* S3C2412 compatible routines */
244
245extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
246 struct s3c_iotimings *timings);
247
248extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
249 struct s3c_iotimings *timings);
250
251extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
252 struct s3c_iotimings *iot);
253
254extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
255 struct s3c_iotimings *iot);
256
257#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG
258#define s3c_freq_dbg(x...) printk(KERN_INFO x)
259#else
260#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
261#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */
262
263#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG
264#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
265#else
266#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
267#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */
268
269static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
270 int index, size_t table_size,
271 unsigned int freq)
272{
273 if (index < 0)
274 return index;
275
276 if (table) {
277 if (index >= table_size)
278 return -ENOMEM;
279
280 s3c_freq_dbg("%s: { %d = %u kHz }\n",
281 __func__, index, freq);
282
283 table[index].index = index;
284 table[index].frequency = freq;
285 }
286
287 return index + 1;
288}
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 24ebb1e1de4..ab633c9c2ae 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -30,30 +30,24 @@ extern struct s3c24xx_uart_resources s5p_uart_resources[];
30extern struct platform_device *s3c24xx_uart_devs[]; 30extern struct platform_device *s3c24xx_uart_devs[];
31extern struct platform_device *s3c24xx_uart_src[]; 31extern struct platform_device *s3c24xx_uart_src[];
32 32
33extern struct platform_device s3c_device_timer[]; 33extern struct platform_device s3c64xx_device_ac97;
34
35extern struct platform_device s3c64xx_device_iis0; 34extern struct platform_device s3c64xx_device_iis0;
36extern struct platform_device s3c64xx_device_iis1; 35extern struct platform_device s3c64xx_device_iis1;
37extern struct platform_device s3c64xx_device_iisv4; 36extern struct platform_device s3c64xx_device_iisv4;
38 37extern struct platform_device s3c64xx_device_onenand1;
39extern struct platform_device s3c64xx_device_spi0;
40extern struct platform_device s3c64xx_device_spi1;
41
42extern struct platform_device samsung_asoc_dma;
43extern struct platform_device samsung_asoc_idma;
44
45extern struct platform_device s3c64xx_device_pcm0; 38extern struct platform_device s3c64xx_device_pcm0;
46extern struct platform_device s3c64xx_device_pcm1; 39extern struct platform_device s3c64xx_device_pcm1;
40extern struct platform_device s3c64xx_device_spi0;
41extern struct platform_device s3c64xx_device_spi1;
47 42
48extern struct platform_device s3c64xx_device_ac97; 43extern struct platform_device s3c_device_adc;
49 44extern struct platform_device s3c_device_cfcon;
50extern struct platform_device s3c_device_ts;
51
52extern struct platform_device s3c_device_fb; 45extern struct platform_device s3c_device_fb;
53extern struct platform_device s5p_device_fimd0; 46extern struct platform_device s3c_device_hwmon;
54extern struct platform_device s3c_device_ohci; 47extern struct platform_device s3c_device_hsmmc0;
55extern struct platform_device s3c_device_lcd; 48extern struct platform_device s3c_device_hsmmc1;
56extern struct platform_device s3c_device_wdt; 49extern struct platform_device s3c_device_hsmmc2;
50extern struct platform_device s3c_device_hsmmc3;
57extern struct platform_device s3c_device_i2c0; 51extern struct platform_device s3c_device_i2c0;
58extern struct platform_device s3c_device_i2c1; 52extern struct platform_device s3c_device_i2c1;
59extern struct platform_device s3c_device_i2c2; 53extern struct platform_device s3c_device_i2c2;
@@ -62,93 +56,90 @@ extern struct platform_device s3c_device_i2c4;
62extern struct platform_device s3c_device_i2c5; 56extern struct platform_device s3c_device_i2c5;
63extern struct platform_device s3c_device_i2c6; 57extern struct platform_device s3c_device_i2c6;
64extern struct platform_device s3c_device_i2c7; 58extern struct platform_device s3c_device_i2c7;
59extern struct platform_device s3c_device_iis;
60extern struct platform_device s3c_device_lcd;
61extern struct platform_device s3c_device_nand;
62extern struct platform_device s3c_device_ohci;
63extern struct platform_device s3c_device_onenand;
65extern struct platform_device s3c_device_rtc; 64extern struct platform_device s3c_device_rtc;
66extern struct platform_device s3c_device_adc;
67extern struct platform_device s3c_device_sdi; 65extern struct platform_device s3c_device_sdi;
68extern struct platform_device s3c_device_iis;
69extern struct platform_device s3c_device_hwmon;
70extern struct platform_device s3c_device_hsmmc0;
71extern struct platform_device s3c_device_hsmmc1;
72extern struct platform_device s3c_device_hsmmc2;
73extern struct platform_device s3c_device_hsmmc3;
74extern struct platform_device s3c_device_cfcon;
75
76extern struct platform_device s3c_device_spi0; 66extern struct platform_device s3c_device_spi0;
77extern struct platform_device s3c_device_spi1; 67extern struct platform_device s3c_device_spi1;
78 68extern struct platform_device s3c_device_ts;
79extern struct platform_device s5pc100_device_spi0; 69extern struct platform_device s3c_device_timer[];
80extern struct platform_device s5pc100_device_spi1;
81extern struct platform_device s5pc100_device_spi2;
82extern struct platform_device s5pv210_device_spi0;
83extern struct platform_device s5pv210_device_spi1;
84extern struct platform_device s5p64x0_device_spi0;
85extern struct platform_device s5p64x0_device_spi1;
86
87extern struct platform_device s3c_device_hwmon;
88
89extern struct platform_device s3c_device_nand;
90extern struct platform_device s3c_device_onenand;
91extern struct platform_device s3c64xx_device_onenand1;
92extern struct platform_device s5p_device_onenand;
93
94extern struct platform_device s3c_device_usbgadget; 70extern struct platform_device s3c_device_usbgadget;
95extern struct platform_device s3c_device_usb_hsudc;
96extern struct platform_device s3c_device_usb_hsotg; 71extern struct platform_device s3c_device_usb_hsotg;
72extern struct platform_device s3c_device_usb_hsudc;
73extern struct platform_device s3c_device_wdt;
97 74
98extern struct platform_device s5pv210_device_ac97; 75extern struct platform_device s5p_device_ehci;
99extern struct platform_device s5pv210_device_pcm0; 76extern struct platform_device s5p_device_fimc0;
100extern struct platform_device s5pv210_device_pcm1; 77extern struct platform_device s5p_device_fimc1;
101extern struct platform_device s5pv210_device_pcm2; 78extern struct platform_device s5p_device_fimc2;
102extern struct platform_device s5pv210_device_iis0; 79extern struct platform_device s5p_device_fimc3;
103extern struct platform_device s5pv210_device_iis1; 80extern struct platform_device s5p_device_fimc_md;
104extern struct platform_device s5pv210_device_iis2; 81extern struct platform_device s5p_device_fimd0;
105extern struct platform_device s5pv210_device_spdif; 82extern struct platform_device s5p_device_hdmi;
106 83extern struct platform_device s5p_device_i2c_hdmiphy;
107extern struct platform_device exynos4_device_ac97; 84extern struct platform_device s5p_device_mfc;
108extern struct platform_device exynos4_device_pcm0; 85extern struct platform_device s5p_device_mfc_l;
109extern struct platform_device exynos4_device_pcm1; 86extern struct platform_device s5p_device_mfc_r;
110extern struct platform_device exynos4_device_pcm2; 87extern struct platform_device s5p_device_mipi_csis0;
111extern struct platform_device exynos4_device_i2s0; 88extern struct platform_device s5p_device_mipi_csis1;
112extern struct platform_device exynos4_device_i2s1; 89extern struct platform_device s5p_device_mixer;
113extern struct platform_device exynos4_device_i2s2; 90extern struct platform_device s5p_device_onenand;
114extern struct platform_device exynos4_device_spdif; 91extern struct platform_device s5p_device_sdo;
115extern struct platform_device exynos4_device_pd[];
116extern struct platform_device exynos4_device_ahci;
117extern struct platform_device exynos4_device_dwmci;
118 92
119extern struct platform_device s5p6440_device_pcm;
120extern struct platform_device s5p6440_device_iis; 93extern struct platform_device s5p6440_device_iis;
94extern struct platform_device s5p6440_device_pcm;
121 95
122extern struct platform_device s5p6450_device_iis0; 96extern struct platform_device s5p6450_device_iis0;
123extern struct platform_device s5p6450_device_iis1; 97extern struct platform_device s5p6450_device_iis1;
124extern struct platform_device s5p6450_device_iis2; 98extern struct platform_device s5p6450_device_iis2;
125extern struct platform_device s5p6450_device_pcm0; 99extern struct platform_device s5p6450_device_pcm0;
126 100
101extern struct platform_device s5p64x0_device_spi0;
102extern struct platform_device s5p64x0_device_spi1;
103
127extern struct platform_device s5pc100_device_ac97; 104extern struct platform_device s5pc100_device_ac97;
128extern struct platform_device s5pc100_device_pcm0;
129extern struct platform_device s5pc100_device_pcm1;
130extern struct platform_device s5pc100_device_iis0; 105extern struct platform_device s5pc100_device_iis0;
131extern struct platform_device s5pc100_device_iis1; 106extern struct platform_device s5pc100_device_iis1;
132extern struct platform_device s5pc100_device_iis2; 107extern struct platform_device s5pc100_device_iis2;
108extern struct platform_device s5pc100_device_pcm0;
109extern struct platform_device s5pc100_device_pcm1;
133extern struct platform_device s5pc100_device_spdif; 110extern struct platform_device s5pc100_device_spdif;
111extern struct platform_device s5pc100_device_spi0;
112extern struct platform_device s5pc100_device_spi1;
113extern struct platform_device s5pc100_device_spi2;
134 114
135extern struct platform_device samsung_device_keypad; 115extern struct platform_device s5pv210_device_ac97;
136 116extern struct platform_device s5pv210_device_iis0;
137extern struct platform_device s5p_device_fimc0; 117extern struct platform_device s5pv210_device_iis1;
138extern struct platform_device s5p_device_fimc1; 118extern struct platform_device s5pv210_device_iis2;
139extern struct platform_device s5p_device_fimc2; 119extern struct platform_device s5pv210_device_pcm0;
140extern struct platform_device s5p_device_fimc3; 120extern struct platform_device s5pv210_device_pcm1;
141 121extern struct platform_device s5pv210_device_pcm2;
142extern struct platform_device s5p_device_mfc; 122extern struct platform_device s5pv210_device_spdif;
143extern struct platform_device s5p_device_mfc_l; 123extern struct platform_device s5pv210_device_spi0;
144extern struct platform_device s5p_device_mfc_r; 124extern struct platform_device s5pv210_device_spi1;
145extern struct platform_device s5p_device_mipi_csis0;
146extern struct platform_device s5p_device_mipi_csis1;
147
148extern struct platform_device s5p_device_ehci;
149 125
126extern struct platform_device exynos4_device_ac97;
127extern struct platform_device exynos4_device_ahci;
128extern struct platform_device exynos4_device_dwmci;
129extern struct platform_device exynos4_device_i2s0;
130extern struct platform_device exynos4_device_i2s1;
131extern struct platform_device exynos4_device_i2s2;
132extern struct platform_device exynos4_device_pcm0;
133extern struct platform_device exynos4_device_pcm1;
134extern struct platform_device exynos4_device_pcm2;
135extern struct platform_device exynos4_device_pd[];
136extern struct platform_device exynos4_device_spdif;
150extern struct platform_device exynos4_device_sysmmu; 137extern struct platform_device exynos4_device_sysmmu;
151 138
139extern struct platform_device samsung_asoc_dma;
140extern struct platform_device samsung_asoc_idma;
141extern struct platform_device samsung_device_keypad;
142
152/* s3c2440 specific devices */ 143/* s3c2440 specific devices */
153 144
154#ifdef CONFIG_CPU_S3C2440 145#ifdef CONFIG_CPU_S3C2440
diff --git a/arch/arm/plat-samsung/include/plat/ehci.h b/arch/arm/plat-samsung/include/plat/ehci.h
new file mode 100644
index 00000000000..5f28cae1858
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/ehci.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __PLAT_SAMSUNG_EHCI_H
12#define __PLAT_SAMSUNG_EHCI_H __FILE__
13
14struct s5p_ehci_platdata {
15 int (*phy_init)(struct platform_device *pdev, int type);
16 int (*phy_exit)(struct platform_device *pdev, int type);
17};
18
19extern void s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd);
20
21#endif /* __PLAT_SAMSUNG_EHCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/exynos4.h b/arch/arm/plat-samsung/include/plat/exynos4.h
new file mode 100644
index 00000000000..20d73bf7753
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/exynos4.h
@@ -0,0 +1,35 @@
1/* linux/arch/arm/plat-samsung/include/plat/exynos4.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for exynos4 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for EXYNOS4 related SoCs */
14
15extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void exynos4_register_clocks(void);
17extern void exynos4210_register_clocks(void);
18extern void exynos4212_register_clocks(void);
19extern void exynos4_setup_clocks(void);
20
21#ifdef CONFIG_ARCH_EXYNOS4
22extern int exynos4_init(void);
23extern void exynos4_init_irq(void);
24extern void exynos4_map_io(void);
25extern void exynos4_init_clocks(int xtal);
26extern struct sys_timer exynos4_timer;
27
28#define exynos4_init_uarts exynos4_common_init_uarts
29
30#else
31#define exynos4_init_clocks NULL
32#define exynos4_init_uarts NULL
33#define exynos4_map_io NULL
34#define exynos4_init NULL
35#endif
diff --git a/arch/arm/plat-samsung/include/plat/fb-s3c2410.h b/arch/arm/plat-samsung/include/plat/fb-s3c2410.h
new file mode 100644
index 00000000000..4e5d9588b5b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/fb-s3c2410.h
@@ -0,0 +1,72 @@
1/* arch/arm/plat-samsung/include/plat/fb-s3c2410.h
2 *
3 * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
4 *
5 * Inspired by pxafb.h
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_PLAT_FB_S3C2410_H
13#define __ASM_PLAT_FB_S3C2410_H __FILE__
14
15struct s3c2410fb_hw {
16 unsigned long lcdcon1;
17 unsigned long lcdcon2;
18 unsigned long lcdcon3;
19 unsigned long lcdcon4;
20 unsigned long lcdcon5;
21};
22
23/* LCD description */
24struct s3c2410fb_display {
25 /* LCD type */
26 unsigned type;
27
28 /* Screen size */
29 unsigned short width;
30 unsigned short height;
31
32 /* Screen info */
33 unsigned short xres;
34 unsigned short yres;
35 unsigned short bpp;
36
37 unsigned pixclock; /* pixclock in picoseconds */
38 unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */
39 unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
40 unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */
41 unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */
42 unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */
43 unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */
44
45 /* lcd configuration registers */
46 unsigned long lcdcon5;
47};
48
49struct s3c2410fb_mach_info {
50
51 struct s3c2410fb_display *displays; /* attached diplays info */
52 unsigned num_displays; /* number of defined displays */
53 unsigned default_display;
54
55 /* GPIOs */
56
57 unsigned long gpcup;
58 unsigned long gpcup_mask;
59 unsigned long gpccon;
60 unsigned long gpccon_mask;
61 unsigned long gpdup;
62 unsigned long gpdup_mask;
63 unsigned long gpdcon;
64 unsigned long gpdcon_mask;
65
66 /* lpc3600 control register */
67 unsigned long lpcsel;
68};
69
70extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
71
72#endif /* __ASM_PLAT_FB_S3C2410_H */
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 01f10e4d00c..0fedf47fa50 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -109,4 +109,11 @@ extern void s5pv210_fb_gpio_setup_24bpp(void);
109 */ 109 */
110extern void exynos4_fimd0_gpio_setup_24bpp(void); 110extern void exynos4_fimd0_gpio_setup_24bpp(void);
111 111
112/**
113 * s5p64x0_fb_gpio_setup_24bpp() - S5P6440/S5P6450 setup function for 24bpp LCD
114 *
115 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
116 */
117extern void s5p64x0_fb_gpio_setup_24bpp(void);
118
112#endif /* __PLAT_S3C_FB_H */ 119#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/fiq.h b/arch/arm/plat-samsung/include/plat/fiq.h
new file mode 100644
index 00000000000..535d06a3562
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/fiq.h
@@ -0,0 +1,13 @@
1/* linux/arch/arm/plat-samsung/include/plat/fiq.h
2 *
3 * Copyright (c) 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU FIQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13extern int s3c24xx_set_fiq(unsigned int irq, bool on);
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index 9a4e53d5296..a181d7ce81c 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -1,11 +1,11 @@
1/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h 1/* linux/arch/arm/plat-samsung/include/plat/gpio-cfg-helper.h
2 * 2 *
3 * Copyright 2008 Openmoko, Inc. 3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics 4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/ 5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk> 6 * Ben Dooks <ben@simtec.co.uk>
7 * 7 *
8 * S3C Platform - GPIO pin configuration helper definitions 8 * Samsung Platform - GPIO pin configuration helper definitions
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
@@ -24,120 +24,30 @@
24 * by disabling interrupts. 24 * by disabling interrupts.
25*/ 25*/
26 26
27static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip, 27static inline int samsung_gpio_do_setcfg(struct samsung_gpio_chip *chip,
28 unsigned int off, unsigned int config) 28 unsigned int off, unsigned int config)
29{ 29{
30 return (chip->config->set_config)(chip, off, config); 30 return (chip->config->set_config)(chip, off, config);
31} 31}
32 32
33static inline unsigned s3c_gpio_do_getcfg(struct s3c_gpio_chip *chip, 33static inline unsigned samsung_gpio_do_getcfg(struct samsung_gpio_chip *chip,
34 unsigned int off) 34 unsigned int off)
35{ 35{
36 return (chip->config->get_config)(chip, off); 36 return (chip->config->get_config)(chip, off);
37} 37}
38 38
39static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip, 39static inline int samsung_gpio_do_setpull(struct samsung_gpio_chip *chip,
40 unsigned int off, s3c_gpio_pull_t pull) 40 unsigned int off, samsung_gpio_pull_t pull)
41{ 41{
42 return (chip->config->set_pull)(chip, off, pull); 42 return (chip->config->set_pull)(chip, off, pull);
43} 43}
44 44
45static inline s3c_gpio_pull_t s3c_gpio_do_getpull(struct s3c_gpio_chip *chip, 45static inline samsung_gpio_pull_t samsung_gpio_do_getpull(struct samsung_gpio_chip *chip,
46 unsigned int off) 46 unsigned int off)
47{ 47{
48 return chip->config->get_pull(chip, off); 48 return chip->config->get_pull(chip, off);
49} 49}
50 50
51/**
52 * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
53 * @chip: The gpio chip that is being configured.
54 * @off: The offset for the GPIO being configured.
55 * @cfg: The configuration value to set.
56 *
57 * This helper deal with the GPIO cases where the control register
58 * has two bits of configuration per gpio, which have the following
59 * functions:
60 * 00 = input
61 * 01 = output
62 * 1x = special function
63*/
64extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
65 unsigned int off, unsigned int cfg);
66
67/**
68 * s3c_gpio_getcfg_s3c24xx - S3C24XX style GPIO configuration read.
69 * @chip: The gpio chip that is being configured.
70 * @off: The offset for the GPIO being configured.
71 *
72 * The reverse of s3c_gpio_setcfg_s3c24xx(). Will return a value whicg
73 * could be directly passed back to s3c_gpio_setcfg_s3c24xx(), from the
74 * S3C_GPIO_SPECIAL() macro.
75 */
76unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
77 unsigned int off);
78
79/**
80 * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
81 * @chip: The gpio chip that is being configured.
82 * @off: The offset for the GPIO being configured.
83 * @cfg: The configuration value to set.
84 *
85 * This helper deal with the GPIO cases where the control register
86 * has one bit of configuration for the gpio, where setting the bit
87 * means the pin is in special function mode and unset means output.
88*/
89extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
90 unsigned int off, unsigned int cfg);
91
92
93/**
94 * s3c_gpio_getcfg_s3c24xx_a - S3C24XX style GPIO configuration read (Bank A)
95 * @chip: The gpio chip that is being configured.
96 * @off: The offset for the GPIO being configured.
97 *
98 * The reverse of s3c_gpio_setcfg_s3c24xx_a() turning an GPIO into a usable
99 * GPIO configuration value.
100 *
101 * @sa s3c_gpio_getcfg_s3c24xx
102 * @sa s3c_gpio_getcfg_s3c64xx_4bit
103 */
104extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
105 unsigned int off);
106
107/**
108 * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
109 * @chip: The gpio chip that is being configured.
110 * @off: The offset for the GPIO being configured.
111 * @cfg: The configuration value to set.
112 *
113 * This helper deal with the GPIO cases where the control register has 4 bits
114 * of control per GPIO, generally in the form of:
115 * 0000 = Input
116 * 0001 = Output
117 * others = Special functions (dependent on bank)
118 *
119 * Note, since the code to deal with the case where there are two control
120 * registers instead of one, we do not have a separate set of functions for
121 * each case.
122*/
123extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
124 unsigned int off, unsigned int cfg);
125
126
127/**
128 * s3c_gpio_getcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config read.
129 * @chip: The gpio chip that is being configured.
130 * @off: The offset for the GPIO being configured.
131 *
132 * The reverse of s3c_gpio_setcfg_s3c64xx_4bit(), turning a gpio configuration
133 * register setting into a value the software can use, such as could be passed
134 * to s3c_gpio_setcfg_s3c64xx_4bit().
135 *
136 * @sa s3c_gpio_getcfg_s3c24xx
137 */
138extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
139 unsigned int off);
140
141/* Pull-{up,down} resistor controls. 51/* Pull-{up,down} resistor controls.
142 * 52 *
143 * S3C2410,S3C2440 = Pull-UP, 53 * S3C2410,S3C2440 = Pull-UP,
@@ -147,7 +57,7 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
147 */ 57 */
148 58
149/** 59/**
150 * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none. 60 * s3c24xx_gpio_setpull_1up() - Pull configuration for choice of up or none.
151 * @chip: The gpio chip that is being configured. 61 * @chip: The gpio chip that is being configured.
152 * @off: The offset for the GPIO being configured. 62 * @off: The offset for the GPIO being configured.
153 * @param: pull: The pull mode being requested. 63 * @param: pull: The pull mode being requested.
@@ -155,11 +65,11 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
155 * This is a helper function for the case where we have GPIOs with one 65 * This is a helper function for the case where we have GPIOs with one
156 * bit configuring the presence of a pull-up resistor. 66 * bit configuring the presence of a pull-up resistor.
157 */ 67 */
158extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, 68extern int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
159 unsigned int off, s3c_gpio_pull_t pull); 69 unsigned int off, samsung_gpio_pull_t pull);
160 70
161/** 71/**
162 * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none 72 * s3c24xx_gpio_setpull_1down() - Pull configuration for choice of down or none
163 * @chip: The gpio chip that is being configured 73 * @chip: The gpio chip that is being configured
164 * @off: The offset for the GPIO being configured 74 * @off: The offset for the GPIO being configured
165 * @param: pull: The pull mode being requested 75 * @param: pull: The pull mode being requested
@@ -167,11 +77,13 @@ extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
167 * This is a helper function for the case where we have GPIOs with one 77 * This is a helper function for the case where we have GPIOs with one
168 * bit configuring the presence of a pull-down resistor. 78 * bit configuring the presence of a pull-down resistor.
169 */ 79 */
170extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, 80extern int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
171 unsigned int off, s3c_gpio_pull_t pull); 81 unsigned int off, samsung_gpio_pull_t pull);
172 82
173/** 83/**
174 * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none 84 * samsung_gpio_setpull_upown() - Pull configuration for choice of up,
85 * down or none
86 *
175 * @chip: The gpio chip that is being configured. 87 * @chip: The gpio chip that is being configured.
176 * @off: The offset for the GPIO being configured. 88 * @off: The offset for the GPIO being configured.
177 * @param: pull: The pull mode being requested. 89 * @param: pull: The pull mode being requested.
@@ -183,45 +95,46 @@ extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
183 * 01 = Pull-up resistor connected 95 * 01 = Pull-up resistor connected
184 * 10 = Pull-down resistor connected 96 * 10 = Pull-down resistor connected
185 */ 97 */
186extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, 98extern int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
187 unsigned int off, s3c_gpio_pull_t pull); 99 unsigned int off, samsung_gpio_pull_t pull);
188
189 100
190/** 101/**
191 * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none 102 * samsung_gpio_getpull_updown() - Get configuration for choice of up,
103 * down or none
104 *
192 * @chip: The gpio chip that the GPIO pin belongs to 105 * @chip: The gpio chip that the GPIO pin belongs to
193 * @off: The offset to the pin to get the configuration of. 106 * @off: The offset to the pin to get the configuration of.
194 * 107 *
195 * This helper function reads the state of the pull-{up,down} resistor for the 108 * This helper function reads the state of the pull-{up,down} resistor
196 * given GPIO in the same case as s3c_gpio_setpull_upown. 109 * for the given GPIO in the same case as samsung_gpio_setpull_upown.
197*/ 110*/
198extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, 111extern samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
199 unsigned int off); 112 unsigned int off);
200 113
201/** 114/**
202 * s3c_gpio_getpull_1up() - Get configuration for choice of up or none 115 * s3c24xx_gpio_getpull_1up() - Get configuration for choice of up or none
203 * @chip: The gpio chip that the GPIO pin belongs to 116 * @chip: The gpio chip that the GPIO pin belongs to
204 * @off: The offset to the pin to get the configuration of. 117 * @off: The offset to the pin to get the configuration of.
205 * 118 *
206 * This helper function reads the state of the pull-up resistor for the 119 * This helper function reads the state of the pull-up resistor for the
207 * given GPIO in the same case as s3c_gpio_setpull_1up. 120 * given GPIO in the same case as s3c24xx_gpio_setpull_1up.
208*/ 121*/
209extern s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip, 122extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
210 unsigned int off); 123 unsigned int off);
211 124
212/** 125/**
213 * s3c_gpio_getpull_1down() - Get configuration for choice of down or none 126 * s3c24xx_gpio_getpull_1down() - Get configuration for choice of down or none
214 * @chip: The gpio chip that the GPIO pin belongs to 127 * @chip: The gpio chip that the GPIO pin belongs to
215 * @off: The offset to the pin to get the configuration of. 128 * @off: The offset to the pin to get the configuration of.
216 * 129 *
217 * This helper function reads the state of the pull-down resistor for the 130 * This helper function reads the state of the pull-down resistor for the
218 * given GPIO in the same case as s3c_gpio_setpull_1down. 131 * given GPIO in the same case as s3c24xx_gpio_setpull_1down.
219*/ 132*/
220extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip, 133extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
221 unsigned int off); 134 unsigned int off);
222 135
223/** 136/**
224 * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443. 137 * s3c2443_gpio_setpull() - Pull configuration for s3c2443.
225 * @chip: The gpio chip that is being configured. 138 * @chip: The gpio chip that is being configured.
226 * @off: The offset for the GPIO being configured. 139 * @off: The offset for the GPIO being configured.
227 * @param: pull: The pull mode being requested. 140 * @param: pull: The pull mode being requested.
@@ -233,19 +146,18 @@ extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip,
233 * 10 = Pull-down resistor connected 146 * 10 = Pull-down resistor connected
234 * x1 = No pull up resistor 147 * x1 = No pull up resistor
235 */ 148 */
236extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, 149extern int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
237 unsigned int off, s3c_gpio_pull_t pull); 150 unsigned int off, samsung_gpio_pull_t pull);
238 151
239/** 152/**
240 * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors 153 * s3c2443_gpio_getpull() - Get configuration for s3c2443 pull resistors
241 * @chip: The gpio chip that the GPIO pin belongs to. 154 * @chip: The gpio chip that the GPIO pin belongs to.
242 * @off: The offset to the pin to get the configuration of. 155 * @off: The offset to the pin to get the configuration of.
243 * 156 *
244 * This helper function reads the state of the pull-{up,down} resistor for the 157 * This helper function reads the state of the pull-{up,down} resistor for the
245 * given GPIO in the same case as s3c_gpio_setpull_upown. 158 * given GPIO in the same case as samsung_gpio_setpull_upown.
246*/ 159*/
247extern s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip, 160extern samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
248 unsigned int off); 161 unsigned int off);
249 162
250#endif /* __PLAT_GPIO_CFG_HELPERS_H */ 163#endif /* __PLAT_GPIO_CFG_HELPERS_H */
251
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 1762dcb4cb9..d48245bb02b 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -24,14 +24,14 @@
24#ifndef __PLAT_GPIO_CFG_H 24#ifndef __PLAT_GPIO_CFG_H
25#define __PLAT_GPIO_CFG_H __FILE__ 25#define __PLAT_GPIO_CFG_H __FILE__
26 26
27typedef unsigned int __bitwise__ s3c_gpio_pull_t; 27typedef unsigned int __bitwise__ samsung_gpio_pull_t;
28typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; 28typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
29 29
30/* forward declaration if gpio-core.h hasn't been included */ 30/* forward declaration if gpio-core.h hasn't been included */
31struct s3c_gpio_chip; 31struct samsung_gpio_chip;
32 32
33/** 33/**
34 * struct s3c_gpio_cfg GPIO configuration 34 * struct samsung_gpio_cfg GPIO configuration
35 * @cfg_eint: Configuration setting when used for external interrupt source 35 * @cfg_eint: Configuration setting when used for external interrupt source
36 * @get_pull: Read the current pull configuration for the GPIO 36 * @get_pull: Read the current pull configuration for the GPIO
37 * @set_pull: Set the current pull configuraiton for the GPIO 37 * @set_pull: Set the current pull configuraiton for the GPIO
@@ -44,20 +44,20 @@ struct s3c_gpio_chip;
44 * per-bank configuration information that other systems such as the 44 * per-bank configuration information that other systems such as the
45 * external interrupt code will need. 45 * external interrupt code will need.
46 * 46 *
47 * @sa s3c_gpio_cfgpin 47 * @sa samsung_gpio_cfgpin
48 * @sa s3c_gpio_getcfg 48 * @sa s3c_gpio_getcfg
49 * @sa s3c_gpio_setpull 49 * @sa s3c_gpio_setpull
50 * @sa s3c_gpio_getpull 50 * @sa s3c_gpio_getpull
51 */ 51 */
52struct s3c_gpio_cfg { 52struct samsung_gpio_cfg {
53 unsigned int cfg_eint; 53 unsigned int cfg_eint;
54 54
55 s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs); 55 samsung_gpio_pull_t (*get_pull)(struct samsung_gpio_chip *chip, unsigned offs);
56 int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs, 56 int (*set_pull)(struct samsung_gpio_chip *chip, unsigned offs,
57 s3c_gpio_pull_t pull); 57 samsung_gpio_pull_t pull);
58 58
59 unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs); 59 unsigned (*get_config)(struct samsung_gpio_chip *chip, unsigned offs);
60 int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs, 60 int (*set_config)(struct samsung_gpio_chip *chip, unsigned offs,
61 unsigned config); 61 unsigned config);
62}; 62};
63 63
@@ -69,7 +69,7 @@ struct s3c_gpio_cfg {
69#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1)) 69#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1))
70#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x)) 70#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x))
71 71
72#define s3c_gpio_is_cfg_special(_cfg) \ 72#define samsung_gpio_is_cfg_special(_cfg) \
73 (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK) 73 (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
74 74
75/** 75/**
@@ -128,9 +128,9 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
128 * up or down settings, and it may be dependent on the chip that is being 128 * up or down settings, and it may be dependent on the chip that is being
129 * used to whether the particular mode is available. 129 * used to whether the particular mode is available.
130 */ 130 */
131#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) 131#define S3C_GPIO_PULL_NONE ((__force samsung_gpio_pull_t)0x00)
132#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01) 132#define S3C_GPIO_PULL_DOWN ((__force samsung_gpio_pull_t)0x01)
133#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02) 133#define S3C_GPIO_PULL_UP ((__force samsung_gpio_pull_t)0x02)
134 134
135/** 135/**
136 * s3c_gpio_setpull() - set the state of a gpio pin pull resistor 136 * s3c_gpio_setpull() - set the state of a gpio pin pull resistor
@@ -143,7 +143,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
143 * 143 *
144 * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP. 144 * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP.
145*/ 145*/
146extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); 146extern int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull);
147 147
148/** 148/**
149 * s3c_gpio_getpull() - get the pull resistor state of a gpio pin 149 * s3c_gpio_getpull() - get the pull resistor state of a gpio pin
@@ -151,7 +151,7 @@ extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
151 * 151 *
152 * Read the pull resistor value for the specified pin. 152 * Read the pull resistor value for the specified pin.
153*/ 153*/
154extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); 154extern samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
155 155
156/* configure `all` aspects of an gpio */ 156/* configure `all` aspects of an gpio */
157 157
@@ -170,7 +170,7 @@ extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
170 * @sa s3c_gpio_cfgpin_range 170 * @sa s3c_gpio_cfgpin_range
171 */ 171 */
172extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, 172extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
173 unsigned int cfg, s3c_gpio_pull_t pull); 173 unsigned int cfg, samsung_gpio_pull_t pull);
174 174
175static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size, 175static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size,
176 unsigned int cfg) 176 unsigned int cfg)
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index 8cad4cf19c3..1fe6917f6a2 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -25,22 +25,22 @@
25 * specific code. 25 * specific code.
26*/ 26*/
27 27
28struct s3c_gpio_chip; 28struct samsung_gpio_chip;
29 29
30/** 30/**
31 * struct s3c_gpio_pm - power management (suspend/resume) information 31 * struct samsung_gpio_pm - power management (suspend/resume) information
32 * @save: Routine to save the state of the GPIO block 32 * @save: Routine to save the state of the GPIO block
33 * @resume: Routine to resume the GPIO block. 33 * @resume: Routine to resume the GPIO block.
34 */ 34 */
35struct s3c_gpio_pm { 35struct samsung_gpio_pm {
36 void (*save)(struct s3c_gpio_chip *chip); 36 void (*save)(struct samsung_gpio_chip *chip);
37 void (*resume)(struct s3c_gpio_chip *chip); 37 void (*resume)(struct samsung_gpio_chip *chip);
38}; 38};
39 39
40struct s3c_gpio_cfg; 40struct samsung_gpio_cfg;
41 41
42/** 42/**
43 * struct s3c_gpio_chip - wrapper for specific implementation of gpio 43 * struct samsung_gpio_chip - wrapper for specific implementation of gpio
44 * @chip: The chip structure to be exported via gpiolib. 44 * @chip: The chip structure to be exported via gpiolib.
45 * @base: The base pointer to the gpio configuration registers. 45 * @base: The base pointer to the gpio configuration registers.
46 * @group: The group register number for gpio interrupt support. 46 * @group: The group register number for gpio interrupt support.
@@ -60,10 +60,10 @@ struct s3c_gpio_cfg;
60 * CPU cores trying to get one lock for different GPIO banks, where each 60 * CPU cores trying to get one lock for different GPIO banks, where each
61 * bank of GPIO has its own register space and configuration registers. 61 * bank of GPIO has its own register space and configuration registers.
62 */ 62 */
63struct s3c_gpio_chip { 63struct samsung_gpio_chip {
64 struct gpio_chip chip; 64 struct gpio_chip chip;
65 struct s3c_gpio_cfg *config; 65 struct samsung_gpio_cfg *config;
66 struct s3c_gpio_pm *pm; 66 struct samsung_gpio_pm *pm;
67 void __iomem *base; 67 void __iomem *base;
68 int irq_base; 68 int irq_base;
69 int group; 69 int group;
@@ -73,58 +73,11 @@ struct s3c_gpio_chip {
73#endif 73#endif
74}; 74};
75 75
76static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) 76static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc)
77{ 77{
78 return container_of(gpc, struct s3c_gpio_chip, chip); 78 return container_of(gpc, struct samsung_gpio_chip, chip);
79} 79}
80 80
81/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
82 * @chip: The chip to register
83 *
84 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
85 * information and makes the necessary alterations for the platform and
86 * notes the information for use with the configuration systems and any
87 * other parts of the system.
88 */
89extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
90
91/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
92 * for use with the configuration calls, and other parts of the s3c gpiolib
93 * support code.
94 *
95 * Not all s3c support code will need this, as some configurations of cpu
96 * may only support one or two different configuration options and have an
97 * easy gpio to s3c_gpio_chip mapping function. If this is the case, then
98 * the machine support file should provide its own s3c_gpiolib_getchip()
99 * and any other necessary functions.
100 */
101
102/**
103 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
104 * @chip: The gpio chip that is being configured.
105 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
106 *
107 * This helper deal with the GPIO cases where the control register has 4 bits
108 * of control per GPIO, generally in the form of:
109 * 0000 = Input
110 * 0001 = Output
111 * others = Special functions (dependent on bank)
112 *
113 * Note, since the code to deal with the case where there are two control
114 * registers instead of one, we do not have a separate set of function
115 * (samsung_gpiolib_add_4bit2_chips)for each case.
116 */
117extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
118 int nr_chips);
119extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
120 int nr_chips);
121extern void samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
122 int nr_chips);
123
124extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
125extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
126
127
128/** 81/**
129 * samsung_gpiolib_to_irq - convert gpio pin to irq number 82 * samsung_gpiolib_to_irq - convert gpio pin to irq number
130 * @chip: The gpio chip that the pin belongs to. 83 * @chip: The gpio chip that the pin belongs to.
@@ -136,36 +89,36 @@ extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
136extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset); 89extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset);
137 90
138/* exported for core SoC support to change */ 91/* exported for core SoC support to change */
139extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default; 92extern struct samsung_gpio_cfg s3c24xx_gpiocfg_default;
140 93
141#ifdef CONFIG_S3C_GPIO_TRACK 94#ifdef CONFIG_S3C_GPIO_TRACK
142extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; 95extern struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
143 96
144static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) 97static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int chip)
145{ 98{
146 return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; 99 return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
147} 100}
148#else 101#else
149/* machine specific code should provide s3c_gpiolib_getchip */ 102/* machine specific code should provide samsung_gpiolib_getchip */
150 103
151#include <mach/gpio-track.h> 104#include <mach/gpio-track.h>
152 105
153static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } 106static inline void s3c_gpiolib_track(struct samsung_gpio_chip *chip) { }
154#endif 107#endif
155 108
156#ifdef CONFIG_PM 109#ifdef CONFIG_PM
157extern struct s3c_gpio_pm s3c_gpio_pm_1bit; 110extern struct samsung_gpio_pm samsung_gpio_pm_1bit;
158extern struct s3c_gpio_pm s3c_gpio_pm_2bit; 111extern struct samsung_gpio_pm samsung_gpio_pm_2bit;
159extern struct s3c_gpio_pm s3c_gpio_pm_4bit; 112extern struct samsung_gpio_pm samsung_gpio_pm_4bit;
160#define __gpio_pm(x) x 113#define __gpio_pm(x) x
161#else 114#else
162#define s3c_gpio_pm_1bit NULL 115#define samsung_gpio_pm_1bit NULL
163#define s3c_gpio_pm_2bit NULL 116#define samsung_gpio_pm_2bit NULL
164#define s3c_gpio_pm_4bit NULL 117#define samsung_gpio_pm_4bit NULL
165#define __gpio_pm(x) NULL 118#define __gpio_pm(x) NULL
166 119
167#endif /* CONFIG_PM */ 120#endif /* CONFIG_PM */
168 121
169/* locking wrappers to deal with multiple access to the same gpio bank */ 122/* locking wrappers to deal with multiple access to the same gpio bank */
170#define s3c_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) 123#define samsung_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl)
171#define s3c_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) 124#define samsung_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl)
diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h
new file mode 100644
index 00000000000..bab13920176
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/gpio-fns.h
@@ -0,0 +1,98 @@
1/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
2 *
3 * Copyright (c) 2003-2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - hardware
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __MACH_GPIO_FNS_H
14#define __MACH_GPIO_FNS_H __FILE__
15
16/* These functions are in the to-be-removed category and it is strongly
17 * encouraged not to use these in new code. They will be marked deprecated
18 * very soon.
19 *
20 * Most of the functionality can be either replaced by the gpiocfg calls
21 * for the s3c platform or by the generic GPIOlib API.
22 *
23 * As of 2.6.35-rc, these will be removed, with the few drivers using them
24 * either replaced or given a wrapper until the calls can be removed.
25*/
26
27#include <plat/gpio-cfg.h>
28
29static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
30{
31 /* 1:1 mapping between cfgpin and setcfg calls at the moment */
32 s3c_gpio_cfgpin(pin, cfg);
33}
34
35/* external functions for GPIO support
36 *
37 * These allow various different clients to access the same GPIO
38 * registers without conflicting. If your driver only owns the entire
39 * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
40*/
41
42extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
43
44/* s3c2410_gpio_getirq
45 *
46 * turn the given pin number into the corresponding IRQ number
47 *
48 * returns:
49 * < 0 = no interrupt for this pin
50 * >=0 = interrupt number for the pin
51*/
52
53extern int s3c2410_gpio_getirq(unsigned int pin);
54
55/* s3c2410_gpio_irqfilter
56 *
57 * set the irq filtering on the given pin
58 *
59 * on = 0 => disable filtering
60 * 1 => enable filtering
61 *
62 * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
63 * width of filter (0 through 63)
64 *
65 *
66*/
67
68extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
69 unsigned int config);
70
71/* s3c2410_gpio_pullup
72 *
73 * This call should be replaced with s3c_gpio_setpull().
74 *
75 * As a note, there is currently no distinction between pull-up and pull-down
76 * in the s3c24xx series devices with only an on/off configuration.
77 */
78
79/* s3c2410_gpio_pullup
80 *
81 * configure the pull-up control on the given pin
82 *
83 * to = 1 => disable the pull-up
84 * 0 => enable the pull-up
85 *
86 * eg;
87 *
88 * s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
89 * s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
90*/
91
92extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
93
94extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
95
96extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
97
98#endif /* __MACH_GPIO_FNS_H */
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h
index 56b0059439e..51d52e767a1 100644
--- a/arch/arm/plat-samsung/include/plat/iic.h
+++ b/arch/arm/plat-samsung/include/plat/iic.h
@@ -60,6 +60,7 @@ extern void s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *i2c);
60extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c); 60extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c);
61extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c); 61extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c);
62extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c); 62extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c);
63extern void s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *i2c);
63 64
64/* defined by architecture to configure gpio */ 65/* defined by architecture to configure gpio */
65extern void s3c_i2c0_cfg_gpio(struct platform_device *dev); 66extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
diff --git a/arch/arm/plat-samsung/include/plat/irq.h b/arch/arm/plat-samsung/include/plat/irq.h
new file mode 100644
index 00000000000..e21a89bc26c
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/irq.h
@@ -0,0 +1,116 @@
1/* linux/arch/arm/plat-samsung/include/plat/irq.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU IRQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14
15#include <mach/hardware.h>
16#include <mach/regs-irq.h>
17#include <mach/regs-gpio.h>
18
19#define irqdbf(x...)
20#define irqdbf2(x...)
21
22#define EXTINT_OFF (IRQ_EINT4 - 4)
23
24/* these are exported for arch/arm/mach-* usage */
25extern struct irq_chip s3c_irq_level_chip;
26extern struct irq_chip s3c_irq_chip;
27
28static inline void s3c_irqsub_mask(unsigned int irqno,
29 unsigned int parentbit,
30 int subcheck)
31{
32 unsigned long mask;
33 unsigned long submask;
34
35 submask = __raw_readl(S3C2410_INTSUBMSK);
36 mask = __raw_readl(S3C2410_INTMSK);
37
38 submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
39
40 /* check to see if we need to mask the parent IRQ */
41
42 if ((submask & subcheck) == subcheck)
43 __raw_writel(mask | parentbit, S3C2410_INTMSK);
44
45 /* write back masks */
46 __raw_writel(submask, S3C2410_INTSUBMSK);
47
48}
49
50static inline void s3c_irqsub_unmask(unsigned int irqno,
51 unsigned int parentbit)
52{
53 unsigned long mask;
54 unsigned long submask;
55
56 submask = __raw_readl(S3C2410_INTSUBMSK);
57 mask = __raw_readl(S3C2410_INTMSK);
58
59 submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
60 mask &= ~parentbit;
61
62 /* write back masks */
63 __raw_writel(submask, S3C2410_INTSUBMSK);
64 __raw_writel(mask, S3C2410_INTMSK);
65}
66
67
68static inline void s3c_irqsub_maskack(unsigned int irqno,
69 unsigned int parentmask,
70 unsigned int group)
71{
72 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
73
74 s3c_irqsub_mask(irqno, parentmask, group);
75
76 __raw_writel(bit, S3C2410_SUBSRCPND);
77
78 /* only ack parent if we've got all the irqs (seems we must
79 * ack, all and hope that the irq system retriggers ok when
80 * the interrupt goes off again)
81 */
82
83 if (1) {
84 __raw_writel(parentmask, S3C2410_SRCPND);
85 __raw_writel(parentmask, S3C2410_INTPND);
86 }
87}
88
89static inline void s3c_irqsub_ack(unsigned int irqno,
90 unsigned int parentmask,
91 unsigned int group)
92{
93 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
94
95 __raw_writel(bit, S3C2410_SUBSRCPND);
96
97 /* only ack parent if we've got all the irqs (seems we must
98 * ack, all and hope that the irq system retriggers ok when
99 * the interrupt goes off again)
100 */
101
102 if (1) {
103 __raw_writel(parentmask, S3C2410_SRCPND);
104 __raw_writel(parentmask, S3C2410_INTPND);
105 }
106}
107
108/* exported for use in arch/arm/mach-s3c2410 */
109
110#ifdef CONFIG_PM
111extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
112#else
113#define s3c_irq_wake NULL
114#endif
115
116extern int s3c_irqext_type(struct irq_data *d, unsigned int type);
diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h
new file mode 100644
index 00000000000..08d1a7ef97b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/irqs.h
@@ -0,0 +1,80 @@
1/* linux/arch/arm/plat-samsung/include/plat/irqs.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P Common IRQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_SAMSUNG_IRQS_H
14#define __PLAT_SAMSUNG_IRQS_H __FILE__
15
16/* we keep the first set of CPU IRQs out of the range of
17 * the ISA space, so that the PC104 has them to itself
18 * and we don't end up having to do horrible things to the
19 * standard ISA drivers....
20 *
21 * note, since we're using the VICs, our start must be a
22 * mulitple of 32 to allow the common code to work
23 */
24
25#define S5P_IRQ_OFFSET (32)
26
27#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET)
28
29#define S5P_VIC0_BASE S5P_IRQ(0)
30#define S5P_VIC1_BASE S5P_IRQ(32)
31#define S5P_VIC2_BASE S5P_IRQ(64)
32#define S5P_VIC3_BASE S5P_IRQ(96)
33
34#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32))
35
36#define IRQ_VIC0_BASE S5P_VIC0_BASE
37#define IRQ_VIC1_BASE S5P_VIC1_BASE
38#define IRQ_VIC2_BASE S5P_VIC2_BASE
39
40/* VIC based IRQs */
41
42#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
43#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
44#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
45#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
46
47#define S5P_TIMER_IRQ(x) (11 + (x))
48
49#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
50#define IRQ_TIMER1 S5P_TIMER_IRQ(1)
51#define IRQ_TIMER2 S5P_TIMER_IRQ(2)
52#define IRQ_TIMER3 S5P_TIMER_IRQ(3)
53#define IRQ_TIMER4 S5P_TIMER_IRQ(4)
54
55#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
56 : ((x) - 16 + S5P_EINT_BASE2))
57
58#define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \
59 ((irq) - S5P_EINT_BASE1) : \
60 ((irq) + 16 - S5P_EINT_BASE2))
61
62#define IRQ_EINT_BIT(x) EINT_OFFSET(x)
63
64/* Typically only a few gpio chips require gpio interrupt support.
65 To avoid memory waste irq descriptors are allocated only for
66 S5P_GPIOINT_GROUP_COUNT chips, each with total number of
67 S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
68 to any gpio chip with the s5p_register_gpio_interrupt() function */
69#define S5P_GPIOINT_GROUP_COUNT 4
70#define S5P_GPIOINT_GROUP_SIZE 8
71#define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
72
73/* IRQ types common for all s5p platforms */
74#define S5P_IRQ_TYPE_LEVEL_LOW (0x00)
75#define S5P_IRQ_TYPE_LEVEL_HIGH (0x01)
76#define S5P_IRQ_TYPE_EDGE_FALLING (0x02)
77#define S5P_IRQ_TYPE_EDGE_RISING (0x03)
78#define S5P_IRQ_TYPE_EDGE_BOTH (0x04)
79
80#endif /* __PLAT_SAMSUNG_IRQS_H */
diff --git a/arch/arm/plat-samsung/include/plat/mci.h b/arch/arm/plat-samsung/include/plat/mci.h
new file mode 100644
index 00000000000..c42d3171194
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/mci.h
@@ -0,0 +1,52 @@
1#ifndef _ARCH_MCI_H
2#define _ARCH_MCI_H
3
4/**
5 * struct s3c24xx_mci_pdata - sd/mmc controller platform data
6 * @no_wprotect: Set this to indicate there is no write-protect switch.
7 * @no_detect: Set this if there is no detect switch.
8 * @wprotect_invert: Invert the default sense of the write protect switch.
9 * @detect_invert: Invert the default sense of the write protect switch.
10 * @use_dma: Set to allow the use of DMA.
11 * @gpio_detect: GPIO number for the card detect line.
12 * @gpio_wprotect: GPIO number for the write protect line.
13 * @ocr_avail: The mask of the available power states, non-zero to use.
14 * @set_power: Callback to control the power mode.
15 *
16 * The @gpio_detect is used for card detection when @no_wprotect is unset,
17 * and the default sense is that 0 returned from gpio_get_value() means
18 * that a card is inserted. If @detect_invert is set, then the value from
19 * gpio_get_value() is inverted, which makes 1 mean card inserted.
20 *
21 * The driver will use @gpio_wprotect to signal whether the card is write
22 * protected if @no_wprotect is not set. A 0 returned from gpio_get_value()
23 * means the card is read/write, and 1 means read-only. The @wprotect_invert
24 * will invert the value returned from gpio_get_value().
25 *
26 * Card power is set by @ocr_availa, using MCC_VDD_ constants if it is set
27 * to a non-zero value, otherwise the default of 3.2-3.4V is used.
28 */
29struct s3c24xx_mci_pdata {
30 unsigned int no_wprotect:1;
31 unsigned int no_detect:1;
32 unsigned int wprotect_invert:1;
33 unsigned int detect_invert:1; /* set => detect active high */
34 unsigned int use_dma:1;
35
36 unsigned int gpio_detect;
37 unsigned int gpio_wprotect;
38 unsigned long ocr_avail;
39 void (*set_power)(unsigned char power_mode,
40 unsigned short vdd);
41};
42
43/**
44 * s3c24xx_mci_set_platdata - set platform data for mmc/sdi device
45 * @pdata: The platform data
46 *
47 * Copy the platform data supplied by @pdata so that this can be marked
48 * __initdata.
49 */
50extern void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata);
51
52#endif /* _ARCH_NCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h
new file mode 100644
index 00000000000..ac13227272f
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/mfc.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __PLAT_SAMSUNG_MFC_H
11#define __PLAT_SAMSUNG_MFC_H __FILE__
12
13/**
14 * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
15 * @rbase: base address for MFC 'right' memory interface
16 * @rsize: size of the memory reserved for MFC 'right' interface
17 * @lbase: base address for MFC 'left' memory interface
18 * @lsize: size of the memory reserved for MFC 'left' interface
19 *
20 * This function reserves system memory for both MFC device memory
21 * interfaces and registers it to respective struct device entries as
22 * coherent memory.
23 */
24void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
25 phys_addr_t lbase, unsigned int lsize);
26
27#endif /* __PLAT_SAMSUNG_MFC_H */
diff --git a/arch/arm/plat-samsung/include/plat/mipi_csis.h b/arch/arm/plat-samsung/include/plat/mipi_csis.h
new file mode 100644
index 00000000000..c45b1e8d4c2
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/mipi_csis.h
@@ -0,0 +1,43 @@
1/*
2 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
3 *
4 * S5P series MIPI CSI slave device support
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __PLAT_SAMSUNG_MIPI_CSIS_H_
12#define __PLAT_SAMSUNG_MIPI_CSIS_H_ __FILE__
13
14struct platform_device;
15
16/**
17 * struct s5p_platform_mipi_csis - platform data for S5P MIPI-CSIS driver
18 * @clk_rate: bus clock frequency
19 * @lanes: number of data lanes used
20 * @alignment: data alignment in bits
21 * @hs_settle: HS-RX settle time
22 * @fixed_phy_vdd: false to enable external D-PHY regulator management in the
23 * driver or true in case this regulator has no enable function
24 * @phy_enable: pointer to a callback controlling D-PHY enable/reset
25 */
26struct s5p_platform_mipi_csis {
27 unsigned long clk_rate;
28 u8 lanes;
29 u8 alignment;
30 u8 hs_settle;
31 bool fixed_phy_vdd;
32 int (*phy_enable)(struct platform_device *pdev, bool on);
33};
34
35/**
36 * s5p_csis_phy_enable - global MIPI-CSI receiver D-PHY control
37 * @pdev: MIPI-CSIS platform device
38 * @on: true to enable D-PHY and deassert its reset
39 * false to disable D-PHY
40 */
41int s5p_csis_phy_enable(struct platform_device *pdev, bool on);
42
43#endif /* __PLAT_SAMSUNG_MIPI_CSIS_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/pll.h b/arch/arm/plat-samsung/include/plat/pll.h
new file mode 100644
index 00000000000..357af7c1c66
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pll.h
@@ -0,0 +1,323 @@
1/* linux/arch/arm/plat-samsung/include/plat/pll.h
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * Samsung PLL codes
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#include <asm/div64.h>
19
20#define S3C24XX_PLL_MDIV_MASK (0xFF)
21#define S3C24XX_PLL_PDIV_MASK (0x1F)
22#define S3C24XX_PLL_SDIV_MASK (0x3)
23#define S3C24XX_PLL_MDIV_SHIFT (12)
24#define S3C24XX_PLL_PDIV_SHIFT (4)
25#define S3C24XX_PLL_SDIV_SHIFT (0)
26
27static inline unsigned int s3c24xx_get_pll(unsigned int pllval,
28 unsigned int baseclk)
29{
30 unsigned int mdiv, pdiv, sdiv;
31 uint64_t fvco;
32
33 mdiv = (pllval >> S3C24XX_PLL_MDIV_SHIFT) & S3C24XX_PLL_MDIV_MASK;
34 pdiv = (pllval >> S3C24XX_PLL_PDIV_SHIFT) & S3C24XX_PLL_PDIV_MASK;
35 sdiv = (pllval >> S3C24XX_PLL_SDIV_SHIFT) & S3C24XX_PLL_SDIV_MASK;
36
37 fvco = (uint64_t)baseclk * (mdiv + 8);
38 do_div(fvco, (pdiv + 2) << sdiv);
39
40 return (unsigned int)fvco;
41}
42
43#define S3C2416_PLL_MDIV_MASK (0x3FF)
44#define S3C2416_PLL_PDIV_MASK (0x3F)
45#define S3C2416_PLL_SDIV_MASK (0x7)
46#define S3C2416_PLL_MDIV_SHIFT (14)
47#define S3C2416_PLL_PDIV_SHIFT (5)
48#define S3C2416_PLL_SDIV_SHIFT (0)
49
50static inline unsigned int s3c2416_get_pll(unsigned int pllval,
51 unsigned int baseclk)
52{
53 unsigned int mdiv, pdiv, sdiv;
54 uint64_t fvco;
55
56 mdiv = (pllval >> S3C2416_PLL_MDIV_SHIFT) & S3C2416_PLL_MDIV_MASK;
57 pdiv = (pllval >> S3C2416_PLL_PDIV_SHIFT) & S3C2416_PLL_PDIV_MASK;
58 sdiv = (pllval >> S3C2416_PLL_SDIV_SHIFT) & S3C2416_PLL_SDIV_MASK;
59
60 fvco = (uint64_t)baseclk * mdiv;
61 do_div(fvco, (pdiv << sdiv));
62
63 return (unsigned int)fvco;
64}
65
66#define S3C6400_PLL_MDIV_MASK (0x3FF)
67#define S3C6400_PLL_PDIV_MASK (0x3F)
68#define S3C6400_PLL_SDIV_MASK (0x7)
69#define S3C6400_PLL_MDIV_SHIFT (16)
70#define S3C6400_PLL_PDIV_SHIFT (8)
71#define S3C6400_PLL_SDIV_SHIFT (0)
72
73static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
74 u32 pllcon)
75{
76 u32 mdiv, pdiv, sdiv;
77 u64 fvco = baseclk;
78
79 mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
80 pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
81 sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
82
83 fvco *= mdiv;
84 do_div(fvco, (pdiv << sdiv));
85
86 return (unsigned long)fvco;
87}
88
89#define PLL6553X_MDIV_MASK (0x7F)
90#define PLL6553X_PDIV_MASK (0x1F)
91#define PLL6553X_SDIV_MASK (0x3)
92#define PLL6553X_KDIV_MASK (0xFFFF)
93#define PLL6553X_MDIV_SHIFT (16)
94#define PLL6553X_PDIV_SHIFT (8)
95#define PLL6553X_SDIV_SHIFT (0)
96
97static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
98 u32 pll_con0, u32 pll_con1)
99{
100 unsigned long result;
101 u32 mdiv, pdiv, sdiv, kdiv;
102 u64 tmp;
103
104 mdiv = (pll_con0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
105 pdiv = (pll_con0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
106 sdiv = (pll_con0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
107 kdiv = pll_con1 & PLL6553X_KDIV_MASK;
108
109 /*
110 * We need to multiple baseclk by mdiv (the integer part) and kdiv
111 * which is in 2^16ths, so shift mdiv up (does not overflow) and
112 * add kdiv before multiplying. The use of tmp is to avoid any
113 * overflows before shifting bac down into result when multipling
114 * by the mdiv and kdiv pair.
115 */
116
117 tmp = baseclk;
118 tmp *= (mdiv << 16) + kdiv;
119 do_div(tmp, (pdiv << sdiv));
120 result = tmp >> 16;
121
122 return result;
123}
124
125#define PLL35XX_MDIV_MASK (0x3FF)
126#define PLL35XX_PDIV_MASK (0x3F)
127#define PLL35XX_SDIV_MASK (0x7)
128#define PLL35XX_MDIV_SHIFT (16)
129#define PLL35XX_PDIV_SHIFT (8)
130#define PLL35XX_SDIV_SHIFT (0)
131
132static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
133{
134 u32 mdiv, pdiv, sdiv;
135 u64 fvco = baseclk;
136
137 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
138 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
139 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
140
141 fvco *= mdiv;
142 do_div(fvco, (pdiv << sdiv));
143
144 return (unsigned long)fvco;
145}
146
147#define PLL36XX_KDIV_MASK (0xFFFF)
148#define PLL36XX_MDIV_MASK (0x1FF)
149#define PLL36XX_PDIV_MASK (0x3F)
150#define PLL36XX_SDIV_MASK (0x7)
151#define PLL36XX_MDIV_SHIFT (16)
152#define PLL36XX_PDIV_SHIFT (8)
153#define PLL36XX_SDIV_SHIFT (0)
154
155static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
156 u32 pll_con0, u32 pll_con1)
157{
158 unsigned long result;
159 u32 mdiv, pdiv, sdiv, kdiv;
160 u64 tmp;
161
162 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
163 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
164 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
165 kdiv = pll_con1 & PLL36XX_KDIV_MASK;
166
167 tmp = baseclk;
168
169 tmp *= (mdiv << 16) + kdiv;
170 do_div(tmp, (pdiv << sdiv));
171 result = tmp >> 16;
172
173 return result;
174}
175
176#define PLL45XX_MDIV_MASK (0x3FF)
177#define PLL45XX_PDIV_MASK (0x3F)
178#define PLL45XX_SDIV_MASK (0x7)
179#define PLL45XX_MDIV_SHIFT (16)
180#define PLL45XX_PDIV_SHIFT (8)
181#define PLL45XX_SDIV_SHIFT (0)
182
183enum pll45xx_type_t {
184 pll_4500,
185 pll_4502,
186 pll_4508
187};
188
189static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
190 enum pll45xx_type_t pll_type)
191{
192 u32 mdiv, pdiv, sdiv;
193 u64 fvco = baseclk;
194
195 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
196 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
197 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
198
199 if (pll_type == pll_4508)
200 sdiv = sdiv - 1;
201
202 fvco *= mdiv;
203 do_div(fvco, (pdiv << sdiv));
204
205 return (unsigned long)fvco;
206}
207
208/* CON0 bit-fields */
209#define PLL46XX_MDIV_MASK (0x1FF)
210#define PLL46XX_PDIV_MASK (0x3F)
211#define PLL46XX_SDIV_MASK (0x7)
212#define PLL46XX_LOCKED_SHIFT (29)
213#define PLL46XX_MDIV_SHIFT (16)
214#define PLL46XX_PDIV_SHIFT (8)
215#define PLL46XX_SDIV_SHIFT (0)
216
217/* CON1 bit-fields */
218#define PLL46XX_MRR_MASK (0x1F)
219#define PLL46XX_MFR_MASK (0x3F)
220#define PLL46XX_KDIV_MASK (0xFFFF)
221#define PLL4650C_KDIV_MASK (0xFFF)
222#define PLL46XX_MRR_SHIFT (24)
223#define PLL46XX_MFR_SHIFT (16)
224#define PLL46XX_KDIV_SHIFT (0)
225
226enum pll46xx_type_t {
227 pll_4600,
228 pll_4650,
229 pll_4650c,
230};
231
232static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
233 u32 pll_con0, u32 pll_con1,
234 enum pll46xx_type_t pll_type)
235{
236 unsigned long result;
237 u32 mdiv, pdiv, sdiv, kdiv;
238 u64 tmp;
239
240 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
241 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
242 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
243 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
244
245 if (pll_type == pll_4650c)
246 kdiv = pll_con1 & PLL4650C_KDIV_MASK;
247 else
248 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
249
250 tmp = baseclk;
251
252 if (pll_type == pll_4600) {
253 tmp *= (mdiv << 16) + kdiv;
254 do_div(tmp, (pdiv << sdiv));
255 result = tmp >> 16;
256 } else {
257 tmp *= (mdiv << 10) + kdiv;
258 do_div(tmp, (pdiv << sdiv));
259 result = tmp >> 10;
260 }
261
262 return result;
263}
264
265#define PLL90XX_MDIV_MASK (0xFF)
266#define PLL90XX_PDIV_MASK (0x3F)
267#define PLL90XX_SDIV_MASK (0x7)
268#define PLL90XX_KDIV_MASK (0xffff)
269#define PLL90XX_LOCKED_SHIFT (29)
270#define PLL90XX_MDIV_SHIFT (16)
271#define PLL90XX_PDIV_SHIFT (8)
272#define PLL90XX_SDIV_SHIFT (0)
273#define PLL90XX_KDIV_SHIFT (0)
274
275static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
276 u32 pll_con, u32 pll_conk)
277{
278 unsigned long result;
279 u32 mdiv, pdiv, sdiv, kdiv;
280 u64 tmp;
281
282 mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
283 pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
284 sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
285 kdiv = pll_conk & PLL90XX_KDIV_MASK;
286
287 /*
288 * We need to multiple baseclk by mdiv (the integer part) and kdiv
289 * which is in 2^16ths, so shift mdiv up (does not overflow) and
290 * add kdiv before multiplying. The use of tmp is to avoid any
291 * overflows before shifting bac down into result when multipling
292 * by the mdiv and kdiv pair.
293 */
294
295 tmp = baseclk;
296 tmp *= (mdiv << 16) + kdiv;
297 do_div(tmp, (pdiv << sdiv));
298 result = tmp >> 16;
299
300 return result;
301}
302
303#define PLL65XX_MDIV_MASK (0x3FF)
304#define PLL65XX_PDIV_MASK (0x3F)
305#define PLL65XX_SDIV_MASK (0x7)
306#define PLL65XX_MDIV_SHIFT (16)
307#define PLL65XX_PDIV_SHIFT (8)
308#define PLL65XX_SDIV_SHIFT (0)
309
310static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
311{
312 u32 mdiv, pdiv, sdiv;
313 u64 fvco = baseclk;
314
315 mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
316 pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
317 sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
318
319 fvco *= mdiv;
320 do_div(fvco, (pdiv << sdiv));
321
322 return (unsigned long)fvco;
323}
diff --git a/arch/arm/plat-samsung/include/plat/pll6553x.h b/arch/arm/plat-samsung/include/plat/pll6553x.h
deleted file mode 100644
index b8b7e1d884f..00000000000
--- a/arch/arm/plat-samsung/include/plat/pll6553x.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/* arch/arm/plat-samsung/include/plat/pll6553x.h
2 * partially from arch/arm/mach-s3c64xx/include/mach/pll.h
3 *
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * Samsung PLL6553x PLL code
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16/* S3C6400 and compatible (S3C2416, etc.) EPLL code */
17
18#define PLL6553X_MDIV_MASK ((1 << (23-16)) - 1)
19#define PLL6553X_PDIV_MASK ((1 << (13-8)) - 1)
20#define PLL6553X_SDIV_MASK ((1 << (2-0)) - 1)
21#define PLL6553X_MDIV_SHIFT (16)
22#define PLL6553X_PDIV_SHIFT (8)
23#define PLL6553X_SDIV_SHIFT (0)
24#define PLL6553X_KDIV_MASK (0xffff)
25
26static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
27 u32 pll0, u32 pll1)
28{
29 unsigned long result;
30 u32 mdiv, pdiv, sdiv, kdiv;
31 u64 tmp;
32
33 mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
34 pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
35 sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
36 kdiv = pll1 & PLL6553X_KDIV_MASK;
37
38 /* We need to multiple baseclk by mdiv (the integer part) and kdiv
39 * which is in 2^16ths, so shift mdiv up (does not overflow) and
40 * add kdiv before multiplying. The use of tmp is to avoid any
41 * overflows before shifting bac down into result when multipling
42 * by the mdiv and kdiv pair.
43 */
44
45 tmp = baseclk;
46 tmp *= (mdiv << 16) + kdiv;
47 do_div(tmp, (pdiv << sdiv));
48 result = tmp >> 16;
49
50 return result;
51}
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index f6749916d19..dcf68709f9c 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -165,20 +165,20 @@ extern void s3c_pm_check_store(void);
165extern void s3c_pm_configure_extint(void); 165extern void s3c_pm_configure_extint(void);
166 166
167/** 167/**
168 * s3c_pm_restore_gpios() - restore the state of the gpios after sleep. 168 * samsung_pm_restore_gpios() - restore the state of the gpios after sleep.
169 * 169 *
170 * Restore the state of the GPIO pins after sleep, which may involve ensuring 170 * Restore the state of the GPIO pins after sleep, which may involve ensuring
171 * that we do not glitch the state of the pins from that the bootloader's 171 * that we do not glitch the state of the pins from that the bootloader's
172 * resume code has done. 172 * resume code has done.
173*/ 173*/
174extern void s3c_pm_restore_gpios(void); 174extern void samsung_pm_restore_gpios(void);
175 175
176/** 176/**
177 * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep. 177 * samsung_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
178 * 178 *
179 * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios(). 179 * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios().
180 */ 180 */
181extern void s3c_pm_save_gpios(void); 181extern void samsung_pm_save_gpios(void);
182 182
183extern void s3c_pm_save_core(void); 183extern void s3c_pm_save_core(void);
184extern void s3c_pm_restore_core(void); 184extern void s3c_pm_restore_core(void);
diff --git a/arch/arm/plat-samsung/include/plat/pwm-clock.h b/arch/arm/plat-samsung/include/plat/pwm-clock.h
new file mode 100644
index 00000000000..bf6a60eb623
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pwm-clock.h
@@ -0,0 +1,81 @@
1/* linux/arch/arm/plat-samsung/include/plat/pwm-clock.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * SAMSUNG - pwm clock and timer support
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#ifndef __ASM_PLAT_PWM_CLOCK_H
19#define __ASM_PLAT_PWM_CLOCK_H __FILE__
20
21/**
22 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
23 * @tcfg: The timer TCFG1 register bits shifted down to 0.
24 *
25 * Return true if the given configuration from TCFG1 is a TCLK instead
26 * any of the TDIV clocks.
27 */
28static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
29{
30 if (soc_is_s3c24xx())
31 return tcfg == S3C2410_TCFG1_MUX_TCLK;
32 else if (soc_is_s3c64xx() || soc_is_s5pc100())
33 return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
34 else if (soc_is_s5p6440() || soc_is_s5p6450())
35 return 0;
36 else
37 return tcfg == S3C64XX_TCFG1_MUX_TCLK;
38}
39
40/**
41 * tcfg_to_divisor() - convert tcfg1 setting to a divisor
42 * @tcfg1: The tcfg1 setting, shifted down.
43 *
44 * Get the divisor value for the given tcfg1 setting. We assume the
45 * caller has already checked to see if this is not a TCLK source.
46 */
47static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
48{
49 if (soc_is_s3c24xx())
50 return 1 << (tcfg1 + 1);
51 else
52 return 1 << tcfg1;
53}
54
55/**
56 * pwm_tdiv_has_div1() - does the tdiv setting have a /1
57 *
58 * Return true if we have a /1 in the tdiv setting.
59 */
60static inline unsigned int pwm_tdiv_has_div1(void)
61{
62 if (soc_is_s3c24xx())
63 return 0;
64 else
65 return 1;
66}
67
68/**
69 * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
70 * @div: The divisor to calculate the bit information for.
71 *
72 * Turn a divisor into the necessary bit field for TCFG1.
73 */
74static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
75{
76 if (soc_is_s3c24xx())
77 return ilog2(div) - 1;
78 else
79 return ilog2(div);
80}
81#endif /* __ASM_PLAT_PWM_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-dma.h b/arch/arm/plat-samsung/include/plat/regs-dma.h
new file mode 100644
index 00000000000..178bccbe480
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-dma.h
@@ -0,0 +1,151 @@
1/* arch/arm/plat-samsung/include/plat/regs-dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_REGS_DMA_H
14#define __ASM_PLAT_REGS_DMA_H __FILE__
15
16#define S3C2410_DMA_DISRC (0x00)
17#define S3C2410_DMA_DISRCC (0x04)
18#define S3C2410_DMA_DIDST (0x08)
19#define S3C2410_DMA_DIDSTC (0x0C)
20#define S3C2410_DMA_DCON (0x10)
21#define S3C2410_DMA_DSTAT (0x14)
22#define S3C2410_DMA_DCSRC (0x18)
23#define S3C2410_DMA_DCDST (0x1C)
24#define S3C2410_DMA_DMASKTRIG (0x20)
25#define S3C2412_DMA_DMAREQSEL (0x24)
26#define S3C2443_DMA_DMAREQSEL (0x24)
27
28#define S3C2410_DISRCC_INC (1 << 0)
29#define S3C2410_DISRCC_APB (1 << 1)
30
31#define S3C2410_DMASKTRIG_STOP (1 << 2)
32#define S3C2410_DMASKTRIG_ON (1 << 1)
33#define S3C2410_DMASKTRIG_SWTRIG (1 << 0)
34
35#define S3C2410_DCON_DEMAND (0 << 31)
36#define S3C2410_DCON_HANDSHAKE (1 << 31)
37#define S3C2410_DCON_SYNC_PCLK (0 << 30)
38#define S3C2410_DCON_SYNC_HCLK (1 << 30)
39
40#define S3C2410_DCON_INTREQ (1 << 29)
41
42#define S3C2410_DCON_CH0_XDREQ0 (0 << 24)
43#define S3C2410_DCON_CH0_UART0 (1 << 24)
44#define S3C2410_DCON_CH0_SDI (2 << 24)
45#define S3C2410_DCON_CH0_TIMER (3 << 24)
46#define S3C2410_DCON_CH0_USBEP1 (4 << 24)
47
48#define S3C2410_DCON_CH1_XDREQ1 (0 << 24)
49#define S3C2410_DCON_CH1_UART1 (1 << 24)
50#define S3C2410_DCON_CH1_I2SSDI (2 << 24)
51#define S3C2410_DCON_CH1_SPI (3 << 24)
52#define S3C2410_DCON_CH1_USBEP2 (4 << 24)
53
54#define S3C2410_DCON_CH2_I2SSDO (0 << 24)
55#define S3C2410_DCON_CH2_I2SSDI (1 << 24)
56#define S3C2410_DCON_CH2_SDI (2 << 24)
57#define S3C2410_DCON_CH2_TIMER (3 << 24)
58#define S3C2410_DCON_CH2_USBEP3 (4 << 24)
59
60#define S3C2410_DCON_CH3_UART2 (0 << 24)
61#define S3C2410_DCON_CH3_SDI (1 << 24)
62#define S3C2410_DCON_CH3_SPI (2 << 24)
63#define S3C2410_DCON_CH3_TIMER (3 << 24)
64#define S3C2410_DCON_CH3_USBEP4 (4 << 24)
65
66#define S3C2410_DCON_SRCSHIFT (24)
67#define S3C2410_DCON_SRCMASK (7 << 24)
68
69#define S3C2410_DCON_BYTE (0 << 20)
70#define S3C2410_DCON_HALFWORD (1 << 20)
71#define S3C2410_DCON_WORD (2 << 20)
72
73#define S3C2410_DCON_AUTORELOAD (0 << 22)
74#define S3C2410_DCON_NORELOAD (1 << 22)
75#define S3C2410_DCON_HWTRIG (1 << 23)
76
77#ifdef CONFIG_CPU_S3C2440
78
79#define S3C2440_DIDSTC_CHKINT (1 << 2)
80
81#define S3C2440_DCON_CH0_I2SSDO (5 << 24)
82#define S3C2440_DCON_CH0_PCMIN (6 << 24)
83
84#define S3C2440_DCON_CH1_PCMOUT (5 << 24)
85#define S3C2440_DCON_CH1_SDI (6 << 24)
86
87#define S3C2440_DCON_CH2_PCMIN (5 << 24)
88#define S3C2440_DCON_CH2_MICIN (6 << 24)
89
90#define S3C2440_DCON_CH3_MICIN (5 << 24)
91#define S3C2440_DCON_CH3_PCMOUT (6 << 24)
92#endif /* CONFIG_CPU_S3C2440 */
93
94#ifdef CONFIG_CPU_S3C2412
95
96#define S3C2412_DMAREQSEL_SRC(x) ((x) << 1)
97
98#define S3C2412_DMAREQSEL_HW (1)
99
100#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
101#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
102#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
103#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
104#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
105#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
106#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
107#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
108#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
109#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
110#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
111#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
112#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
113#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
114#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
115#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
116#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
117#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
118#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
119#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
120#endif /* CONFIG_CPU_S3C2412 */
121
122#ifdef CONFIG_CPU_S3C2443
123
124#define S3C2443_DMAREQSEL_SRC(x) ((x) << 1)
125
126#define S3C2443_DMAREQSEL_HW (1)
127
128#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
129#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
130#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
131#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
132#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
133#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
134#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
135#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
136#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
137#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
138#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
139#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
140#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
141#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
142#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
143#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
144#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
145#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
146#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
147#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
148#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
149#endif /* CONFIG_CPU_S3C2443 */
150
151#endif /* __ASM_PLAT_REGS_DMA_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-iis.h b/arch/arm/plat-samsung/include/plat/regs-iis.h
new file mode 100644
index 00000000000..a18d35e7a73
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-iis.h
@@ -0,0 +1,70 @@
1/* arch/arm/plat-samsung/include/plat/regs-iis.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 IIS register definition
11*/
12
13#ifndef __ASM_ARCH_REGS_IIS_H
14#define __ASM_ARCH_REGS_IIS_H
15
16#define S3C2410_IISCON (0x00)
17
18#define S3C2410_IISCON_LRINDEX (1 << 8)
19#define S3C2410_IISCON_TXFIFORDY (1 << 7)
20#define S3C2410_IISCON_RXFIFORDY (1 << 6)
21#define S3C2410_IISCON_TXDMAEN (1 << 5)
22#define S3C2410_IISCON_RXDMAEN (1 << 4)
23#define S3C2410_IISCON_TXIDLE (1 << 3)
24#define S3C2410_IISCON_RXIDLE (1 << 2)
25#define S3C2410_IISCON_PSCEN (1 << 1)
26#define S3C2410_IISCON_IISEN (1 << 0)
27
28#define S3C2410_IISMOD (0x04)
29
30#define S3C2440_IISMOD_MPLL (1 << 9)
31#define S3C2410_IISMOD_SLAVE (1 << 8)
32#define S3C2410_IISMOD_NOXFER (0 << 6)
33#define S3C2410_IISMOD_RXMODE (1 << 6)
34#define S3C2410_IISMOD_TXMODE (2 << 6)
35#define S3C2410_IISMOD_TXRXMODE (3 << 6)
36#define S3C2410_IISMOD_LR_LLOW (0 << 5)
37#define S3C2410_IISMOD_LR_RLOW (1 << 5)
38#define S3C2410_IISMOD_IIS (0 << 4)
39#define S3C2410_IISMOD_MSB (1 << 4)
40#define S3C2410_IISMOD_8BIT (0 << 3)
41#define S3C2410_IISMOD_16BIT (1 << 3)
42#define S3C2410_IISMOD_BITMASK (1 << 3)
43#define S3C2410_IISMOD_256FS (0 << 2)
44#define S3C2410_IISMOD_384FS (1 << 2)
45#define S3C2410_IISMOD_16FS (0 << 0)
46#define S3C2410_IISMOD_32FS (1 << 0)
47#define S3C2410_IISMOD_48FS (2 << 0)
48#define S3C2410_IISMOD_FS_MASK (3 << 0)
49
50#define S3C2410_IISPSR (0x08)
51
52#define S3C2410_IISPSR_INTMASK (31 << 5)
53#define S3C2410_IISPSR_INTSHIFT (5)
54#define S3C2410_IISPSR_EXTMASK (31 << 0)
55#define S3C2410_IISPSR_EXTSHFIT (0)
56
57#define S3C2410_IISFCON (0x0c)
58
59#define S3C2410_IISFCON_TXDMA (1 << 15)
60#define S3C2410_IISFCON_RXDMA (1 << 14)
61#define S3C2410_IISFCON_TXENABLE (1 << 13)
62#define S3C2410_IISFCON_RXENABLE (1 << 12)
63#define S3C2410_IISFCON_TXMASK (0x3f << 6)
64#define S3C2410_IISFCON_TXSHIFT (6)
65#define S3C2410_IISFCON_RXMASK (0x3f)
66#define S3C2410_IISFCON_RXSHIFT (0)
67
68#define S3C2410_IISFIFO (0x10)
69
70#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-spi.h b/arch/arm/plat-samsung/include/plat/regs-spi.h
new file mode 100644
index 00000000000..552fe7cfe28
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-spi.h
@@ -0,0 +1,48 @@
1/* arch/arm/plat-samsung/include/plat/regs-spi.h
2 *
3 * Copyright (c) 2004 Fetron GmbH
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 SPI register definition
10*/
11
12#ifndef __ASM_ARCH_REGS_SPI_H
13#define __ASM_ARCH_REGS_SPI_H
14
15#define S3C2410_SPI1 (0x20)
16#define S3C2412_SPI1 (0x100)
17
18#define S3C2410_SPCON (0x00)
19
20#define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */
21#define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */
22#define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */
23#define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */
24#define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */
25#define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */
26#define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */
27
28#define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */
29#define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */
30
31#define S3C2410_SPSTA (0x04)
32
33#define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */
34#define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */
35#define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */
36#define S3C2412_SPSTA_READY_ORG (1 << 3)
37
38#define S3C2410_SPPIN (0x08)
39
40#define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */
41#define S3C2410_SPPIN_RESERVED (1 << 1)
42#define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */
43
44#define S3C2410_SPPRE (0x0C)
45#define S3C2410_SPTDAT (0x10)
46#define S3C2410_SPRDAT (0x14)
47
48#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-srom.h b/arch/arm/plat-samsung/include/plat/regs-srom.h
new file mode 100644
index 00000000000..9b6729c81cd
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-srom.h
@@ -0,0 +1,54 @@
1/* linux/arch/arm/plat-samsung/include/plat/regs-srom.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P SROMC register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_SAMSUNG_REGS_SROM_H
14#define __PLAT_SAMSUNG_REGS_SROM_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_SROMREG(x) (S5P_VA_SROMC + (x))
19
20#define S5P_SROM_BW S5P_SROMREG(0x0)
21#define S5P_SROM_BC0 S5P_SROMREG(0x4)
22#define S5P_SROM_BC1 S5P_SROMREG(0x8)
23#define S5P_SROM_BC2 S5P_SROMREG(0xc)
24#define S5P_SROM_BC3 S5P_SROMREG(0x10)
25#define S5P_SROM_BC4 S5P_SROMREG(0x14)
26#define S5P_SROM_BC5 S5P_SROMREG(0x18)
27
28/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
29
30#define S5P_SROM_BW__DATAWIDTH__SHIFT 0
31#define S5P_SROM_BW__ADDRMODE__SHIFT 1
32#define S5P_SROM_BW__WAITENABLE__SHIFT 2
33#define S5P_SROM_BW__BYTEENABLE__SHIFT 3
34
35#define S5P_SROM_BW__CS_MASK 0xf
36
37#define S5P_SROM_BW__NCS0__SHIFT 0
38#define S5P_SROM_BW__NCS1__SHIFT 4
39#define S5P_SROM_BW__NCS2__SHIFT 8
40#define S5P_SROM_BW__NCS3__SHIFT 12
41#define S5P_SROM_BW__NCS4__SHIFT 16
42#define S5P_SROM_BW__NCS5__SHIFT 20
43
44/* applies to same to BCS0 - BCS3 */
45
46#define S5P_SROM_BCX__PMC__SHIFT 0
47#define S5P_SROM_BCX__TACP__SHIFT 4
48#define S5P_SROM_BCX__TCAH__SHIFT 8
49#define S5P_SROM_BCX__TCOH__SHIFT 12
50#define S5P_SROM_BCX__TACC__SHIFT 16
51#define S5P_SROM_BCX__TCOS__SHIFT 24
52#define S5P_SROM_BCX__TACS__SHIFT 28
53
54#endif /* __PLAT_SAMSUNG_REGS_SROM_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-udc.h b/arch/arm/plat-samsung/include/plat/regs-udc.h
new file mode 100644
index 00000000000..4003d3dab4e
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-udc.h
@@ -0,0 +1,151 @@
1/* arch/arm/plat-samsung/include/plat/regs-udc.h
2 *
3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
4 *
5 * This include file is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9*/
10
11#ifndef __ASM_ARCH_REGS_UDC_H
12#define __ASM_ARCH_REGS_UDC_H
13
14#define S3C2410_USBDREG(x) (x)
15
16#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
17#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
18#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
19
20#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
21#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
22
23#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
24
25#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
26#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
27
28#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
29#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
30#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
31#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
32#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
33
34#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
35#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
36#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
37#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
38#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
39#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
40
41#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
42#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
43#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
44#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
45#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
46#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
47
48#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
49#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
50#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
51#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
52#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
53#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
54
55#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
56#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
57#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
58#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
59#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
60#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
61
62#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
63
64/* indexed registers */
65
66#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
67
68#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
69
70#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
71#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
72
73#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
74#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
75#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
76#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
77
78#define S3C2410_UDC_FUNCADDR_UPDATE (1 << 7)
79
80#define S3C2410_UDC_PWR_ISOUP (1 << 7) /* R/W */
81#define S3C2410_UDC_PWR_RESET (1 << 3) /* R */
82#define S3C2410_UDC_PWR_RESUME (1 << 2) /* R/W */
83#define S3C2410_UDC_PWR_SUSPEND (1 << 1) /* R */
84#define S3C2410_UDC_PWR_ENSUSPEND (1 << 0) /* R/W */
85
86#define S3C2410_UDC_PWR_DEFAULT (0x00)
87
88#define S3C2410_UDC_INT_EP4 (1 << 4) /* R/W (clear only) */
89#define S3C2410_UDC_INT_EP3 (1 << 3) /* R/W (clear only) */
90#define S3C2410_UDC_INT_EP2 (1 << 2) /* R/W (clear only) */
91#define S3C2410_UDC_INT_EP1 (1 << 1) /* R/W (clear only) */
92#define S3C2410_UDC_INT_EP0 (1 << 0) /* R/W (clear only) */
93
94#define S3C2410_UDC_USBINT_RESET (1 << 2) /* R/W (clear only) */
95#define S3C2410_UDC_USBINT_RESUME (1 << 1) /* R/W (clear only) */
96#define S3C2410_UDC_USBINT_SUSPEND (1 << 0) /* R/W (clear only) */
97
98#define S3C2410_UDC_INTE_EP4 (1 << 4) /* R/W */
99#define S3C2410_UDC_INTE_EP3 (1 << 3) /* R/W */
100#define S3C2410_UDC_INTE_EP2 (1 << 2) /* R/W */
101#define S3C2410_UDC_INTE_EP1 (1 << 1) /* R/W */
102#define S3C2410_UDC_INTE_EP0 (1 << 0) /* R/W */
103
104#define S3C2410_UDC_USBINTE_RESET (1 << 2) /* R/W */
105#define S3C2410_UDC_USBINTE_SUSPEND (1 << 0) /* R/W */
106
107#define S3C2410_UDC_INDEX_EP0 (0x00)
108#define S3C2410_UDC_INDEX_EP1 (0x01)
109#define S3C2410_UDC_INDEX_EP2 (0x02)
110#define S3C2410_UDC_INDEX_EP3 (0x03)
111#define S3C2410_UDC_INDEX_EP4 (0x04)
112
113#define S3C2410_UDC_ICSR1_CLRDT (1 << 6) /* R/W */
114#define S3C2410_UDC_ICSR1_SENTSTL (1 << 5) /* R/W (clear only) */
115#define S3C2410_UDC_ICSR1_SENDSTL (1 << 4) /* R/W */
116#define S3C2410_UDC_ICSR1_FFLUSH (1 << 3) /* W (set only) */
117#define S3C2410_UDC_ICSR1_UNDRUN (1 << 2) /* R/W (clear only) */
118#define S3C2410_UDC_ICSR1_PKTRDY (1 << 0) /* R/W (set only) */
119
120#define S3C2410_UDC_ICSR2_AUTOSET (1 << 7) /* R/W */
121#define S3C2410_UDC_ICSR2_ISO (1 << 6) /* R/W */
122#define S3C2410_UDC_ICSR2_MODEIN (1 << 5) /* R/W */
123#define S3C2410_UDC_ICSR2_DMAIEN (1 << 4) /* R/W */
124
125#define S3C2410_UDC_OCSR1_CLRDT (1 << 7) /* R/W */
126#define S3C2410_UDC_OCSR1_SENTSTL (1 << 6) /* R/W (clear only) */
127#define S3C2410_UDC_OCSR1_SENDSTL (1 << 5) /* R/W */
128#define S3C2410_UDC_OCSR1_FFLUSH (1 << 4) /* R/W */
129#define S3C2410_UDC_OCSR1_DERROR (1 << 3) /* R */
130#define S3C2410_UDC_OCSR1_OVRRUN (1 << 2) /* R/W (clear only) */
131#define S3C2410_UDC_OCSR1_PKTRDY (1 << 0) /* R/W (clear only) */
132
133#define S3C2410_UDC_OCSR2_AUTOCLR (1 << 7) /* R/W */
134#define S3C2410_UDC_OCSR2_ISO (1 << 6) /* R/W */
135#define S3C2410_UDC_OCSR2_DMAIEN (1 << 5) /* R/W */
136
137#define S3C2410_UDC_EP0_CSR_OPKRDY (1 << 0)
138#define S3C2410_UDC_EP0_CSR_IPKRDY (1 << 1)
139#define S3C2410_UDC_EP0_CSR_SENTSTL (1 << 2)
140#define S3C2410_UDC_EP0_CSR_DE (1 << 3)
141#define S3C2410_UDC_EP0_CSR_SE (1 << 4)
142#define S3C2410_UDC_EP0_CSR_SENDSTL (1 << 5)
143#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1 << 6)
144#define S3C2410_UDC_EP0_CSR_SSE (1 << 7)
145
146#define S3C2410_UDC_MAXP_8 (1 << 0)
147#define S3C2410_UDC_MAXP_16 (1 << 1)
148#define S3C2410_UDC_MAXP_32 (1 << 2)
149#define S3C2410_UDC_MAXP_64 (1 << 3)
150
151#endif
diff --git a/arch/arm/plat-samsung/include/plat/reset.h b/arch/arm/plat-samsung/include/plat/reset.h
new file mode 100644
index 00000000000..32ca5179c6e
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/reset.h
@@ -0,0 +1,16 @@
1/* linux/arch/arm/plat-samsung/include/plat/reset.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#ifndef __PLAT_SAMSUNG_RESET_H
12#define __PLAT_SAMSUNG_RESET_H __FILE__
13
14extern void (*s5p_reset_hook)(void);
15
16#endif /* __PLAT_SAMSUNG_RESET_H */
diff --git a/arch/arm/plat-samsung/include/plat/s3c2410.h b/arch/arm/plat-samsung/include/plat/s3c2410.h
new file mode 100644
index 00000000000..3986497dd3f
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c2410.h
@@ -0,0 +1,33 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c2410.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2410 machine directory
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#ifdef CONFIG_CPU_S3C2410
15
16extern int s3c2410_init(void);
17extern int s3c2410a_init(void);
18
19extern void s3c2410_map_io(void);
20
21extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
22
23extern void s3c2410_init_clocks(int xtal);
24
25#else
26#define s3c2410_init_clocks NULL
27#define s3c2410_init_uarts NULL
28#define s3c2410_map_io NULL
29#define s3c2410_init NULL
30#define s3c2410a_init NULL
31#endif
32
33extern int s3c2410_baseclk_add(void);
diff --git a/arch/arm/plat-samsung/include/plat/s3c2412.h b/arch/arm/plat-samsung/include/plat/s3c2412.h
new file mode 100644
index 00000000000..5bcfd143ba1
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c2412.h
@@ -0,0 +1,29 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c2412.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2412 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2412
14
15extern int s3c2412_init(void);
16
17extern void s3c2412_map_io(void);
18
19extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
20
21extern void s3c2412_init_clocks(int xtal);
22
23extern int s3c2412_baseclk_add(void);
24#else
25#define s3c2412_init_clocks NULL
26#define s3c2412_init_uarts NULL
27#define s3c2412_map_io NULL
28#define s3c2412_init NULL
29#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h
new file mode 100644
index 00000000000..a764f8503f5
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c2416.h
@@ -0,0 +1,31 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c2416.h
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>
4 *
5 * Header file for s3c2416 cpu support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifdef CONFIG_CPU_S3C2416
13
14struct s3c2410_uartcfg;
15
16extern int s3c2416_init(void);
17
18extern void s3c2416_map_io(void);
19
20extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
21
22extern void s3c2416_init_clocks(int xtal);
23
24extern int s3c2416_baseclk_add(void);
25
26#else
27#define s3c2416_init_clocks NULL
28#define s3c2416_init_uarts NULL
29#define s3c2416_map_io NULL
30#define s3c2416_init NULL
31#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h
new file mode 100644
index 00000000000..4b2ac9a272b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c2443.h
@@ -0,0 +1,51 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c2443.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2443 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2443
14
15struct s3c2410_uartcfg;
16
17extern int s3c2443_init(void);
18
19extern void s3c2443_map_io(void);
20
21extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
22
23extern void s3c2443_init_clocks(int xtal);
24
25extern int s3c2443_baseclk_add(void);
26
27#else
28#define s3c2443_init_clocks NULL
29#define s3c2443_init_uarts NULL
30#define s3c2443_map_io NULL
31#define s3c2443_init NULL
32#endif
33
34/* common code used by s3c2443 and others.
35 * note, not to be used outside of arch/arm/mach-s3c* */
36
37struct clk; /* some files don't need clk.h otherwise */
38
39typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
40typedef unsigned int (*fdiv_fn)(unsigned long clkcon0);
41
42extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv);
43extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv);
44
45extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
46extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
47extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
48
49extern struct clksrc_clk clk_epllref;
50extern struct clksrc_clk clk_esysclk;
51extern struct clksrc_clk clk_msysclk;
diff --git a/arch/arm/plat-samsung/include/plat/s3c244x.h b/arch/arm/plat-samsung/include/plat/s3c244x.h
new file mode 100644
index 00000000000..ea0c961b760
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c244x.h
@@ -0,0 +1,42 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c244x.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C2440 and S3C2442 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
14
15extern void s3c244x_map_io(void);
16
17extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
18
19extern void s3c244x_init_clocks(int xtal);
20
21#else
22#define s3c244x_init_clocks NULL
23#define s3c244x_init_uarts NULL
24#endif
25
26#ifdef CONFIG_CPU_S3C2440
27extern int s3c2440_init(void);
28
29extern void s3c2440_map_io(void);
30#else
31#define s3c2440_init NULL
32#define s3c2440_map_io NULL
33#endif
34
35#ifdef CONFIG_CPU_S3C2442
36extern int s3c2442_init(void);
37
38extern void s3c2442_map_io(void);
39#else
40#define s3c2442_init NULL
41#define s3c2442_map_io NULL
42#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c6400.h b/arch/arm/plat-samsung/include/plat/s3c6400.h
new file mode 100644
index 00000000000..37d428aaaeb
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c6400.h
@@ -0,0 +1,36 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c6400.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Header file for s3c6400 cpu support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Common init code for S3C6400 related SoCs */
16
17extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
18extern void s3c6400_setup_clocks(void);
19
20extern void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
21
22#ifdef CONFIG_CPU_S3C6400
23
24extern int s3c6400_init(void);
25extern void s3c6400_init_irq(void);
26extern void s3c6400_map_io(void);
27extern void s3c6400_init_clocks(int xtal);
28
29#define s3c6400_init_uarts s3c6400_common_init_uarts
30
31#else
32#define s3c6400_init_clocks NULL
33#define s3c6400_init_uarts NULL
34#define s3c6400_map_io NULL
35#define s3c6400_init NULL
36#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c6410.h b/arch/arm/plat-samsung/include/plat/s3c6410.h
new file mode 100644
index 00000000000..20a6675b9d1
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c6410.h
@@ -0,0 +1,29 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c6410.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Header file for s3c6410 cpu support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifdef CONFIG_CPU_S3C6410
16
17extern int s3c6410_init(void);
18extern void s3c6410_init_irq(void);
19extern void s3c6410_map_io(void);
20extern void s3c6410_init_clocks(int xtal);
21
22#define s3c6410_init_uarts s3c6400_common_init_uarts
23
24#else
25#define s3c6410_init_clocks NULL
26#define s3c6410_init_uarts NULL
27#define s3c6410_map_io NULL
28#define s3c6410_init NULL
29#endif
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
new file mode 100644
index 00000000000..984bf9e7bc8
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -0,0 +1,55 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5p-clock.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for s5p clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S5P_CLOCK_H
14#define __ASM_PLAT_S5P_CLOCK_H __FILE__
15
16#include <linux/clk.h>
17
18#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
19
20#define clk_fin_apll clk_ext_xtal_mux
21#define clk_fin_mpll clk_ext_xtal_mux
22#define clk_fin_epll clk_ext_xtal_mux
23#define clk_fin_dpll clk_ext_xtal_mux
24#define clk_fin_vpll clk_ext_xtal_mux
25#define clk_fin_hpll clk_ext_xtal_mux
26
27extern struct clk clk_ext_xtal_mux;
28extern struct clk clk_xusbxti;
29extern struct clk clk_48m;
30extern struct clk s5p_clk_27m;
31extern struct clk clk_fout_apll;
32extern struct clk clk_fout_mpll;
33extern struct clk clk_fout_epll;
34extern struct clk clk_fout_dpll;
35extern struct clk clk_fout_vpll;
36extern struct clk clk_arm;
37extern struct clk clk_vpll;
38
39extern struct clksrc_sources clk_src_apll;
40extern struct clksrc_sources clk_src_mpll;
41extern struct clksrc_sources clk_src_epll;
42extern struct clksrc_sources clk_src_dpll;
43
44extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
45
46/* Common EPLL operations for S5P platform */
47extern int s5p_epll_enable(struct clk *clk, int enable);
48extern unsigned long s5p_epll_get_rate(struct clk *clk);
49
50/* SPDIF clk operations common for S5PC100/V210/C110 and Exynos4 */
51extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
52extern unsigned long s5p_spdif_get_rate(struct clk *clk);
53
54extern struct clk_ops s5p_sclk_spdif_ops;
55#endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/s5p-time.h b/arch/arm/plat-samsung/include/plat/s5p-time.h
new file mode 100644
index 00000000000..3a70aebc920
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s5p-time.h
@@ -0,0 +1,40 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5p-time.h
2 *
3 * Copyright 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5p time support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S5P_TIME_H
14#define __ASM_PLAT_S5P_TIME_H __FILE__
15
16/* S5P HR-Timer Clock mode */
17enum s5p_timer_mode {
18 S5P_PWM0,
19 S5P_PWM1,
20 S5P_PWM2,
21 S5P_PWM3,
22 S5P_PWM4,
23};
24
25struct s5p_timer_source {
26 unsigned int event_id;
27 unsigned int source_id;
28};
29
30/* Be able to sleep for atleast 4 seconds (usually more) */
31#define S5PTIMER_MIN_RANGE 4
32
33#define TCNT_MAX 0xffffffff
34#define NON_PERIODIC 0
35#define PERIODIC 1
36
37extern void __init s5p_set_timer_source(enum s5p_timer_mode event,
38 enum s5p_timer_mode source);
39extern struct sys_timer s5p_timer;
40#endif /* __ASM_PLAT_S5P_TIME_H */
diff --git a/arch/arm/plat-samsung/include/plat/s5p6440.h b/arch/arm/plat-samsung/include/plat/s5p6440.h
new file mode 100644
index 00000000000..bf85ebbb4fb
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s5p6440.h
@@ -0,0 +1,36 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5p6440.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5p6440 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13 /* Common init code for S5P6440 related SoCs */
14
15extern void s5p6440_register_clocks(void);
16extern void s5p6440_setup_clocks(void);
17
18#ifdef CONFIG_CPU_S5P6440
19
20extern int s5p64x0_init(void);
21extern void s5p6440_init_irq(void);
22extern void s5p6440_map_io(void);
23extern void s5p6440_init_clocks(int xtal);
24
25extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
26
27#else
28#define s5p6440_init_clocks NULL
29#define s5p6440_init_uarts NULL
30#define s5p6440_map_io NULL
31#define s5p64x0_init NULL
32#endif
33
34/* S5P6440 timer */
35
36extern struct sys_timer s5p6440_timer;
diff --git a/arch/arm/plat-samsung/include/plat/s5p6450.h b/arch/arm/plat-samsung/include/plat/s5p6450.h
new file mode 100644
index 00000000000..da25f9a1c54
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s5p6450.h
@@ -0,0 +1,36 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5p6450.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for s5p6450 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5P6450 related SoCs */
14
15extern void s5p6450_register_clocks(void);
16extern void s5p6450_setup_clocks(void);
17
18#ifdef CONFIG_CPU_S5P6450
19
20extern int s5p64x0_init(void);
21extern void s5p6450_init_irq(void);
22extern void s5p6450_map_io(void);
23extern void s5p6450_init_clocks(int xtal);
24
25extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
26
27#else
28#define s5p6450_init_clocks NULL
29#define s5p6450_init_uarts NULL
30#define s5p6450_map_io NULL
31#define s5p64x0_init NULL
32#endif
33
34/* S5P6450 timer */
35
36extern struct sys_timer s5p6450_timer;
diff --git a/arch/arm/plat-samsung/include/plat/s5pc100.h b/arch/arm/plat-samsung/include/plat/s5pc100.h
new file mode 100644
index 00000000000..9a21aeaaf45
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s5pc100.h
@@ -0,0 +1,33 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5pc100.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5pc100 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5PC100 related SoCs */
14
15extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void s5pc100_register_clocks(void);
17extern void s5pc100_setup_clocks(void);
18
19#ifdef CONFIG_CPU_S5PC100
20
21extern int s5pc100_init(void);
22extern void s5pc100_init_irq(void);
23extern void s5pc100_map_io(void);
24extern void s5pc100_init_clocks(int xtal);
25
26#define s5pc100_init_uarts s5pc100_common_init_uarts
27
28#else
29#define s5pc100_init_clocks NULL
30#define s5pc100_init_uarts NULL
31#define s5pc100_map_io NULL
32#define s5pc100_init NULL
33#endif
diff --git a/arch/arm/plat-samsung/include/plat/s5pv210.h b/arch/arm/plat-samsung/include/plat/s5pv210.h
new file mode 100644
index 00000000000..b4bc6be7707
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s5pv210.h
@@ -0,0 +1,33 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5pv210.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5pv210 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5PV210 related SoCs */
14
15extern void s5pv210_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void s5pv210_register_clocks(void);
17extern void s5pv210_setup_clocks(void);
18
19#ifdef CONFIG_CPU_S5PV210
20
21extern int s5pv210_init(void);
22extern void s5pv210_init_irq(void);
23extern void s5pv210_map_io(void);
24extern void s5pv210_init_clocks(int xtal);
25
26#define s5pv210_init_uarts s5pv210_common_init_uarts
27
28#else
29#define s5pv210_init_clocks NULL
30#define s5pv210_init_uarts NULL
31#define s5pv210_map_io NULL
32#define s5pv210_init NULL
33#endif
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 4a6552066c7..e7b3c752e91 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -55,10 +55,6 @@ enum clk_types {
55 * cd_type == S3C_SDHCI_CD_GPIO 55 * cd_type == S3C_SDHCI_CD_GPIO
56 * @ext_cd_gpio_invert: invert values for external CD gpio line 56 * @ext_cd_gpio_invert: invert values for external CD gpio line
57 * @cfg_gpio: Configure the GPIO for a specific card bit-width 57 * @cfg_gpio: Configure the GPIO for a specific card bit-width
58 * @cfg_card: Configure the interface for a specific card and speed. This
59 * is necessary the controllers and/or GPIO blocks require the
60 * changing of driver-strength and other controls dependent on
61 * the card and speed of operation.
62 * 58 *
63 * Initialisation data specific to either the machine or the platform 59 * Initialisation data specific to either the machine or the platform
64 * for the device driver to use or call-back when configuring gpio or 60 * for the device driver to use or call-back when configuring gpio or
@@ -80,10 +76,6 @@ struct s3c_sdhci_platdata {
80 int state)); 76 int state));
81 77
82 void (*cfg_gpio)(struct platform_device *dev, int width); 78 void (*cfg_gpio)(struct platform_device *dev, int width);
83 void (*cfg_card)(struct platform_device *dev,
84 void __iomem *regbase,
85 struct mmc_ios *ios,
86 struct mmc_card *card);
87}; 79};
88 80
89/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data 81/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data
@@ -139,17 +131,11 @@ extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
139#ifdef CONFIG_S3C2416_SETUP_SDHCI 131#ifdef CONFIG_S3C2416_SETUP_SDHCI
140extern char *s3c2416_hsmmc_clksrcs[4]; 132extern char *s3c2416_hsmmc_clksrcs[4];
141 133
142extern void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
143 void __iomem *r,
144 struct mmc_ios *ios,
145 struct mmc_card *card);
146
147static inline void s3c2416_default_sdhci0(void) 134static inline void s3c2416_default_sdhci0(void)
148{ 135{
149#ifdef CONFIG_S3C_DEV_HSMMC 136#ifdef CONFIG_S3C_DEV_HSMMC
150 s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs; 137 s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
151 s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; 138 s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
152 s3c_hsmmc0_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
153#endif /* CONFIG_S3C_DEV_HSMMC */ 139#endif /* CONFIG_S3C_DEV_HSMMC */
154} 140}
155 141
@@ -158,7 +144,6 @@ static inline void s3c2416_default_sdhci1(void)
158#ifdef CONFIG_S3C_DEV_HSMMC1 144#ifdef CONFIG_S3C_DEV_HSMMC1
159 s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs; 145 s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
160 s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; 146 s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
161 s3c_hsmmc1_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
162#endif /* CONFIG_S3C_DEV_HSMMC1 */ 147#endif /* CONFIG_S3C_DEV_HSMMC1 */
163} 148}
164 149
@@ -172,17 +157,11 @@ static inline void s3c2416_default_sdhci1(void) { }
172#ifdef CONFIG_S3C64XX_SETUP_SDHCI 157#ifdef CONFIG_S3C64XX_SETUP_SDHCI
173extern char *s3c64xx_hsmmc_clksrcs[4]; 158extern char *s3c64xx_hsmmc_clksrcs[4];
174 159
175extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
176 void __iomem *r,
177 struct mmc_ios *ios,
178 struct mmc_card *card);
179
180static inline void s3c6400_default_sdhci0(void) 160static inline void s3c6400_default_sdhci0(void)
181{ 161{
182#ifdef CONFIG_S3C_DEV_HSMMC 162#ifdef CONFIG_S3C_DEV_HSMMC
183 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; 163 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
184 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; 164 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
185 s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
186#endif 165#endif
187} 166}
188 167
@@ -191,7 +170,6 @@ static inline void s3c6400_default_sdhci1(void)
191#ifdef CONFIG_S3C_DEV_HSMMC1 170#ifdef CONFIG_S3C_DEV_HSMMC1
192 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; 171 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
193 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; 172 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
194 s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
195#endif 173#endif
196} 174}
197 175
@@ -200,21 +178,14 @@ static inline void s3c6400_default_sdhci2(void)
200#ifdef CONFIG_S3C_DEV_HSMMC2 178#ifdef CONFIG_S3C_DEV_HSMMC2
201 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; 179 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
202 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; 180 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
203 s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
204#endif 181#endif
205} 182}
206 183
207extern void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev,
208 void __iomem *r,
209 struct mmc_ios *ios,
210 struct mmc_card *card);
211
212static inline void s3c6410_default_sdhci0(void) 184static inline void s3c6410_default_sdhci0(void)
213{ 185{
214#ifdef CONFIG_S3C_DEV_HSMMC 186#ifdef CONFIG_S3C_DEV_HSMMC
215 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; 187 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
216 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; 188 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
217 s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
218#endif 189#endif
219} 190}
220 191
@@ -223,7 +194,6 @@ static inline void s3c6410_default_sdhci1(void)
223#ifdef CONFIG_S3C_DEV_HSMMC1 194#ifdef CONFIG_S3C_DEV_HSMMC1
224 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; 195 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
225 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; 196 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
226 s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
227#endif 197#endif
228} 198}
229 199
@@ -232,7 +202,6 @@ static inline void s3c6410_default_sdhci2(void)
232#ifdef CONFIG_S3C_DEV_HSMMC2 202#ifdef CONFIG_S3C_DEV_HSMMC2
233 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; 203 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
234 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; 204 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
235 s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
236#endif 205#endif
237} 206}
238 207
@@ -251,17 +220,11 @@ static inline void s3c6400_default_sdhci2(void) { }
251#ifdef CONFIG_S5PC100_SETUP_SDHCI 220#ifdef CONFIG_S5PC100_SETUP_SDHCI
252extern char *s5pc100_hsmmc_clksrcs[4]; 221extern char *s5pc100_hsmmc_clksrcs[4];
253 222
254extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
255 void __iomem *r,
256 struct mmc_ios *ios,
257 struct mmc_card *card);
258
259static inline void s5pc100_default_sdhci0(void) 223static inline void s5pc100_default_sdhci0(void)
260{ 224{
261#ifdef CONFIG_S3C_DEV_HSMMC 225#ifdef CONFIG_S3C_DEV_HSMMC
262 s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs; 226 s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
263 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; 227 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
264 s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
265#endif 228#endif
266} 229}
267 230
@@ -270,7 +233,6 @@ static inline void s5pc100_default_sdhci1(void)
270#ifdef CONFIG_S3C_DEV_HSMMC1 233#ifdef CONFIG_S3C_DEV_HSMMC1
271 s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs; 234 s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
272 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; 235 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
273 s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
274#endif 236#endif
275} 237}
276 238
@@ -279,7 +241,6 @@ static inline void s5pc100_default_sdhci2(void)
279#ifdef CONFIG_S3C_DEV_HSMMC2 241#ifdef CONFIG_S3C_DEV_HSMMC2
280 s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs; 242 s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
281 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; 243 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
282 s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
283#endif 244#endif
284} 245}
285 246
@@ -295,17 +256,11 @@ static inline void s5pc100_default_sdhci2(void) { }
295#ifdef CONFIG_S5PV210_SETUP_SDHCI 256#ifdef CONFIG_S5PV210_SETUP_SDHCI
296extern char *s5pv210_hsmmc_clksrcs[4]; 257extern char *s5pv210_hsmmc_clksrcs[4];
297 258
298extern void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
299 void __iomem *r,
300 struct mmc_ios *ios,
301 struct mmc_card *card);
302
303static inline void s5pv210_default_sdhci0(void) 259static inline void s5pv210_default_sdhci0(void)
304{ 260{
305#ifdef CONFIG_S3C_DEV_HSMMC 261#ifdef CONFIG_S3C_DEV_HSMMC
306 s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs; 262 s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
307 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; 263 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
308 s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
309#endif 264#endif
310} 265}
311 266
@@ -314,7 +269,6 @@ static inline void s5pv210_default_sdhci1(void)
314#ifdef CONFIG_S3C_DEV_HSMMC1 269#ifdef CONFIG_S3C_DEV_HSMMC1
315 s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs; 270 s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
316 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; 271 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
317 s3c_hsmmc1_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
318#endif 272#endif
319} 273}
320 274
@@ -323,7 +277,6 @@ static inline void s5pv210_default_sdhci2(void)
323#ifdef CONFIG_S3C_DEV_HSMMC2 277#ifdef CONFIG_S3C_DEV_HSMMC2
324 s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs; 278 s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
325 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; 279 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
326 s3c_hsmmc2_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
327#endif 280#endif
328} 281}
329 282
@@ -332,7 +285,6 @@ static inline void s5pv210_default_sdhci3(void)
332#ifdef CONFIG_S3C_DEV_HSMMC3 285#ifdef CONFIG_S3C_DEV_HSMMC3
333 s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs; 286 s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
334 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; 287 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
335 s3c_hsmmc3_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
336#endif 288#endif
337} 289}
338 290
@@ -348,17 +300,11 @@ static inline void s5pv210_default_sdhci3(void) { }
348#ifdef CONFIG_EXYNOS4_SETUP_SDHCI 300#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
349extern char *exynos4_hsmmc_clksrcs[4]; 301extern char *exynos4_hsmmc_clksrcs[4];
350 302
351extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev,
352 void __iomem *r,
353 struct mmc_ios *ios,
354 struct mmc_card *card);
355
356static inline void exynos4_default_sdhci0(void) 303static inline void exynos4_default_sdhci0(void)
357{ 304{
358#ifdef CONFIG_S3C_DEV_HSMMC 305#ifdef CONFIG_S3C_DEV_HSMMC
359 s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs; 306 s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
360 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; 307 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
361 s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
362#endif 308#endif
363} 309}
364 310
@@ -367,7 +313,6 @@ static inline void exynos4_default_sdhci1(void)
367#ifdef CONFIG_S3C_DEV_HSMMC1 313#ifdef CONFIG_S3C_DEV_HSMMC1
368 s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs; 314 s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
369 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; 315 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
370 s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
371#endif 316#endif
372} 317}
373 318
@@ -376,7 +321,6 @@ static inline void exynos4_default_sdhci2(void)
376#ifdef CONFIG_S3C_DEV_HSMMC2 321#ifdef CONFIG_S3C_DEV_HSMMC2
377 s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs; 322 s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
378 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; 323 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
379 s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
380#endif 324#endif
381} 325}
382 326
@@ -385,7 +329,6 @@ static inline void exynos4_default_sdhci3(void)
385#ifdef CONFIG_S3C_DEV_HSMMC3 329#ifdef CONFIG_S3C_DEV_HSMMC3
386 s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs; 330 s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
387 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; 331 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
388 s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
389#endif 332#endif
390} 333}
391 334
diff --git a/arch/arm/plat-samsung/include/plat/sysmmu.h b/arch/arm/plat-samsung/include/plat/sysmmu.h
new file mode 100644
index 00000000000..5fe8ee01a5b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/sysmmu.h
@@ -0,0 +1,95 @@
1/* linux/arch/arm/plat-samsung/include/plat/sysmmu.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung System MMU driver for S5P platform
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_SAMSUNG_SYSMMU_H
14#define __PLAT_SAMSUNG_SYSMMU_H __FILE__
15
16enum S5P_SYSMMU_INTERRUPT_TYPE {
17 SYSMMU_PAGEFAULT,
18 SYSMMU_AR_MULTIHIT,
19 SYSMMU_AW_MULTIHIT,
20 SYSMMU_BUSERROR,
21 SYSMMU_AR_SECURITY,
22 SYSMMU_AR_ACCESS,
23 SYSMMU_AW_SECURITY,
24 SYSMMU_AW_PROTECTION, /* 7 */
25 SYSMMU_FAULTS_NUM
26};
27
28#ifdef CONFIG_S5P_SYSTEM_MMU
29
30#include <mach/sysmmu.h>
31
32/**
33 * s5p_sysmmu_enable() - enable system mmu of ip
34 * @ips: The ip connected system mmu.
35 * #pgd: Base physical address of the 1st level page table
36 *
37 * This function enable system mmu to transfer address
38 * from virtual address to physical address
39 */
40void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd);
41
42/**
43 * s5p_sysmmu_disable() - disable sysmmu mmu of ip
44 * @ips: The ip connected system mmu.
45 *
46 * This function disable system mmu to transfer address
47 * from virtual address to physical address
48 */
49void s5p_sysmmu_disable(sysmmu_ips ips);
50
51/**
52 * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
53 * @ips: The ip connected system mmu.
54 * @pgd: The page table base address.
55 *
56 * This function set page table base address
57 * When system mmu transfer address from virtaul address to physical address,
58 * system mmu refer address information from page table
59 */
60void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
61
62/**
63 * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
64 * @ips: The ip connected system mmu.
65 *
66 * This function flush all TLB entry in system mmu
67 */
68void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
69
70/** s5p_sysmmu_set_fault_handler() - Fault handler for System MMUs
71 * @itype: type of fault.
72 * @pgtable_base: the physical address of page table base. This is 0 if @ips is
73 * SYSMMU_BUSERROR.
74 * @fault_addr: the device (virtual) address that the System MMU tried to
75 * translated. This is 0 if @ips is SYSMMU_BUSERROR.
76 * Called when interrupt occurred by the System MMUs
77 * The device drivers of peripheral devices that has a System MMU can implement
78 * a fault handler to resolve address translation fault by System MMU.
79 * The meanings of return value and parameters are described below.
80
81 * return value: non-zero if the fault is correctly resolved.
82 * zero if the fault is not handled.
83 */
84void s5p_sysmmu_set_fault_handler(sysmmu_ips ips,
85 int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
86 unsigned long pgtable_base,
87 unsigned long fault_addr));
88#else
89#define s5p_sysmmu_enable(ips, pgd) do { } while (0)
90#define s5p_sysmmu_disable(ips) do { } while (0)
91#define s5p_sysmmu_set_tablebase_pgd(ips, pgd) do { } while (0)
92#define s5p_sysmmu_tlb_invalidate(ips) do { } while (0)
93#define s5p_sysmmu_set_fault_handler(ips, handler) do { } while (0)
94#endif
95#endif /* __ASM_PLAT_SYSMMU_H */
diff --git a/arch/arm/plat-samsung/include/plat/system-reset.h b/arch/arm/plat-samsung/include/plat/system-reset.h
new file mode 100644
index 00000000000..a448e990964
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/system-reset.h
@@ -0,0 +1,31 @@
1/* linux/arch/arm/plat-samsung/include/plat/system-reset.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/mach-s3c2410/include/mach/system-reset.h
7 *
8 * S5P - System define for arch_reset()
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <plat/watchdog-reset.h>
16
17void (*s5p_reset_hook)(void);
18
19static void arch_reset(char mode, const char *cmd)
20{
21 /* SWRESET support in s5p_reset_hook() */
22
23 if (s5p_reset_hook)
24 s5p_reset_hook();
25
26 /* Perform reset using Watchdog reset
27 * if there is no s5p_reset_hook()
28 */
29
30 arch_wdt_reset();
31}
diff --git a/arch/arm/plat-samsung/include/plat/tv-core.h b/arch/arm/plat-samsung/include/plat/tv-core.h
new file mode 100644
index 00000000000..3bc34f3ce28
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/tv-core.h
@@ -0,0 +1,44 @@
1/*
2 * arch/arm/plat-samsung/include/plat/tv.h
3 *
4 * Copyright 2011 Samsung Electronics Co., Ltd.
5 * Tomasz Stanislawski <t.stanislaws@samsung.com>
6 *
7 * Samsung TV driver core functions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __SAMSUNG_PLAT_TV_H
15#define __SAMSUNG_PLAT_TV_H __FILE__
16
17/*
18 * These functions are only for use with the core support code, such as
19 * the CPU-specific initialization code.
20 */
21
22/* Re-define device name to differentiate the subsystem in various SoCs. */
23static inline void s5p_hdmi_setname(char *name)
24{
25#ifdef CONFIG_S5P_DEV_TV
26 s5p_device_hdmi.name = name;
27#endif
28}
29
30static inline void s5p_mixer_setname(char *name)
31{
32#ifdef CONFIG_S5P_DEV_TV
33 s5p_device_mixer.name = name;
34#endif
35}
36
37static inline void s5p_sdo_setname(char *name)
38{
39#ifdef CONFIG_S5P_DEV_TV
40 s5p_device_sdo.name = name;
41#endif
42}
43
44#endif /* __SAMSUNG_PLAT_TV_H */
diff --git a/arch/arm/plat-samsung/include/plat/udc.h b/arch/arm/plat-samsung/include/plat/udc.h
new file mode 100644
index 00000000000..8c22d586bef
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/udc.h
@@ -0,0 +1,57 @@
1/* arch/arm/plat-samsung/include/plat/udc.h
2 *
3 * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *
11 * Changelog:
12 * 14-Mar-2005 RTP Created file
13 * 02-Aug-2005 RTP File rename
14 * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum
15 * 18-Jan-2007 HMW Add per-platform vbus_draw function
16*/
17
18#ifndef __ASM_ARM_ARCH_UDC_H
19#define __ASM_ARM_ARCH_UDC_H
20
21enum s3c2410_udc_cmd_e {
22 S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */
23 S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */
24 S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
25};
26
27struct s3c2410_udc_mach_info {
28 void (*udc_command)(enum s3c2410_udc_cmd_e);
29 void (*vbus_draw)(unsigned int ma);
30
31 unsigned int pullup_pin;
32 unsigned int pullup_pin_inverted;
33
34 unsigned int vbus_pin;
35 unsigned char vbus_pin_inverted;
36};
37
38extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
39
40/**
41 * s3c24xx_hsudc_platdata - Platform data for USB High-Speed gadget controller.
42 * @epnum: Number of endpoints to be instantiated by the controller driver.
43 * @gpio_init: Platform specific USB related GPIO initialization.
44 * @gpio_uninit: Platform specific USB releted GPIO uninitialzation.
45 *
46 * Representation of platform data for the S3C24XX USB 2.0 High Speed gadget
47 * controllers.
48 */
49struct s3c24xx_hsudc_platdata {
50 unsigned int epnum;
51 void (*gpio_init)(void);
52 void (*gpio_uninit)(void);
53};
54
55extern void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd);
56
57#endif /* __ASM_ARM_ARCH_UDC_H */
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
new file mode 100644
index 00000000000..959bcdb03a2
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __PLAT_SAMSUNG_USB_PHY_H
12#define __PLAT_SAMSUNG_USB_PHY_H __FILE__
13
14enum s5p_usb_phy_type {
15 S5P_USB_PHY_DEVICE,
16 S5P_USB_PHY_HOST,
17};
18
19extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
20extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
21
22#endif /* __PLAT_SAMSUNG_USB_PHY_H */
diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c
index 6de1a382592..4c9a20734fe 100644
--- a/arch/arm/plat-samsung/platformdata.c
+++ b/arch/arm/plat-samsung/platformdata.c
@@ -50,8 +50,6 @@ void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
50 set->max_width = pd->max_width; 50 set->max_width = pd->max_width;
51 if (pd->cfg_gpio) 51 if (pd->cfg_gpio)
52 set->cfg_gpio = pd->cfg_gpio; 52 set->cfg_gpio = pd->cfg_gpio;
53 if (pd->cfg_card)
54 set->cfg_card = pd->cfg_card;
55 if (pd->host_caps) 53 if (pd->host_caps)
56 set->host_caps |= pd->host_caps; 54 set->host_caps |= pd->host_caps;
57 if (pd->clk_type) 55 if (pd->clk_type)
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index 96528200eb7..4be016eaa6d 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -28,13 +28,13 @@
28#define OFFS_DAT (0x04) 28#define OFFS_DAT (0x04)
29#define OFFS_UP (0x08) 29#define OFFS_UP (0x08)
30 30
31static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip) 31static void samsung_gpio_pm_1bit_save(struct samsung_gpio_chip *chip)
32{ 32{
33 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); 33 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
34 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); 34 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
35} 35}
36 36
37static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip) 37static void samsung_gpio_pm_1bit_resume(struct samsung_gpio_chip *chip)
38{ 38{
39 void __iomem *base = chip->base; 39 void __iomem *base = chip->base;
40 u32 old_gpcon = __raw_readl(base + OFFS_CON); 40 u32 old_gpcon = __raw_readl(base + OFFS_CON);
@@ -60,12 +60,12 @@ static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
60 chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); 60 chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
61} 61}
62 62
63struct s3c_gpio_pm s3c_gpio_pm_1bit = { 63struct samsung_gpio_pm samsung_gpio_pm_1bit = {
64 .save = s3c_gpio_pm_1bit_save, 64 .save = samsung_gpio_pm_1bit_save,
65 .resume = s3c_gpio_pm_1bit_resume, 65 .resume = samsung_gpio_pm_1bit_resume,
66}; 66};
67 67
68static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip) 68static void samsung_gpio_pm_2bit_save(struct samsung_gpio_chip *chip)
69{ 69{
70 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); 70 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
71 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); 71 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
@@ -95,7 +95,7 @@ static inline int is_out(unsigned long con)
95} 95}
96 96
97/** 97/**
98 * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank 98 * samsung_gpio_pm_2bit_resume() - restore the given GPIO bank
99 * @chip: The chip information to resume. 99 * @chip: The chip information to resume.
100 * 100 *
101 * Restore one of the GPIO banks that was saved during suspend. This is 101 * Restore one of the GPIO banks that was saved during suspend. This is
@@ -121,7 +121,7 @@ static inline int is_out(unsigned long con)
121 * [1] this assumes that writing to a pin DAT whilst in SFN will set the 121 * [1] this assumes that writing to a pin DAT whilst in SFN will set the
122 * state for when it is next output. 122 * state for when it is next output.
123 */ 123 */
124static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip) 124static void samsung_gpio_pm_2bit_resume(struct samsung_gpio_chip *chip)
125{ 125{
126 void __iomem *base = chip->base; 126 void __iomem *base = chip->base;
127 u32 old_gpcon = __raw_readl(base + OFFS_CON); 127 u32 old_gpcon = __raw_readl(base + OFFS_CON);
@@ -187,13 +187,13 @@ static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
187 chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); 187 chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
188} 188}
189 189
190struct s3c_gpio_pm s3c_gpio_pm_2bit = { 190struct samsung_gpio_pm samsung_gpio_pm_2bit = {
191 .save = s3c_gpio_pm_2bit_save, 191 .save = samsung_gpio_pm_2bit_save,
192 .resume = s3c_gpio_pm_2bit_resume, 192 .resume = samsung_gpio_pm_2bit_resume,
193}; 193};
194 194
195#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) 195#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
196static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip) 196static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
197{ 197{
198 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); 198 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
199 chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); 199 chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
@@ -203,7 +203,7 @@ static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
203 chip->pm_save[0] = __raw_readl(chip->base - 4); 203 chip->pm_save[0] = __raw_readl(chip->base - 4);
204} 204}
205 205
206static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon) 206static u32 samsung_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
207{ 207{
208 u32 old, new, mask; 208 u32 old, new, mask;
209 u32 change_mask = 0x0; 209 u32 change_mask = 0x0;
@@ -242,14 +242,14 @@ static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
242 return change_mask; 242 return change_mask;
243} 243}
244 244
245static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index) 245static void samsung_gpio_pm_4bit_con(struct samsung_gpio_chip *chip, int index)
246{ 246{
247 void __iomem *con = chip->base + (index * 4); 247 void __iomem *con = chip->base + (index * 4);
248 u32 old_gpcon = __raw_readl(con); 248 u32 old_gpcon = __raw_readl(con);
249 u32 gps_gpcon = chip->pm_save[index + 1]; 249 u32 gps_gpcon = chip->pm_save[index + 1];
250 u32 gpcon, mask; 250 u32 gpcon, mask;
251 251
252 mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon); 252 mask = samsung_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
253 253
254 gpcon = old_gpcon & ~mask; 254 gpcon = old_gpcon & ~mask;
255 gpcon |= gps_gpcon & mask; 255 gpcon |= gps_gpcon & mask;
@@ -257,7 +257,7 @@ static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
257 __raw_writel(gpcon, con); 257 __raw_writel(gpcon, con);
258} 258}
259 259
260static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip) 260static void samsung_gpio_pm_4bit_resume(struct samsung_gpio_chip *chip)
261{ 261{
262 void __iomem *base = chip->base; 262 void __iomem *base = chip->base;
263 u32 old_gpcon[2]; 263 u32 old_gpcon[2];
@@ -269,10 +269,10 @@ static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
269 old_gpcon[0] = 0; 269 old_gpcon[0] = 0;
270 old_gpcon[1] = __raw_readl(base + OFFS_CON); 270 old_gpcon[1] = __raw_readl(base + OFFS_CON);
271 271
272 s3c_gpio_pm_4bit_con(chip, 0); 272 samsung_gpio_pm_4bit_con(chip, 0);
273 if (chip->chip.ngpio > 8) { 273 if (chip->chip.ngpio > 8) {
274 old_gpcon[0] = __raw_readl(base - 4); 274 old_gpcon[0] = __raw_readl(base - 4);
275 s3c_gpio_pm_4bit_con(chip, -1); 275 samsung_gpio_pm_4bit_con(chip, -1);
276 } 276 }
277 277
278 /* Now change the configurations that require DAT,CON */ 278 /* Now change the configurations that require DAT,CON */
@@ -298,19 +298,19 @@ static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
298 old_gpdat, gps_gpdat); 298 old_gpdat, gps_gpdat);
299} 299}
300 300
301struct s3c_gpio_pm s3c_gpio_pm_4bit = { 301struct samsung_gpio_pm samsung_gpio_pm_4bit = {
302 .save = s3c_gpio_pm_4bit_save, 302 .save = samsung_gpio_pm_4bit_save,
303 .resume = s3c_gpio_pm_4bit_resume, 303 .resume = samsung_gpio_pm_4bit_resume,
304}; 304};
305#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */ 305#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
306 306
307/** 307/**
308 * s3c_pm_save_gpio() - save gpio chip data for suspend 308 * samsung_pm_save_gpio() - save gpio chip data for suspend
309 * @ourchip: The chip for suspend. 309 * @ourchip: The chip for suspend.
310 */ 310 */
311static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip) 311static void samsung_pm_save_gpio(struct samsung_gpio_chip *ourchip)
312{ 312{
313 struct s3c_gpio_pm *pm = ourchip->pm; 313 struct samsung_gpio_pm *pm = ourchip->pm;
314 314
315 if (pm == NULL || pm->save == NULL) 315 if (pm == NULL || pm->save == NULL)
316 S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); 316 S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
@@ -319,24 +319,24 @@ static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
319} 319}
320 320
321/** 321/**
322 * s3c_pm_save_gpios() - Save the state of the GPIO banks. 322 * samsung_pm_save_gpios() - Save the state of the GPIO banks.
323 * 323 *
324 * For all the GPIO banks, save the state of each one ready for going 324 * For all the GPIO banks, save the state of each one ready for going
325 * into a suspend mode. 325 * into a suspend mode.
326 */ 326 */
327void s3c_pm_save_gpios(void) 327void samsung_pm_save_gpios(void)
328{ 328{
329 struct s3c_gpio_chip *ourchip; 329 struct samsung_gpio_chip *ourchip;
330 unsigned int gpio_nr; 330 unsigned int gpio_nr;
331 331
332 for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { 332 for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
333 ourchip = s3c_gpiolib_getchip(gpio_nr); 333 ourchip = samsung_gpiolib_getchip(gpio_nr);
334 if (!ourchip) { 334 if (!ourchip) {
335 gpio_nr++; 335 gpio_nr++;
336 continue; 336 continue;
337 } 337 }
338 338
339 s3c_pm_save_gpio(ourchip); 339 samsung_pm_save_gpio(ourchip);
340 340
341 S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n", 341 S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
342 ourchip->chip.label, 342 ourchip->chip.label,
@@ -351,12 +351,12 @@ void s3c_pm_save_gpios(void)
351} 351}
352 352
353/** 353/**
354 * s3c_pm_resume_gpio() - restore gpio chip data after suspend 354 * samsung_pm_resume_gpio() - restore gpio chip data after suspend
355 * @ourchip: The suspended chip. 355 * @ourchip: The suspended chip.
356 */ 356 */
357static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip) 357static void samsung_pm_resume_gpio(struct samsung_gpio_chip *ourchip)
358{ 358{
359 struct s3c_gpio_pm *pm = ourchip->pm; 359 struct samsung_gpio_pm *pm = ourchip->pm;
360 360
361 if (pm == NULL || pm->resume == NULL) 361 if (pm == NULL || pm->resume == NULL)
362 S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); 362 S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
@@ -364,19 +364,19 @@ static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
364 pm->resume(ourchip); 364 pm->resume(ourchip);
365} 365}
366 366
367void s3c_pm_restore_gpios(void) 367void samsung_pm_restore_gpios(void)
368{ 368{
369 struct s3c_gpio_chip *ourchip; 369 struct samsung_gpio_chip *ourchip;
370 unsigned int gpio_nr; 370 unsigned int gpio_nr;
371 371
372 for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { 372 for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
373 ourchip = s3c_gpiolib_getchip(gpio_nr); 373 ourchip = samsung_gpiolib_getchip(gpio_nr);
374 if (!ourchip) { 374 if (!ourchip) {
375 gpio_nr++; 375 gpio_nr++;
376 continue; 376 continue;
377 } 377 }
378 378
379 s3c_pm_resume_gpio(ourchip); 379 samsung_pm_resume_gpio(ourchip);
380 380
381 gpio_nr += ourchip->chip.ngpio; 381 gpio_nr += ourchip->chip.ngpio;
382 gpio_nr += CONFIG_S3C_GPIO_SPACE; 382 gpio_nr += CONFIG_S3C_GPIO_SPACE;
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index ae6f99834cd..64ab65f0fdb 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -268,8 +268,8 @@ static int s3c_pm_enter(suspend_state_t state)
268 268
269 /* save all necessary core registers not covered by the drivers */ 269 /* save all necessary core registers not covered by the drivers */
270 270
271 s3c_pm_save_gpios(); 271 samsung_pm_save_gpios();
272 s3c_pm_saved_gpios(); 272 samsung_pm_saved_gpios();
273 s3c_pm_save_uarts(); 273 s3c_pm_save_uarts();
274 s3c_pm_save_core(); 274 s3c_pm_save_core();
275 275
@@ -306,7 +306,7 @@ static int s3c_pm_enter(suspend_state_t state)
306 306
307 s3c_pm_restore_core(); 307 s3c_pm_restore_core();
308 s3c_pm_restore_uarts(); 308 s3c_pm_restore_uarts();
309 s3c_pm_restore_gpios(); 309 samsung_pm_restore_gpios();
310 s3c_pm_restored_gpios(); 310 s3c_pm_restored_gpios();
311 311
312 s3c_pm_debug_init(); 312 s3c_pm_debug_init();
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c
index f1bba88ed2f..a35ff3bcffe 100644
--- a/arch/arm/plat-samsung/pwm-clock.c
+++ b/arch/arm/plat-samsung/pwm-clock.c
@@ -27,7 +27,7 @@
27#include <plat/cpu.h> 27#include <plat/cpu.h>
28 28
29#include <plat/regs-timer.h> 29#include <plat/regs-timer.h>
30#include <mach/pwm-clock.h> 30#include <plat/pwm-clock.h>
31 31
32/* Each of the timers 0 through 5 go through the following 32/* Each of the timers 0 through 5 go through the following
33 * clock tree, with the inputs depending on the timers. 33 * clock tree, with the inputs depending on the timers.
@@ -339,8 +339,17 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
339 unsigned long bits; 339 unsigned long bits;
340 unsigned long shift = S3C2410_TCFG1_SHIFT(id); 340 unsigned long shift = S3C2410_TCFG1_SHIFT(id);
341 341
342 unsigned long mux_tclk;
343
344 if (soc_is_s3c24xx())
345 mux_tclk = S3C2410_TCFG1_MUX_TCLK;
346 else if (soc_is_s5p6440() || soc_is_s5p6450())
347 mux_tclk = 0;
348 else
349 mux_tclk = S3C64XX_TCFG1_MUX_TCLK;
350
342 if (parent == s3c24xx_pwmclk_tclk(id)) 351 if (parent == s3c24xx_pwmclk_tclk(id))
343 bits = S3C_TCFG1_MUX_TCLK << shift; 352 bits = mux_tclk << shift;
344 else if (parent == s3c24xx_pwmclk_tdiv(id)) 353 else if (parent == s3c24xx_pwmclk_tdiv(id))
345 bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; 354 bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
346 else 355 else
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-20 19:28:52 -0500