ARM: SAMSUNG: Move the last build from plat-s3c to plat-samsung

Move the init.c and time.c files to plat-samsung from plat-s3c, thus
clearing the last files that are being built in here.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>

4 files changed, 448 insertions, 1 deletions

diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index facc7e387fc..22c89d08f6e 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -11,6 +11,8 @@ obj-				:=
 
 # Objects we always build independent of SoC choice
 
+obj-y                           += init.o
+obj-y                           += time.o
 obj-y                           += clock.o
 obj-y                           += pwm-clock.o
 obj-y                           += gpio.o
diff --git a/arch/arm/plat-samsung/dma.c b/arch/arm/plat-samsung/dma.c
index 606db1af5fe..cb459dd9545 100644
--- a/arch/arm/plat-samsung/dma.c
+++ b/arch/arm/plat-samsung/dma.c
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s3c/dma.c
+/* linux/arch/arm/plat-samsung/dma.c
  *
  * Copyright (c) 2003-2009 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
new file mode 100644
index 00000000000..6790edfaca6
--- /dev/null
+++ b/arch/arm/plat-samsung/init.c
@@ -0,0 +1,160 @@
+/* linux/arch/arm/plat-s3c/init.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series CPU initialisation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+
+#include <plat/regs-serial.h>
+
+static struct cpu_table *cpu;
+
+static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode,
+                                                struct cpu_table *tab,
+                                                unsigned int count)
+{
+        for (; count != 0; count--, tab++) {
+                if ((idcode & tab->idmask) == tab->idcode)
+                        return tab;
+        }
+
+        return NULL;
+}
+
+void __init s3c_init_cpu(unsigned long idcode,
+                         struct cpu_table *cputab, unsigned int cputab_size)
+{
+        cpu = s3c_lookup_cpu(idcode, cputab, cputab_size);
+
+        if (cpu == NULL) {
+                printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
+                panic("Unknown S3C24XX CPU");
+        }
+
+        printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
+
+        if (cpu->map_io == NULL || cpu->init == NULL) {
+                printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
+                panic("Unsupported Samsung CPU");
+        }
+
+        cpu->map_io();
+}
+
+/* s3c24xx_init_clocks
+ *
+ * Initialise the clock subsystem and associated information from the
+ * given master crystal value.
+ *
+ * xtal  = 0 -> use default PLL crystal value (normally 12MHz)
+ *      != 0 -> PLL crystal value in Hz
+*/
+
+void __init s3c24xx_init_clocks(int xtal)
+{
+        if (xtal == 0)
+                xtal = 12*1000*1000;
+
+        if (cpu == NULL)
+                panic("s3c24xx_init_clocks: no cpu setup?\n");
+
+        if (cpu->init_clocks == NULL)
+                panic("s3c24xx_init_clocks: cpu has no clock init\n");
+        else
+                (cpu->init_clocks)(xtal);
+}
+
+/* uart management */
+
+static int nr_uarts __initdata = 0;
+
+static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+/* s3c24xx_init_uartdevs
+ *
+ * copy the specified platform data and configuration into our central
+ * set of devices, before the data is thrown away after the init process.
+ *
+ * This also fills in the array passed to the serial driver for the
+ * early initialisation of the console.
+*/
+
+void __init s3c24xx_init_uartdevs(char *name,
+                                  struct s3c24xx_uart_resources *res,
+                                  struct s3c2410_uartcfg *cfg, int no)
+{
+        struct platform_device *platdev;
+        struct s3c2410_uartcfg *cfgptr = uart_cfgs;
+        struct s3c24xx_uart_resources *resp;
+        int uart;
+
+        memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
+
+        for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
+                platdev = s3c24xx_uart_src[cfgptr->hwport];
+
+                resp = res + cfgptr->hwport;
+
+                s3c24xx_uart_devs[uart] = platdev;
+
+                platdev->name = name;
+                platdev->resource = resp->resources;
+                platdev->num_resources = resp->nr_resources;
+
+                platdev->dev.platform_data = cfgptr;
+        }
+
+        nr_uarts = no;
+}
+
+void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        if (cpu == NULL)
+                return;
+
+        if (cpu->init_uarts == NULL) {
+                printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
+        } else
+                (cpu->init_uarts)(cfg, no);
+}
+
+static int __init s3c_arch_init(void)
+{
+        int ret;
+
+        // do the correct init for cpu
+
+        if (cpu == NULL)
+                panic("s3c_arch_init: NULL cpu\n");
+
+        ret = (cpu->init)();
+        if (ret != 0)
+                return ret;
+
+        ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
+        return ret;
+}
+
+arch_initcall(s3c_arch_init);
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
new file mode 100644
index 00000000000..2231d80ad81
--- /dev/null
+++ b/arch/arm/plat-samsung/time.c
@@ -0,0 +1,285 @@
+/* linux/arch/arm/plat-samsung/time.c
+ *
+ * Copyright (C) 2003-2005 Simtec Electronics
+ *      Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <asm/system.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+
+#include <asm/irq.h>
+#include <mach/map.h>
+#include <plat/regs-timer.h>
+#include <mach/regs-irq.h>
+#include <asm/mach/time.h>
+#include <mach/tick.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+static unsigned long timer_startval;
+static unsigned long timer_usec_ticks;
+
+#ifndef TICK_MAX
+#define TICK_MAX (0xffff)
+#endif
+
+#define TIMER_USEC_SHIFT 16
+
+/* we use the shifted arithmetic to work out the ratio of timer ticks
+ * to usecs, as often the peripheral clock is not a nice even multiple
+ * of 1MHz.
+ *
+ * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
+ * for the current HZ value of 200 without producing overflows.
+ *
+ * Original patch by Dimitry Andric, updated by Ben Dooks
+*/
+
+
+/* timer_mask_usec_ticks
+ *
+ * given a clock and divisor, make the value to pass into timer_ticks_to_usec
+ * to scale the ticks into usecs
+*/
+
+static inline unsigned long
+timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
+{
+        unsigned long den = pclk / 1000;
+
+        return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
+}
+
+/* timer_ticks_to_usec
+ *
+ * convert timer ticks to usec.
+*/
+
+static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
+{
+        unsigned long res;
+
+        res = ticks * timer_usec_ticks;
+        res += 1 << (TIMER_USEC_SHIFT - 4);     /* round up slightly */
+
+        return res >> TIMER_USEC_SHIFT;
+}
+
+/***
+ * Returns microsecond  since last clock interrupt.  Note that interrupts
+ * will have been disabled by do_gettimeoffset()
+ * IRQs are disabled before entering here from do_gettimeofday()
+ */
+
+static unsigned long s3c2410_gettimeoffset (void)
+{
+        unsigned long tdone;
+        unsigned long tval;
+
+        /* work out how many ticks have gone since last timer interrupt */
+
+        tval =  __raw_readl(S3C2410_TCNTO(4));
+        tdone = timer_startval - tval;
+
+        /* check to see if there is an interrupt pending */
+
+        if (s3c24xx_ostimer_pending()) {
+                /* re-read the timer, and try and fix up for the missed
+                 * interrupt. Note, the interrupt may go off before the
+                 * timer has re-loaded from wrapping.
+                 */
+
+                tval =  __raw_readl(S3C2410_TCNTO(4));
+                tdone = timer_startval - tval;
+
+                if (tval != 0)
+                        tdone += timer_startval;
+        }
+
+        return timer_ticks_to_usec(tdone);
+}
+
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t
+s3c2410_timer_interrupt(int irq, void *dev_id)
+{
+        timer_tick();
+        return IRQ_HANDLED;
+}
+
+static struct irqaction s3c2410_timer_irq = {
+        .name           = "S3C2410 Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = s3c2410_timer_interrupt,
+};
+
+#define use_tclk1_12() ( \
+        machine_is_bast()       || \
+        machine_is_vr1000()     || \
+        machine_is_anubis()     || \
+        machine_is_osiris())
+
+static struct clk *tin;
+static struct clk *tdiv;
+static struct clk *timerclk;
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ *
+ * Currently we only use timer4, as it is the only timer which has no
+ * other function that can be exploited externally
+ */
+static void s3c2410_timer_setup (void)
+{
+        unsigned long tcon;
+        unsigned long tcnt;
+        unsigned long tcfg1;
+        unsigned long tcfg0;
+
+        tcnt = TICK_MAX;  /* default value for tcnt */
+
+        /* configure the system for whichever machine is in use */
+
+        if (use_tclk1_12()) {
+                /* timer is at 12MHz, scaler is 1 */
+                timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
+                tcnt = 12000000 / HZ;
+
+                tcfg1 = __raw_readl(S3C2410_TCFG1);
+                tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
+                tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
+                __raw_writel(tcfg1, S3C2410_TCFG1);
+        } else {
+                unsigned long pclk;
+                struct clk *tscaler;
+
+                /* for the h1940 (and others), we use the pclk from the core
+                 * to generate the timer values. since values around 50 to
+                 * 70MHz are not values we can directly generate the timer
+                 * value from, we need to pre-scale and divide before using it.
+                 *
+                 * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
+                 * (8.45 ticks per usec)
+                 */
+
+                pclk = clk_get_rate(timerclk);
+
+                /* configure clock tick */
+
+                timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
+
+                tscaler = clk_get_parent(tdiv);
+
+                clk_set_rate(tscaler, pclk / 3);
+                clk_set_rate(tdiv, pclk / 6);
+                clk_set_parent(tin, tdiv);
+
+                tcnt = clk_get_rate(tin) / HZ;
+        }
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcfg0 = __raw_readl(S3C2410_TCFG0);
+        tcfg1 = __raw_readl(S3C2410_TCFG1);
+
+        /* timers reload after counting zero, so reduce the count by 1 */
+
+        tcnt--;
+
+        printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
+               tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
+
+        /* check to see if timer is within 16bit range... */
+        if (tcnt > TICK_MAX) {
+                panic("setup_timer: HZ is too small, cannot configure timer!");
+                return;
+        }
+
+        __raw_writel(tcfg1, S3C2410_TCFG1);
+        __raw_writel(tcfg0, S3C2410_TCFG0);
+
+        timer_startval = tcnt;
+        __raw_writel(tcnt, S3C2410_TCNTB(4));
+
+        /* ensure timer is stopped... */
+
+        tcon &= ~(7<<20);
+        tcon |= S3C2410_TCON_T4RELOAD;
+        tcon |= S3C2410_TCON_T4MANUALUPD;
+
+        __raw_writel(tcon, S3C2410_TCON);
+        __raw_writel(tcnt, S3C2410_TCNTB(4));
+        __raw_writel(tcnt, S3C2410_TCMPB(4));
+
+        /* start the timer running */
+        tcon |= S3C2410_TCON_T4START;
+        tcon &= ~S3C2410_TCON_T4MANUALUPD;
+        __raw_writel(tcon, S3C2410_TCON);
+}
+
+static void __init s3c2410_timer_resources(void)
+{
+        struct platform_device tmpdev;
+
+        tmpdev.dev.bus = &platform_bus_type;
+        tmpdev.id = 4;
+
+        timerclk = clk_get(NULL, "timers");
+        if (IS_ERR(timerclk))
+                panic("failed to get clock for system timer");
+
+        clk_enable(timerclk);
+
+        if (!use_tclk1_12()) {
+                tin = clk_get(&tmpdev.dev, "pwm-tin");
+                if (IS_ERR(tin))
+                        panic("failed to get pwm-tin clock for system timer");
+
+                tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
+                if (IS_ERR(tdiv))
+                        panic("failed to get pwm-tdiv clock for system timer");
+        }
+
+        clk_enable(tin);
+}
+
+static void __init s3c2410_timer_init(void)
+{
+        s3c2410_timer_resources();
+        s3c2410_timer_setup();
+        setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
+}
+
+struct sys_timer s3c24xx_timer = {
+        .init           = s3c2410_timer_init,
+        .offset         = s3c2410_gettimeoffset,
+        .resume         = s3c2410_timer_setup
+};