diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-01-27 17:11:32 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-01-27 17:11:32 -0500 |
commit | a814290e17ae314bd614476cffc6119846eca27e (patch) | |
tree | 9fc40e6a34cd275bedcd2344383bd5e84f6c20df /arch/arm/plat-s5pc1xx/include/plat/regs-clock.h | |
parent | e55d1936f207f81c4e225d6c513e0fa487e544c5 (diff) | |
parent | ab5d97db1c6ced3e95c00d097931471707032b1f (diff) |
Merge branch 'for-rmk/samsung3' of git://git.fluff.org/bjdooks/linux into devel-stable
Diffstat (limited to 'arch/arm/plat-s5pc1xx/include/plat/regs-clock.h')
-rw-r--r-- | arch/arm/plat-s5pc1xx/include/plat/regs-clock.h | 119 |
1 files changed, 6 insertions, 113 deletions
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h index c5cc86e92d6..24dec4e5253 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h | |||
@@ -61,73 +61,10 @@ | |||
61 | #define S5PC100_EPLL_MASK 0xffffffff | 61 | #define S5PC100_EPLL_MASK 0xffffffff |
62 | #define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) | 62 | #define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) |
63 | 63 | ||
64 | /* CLKSRC0 */ | 64 | /* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */ |
65 | #define S5PC100_CLKSRC0_APLL_MASK (0x1<<0) | 65 | #define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24) |
66 | #define S5PC100_CLKSRC0_APLL_SHIFT (0) | ||
67 | #define S5PC100_CLKSRC0_MPLL_MASK (0x1<<4) | ||
68 | #define S5PC100_CLKSRC0_MPLL_SHIFT (4) | ||
69 | #define S5PC100_CLKSRC0_EPLL_MASK (0x1<<8) | ||
70 | #define S5PC100_CLKSRC0_EPLL_SHIFT (8) | ||
71 | #define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12) | ||
72 | #define S5PC100_CLKSRC0_HPLL_SHIFT (12) | ||
73 | #define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16) | ||
74 | #define S5PC100_CLKSRC0_AMMUX_SHIFT (16) | ||
75 | #define S5PC100_CLKSRC0_HREF_MASK (0x1<<20) | ||
76 | #define S5PC100_CLKSRC0_HREF_SHIFT (20) | ||
77 | #define S5PC100_CLKSRC0_ONENAND_MASK (0x1<<24) | ||
78 | #define S5PC100_CLKSRC0_ONENAND_SHIFT (24) | ||
79 | |||
80 | |||
81 | /* CLKSRC1 */ | ||
82 | #define S5PC100_CLKSRC1_UART_MASK (0x1<<0) | ||
83 | #define S5PC100_CLKSRC1_UART_SHIFT (0) | ||
84 | #define S5PC100_CLKSRC1_SPI0_MASK (0x3<<4) | ||
85 | #define S5PC100_CLKSRC1_SPI0_SHIFT (4) | ||
86 | #define S5PC100_CLKSRC1_SPI1_MASK (0x3<<8) | ||
87 | #define S5PC100_CLKSRC1_SPI1_SHIFT (8) | ||
88 | #define S5PC100_CLKSRC1_SPI2_MASK (0x3<<12) | ||
89 | #define S5PC100_CLKSRC1_SPI2_SHIFT (12) | ||
90 | #define S5PC100_CLKSRC1_IRDA_MASK (0x3<<16) | ||
91 | #define S5PC100_CLKSRC1_IRDA_SHIFT (16) | ||
92 | #define S5PC100_CLKSRC1_UHOST_MASK (0x3<<20) | ||
93 | #define S5PC100_CLKSRC1_UHOST_SHIFT (20) | ||
94 | #define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24) | ||
95 | #define S5PC100_CLKSRC1_CLK48M_SHIFT (24) | 66 | #define S5PC100_CLKSRC1_CLK48M_SHIFT (24) |
96 | 67 | ||
97 | /* CLKSRC2 */ | ||
98 | #define S5PC100_CLKSRC2_MMC0_MASK (0x3<<0) | ||
99 | #define S5PC100_CLKSRC2_MMC0_SHIFT (0) | ||
100 | #define S5PC100_CLKSRC2_MMC1_MASK (0x3<<4) | ||
101 | #define S5PC100_CLKSRC2_MMC1_SHIFT (4) | ||
102 | #define S5PC100_CLKSRC2_MMC2_MASK (0x3<<8) | ||
103 | #define S5PC100_CLKSRC2_MMC2_SHIFT (8) | ||
104 | #define S5PC100_CLKSRC2_LCD_MASK (0x3<<12) | ||
105 | #define S5PC100_CLKSRC2_LCD_SHIFT (12) | ||
106 | #define S5PC100_CLKSRC2_FIMC0_MASK (0x3<<16) | ||
107 | #define S5PC100_CLKSRC2_FIMC0_SHIFT (16) | ||
108 | #define S5PC100_CLKSRC2_FIMC1_MASK (0x3<<20) | ||
109 | #define S5PC100_CLKSRC2_FIMC1_SHIFT (20) | ||
110 | #define S5PC100_CLKSRC2_FIMC2_MASK (0x3<<24) | ||
111 | #define S5PC100_CLKSRC2_FIMC2_SHIFT (24) | ||
112 | #define S5PC100_CLKSRC2_MIXER_MASK (0x3<<28) | ||
113 | #define S5PC100_CLKSRC2_MIXER_SHIFT (28) | ||
114 | |||
115 | /* CLKSRC3 */ | ||
116 | #define S5PC100_CLKSRC3_PWI_MASK (0x3<<0) | ||
117 | #define S5PC100_CLKSRC3_PWI_SHIFT (0) | ||
118 | #define S5PC100_CLKSRC3_HCLKD2_MASK (0x1<<4) | ||
119 | #define S5PC100_CLKSRC3_HCLKD2_SHIFT (4) | ||
120 | #define S5PC100_CLKSRC3_I2SD2_MASK (0x3<<8) | ||
121 | #define S5PC100_CLKSRC3_I2SD2_SHIFT (8) | ||
122 | #define S5PC100_CLKSRC3_AUDIO0_MASK (0x7<<12) | ||
123 | #define S5PC100_CLKSRC3_AUDIO0_SHIFT (12) | ||
124 | #define S5PC100_CLKSRC3_AUDIO1_MASK (0x7<<16) | ||
125 | #define S5PC100_CLKSRC3_AUDIO1_SHIFT (16) | ||
126 | #define S5PC100_CLKSRC3_AUDIO2_MASK (0x7<<20) | ||
127 | #define S5PC100_CLKSRC3_AUDIO2_SHIFT (20) | ||
128 | #define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24) | ||
129 | #define S5PC100_CLKSRC3_SPDIF_SHIFT (24) | ||
130 | |||
131 | /* CLKDIV0 */ | 68 | /* CLKDIV0 */ |
132 | #define S5PC100_CLKDIV0_APLL_MASK (0x1<<0) | 69 | #define S5PC100_CLKDIV0_APLL_MASK (0x1<<0) |
133 | #define S5PC100_CLKDIV0_APLL_SHIFT (0) | 70 | #define S5PC100_CLKDIV0_APLL_SHIFT (0) |
@@ -140,7 +77,7 @@ | |||
140 | #define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16) | 77 | #define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16) |
141 | #define S5PC100_CLKDIV0_SECSS_SHIFT (16) | 78 | #define S5PC100_CLKDIV0_SECSS_SHIFT (16) |
142 | 79 | ||
143 | /* CLKDIV1 */ | 80 | /* CLKDIV1 (OneNAND clock only used in one place, removed) */ |
144 | #define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0) | 81 | #define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0) |
145 | #define S5PC100_CLKDIV1_APLL2_SHIFT (0) | 82 | #define S5PC100_CLKDIV1_APLL2_SHIFT (0) |
146 | #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) | 83 | #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) |
@@ -151,56 +88,12 @@ | |||
151 | #define S5PC100_CLKDIV1_D1_SHIFT (12) | 88 | #define S5PC100_CLKDIV1_D1_SHIFT (12) |
152 | #define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16) | 89 | #define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16) |
153 | #define S5PC100_CLKDIV1_PCLKD1_SHIFT (16) | 90 | #define S5PC100_CLKDIV1_PCLKD1_SHIFT (16) |
154 | #define S5PC100_CLKDIV1_ONENAND_MASK (0x3<<20) | ||
155 | #define S5PC100_CLKDIV1_ONENAND_SHIFT (20) | ||
156 | #define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24) | 91 | #define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24) |
157 | #define S5PC100_CLKDIV1_CAM_SHIFT (24) | 92 | #define S5PC100_CLKDIV1_CAM_SHIFT (24) |
158 | 93 | ||
159 | /* CLKDIV2 */ | 94 | /* CLKDIV2 => removed in clksrc update */ |
160 | #define S5PC100_CLKDIV2_UART_MASK (0x7<<0) | 95 | /* CLKDIV3 => removed in clksrc update, or not needed */ |
161 | #define S5PC100_CLKDIV2_UART_SHIFT (0) | 96 | /* CLKDIV4 => removed in clksrc update, or not needed */ |
162 | #define S5PC100_CLKDIV2_SPI0_MASK (0xf<<4) | ||
163 | #define S5PC100_CLKDIV2_SPI0_SHIFT (4) | ||
164 | #define S5PC100_CLKDIV2_SPI1_MASK (0xf<<8) | ||
165 | #define S5PC100_CLKDIV2_SPI1_SHIFT (8) | ||
166 | #define S5PC100_CLKDIV2_SPI2_MASK (0xf<<12) | ||
167 | #define S5PC100_CLKDIV2_SPI2_SHIFT (12) | ||
168 | #define S5PC100_CLKDIV2_IRDA_MASK (0xf<<16) | ||
169 | #define S5PC100_CLKDIV2_IRDA_SHIFT (16) | ||
170 | #define S5PC100_CLKDIV2_UHOST_MASK (0xf<<20) | ||
171 | #define S5PC100_CLKDIV2_UHOST_SHIFT (20) | ||
172 | |||
173 | /* CLKDIV3 */ | ||
174 | #define S5PC100_CLKDIV3_MMC0_MASK (0xf<<0) | ||
175 | #define S5PC100_CLKDIV3_MMC0_SHIFT (0) | ||
176 | #define S5PC100_CLKDIV3_MMC1_MASK (0xf<<4) | ||
177 | #define S5PC100_CLKDIV3_MMC1_SHIFT (4) | ||
178 | #define S5PC100_CLKDIV3_MMC2_MASK (0xf<<8) | ||
179 | #define S5PC100_CLKDIV3_MMC2_SHIFT (8) | ||
180 | #define S5PC100_CLKDIV3_LCD_MASK (0xf<<12) | ||
181 | #define S5PC100_CLKDIV3_LCD_SHIFT (12) | ||
182 | #define S5PC100_CLKDIV3_FIMC0_MASK (0xf<<16) | ||
183 | #define S5PC100_CLKDIV3_FIMC0_SHIFT (16) | ||
184 | #define S5PC100_CLKDIV3_FIMC1_MASK (0xf<<20) | ||
185 | #define S5PC100_CLKDIV3_FIMC1_SHIFT (20) | ||
186 | #define S5PC100_CLKDIV3_FIMC2_MASK (0xf<<24) | ||
187 | #define S5PC100_CLKDIV3_FIMC2_SHIFT (24) | ||
188 | #define S5PC100_CLKDIV3_HDMI_MASK (0xf<<28) | ||
189 | #define S5PC100_CLKDIV3_HDMI_SHIFT (28) | ||
190 | |||
191 | /* CLKDIV4 */ | ||
192 | #define S5PC100_CLKDIV4_PWI_MASK (0x7<<0) | ||
193 | #define S5PC100_CLKDIV4_PWI_SHIFT (0) | ||
194 | #define S5PC100_CLKDIV4_HCLKD2_MASK (0x7<<4) | ||
195 | #define S5PC100_CLKDIV4_HCLKD2_SHIFT (4) | ||
196 | #define S5PC100_CLKDIV4_I2SD2_MASK (0xf<<8) | ||
197 | #define S5PC100_CLKDIV4_I2SD2_SHIFT (8) | ||
198 | #define S5PC100_CLKDIV4_AUDIO0_MASK (0xf<<12) | ||
199 | #define S5PC100_CLKDIV4_AUDIO0_SHIFT (12) | ||
200 | #define S5PC100_CLKDIV4_AUDIO1_MASK (0xf<<16) | ||
201 | #define S5PC100_CLKDIV4_AUDIO1_SHIFT (16) | ||
202 | #define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20) | ||
203 | #define S5PC100_CLKDIV4_AUDIO2_SHIFT (20) | ||
204 | 97 | ||
205 | /* HCLKD0/PCLKD0 Clock Gate 0 Registers */ | 98 | /* HCLKD0/PCLKD0 Clock Gate 0 Registers */ |
206 | #define S5PC100_CLKGATE_D00_INTC (1<<0) | 99 | #define S5PC100_CLKGATE_D00_INTC (1<<0) |