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authorKukjin Kim <kgene.kim@samsung.com>2012-03-02 18:57:03 -0500
committerKukjin Kim <kgene.kim@samsung.com>2012-03-07 04:36:33 -0500
commit880bcd4a8363f24375027f9ded4670960dcfa70a (patch)
tree31894d9dc2c29f31234e479de520a50858cce54c /arch/arm/plat-s3c24xx
parenta5f17d1f4c2831b9b9bf8b1a537cdbac995d6e13 (diff)
parent8c3d7c30c306d83ff9c303f42307765a5a7bc254 (diff)
Merge branch 'topic/cleanup-s3c24xx' into next/cleanup-s3c24xx
Conflicts: arch/arm/mach-s3c24xx/include/mach/system.h
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig34
-rw-r--r--arch/arm/plat-s3c24xx/Makefile11
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c636
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c36
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c38
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c36
6 files changed, 6 insertions, 785 deletions
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index d8973ac46bc..74f76e023e4 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -4,7 +4,7 @@
4 4
5config PLAT_S3C24XX 5config PLAT_S3C24XX
6 bool 6 bool
7 depends on ARCH_S3C2410 7 depends on ARCH_S3C24XX
8 default y 8 default y
9 select NO_IOPORT 9 select NO_IOPORT
10 select ARCH_REQUIRE_GPIOLIB 10 select ARCH_REQUIRE_GPIOLIB
@@ -44,12 +44,6 @@ config S3C2410_CLOCK
44 Clock code for the S3C2410, and similar processors which 44 Clock code for the S3C2410, and similar processors which
45 is currently includes the S3C2410, S3C2440, S3C2442. 45 is currently includes the S3C2410, S3C2440, S3C2442.
46 46
47config S3C2443_CLOCK
48 bool
49 help
50 Clock code for the S3C2443 and similar processors, which includes
51 the S3C2416 and S3C2450.
52
53config S3C24XX_DCLK 47config S3C24XX_DCLK
54 bool 48 bool
55 help 49 help
@@ -82,9 +76,9 @@ config PM_SIMTEC
82 Common power management code for systems that are 76 Common power management code for systems that are
83 compatible with the Simtec style of power management 77 compatible with the Simtec style of power management
84 78
85config S3C2410_DMA 79config S3C24XX_DMA
86 bool "S3C2410 DMA support" 80 bool "S3C2410 DMA support"
87 depends on ARCH_S3C2410 81 depends on ARCH_S3C24XX
88 select S3C_DMA 82 select S3C_DMA
89 help 83 help
90 S3C2410 DMA support. This is needed for drivers like sound which 84 S3C2410 DMA support. This is needed for drivers like sound which
@@ -93,31 +87,11 @@ config S3C2410_DMA
93 87
94config S3C2410_DMA_DEBUG 88config S3C2410_DMA_DEBUG
95 bool "S3C2410 DMA support debug" 89 bool "S3C2410 DMA support debug"
96 depends on ARCH_S3C2410 && S3C2410_DMA 90 depends on ARCH_S3C24XX && S3C2410_DMA
97 help 91 help
98 Enable debugging output for the DMA code. This option sends info 92 Enable debugging output for the DMA code. This option sends info
99 to the kernel log, at priority KERN_DEBUG. 93 to the kernel log, at priority KERN_DEBUG.
100 94
101# SPI default pin configuration code
102
103config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13
104 bool
105 help
106 SPI GPIO configuration code for BUS0 when connected to
107 GPE11, GPE12 and GPE13.
108
109config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7
110 bool
111 help
112 SPI GPIO configuration code for BUS 1 when connected to
113 GPG5, GPG6 and GPG7.
114
115config S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10
116 bool
117 help
118 SPI GPIO configuration code for BUS 1 when connected to
119 GPD8, GPD9 and GPD10.
120
121# common code for s3c24xx based machines, such as the SMDKs. 95# common code for s3c24xx based machines, such as the SMDKs.
122 96
123# cpu frequency items common between s3c2410 and s3c2440/s3c2442 97# cpu frequency items common between s3c2410 and s3c2440/s3c2442
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index b2b01125de6..a7e8843486b 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -28,22 +28,15 @@ obj-$(CONFIG_PM) += pm.o
28obj-$(CONFIG_PM) += irq-pm.o 28obj-$(CONFIG_PM) += irq-pm.o
29obj-$(CONFIG_PM) += sleep.o 29obj-$(CONFIG_PM) += sleep.o
30obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o 30obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
31obj-$(CONFIG_S3C2443_CLOCK) += s3c2443-clock.o 31obj-$(CONFIG_S3C24XX_DMA) += dma.o
32obj-$(CONFIG_S3C2410_DMA) += dma.o
33obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o 32obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o
34obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o 33obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o
35obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o 34obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
36 35
37# device specific setup and/or initialisation 36# device specific setup and/or initialisation
38obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o 37obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o
39obj-$(CONFIG_S3C2410_SETUP_TS) += setup-ts.o 38obj-$(CONFIG_S3C2410_SETUP_TS) += setup-ts.o
40 39
41# SPI gpio central GPIO functions
42
43obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o
44obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7) += spi-bus1-gpg5_6_7.o
45obj-$(CONFIG_S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10) += spi-bus1-gpd8_9_10.o
46
47# machine common support 40# machine common support
48 41
49obj-$(CONFIG_MACH_SMDK) += common-smdk.o 42obj-$(CONFIG_MACH_SMDK) += common-smdk.o
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
deleted file mode 100644
index 95e68190d59..00000000000
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ /dev/null
@@ -1,636 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
2 *
3 * Copyright (c) 2007, 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2443 Clock control suport - common code
7 */
8
9#include <linux/init.h>
10#include <linux/clk.h>
11#include <linux/io.h>
12
13#include <mach/regs-s3c2443-clock.h>
14
15#include <plat/s3c2443.h>
16#include <plat/clock.h>
17#include <plat/clock-clksrc.h>
18#include <plat/cpu.h>
19
20#include <plat/cpu-freq.h>
21
22
23static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
24{
25 u32 ctrlbit = clk->ctrlbit;
26 u32 con = __raw_readl(reg);
27
28 if (enable)
29 con |= ctrlbit;
30 else
31 con &= ~ctrlbit;
32
33 __raw_writel(con, reg);
34 return 0;
35}
36
37int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
38{
39 return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
40}
41
42int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
43{
44 return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
45}
46
47int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
48{
49 return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
50}
51
52/* mpllref is a direct descendant of clk_xtal by default, but it is not
53 * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
54 * such directly equating the two source clocks is impossible.
55 */
56struct clk clk_mpllref = {
57 .name = "mpllref",
58 .parent = &clk_xtal,
59};
60
61static struct clk *clk_epllref_sources[] = {
62 [0] = &clk_mpllref,
63 [1] = &clk_mpllref,
64 [2] = &clk_xtal,
65 [3] = &clk_ext,
66};
67
68struct clksrc_clk clk_epllref = {
69 .clk = {
70 .name = "epllref",
71 },
72 .sources = &(struct clksrc_sources) {
73 .sources = clk_epllref_sources,
74 .nr_sources = ARRAY_SIZE(clk_epllref_sources),
75 },
76 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
77};
78
79/* esysclk
80 *
81 * this is sourced from either the EPLL or the EPLLref clock
82*/
83
84static struct clk *clk_sysclk_sources[] = {
85 [0] = &clk_epllref.clk,
86 [1] = &clk_epll,
87};
88
89struct clksrc_clk clk_esysclk = {
90 .clk = {
91 .name = "esysclk",
92 .parent = &clk_epll,
93 },
94 .sources = &(struct clksrc_sources) {
95 .sources = clk_sysclk_sources,
96 .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
97 },
98 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
99};
100
101static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
102{
103 unsigned long parent_rate = clk_get_rate(clk->parent);
104 unsigned long div = __raw_readl(S3C2443_CLKDIV0);
105
106 div &= S3C2443_CLKDIV0_EXTDIV_MASK;
107 div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
108
109 return parent_rate / (div + 1);
110}
111
112static struct clk clk_mdivclk = {
113 .name = "mdivclk",
114 .parent = &clk_mpllref,
115 .ops = &(struct clk_ops) {
116 .get_rate = s3c2443_getrate_mdivclk,
117 },
118};
119
120static struct clk *clk_msysclk_sources[] = {
121 [0] = &clk_mpllref,
122 [1] = &clk_mpll,
123 [2] = &clk_mdivclk,
124 [3] = &clk_mpllref,
125};
126
127struct clksrc_clk clk_msysclk = {
128 .clk = {
129 .name = "msysclk",
130 .parent = &clk_xtal,
131 },
132 .sources = &(struct clksrc_sources) {
133 .sources = clk_msysclk_sources,
134 .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
135 },
136 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
137};
138
139/* prediv
140 *
141 * this divides the msysclk down to pass to h/p/etc.
142 */
143
144static unsigned long s3c2443_prediv_getrate(struct clk *clk)
145{
146 unsigned long rate = clk_get_rate(clk->parent);
147 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
148
149 clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
150 clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
151
152 return rate / (clkdiv0 + 1);
153}
154
155static struct clk clk_prediv = {
156 .name = "prediv",
157 .parent = &clk_msysclk.clk,
158 .ops = &(struct clk_ops) {
159 .get_rate = s3c2443_prediv_getrate,
160 },
161};
162
163/* armdiv
164 *
165 * this clock is sourced from msysclk and can have a number of
166 * divider values applied to it to then be fed into armclk.
167*/
168
169static unsigned int *armdiv;
170static int nr_armdiv;
171static int armdivmask;
172
173static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
174 unsigned long rate)
175{
176 unsigned long parent = clk_get_rate(clk->parent);
177 unsigned long calc;
178 unsigned best = 256; /* bigger than any value */
179 unsigned div;
180 int ptr;
181
182 if (!nr_armdiv)
183 return -EINVAL;
184
185 for (ptr = 0; ptr < nr_armdiv; ptr++) {
186 div = armdiv[ptr];
187 if (div) {
188 /* cpufreq provides 266mhz as 266666000 not 266666666 */
189 calc = (parent / div / 1000) * 1000;
190 if (calc <= rate && div < best)
191 best = div;
192 }
193 }
194
195 return parent / best;
196}
197
198static unsigned long s3c2443_armclk_getrate(struct clk *clk)
199{
200 unsigned long rate = clk_get_rate(clk->parent);
201 unsigned long clkcon0;
202 int val;
203
204 if (!nr_armdiv || !armdivmask)
205 return -EINVAL;
206
207 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
208 clkcon0 &= armdivmask;
209 val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT;
210
211 return rate / armdiv[val];
212}
213
214static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
215{
216 unsigned long parent = clk_get_rate(clk->parent);
217 unsigned long calc;
218 unsigned div;
219 unsigned best = 256; /* bigger than any value */
220 int ptr;
221 int val = -1;
222
223 if (!nr_armdiv || !armdivmask)
224 return -EINVAL;
225
226 for (ptr = 0; ptr < nr_armdiv; ptr++) {
227 div = armdiv[ptr];
228 if (div) {
229 /* cpufreq provides 266mhz as 266666000 not 266666666 */
230 calc = (parent / div / 1000) * 1000;
231 if (calc <= rate && div < best) {
232 best = div;
233 val = ptr;
234 }
235 }
236 }
237
238 if (val >= 0) {
239 unsigned long clkcon0;
240
241 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
242 clkcon0 &= ~armdivmask;
243 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
244 __raw_writel(clkcon0, S3C2443_CLKDIV0);
245 }
246
247 return (val == -1) ? -EINVAL : 0;
248}
249
250static struct clk clk_armdiv = {
251 .name = "armdiv",
252 .parent = &clk_msysclk.clk,
253 .ops = &(struct clk_ops) {
254 .round_rate = s3c2443_armclk_roundrate,
255 .get_rate = s3c2443_armclk_getrate,
256 .set_rate = s3c2443_armclk_setrate,
257 },
258};
259
260/* armclk
261 *
262 * this is the clock fed into the ARM core itself, from armdiv or from hclk.
263 */
264
265static struct clk *clk_arm_sources[] = {
266 [0] = &clk_armdiv,
267 [1] = &clk_h,
268};
269
270static struct clksrc_clk clk_arm = {
271 .clk = {
272 .name = "armclk",
273 },
274 .sources = &(struct clksrc_sources) {
275 .sources = clk_arm_sources,
276 .nr_sources = ARRAY_SIZE(clk_arm_sources),
277 },
278 .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
279};
280
281/* usbhost
282 *
283 * usb host bus-clock, usually 48MHz to provide USB bus clock timing
284*/
285
286static struct clksrc_clk clk_usb_bus_host = {
287 .clk = {
288 .name = "usb-bus-host-parent",
289 .parent = &clk_esysclk.clk,
290 .ctrlbit = S3C2443_SCLKCON_USBHOST,
291 .enable = s3c2443_clkcon_enable_s,
292 },
293 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
294};
295
296/* common clksrc clocks */
297
298static struct clksrc_clk clksrc_clks[] = {
299 {
300 /* camera interface bus-clock, divided down from esysclk */
301 .clk = {
302 .name = "camif-upll", /* same as 2440 name */
303 .parent = &clk_esysclk.clk,
304 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
305 .enable = s3c2443_clkcon_enable_s,
306 },
307 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
308 }, {
309 .clk = {
310 .name = "display-if",
311 .parent = &clk_esysclk.clk,
312 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
313 .enable = s3c2443_clkcon_enable_s,
314 },
315 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
316 },
317};
318
319static struct clksrc_clk clk_esys_uart = {
320 /* ART baud-rate clock sourced from esysclk via a divisor */
321 .clk = {
322 .name = "uartclk",
323 .parent = &clk_esysclk.clk,
324 },
325 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
326};
327
328static struct clk clk_i2s_ext = {
329 .name = "i2s-ext",
330};
331
332/* i2s_eplldiv
333 *
334 * This clock is the output from the I2S divisor of ESYSCLK, and is separate
335 * from the mux that comes after it (cannot merge into one single clock)
336*/
337
338static struct clksrc_clk clk_i2s_eplldiv = {
339 .clk = {
340 .name = "i2s-eplldiv",
341 .parent = &clk_esysclk.clk,
342 },
343 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
344};
345
346/* i2s-ref
347 *
348 * i2s bus reference clock, selectable from external, esysclk or epllref
349 *
350 * Note, this used to be two clocks, but was compressed into one.
351*/
352
353static struct clk *clk_i2s_srclist[] = {
354 [0] = &clk_i2s_eplldiv.clk,
355 [1] = &clk_i2s_ext,
356 [2] = &clk_epllref.clk,
357 [3] = &clk_epllref.clk,
358};
359
360static struct clksrc_clk clk_i2s = {
361 .clk = {
362 .name = "i2s-if",
363 .ctrlbit = S3C2443_SCLKCON_I2SCLK,
364 .enable = s3c2443_clkcon_enable_s,
365
366 },
367 .sources = &(struct clksrc_sources) {
368 .sources = clk_i2s_srclist,
369 .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
370 },
371 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
372};
373
374static struct clk init_clocks_off[] = {
375 {
376 .name = "iis",
377 .parent = &clk_p,
378 .enable = s3c2443_clkcon_enable_p,
379 .ctrlbit = S3C2443_PCLKCON_IIS,
380 }, {
381 .name = "hsspi",
382 .parent = &clk_p,
383 .enable = s3c2443_clkcon_enable_p,
384 .ctrlbit = S3C2443_PCLKCON_HSSPI,
385 }, {
386 .name = "adc",
387 .parent = &clk_p,
388 .enable = s3c2443_clkcon_enable_p,
389 .ctrlbit = S3C2443_PCLKCON_ADC,
390 }, {
391 .name = "i2c",
392 .parent = &clk_p,
393 .enable = s3c2443_clkcon_enable_p,
394 .ctrlbit = S3C2443_PCLKCON_IIC,
395 }
396};
397
398static struct clk init_clocks[] = {
399 {
400 .name = "dma",
401 .parent = &clk_h,
402 .enable = s3c2443_clkcon_enable_h,
403 .ctrlbit = S3C2443_HCLKCON_DMA0,
404 }, {
405 .name = "dma",
406 .parent = &clk_h,
407 .enable = s3c2443_clkcon_enable_h,
408 .ctrlbit = S3C2443_HCLKCON_DMA1,
409 }, {
410 .name = "dma",
411 .parent = &clk_h,
412 .enable = s3c2443_clkcon_enable_h,
413 .ctrlbit = S3C2443_HCLKCON_DMA2,
414 }, {
415 .name = "dma",
416 .parent = &clk_h,
417 .enable = s3c2443_clkcon_enable_h,
418 .ctrlbit = S3C2443_HCLKCON_DMA3,
419 }, {
420 .name = "dma",
421 .parent = &clk_h,
422 .enable = s3c2443_clkcon_enable_h,
423 .ctrlbit = S3C2443_HCLKCON_DMA4,
424 }, {
425 .name = "dma",
426 .parent = &clk_h,
427 .enable = s3c2443_clkcon_enable_h,
428 .ctrlbit = S3C2443_HCLKCON_DMA5,
429 }, {
430 .name = "gpio",
431 .parent = &clk_p,
432 .enable = s3c2443_clkcon_enable_p,
433 .ctrlbit = S3C2443_PCLKCON_GPIO,
434 }, {
435 .name = "usb-host",
436 .parent = &clk_h,
437 .enable = s3c2443_clkcon_enable_h,
438 .ctrlbit = S3C2443_HCLKCON_USBH,
439 }, {
440 .name = "usb-device",
441 .parent = &clk_h,
442 .enable = s3c2443_clkcon_enable_h,
443 .ctrlbit = S3C2443_HCLKCON_USBD,
444 }, {
445 .name = "lcd",
446 .parent = &clk_h,
447 .enable = s3c2443_clkcon_enable_h,
448 .ctrlbit = S3C2443_HCLKCON_LCDC,
449
450 }, {
451 .name = "timers",
452 .parent = &clk_p,
453 .enable = s3c2443_clkcon_enable_p,
454 .ctrlbit = S3C2443_PCLKCON_PWMT,
455 }, {
456 .name = "cfc",
457 .parent = &clk_h,
458 .enable = s3c2443_clkcon_enable_h,
459 .ctrlbit = S3C2443_HCLKCON_CFC,
460 }, {
461 .name = "ssmc",
462 .parent = &clk_h,
463 .enable = s3c2443_clkcon_enable_h,
464 .ctrlbit = S3C2443_HCLKCON_SSMC,
465 }, {
466 .name = "uart",
467 .devname = "s3c2440-uart.0",
468 .parent = &clk_p,
469 .enable = s3c2443_clkcon_enable_p,
470 .ctrlbit = S3C2443_PCLKCON_UART0,
471 }, {
472 .name = "uart",
473 .devname = "s3c2440-uart.1",
474 .parent = &clk_p,
475 .enable = s3c2443_clkcon_enable_p,
476 .ctrlbit = S3C2443_PCLKCON_UART1,
477 }, {
478 .name = "uart",
479 .devname = "s3c2440-uart.2",
480 .parent = &clk_p,
481 .enable = s3c2443_clkcon_enable_p,
482 .ctrlbit = S3C2443_PCLKCON_UART2,
483 }, {
484 .name = "uart",
485 .devname = "s3c2440-uart.3",
486 .parent = &clk_p,
487 .enable = s3c2443_clkcon_enable_p,
488 .ctrlbit = S3C2443_PCLKCON_UART3,
489 }, {
490 .name = "rtc",
491 .parent = &clk_p,
492 .enable = s3c2443_clkcon_enable_p,
493 .ctrlbit = S3C2443_PCLKCON_RTC,
494 }, {
495 .name = "watchdog",
496 .parent = &clk_p,
497 .ctrlbit = S3C2443_PCLKCON_WDT,
498 }, {
499 .name = "ac97",
500 .parent = &clk_p,
501 .ctrlbit = S3C2443_PCLKCON_AC97,
502 }, {
503 .name = "nand",
504 .parent = &clk_h,
505 }, {
506 .name = "usb-bus-host",
507 .parent = &clk_usb_bus_host.clk,
508 }
509};
510
511static struct clk hsmmc1_clk = {
512 .name = "hsmmc",
513 .devname = "s3c-sdhci.1",
514 .parent = &clk_h,
515 .enable = s3c2443_clkcon_enable_h,
516 .ctrlbit = S3C2443_HCLKCON_HSMMC,
517};
518
519static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
520{
521 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
522
523 return clkcon0 + 1;
524}
525
526/* EPLLCON compatible enough to get on/off information */
527
528void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
529{
530 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
531 unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
532 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
533 struct clk *xtal_clk;
534 unsigned long xtal;
535 unsigned long pll;
536 unsigned long fclk;
537 unsigned long hclk;
538 unsigned long pclk;
539 int ptr;
540
541 xtal_clk = clk_get(NULL, "xtal");
542 xtal = clk_get_rate(xtal_clk);
543 clk_put(xtal_clk);
544
545 pll = get_mpll(mpllcon, xtal);
546 clk_msysclk.clk.rate = pll;
547
548 fclk = clk_get_rate(&clk_armdiv);
549 hclk = s3c2443_prediv_getrate(&clk_prediv);
550 hclk /= s3c2443_get_hdiv(clkdiv0);
551 pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
552
553 s3c24xx_setup_clocks(fclk, hclk, pclk);
554
555 printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
556 (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
557 print_mhz(pll), print_mhz(fclk),
558 print_mhz(hclk), print_mhz(pclk));
559
560 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
561 s3c_set_clksrc(&clksrc_clks[ptr], true);
562
563 /* ensure usb bus clock is within correct rate of 48MHz */
564
565 if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
566 printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
567 clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
568 }
569
570 printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
571 (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
572 print_mhz(clk_get_rate(&clk_epll)),
573 print_mhz(clk_get_rate(&clk_usb_bus)));
574}
575
576static struct clk *clks[] __initdata = {
577 &clk_prediv,
578 &clk_mpllref,
579 &clk_mdivclk,
580 &clk_ext,
581 &clk_epll,
582 &clk_usb_bus,
583 &clk_armdiv,
584 &hsmmc1_clk,
585};
586
587static struct clksrc_clk *clksrcs[] __initdata = {
588 &clk_i2s_eplldiv,
589 &clk_i2s,
590 &clk_usb_bus_host,
591 &clk_epllref,
592 &clk_esysclk,
593 &clk_msysclk,
594 &clk_arm,
595};
596
597static struct clk_lookup s3c2443_clk_lookup[] = {
598 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
599 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
600 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
601 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
602};
603
604void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
605 unsigned int *divs, int nr_divs,
606 int divmask)
607{
608 int ptr;
609
610 armdiv = divs;
611 nr_armdiv = nr_divs;
612 armdivmask = divmask;
613
614 /* s3c2443 parents h and p clocks from prediv */
615 clk_h.parent = &clk_prediv;
616 clk_p.parent = &clk_prediv;
617
618 clk_usb_bus.parent = &clk_usb_bus_host.clk;
619 clk_epll.parent = &clk_epllref.clk;
620
621 s3c24xx_register_baseclocks(xtal);
622 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
623
624 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
625 s3c_register_clksrc(clksrcs[ptr], 1);
626
627 s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
628 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
629
630 /* See s3c2443/etc notes on disabling clocks at init time */
631 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
632 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
633 clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
634
635 s3c2443_common_setup_clocks(get_mpll);
636}
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
deleted file mode 100644
index 704175b0573..00000000000
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ /dev/null
@@ -1,36 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12*/
13
14#include <linux/kernel.h>
15#include <linux/gpio.h>
16
17#include <mach/spi.h>
18#include <mach/regs-gpio.h>
19
20void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
21 int enable)
22{
23 if (enable) {
24 s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
25 s3c_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
26 s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
27 s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
28 s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
29 } else {
30 s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
31 s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
32 s3c_gpio_setpull(S3C2410_GPE(11), S3C_GPIO_PULL_NONE);
33 s3c_gpio_setpull(S3C2410_GPE(12), S3C_GPIO_PULL_NONE);
34 s3c_gpio_setpull(S3C2410_GPE(13), S3C_GPIO_PULL_NONE);
35 }
36}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
deleted file mode 100644
index 72457afd625..00000000000
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpd8_9_10.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX SPI - gpio configuration for bus 1 on gpd8,9,10
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12*/
13
14#include <linux/kernel.h>
15#include <linux/gpio.h>
16
17#include <mach/spi.h>
18#include <mach/regs-gpio.h>
19
20void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
21 int enable)
22{
23
24 printk(KERN_INFO "%s(%d)\n", __func__, enable);
25 if (enable) {
26 s3c_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1);
27 s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1);
28 s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1);
29 s3c2410_gpio_pullup(S3C2410_GPD(10), 0);
30 s3c2410_gpio_pullup(S3C2410_GPD(9), 0);
31 } else {
32 s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT);
33 s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT);
34 s3c_gpio_setpull(S3C2410_GPD(10), S3C_GPIO_PULL_NONE);
35 s3c_gpio_setpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE);
36 s3c_gpio_setpull(S3C2410_GPD(8), S3C_GPIO_PULL_NONE);
37 }
38}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
deleted file mode 100644
index c3972b645d1..00000000000
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ /dev/null
@@ -1,36 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12*/
13
14#include <linux/kernel.h>
15#include <linux/gpio.h>
16
17#include <mach/spi.h>
18#include <mach/regs-gpio.h>
19
20void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
21 int enable)
22{
23 if (enable) {
24 s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
25 s3c_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
26 s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
27 s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
28 s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
29 } else {
30 s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
31 s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
32 s3c_gpio_setpull(S3C2410_GPG(5), S3C_GPIO_PULL_NONE);
33 s3c_gpio_setpull(S3C2410_GPG(6), S3C_GPIO_PULL_NONE);
34 s3c_gpio_setpull(S3C2410_GPG(7), S3C_GPIO_PULL_NONE);
35 }
36}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-17 19:49:38 -0400