diff options
author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
---|---|---|
committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
commit | fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch) | |
tree | a57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/plat-s3c24xx | |
parent | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff) |
Diffstat (limited to 'arch/arm/plat-s3c24xx')
37 files changed, 3869 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c new file mode 100644 index 00000000000..931d26d1a54 --- /dev/null +++ b/arch/arm/plat-s3c24xx/clock.c | |||
@@ -0,0 +1,59 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/clock.c | ||
2 | * | ||
3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C24XX Core clock control support | ||
7 | * | ||
8 | * Based on, and code from linux/arch/arm/mach-versatile/clock.c | ||
9 | ** | ||
10 | ** Copyright (C) 2004 ARM Limited. | ||
11 | ** Written by Deep Blue Solutions Limited. | ||
12 | * | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License as published by | ||
16 | * the Free Software Foundation; either version 2 of the License, or | ||
17 | * (at your option) any later version. | ||
18 | * | ||
19 | * This program is distributed in the hope that it will be useful, | ||
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
22 | * GNU General Public License for more details. | ||
23 | * | ||
24 | * You should have received a copy of the GNU General Public License | ||
25 | * along with this program; if not, write to the Free Software | ||
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
27 | */ | ||
28 | |||
29 | #include <linux/init.h> | ||
30 | #include <linux/kernel.h> | ||
31 | #include <linux/clk.h> | ||
32 | #include <linux/io.h> | ||
33 | |||
34 | #include <mach/hardware.h> | ||
35 | #include <asm/irq.h> | ||
36 | |||
37 | #include <mach/regs-clock.h> | ||
38 | #include <mach/regs-gpio.h> | ||
39 | |||
40 | #include <plat/cpu-freq.h> | ||
41 | |||
42 | #include <plat/clock.h> | ||
43 | #include <plat/cpu.h> | ||
44 | #include <plat/pll.h> | ||
45 | |||
46 | /* initialise all the clocks */ | ||
47 | |||
48 | void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, | ||
49 | unsigned long hclk, | ||
50 | unsigned long pclk) | ||
51 | { | ||
52 | clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), | ||
53 | clk_xtal.rate); | ||
54 | |||
55 | clk_mpll.rate = fclk; | ||
56 | clk_h.rate = hclk; | ||
57 | clk_p.rate = pclk; | ||
58 | clk_f.rate = fclk; | ||
59 | } | ||
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c new file mode 100644 index 00000000000..bcc43f34627 --- /dev/null +++ b/arch/arm/plat-s3c24xx/common-smdk.c | |||
@@ -0,0 +1,207 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/common-smdk.c | ||
2 | * | ||
3 | * Copyright (c) 2006 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Common code for SMDK2410 and SMDK2440 boards | ||
7 | * | ||
8 | * http://www.fluff.org/ben/smdk2440/ | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/list.h> | ||
19 | #include <linux/timer.h> | ||
20 | #include <linux/init.h> | ||
21 | #include <linux/gpio.h> | ||
22 | #include <linux/sysdev.h> | ||
23 | #include <linux/platform_device.h> | ||
24 | |||
25 | #include <linux/mtd/mtd.h> | ||
26 | #include <linux/mtd/nand.h> | ||
27 | #include <linux/mtd/nand_ecc.h> | ||
28 | #include <linux/mtd/partitions.h> | ||
29 | #include <linux/io.h> | ||
30 | |||
31 | #include <asm/mach/arch.h> | ||
32 | #include <asm/mach/map.h> | ||
33 | #include <asm/mach/irq.h> | ||
34 | |||
35 | #include <asm/mach-types.h> | ||
36 | #include <mach/hardware.h> | ||
37 | #include <asm/irq.h> | ||
38 | |||
39 | #include <mach/regs-gpio.h> | ||
40 | #include <mach/leds-gpio.h> | ||
41 | |||
42 | #include <plat/nand.h> | ||
43 | |||
44 | #include <plat/common-smdk.h> | ||
45 | #include <plat/gpio-cfg.h> | ||
46 | #include <plat/devs.h> | ||
47 | #include <plat/pm.h> | ||
48 | |||
49 | /* LED devices */ | ||
50 | |||
51 | static struct s3c24xx_led_platdata smdk_pdata_led4 = { | ||
52 | .gpio = S3C2410_GPF(4), | ||
53 | .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, | ||
54 | .name = "led4", | ||
55 | .def_trigger = "timer", | ||
56 | }; | ||
57 | |||
58 | static struct s3c24xx_led_platdata smdk_pdata_led5 = { | ||
59 | .gpio = S3C2410_GPF(5), | ||
60 | .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, | ||
61 | .name = "led5", | ||
62 | .def_trigger = "nand-disk", | ||
63 | }; | ||
64 | |||
65 | static struct s3c24xx_led_platdata smdk_pdata_led6 = { | ||
66 | .gpio = S3C2410_GPF(6), | ||
67 | .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, | ||
68 | .name = "led6", | ||
69 | }; | ||
70 | |||
71 | static struct s3c24xx_led_platdata smdk_pdata_led7 = { | ||
72 | .gpio = S3C2410_GPF(7), | ||
73 | .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, | ||
74 | .name = "led7", | ||
75 | }; | ||
76 | |||
77 | static struct platform_device smdk_led4 = { | ||
78 | .name = "s3c24xx_led", | ||
79 | .id = 0, | ||
80 | .dev = { | ||
81 | .platform_data = &smdk_pdata_led4, | ||
82 | }, | ||
83 | }; | ||
84 | |||
85 | static struct platform_device smdk_led5 = { | ||
86 | .name = "s3c24xx_led", | ||
87 | .id = 1, | ||
88 | .dev = { | ||
89 | .platform_data = &smdk_pdata_led5, | ||
90 | }, | ||
91 | }; | ||
92 | |||
93 | static struct platform_device smdk_led6 = { | ||
94 | .name = "s3c24xx_led", | ||
95 | .id = 2, | ||
96 | .dev = { | ||
97 | .platform_data = &smdk_pdata_led6, | ||
98 | }, | ||
99 | }; | ||
100 | |||
101 | static struct platform_device smdk_led7 = { | ||
102 | .name = "s3c24xx_led", | ||
103 | .id = 3, | ||
104 | .dev = { | ||
105 | .platform_data = &smdk_pdata_led7, | ||
106 | }, | ||
107 | }; | ||
108 | |||
109 | /* NAND parititon from 2.4.18-swl5 */ | ||
110 | |||
111 | static struct mtd_partition smdk_default_nand_part[] = { | ||
112 | [0] = { | ||
113 | .name = "Boot Agent", | ||
114 | .size = SZ_16K, | ||
115 | .offset = 0, | ||
116 | }, | ||
117 | [1] = { | ||
118 | .name = "S3C2410 flash partition 1", | ||
119 | .offset = 0, | ||
120 | .size = SZ_2M, | ||
121 | }, | ||
122 | [2] = { | ||
123 | .name = "S3C2410 flash partition 2", | ||
124 | .offset = SZ_4M, | ||
125 | .size = SZ_4M, | ||
126 | }, | ||
127 | [3] = { | ||
128 | .name = "S3C2410 flash partition 3", | ||
129 | .offset = SZ_8M, | ||
130 | .size = SZ_2M, | ||
131 | }, | ||
132 | [4] = { | ||
133 | .name = "S3C2410 flash partition 4", | ||
134 | .offset = SZ_1M * 10, | ||
135 | .size = SZ_4M, | ||
136 | }, | ||
137 | [5] = { | ||
138 | .name = "S3C2410 flash partition 5", | ||
139 | .offset = SZ_1M * 14, | ||
140 | .size = SZ_1M * 10, | ||
141 | }, | ||
142 | [6] = { | ||
143 | .name = "S3C2410 flash partition 6", | ||
144 | .offset = SZ_1M * 24, | ||
145 | .size = SZ_1M * 24, | ||
146 | }, | ||
147 | [7] = { | ||
148 | .name = "S3C2410 flash partition 7", | ||
149 | .offset = SZ_1M * 48, | ||
150 | .size = MTDPART_SIZ_FULL, | ||
151 | } | ||
152 | }; | ||
153 | |||
154 | static struct s3c2410_nand_set smdk_nand_sets[] = { | ||
155 | [0] = { | ||
156 | .name = "NAND", | ||
157 | .nr_chips = 1, | ||
158 | .nr_partitions = ARRAY_SIZE(smdk_default_nand_part), | ||
159 | .partitions = smdk_default_nand_part, | ||
160 | }, | ||
161 | }; | ||
162 | |||
163 | /* choose a set of timings which should suit most 512Mbit | ||
164 | * chips and beyond. | ||
165 | */ | ||
166 | |||
167 | static struct s3c2410_platform_nand smdk_nand_info = { | ||
168 | .tacls = 20, | ||
169 | .twrph0 = 60, | ||
170 | .twrph1 = 20, | ||
171 | .nr_sets = ARRAY_SIZE(smdk_nand_sets), | ||
172 | .sets = smdk_nand_sets, | ||
173 | }; | ||
174 | |||
175 | /* devices we initialise */ | ||
176 | |||
177 | static struct platform_device __initdata *smdk_devs[] = { | ||
178 | &s3c_device_nand, | ||
179 | &smdk_led4, | ||
180 | &smdk_led5, | ||
181 | &smdk_led6, | ||
182 | &smdk_led7, | ||
183 | }; | ||
184 | |||
185 | void __init smdk_machine_init(void) | ||
186 | { | ||
187 | /* Configure the LEDs (even if we have no LED support)*/ | ||
188 | |||
189 | s3c_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT); | ||
190 | s3c_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT); | ||
191 | s3c_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT); | ||
192 | s3c_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT); | ||
193 | |||
194 | s3c2410_gpio_setpin(S3C2410_GPF(4), 1); | ||
195 | s3c2410_gpio_setpin(S3C2410_GPF(5), 1); | ||
196 | s3c2410_gpio_setpin(S3C2410_GPF(6), 1); | ||
197 | s3c2410_gpio_setpin(S3C2410_GPF(7), 1); | ||
198 | |||
199 | if (machine_is_smdk2443()) | ||
200 | smdk_nand_info.twrph0 = 50; | ||
201 | |||
202 | s3c_nand_set_platdata(&smdk_nand_info); | ||
203 | |||
204 | platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); | ||
205 | |||
206 | s3c_pm_init(); | ||
207 | } | ||
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c new file mode 100644 index 00000000000..c1fc6c6fac7 --- /dev/null +++ b/arch/arm/plat-s3c24xx/cpu.c | |||
@@ -0,0 +1,233 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/cpu.c | ||
2 | * | ||
3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX CPU Support | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | */ | ||
23 | |||
24 | |||
25 | #include <linux/init.h> | ||
26 | #include <linux/module.h> | ||
27 | #include <linux/interrupt.h> | ||
28 | #include <linux/ioport.h> | ||
29 | #include <linux/serial_core.h> | ||
30 | #include <linux/platform_device.h> | ||
31 | #include <linux/delay.h> | ||
32 | #include <linux/io.h> | ||
33 | |||
34 | #include <mach/hardware.h> | ||
35 | #include <asm/irq.h> | ||
36 | #include <asm/cacheflush.h> | ||
37 | |||
38 | #include <asm/mach/arch.h> | ||
39 | #include <asm/mach/map.h> | ||
40 | |||
41 | #include <mach/system-reset.h> | ||
42 | |||
43 | #include <mach/regs-gpio.h> | ||
44 | #include <plat/regs-serial.h> | ||
45 | |||
46 | #include <plat/cpu.h> | ||
47 | #include <plat/devs.h> | ||
48 | #include <plat/clock.h> | ||
49 | #include <plat/s3c2410.h> | ||
50 | #include <plat/s3c2412.h> | ||
51 | #include <plat/s3c2416.h> | ||
52 | #include <plat/s3c244x.h> | ||
53 | #include <plat/s3c2443.h> | ||
54 | |||
55 | /* table of supported CPUs */ | ||
56 | |||
57 | static const char name_s3c2410[] = "S3C2410"; | ||
58 | static const char name_s3c2412[] = "S3C2412"; | ||
59 | static const char name_s3c2416[] = "S3C2416/S3C2450"; | ||
60 | static const char name_s3c2440[] = "S3C2440"; | ||
61 | static const char name_s3c2442[] = "S3C2442"; | ||
62 | static const char name_s3c2442b[] = "S3C2442B"; | ||
63 | static const char name_s3c2443[] = "S3C2443"; | ||
64 | static const char name_s3c2410a[] = "S3C2410A"; | ||
65 | static const char name_s3c2440a[] = "S3C2440A"; | ||
66 | |||
67 | static struct cpu_table cpu_ids[] __initdata = { | ||
68 | { | ||
69 | .idcode = 0x32410000, | ||
70 | .idmask = 0xffffffff, | ||
71 | .map_io = s3c2410_map_io, | ||
72 | .init_clocks = s3c2410_init_clocks, | ||
73 | .init_uarts = s3c2410_init_uarts, | ||
74 | .init = s3c2410_init, | ||
75 | .name = name_s3c2410 | ||
76 | }, | ||
77 | { | ||
78 | .idcode = 0x32410002, | ||
79 | .idmask = 0xffffffff, | ||
80 | .map_io = s3c2410_map_io, | ||
81 | .init_clocks = s3c2410_init_clocks, | ||
82 | .init_uarts = s3c2410_init_uarts, | ||
83 | .init = s3c2410a_init, | ||
84 | .name = name_s3c2410a | ||
85 | }, | ||
86 | { | ||
87 | .idcode = 0x32440000, | ||
88 | .idmask = 0xffffffff, | ||
89 | .map_io = s3c2440_map_io, | ||
90 | .init_clocks = s3c244x_init_clocks, | ||
91 | .init_uarts = s3c244x_init_uarts, | ||
92 | .init = s3c2440_init, | ||
93 | .name = name_s3c2440 | ||
94 | }, | ||
95 | { | ||
96 | .idcode = 0x32440001, | ||
97 | .idmask = 0xffffffff, | ||
98 | .map_io = s3c2440_map_io, | ||
99 | .init_clocks = s3c244x_init_clocks, | ||
100 | .init_uarts = s3c244x_init_uarts, | ||
101 | .init = s3c2440_init, | ||
102 | .name = name_s3c2440a | ||
103 | }, | ||
104 | { | ||
105 | .idcode = 0x32440aaa, | ||
106 | .idmask = 0xffffffff, | ||
107 | .map_io = s3c2442_map_io, | ||
108 | .init_clocks = s3c244x_init_clocks, | ||
109 | .init_uarts = s3c244x_init_uarts, | ||
110 | .init = s3c2442_init, | ||
111 | .name = name_s3c2442 | ||
112 | }, | ||
113 | { | ||
114 | .idcode = 0x32440aab, | ||
115 | .idmask = 0xffffffff, | ||
116 | .map_io = s3c2442_map_io, | ||
117 | .init_clocks = s3c244x_init_clocks, | ||
118 | .init_uarts = s3c244x_init_uarts, | ||
119 | .init = s3c2442_init, | ||
120 | .name = name_s3c2442b | ||
121 | }, | ||
122 | { | ||
123 | .idcode = 0x32412001, | ||
124 | .idmask = 0xffffffff, | ||
125 | .map_io = s3c2412_map_io, | ||
126 | .init_clocks = s3c2412_init_clocks, | ||
127 | .init_uarts = s3c2412_init_uarts, | ||
128 | .init = s3c2412_init, | ||
129 | .name = name_s3c2412, | ||
130 | }, | ||
131 | { /* a newer version of the s3c2412 */ | ||
132 | .idcode = 0x32412003, | ||
133 | .idmask = 0xffffffff, | ||
134 | .map_io = s3c2412_map_io, | ||
135 | .init_clocks = s3c2412_init_clocks, | ||
136 | .init_uarts = s3c2412_init_uarts, | ||
137 | .init = s3c2412_init, | ||
138 | .name = name_s3c2412, | ||
139 | }, | ||
140 | { /* a strange version of the s3c2416 */ | ||
141 | .idcode = 0x32450003, | ||
142 | .idmask = 0xffffffff, | ||
143 | .map_io = s3c2416_map_io, | ||
144 | .init_clocks = s3c2416_init_clocks, | ||
145 | .init_uarts = s3c2416_init_uarts, | ||
146 | .init = s3c2416_init, | ||
147 | .name = name_s3c2416, | ||
148 | }, | ||
149 | { | ||
150 | .idcode = 0x32443001, | ||
151 | .idmask = 0xffffffff, | ||
152 | .map_io = s3c2443_map_io, | ||
153 | .init_clocks = s3c2443_init_clocks, | ||
154 | .init_uarts = s3c2443_init_uarts, | ||
155 | .init = s3c2443_init, | ||
156 | .name = name_s3c2443, | ||
157 | }, | ||
158 | }; | ||
159 | |||
160 | /* minimal IO mapping */ | ||
161 | |||
162 | static struct map_desc s3c_iodesc[] __initdata = { | ||
163 | IODESC_ENT(GPIO), | ||
164 | IODESC_ENT(IRQ), | ||
165 | IODESC_ENT(MEMCTRL), | ||
166 | IODESC_ENT(UART) | ||
167 | }; | ||
168 | |||
169 | /* read cpu identificaiton code */ | ||
170 | |||
171 | static unsigned long s3c24xx_read_idcode_v5(void) | ||
172 | { | ||
173 | #if defined(CONFIG_CPU_S3C2416) | ||
174 | /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */ | ||
175 | |||
176 | u32 gs = __raw_readl(S3C24XX_GSTATUS1); | ||
177 | |||
178 | /* test for s3c2416 or similar device */ | ||
179 | if ((gs >> 16) == 0x3245) | ||
180 | return gs; | ||
181 | #endif | ||
182 | |||
183 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | ||
184 | return __raw_readl(S3C2412_GSTATUS1); | ||
185 | #else | ||
186 | return 1UL; /* don't look like an 2400 */ | ||
187 | #endif | ||
188 | } | ||
189 | |||
190 | static unsigned long s3c24xx_read_idcode_v4(void) | ||
191 | { | ||
192 | return __raw_readl(S3C2410_GSTATUS1); | ||
193 | } | ||
194 | |||
195 | /* Hook for arm_pm_restart to ensure we execute the reset code | ||
196 | * with the caches enabled. It seems at least the S3C2440 has a problem | ||
197 | * resetting if there is bus activity interrupted by the reset. | ||
198 | */ | ||
199 | static void s3c24xx_pm_restart(char mode, const char *cmd) | ||
200 | { | ||
201 | if (mode != 's') { | ||
202 | unsigned long flags; | ||
203 | |||
204 | local_irq_save(flags); | ||
205 | __cpuc_flush_kern_all(); | ||
206 | __cpuc_flush_user_all(); | ||
207 | |||
208 | arch_reset(mode, cmd); | ||
209 | local_irq_restore(flags); | ||
210 | } | ||
211 | |||
212 | /* fallback, or unhandled */ | ||
213 | arm_machine_restart(mode, cmd); | ||
214 | } | ||
215 | |||
216 | void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) | ||
217 | { | ||
218 | unsigned long idcode = 0x0; | ||
219 | |||
220 | /* initialise the io descriptors we need for initialisation */ | ||
221 | iotable_init(mach_desc, size); | ||
222 | iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); | ||
223 | |||
224 | if (cpu_architecture() >= CPU_ARCH_ARMv5) { | ||
225 | idcode = s3c24xx_read_idcode_v5(); | ||
226 | } else { | ||
227 | idcode = s3c24xx_read_idcode_v4(); | ||
228 | } | ||
229 | |||
230 | arm_pm_restart = s3c24xx_pm_restart; | ||
231 | |||
232 | s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); | ||
233 | } | ||
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c new file mode 100644 index 00000000000..a76bf2df333 --- /dev/null +++ b/arch/arm/plat-s3c24xx/devs.c | |||
@@ -0,0 +1,528 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/devs.c | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Base S3C24XX platform device definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/types.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/list.h> | ||
18 | #include <linux/timer.h> | ||
19 | #include <linux/init.h> | ||
20 | #include <linux/serial_core.h> | ||
21 | #include <linux/platform_device.h> | ||
22 | #include <linux/io.h> | ||
23 | #include <linux/slab.h> | ||
24 | #include <linux/string.h> | ||
25 | #include <linux/dma-mapping.h> | ||
26 | |||
27 | #include <asm/mach/arch.h> | ||
28 | #include <asm/mach/map.h> | ||
29 | #include <asm/mach/irq.h> | ||
30 | #include <mach/fb.h> | ||
31 | #include <mach/hardware.h> | ||
32 | #include <mach/dma.h> | ||
33 | #include <mach/irqs.h> | ||
34 | #include <asm/irq.h> | ||
35 | |||
36 | #include <plat/regs-serial.h> | ||
37 | #include <plat/udc.h> | ||
38 | #include <plat/mci.h> | ||
39 | |||
40 | #include <plat/devs.h> | ||
41 | #include <plat/cpu.h> | ||
42 | #include <plat/regs-spi.h> | ||
43 | #include <plat/ts.h> | ||
44 | |||
45 | /* Serial port registrations */ | ||
46 | |||
47 | static struct resource s3c2410_uart0_resource[] = { | ||
48 | [0] = { | ||
49 | .start = S3C2410_PA_UART0, | ||
50 | .end = S3C2410_PA_UART0 + 0x3fff, | ||
51 | .flags = IORESOURCE_MEM, | ||
52 | }, | ||
53 | [1] = { | ||
54 | .start = IRQ_S3CUART_RX0, | ||
55 | .end = IRQ_S3CUART_ERR0, | ||
56 | .flags = IORESOURCE_IRQ, | ||
57 | } | ||
58 | }; | ||
59 | |||
60 | static struct resource s3c2410_uart1_resource[] = { | ||
61 | [0] = { | ||
62 | .start = S3C2410_PA_UART1, | ||
63 | .end = S3C2410_PA_UART1 + 0x3fff, | ||
64 | .flags = IORESOURCE_MEM, | ||
65 | }, | ||
66 | [1] = { | ||
67 | .start = IRQ_S3CUART_RX1, | ||
68 | .end = IRQ_S3CUART_ERR1, | ||
69 | .flags = IORESOURCE_IRQ, | ||
70 | } | ||
71 | }; | ||
72 | |||
73 | static struct resource s3c2410_uart2_resource[] = { | ||
74 | [0] = { | ||
75 | .start = S3C2410_PA_UART2, | ||
76 | .end = S3C2410_PA_UART2 + 0x3fff, | ||
77 | .flags = IORESOURCE_MEM, | ||
78 | }, | ||
79 | [1] = { | ||
80 | .start = IRQ_S3CUART_RX2, | ||
81 | .end = IRQ_S3CUART_ERR2, | ||
82 | .flags = IORESOURCE_IRQ, | ||
83 | } | ||
84 | }; | ||
85 | |||
86 | static struct resource s3c2410_uart3_resource[] = { | ||
87 | [0] = { | ||
88 | .start = S3C2443_PA_UART3, | ||
89 | .end = S3C2443_PA_UART3 + 0x3fff, | ||
90 | .flags = IORESOURCE_MEM, | ||
91 | }, | ||
92 | [1] = { | ||
93 | .start = IRQ_S3CUART_RX3, | ||
94 | .end = IRQ_S3CUART_ERR3, | ||
95 | .flags = IORESOURCE_IRQ, | ||
96 | }, | ||
97 | }; | ||
98 | |||
99 | struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { | ||
100 | [0] = { | ||
101 | .resources = s3c2410_uart0_resource, | ||
102 | .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource), | ||
103 | }, | ||
104 | [1] = { | ||
105 | .resources = s3c2410_uart1_resource, | ||
106 | .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource), | ||
107 | }, | ||
108 | [2] = { | ||
109 | .resources = s3c2410_uart2_resource, | ||
110 | .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), | ||
111 | }, | ||
112 | [3] = { | ||
113 | .resources = s3c2410_uart3_resource, | ||
114 | .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource), | ||
115 | }, | ||
116 | }; | ||
117 | |||
118 | /* LCD Controller */ | ||
119 | |||
120 | static struct resource s3c_lcd_resource[] = { | ||
121 | [0] = { | ||
122 | .start = S3C24XX_PA_LCD, | ||
123 | .end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1, | ||
124 | .flags = IORESOURCE_MEM, | ||
125 | }, | ||
126 | [1] = { | ||
127 | .start = IRQ_LCD, | ||
128 | .end = IRQ_LCD, | ||
129 | .flags = IORESOURCE_IRQ, | ||
130 | } | ||
131 | |||
132 | }; | ||
133 | |||
134 | static u64 s3c_device_lcd_dmamask = 0xffffffffUL; | ||
135 | |||
136 | struct platform_device s3c_device_lcd = { | ||
137 | .name = "s3c2410-lcd", | ||
138 | .id = -1, | ||
139 | .num_resources = ARRAY_SIZE(s3c_lcd_resource), | ||
140 | .resource = s3c_lcd_resource, | ||
141 | .dev = { | ||
142 | .dma_mask = &s3c_device_lcd_dmamask, | ||
143 | .coherent_dma_mask = 0xffffffffUL | ||
144 | } | ||
145 | }; | ||
146 | |||
147 | EXPORT_SYMBOL(s3c_device_lcd); | ||
148 | |||
149 | void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) | ||
150 | { | ||
151 | struct s3c2410fb_mach_info *npd; | ||
152 | |||
153 | npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd); | ||
154 | if (npd) { | ||
155 | npd->displays = kmemdup(pd->displays, | ||
156 | sizeof(struct s3c2410fb_display) * npd->num_displays, | ||
157 | GFP_KERNEL); | ||
158 | if (!npd->displays) | ||
159 | printk(KERN_ERR "no memory for LCD display data\n"); | ||
160 | } else { | ||
161 | printk(KERN_ERR "no memory for LCD platform data\n"); | ||
162 | } | ||
163 | } | ||
164 | |||
165 | /* Touchscreen */ | ||
166 | |||
167 | static struct resource s3c_ts_resource[] = { | ||
168 | [0] = { | ||
169 | .start = S3C24XX_PA_ADC, | ||
170 | .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1, | ||
171 | .flags = IORESOURCE_MEM, | ||
172 | }, | ||
173 | [1] = { | ||
174 | .start = IRQ_TC, | ||
175 | .end = IRQ_TC, | ||
176 | .flags = IORESOURCE_IRQ, | ||
177 | }, | ||
178 | |||
179 | }; | ||
180 | |||
181 | struct platform_device s3c_device_ts = { | ||
182 | .name = "s3c2410-ts", | ||
183 | .id = -1, | ||
184 | .dev.parent = &s3c_device_adc.dev, | ||
185 | .num_resources = ARRAY_SIZE(s3c_ts_resource), | ||
186 | .resource = s3c_ts_resource, | ||
187 | }; | ||
188 | EXPORT_SYMBOL(s3c_device_ts); | ||
189 | |||
190 | void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info) | ||
191 | { | ||
192 | s3c_set_platdata(hard_s3c2410ts_info, | ||
193 | sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts); | ||
194 | } | ||
195 | |||
196 | /* USB Device (Gadget)*/ | ||
197 | |||
198 | static struct resource s3c_usbgadget_resource[] = { | ||
199 | [0] = { | ||
200 | .start = S3C24XX_PA_USBDEV, | ||
201 | .end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1, | ||
202 | .flags = IORESOURCE_MEM, | ||
203 | }, | ||
204 | [1] = { | ||
205 | .start = IRQ_USBD, | ||
206 | .end = IRQ_USBD, | ||
207 | .flags = IORESOURCE_IRQ, | ||
208 | } | ||
209 | |||
210 | }; | ||
211 | |||
212 | struct platform_device s3c_device_usbgadget = { | ||
213 | .name = "s3c2410-usbgadget", | ||
214 | .id = -1, | ||
215 | .num_resources = ARRAY_SIZE(s3c_usbgadget_resource), | ||
216 | .resource = s3c_usbgadget_resource, | ||
217 | }; | ||
218 | |||
219 | EXPORT_SYMBOL(s3c_device_usbgadget); | ||
220 | |||
221 | void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd) | ||
222 | { | ||
223 | s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget); | ||
224 | } | ||
225 | |||
226 | /* USB High Speed 2.0 Device (Gadget) */ | ||
227 | static struct resource s3c_hsudc_resource[] = { | ||
228 | [0] = { | ||
229 | .start = S3C2416_PA_HSUDC, | ||
230 | .end = S3C2416_PA_HSUDC + S3C2416_SZ_HSUDC - 1, | ||
231 | .flags = IORESOURCE_MEM, | ||
232 | }, | ||
233 | [1] = { | ||
234 | .start = IRQ_USBD, | ||
235 | .end = IRQ_USBD, | ||
236 | .flags = IORESOURCE_IRQ, | ||
237 | } | ||
238 | }; | ||
239 | |||
240 | static u64 s3c_hsudc_dmamask = DMA_BIT_MASK(32); | ||
241 | |||
242 | struct platform_device s3c_device_usb_hsudc = { | ||
243 | .name = "s3c-hsudc", | ||
244 | .id = -1, | ||
245 | .num_resources = ARRAY_SIZE(s3c_hsudc_resource), | ||
246 | .resource = s3c_hsudc_resource, | ||
247 | .dev = { | ||
248 | .dma_mask = &s3c_hsudc_dmamask, | ||
249 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
250 | }, | ||
251 | }; | ||
252 | |||
253 | void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd) | ||
254 | { | ||
255 | s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc); | ||
256 | } | ||
257 | |||
258 | /* IIS */ | ||
259 | |||
260 | static struct resource s3c_iis_resource[] = { | ||
261 | [0] = { | ||
262 | .start = S3C24XX_PA_IIS, | ||
263 | .end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1, | ||
264 | .flags = IORESOURCE_MEM, | ||
265 | } | ||
266 | }; | ||
267 | |||
268 | static u64 s3c_device_iis_dmamask = 0xffffffffUL; | ||
269 | |||
270 | struct platform_device s3c_device_iis = { | ||
271 | .name = "s3c24xx-iis", | ||
272 | .id = -1, | ||
273 | .num_resources = ARRAY_SIZE(s3c_iis_resource), | ||
274 | .resource = s3c_iis_resource, | ||
275 | .dev = { | ||
276 | .dma_mask = &s3c_device_iis_dmamask, | ||
277 | .coherent_dma_mask = 0xffffffffUL | ||
278 | } | ||
279 | }; | ||
280 | |||
281 | EXPORT_SYMBOL(s3c_device_iis); | ||
282 | |||
283 | /* RTC */ | ||
284 | |||
285 | static struct resource s3c_rtc_resource[] = { | ||
286 | [0] = { | ||
287 | .start = S3C24XX_PA_RTC, | ||
288 | .end = S3C24XX_PA_RTC + 0xff, | ||
289 | .flags = IORESOURCE_MEM, | ||
290 | }, | ||
291 | [1] = { | ||
292 | .start = IRQ_RTC, | ||
293 | .end = IRQ_RTC, | ||
294 | .flags = IORESOURCE_IRQ, | ||
295 | }, | ||
296 | [2] = { | ||
297 | .start = IRQ_TICK, | ||
298 | .end = IRQ_TICK, | ||
299 | .flags = IORESOURCE_IRQ | ||
300 | } | ||
301 | }; | ||
302 | |||
303 | struct platform_device s3c_device_rtc = { | ||
304 | .name = "s3c2410-rtc", | ||
305 | .id = -1, | ||
306 | .num_resources = ARRAY_SIZE(s3c_rtc_resource), | ||
307 | .resource = s3c_rtc_resource, | ||
308 | }; | ||
309 | |||
310 | EXPORT_SYMBOL(s3c_device_rtc); | ||
311 | |||
312 | /* ADC */ | ||
313 | |||
314 | static struct resource s3c_adc_resource[] = { | ||
315 | [0] = { | ||
316 | .start = S3C24XX_PA_ADC, | ||
317 | .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1, | ||
318 | .flags = IORESOURCE_MEM, | ||
319 | }, | ||
320 | [1] = { | ||
321 | .start = IRQ_TC, | ||
322 | .end = IRQ_TC, | ||
323 | .flags = IORESOURCE_IRQ, | ||
324 | }, | ||
325 | [2] = { | ||
326 | .start = IRQ_ADC, | ||
327 | .end = IRQ_ADC, | ||
328 | .flags = IORESOURCE_IRQ, | ||
329 | } | ||
330 | |||
331 | }; | ||
332 | |||
333 | struct platform_device s3c_device_adc = { | ||
334 | .name = "s3c24xx-adc", | ||
335 | .id = -1, | ||
336 | .num_resources = ARRAY_SIZE(s3c_adc_resource), | ||
337 | .resource = s3c_adc_resource, | ||
338 | }; | ||
339 | |||
340 | /* SDI */ | ||
341 | |||
342 | static struct resource s3c_sdi_resource[] = { | ||
343 | [0] = { | ||
344 | .start = S3C24XX_PA_SDI, | ||
345 | .end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1, | ||
346 | .flags = IORESOURCE_MEM, | ||
347 | }, | ||
348 | [1] = { | ||
349 | .start = IRQ_SDI, | ||
350 | .end = IRQ_SDI, | ||
351 | .flags = IORESOURCE_IRQ, | ||
352 | } | ||
353 | |||
354 | }; | ||
355 | |||
356 | struct platform_device s3c_device_sdi = { | ||
357 | .name = "s3c2410-sdi", | ||
358 | .id = -1, | ||
359 | .num_resources = ARRAY_SIZE(s3c_sdi_resource), | ||
360 | .resource = s3c_sdi_resource, | ||
361 | }; | ||
362 | |||
363 | EXPORT_SYMBOL(s3c_device_sdi); | ||
364 | |||
365 | void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) | ||
366 | { | ||
367 | s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata), | ||
368 | &s3c_device_sdi); | ||
369 | } | ||
370 | |||
371 | |||
372 | /* SPI (0) */ | ||
373 | |||
374 | static struct resource s3c_spi0_resource[] = { | ||
375 | [0] = { | ||
376 | .start = S3C24XX_PA_SPI, | ||
377 | .end = S3C24XX_PA_SPI + 0x1f, | ||
378 | .flags = IORESOURCE_MEM, | ||
379 | }, | ||
380 | [1] = { | ||
381 | .start = IRQ_SPI0, | ||
382 | .end = IRQ_SPI0, | ||
383 | .flags = IORESOURCE_IRQ, | ||
384 | } | ||
385 | |||
386 | }; | ||
387 | |||
388 | static u64 s3c_device_spi0_dmamask = 0xffffffffUL; | ||
389 | |||
390 | struct platform_device s3c_device_spi0 = { | ||
391 | .name = "s3c2410-spi", | ||
392 | .id = 0, | ||
393 | .num_resources = ARRAY_SIZE(s3c_spi0_resource), | ||
394 | .resource = s3c_spi0_resource, | ||
395 | .dev = { | ||
396 | .dma_mask = &s3c_device_spi0_dmamask, | ||
397 | .coherent_dma_mask = 0xffffffffUL | ||
398 | } | ||
399 | }; | ||
400 | |||
401 | EXPORT_SYMBOL(s3c_device_spi0); | ||
402 | |||
403 | /* SPI (1) */ | ||
404 | |||
405 | static struct resource s3c_spi1_resource[] = { | ||
406 | [0] = { | ||
407 | .start = S3C24XX_PA_SPI + S3C2410_SPI1, | ||
408 | .end = S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f, | ||
409 | .flags = IORESOURCE_MEM, | ||
410 | }, | ||
411 | [1] = { | ||
412 | .start = IRQ_SPI1, | ||
413 | .end = IRQ_SPI1, | ||
414 | .flags = IORESOURCE_IRQ, | ||
415 | } | ||
416 | |||
417 | }; | ||
418 | |||
419 | static u64 s3c_device_spi1_dmamask = 0xffffffffUL; | ||
420 | |||
421 | struct platform_device s3c_device_spi1 = { | ||
422 | .name = "s3c2410-spi", | ||
423 | .id = 1, | ||
424 | .num_resources = ARRAY_SIZE(s3c_spi1_resource), | ||
425 | .resource = s3c_spi1_resource, | ||
426 | .dev = { | ||
427 | .dma_mask = &s3c_device_spi1_dmamask, | ||
428 | .coherent_dma_mask = 0xffffffffUL | ||
429 | } | ||
430 | }; | ||
431 | |||
432 | EXPORT_SYMBOL(s3c_device_spi1); | ||
433 | |||
434 | #ifdef CONFIG_CPU_S3C2440 | ||
435 | |||
436 | /* Camif Controller */ | ||
437 | |||
438 | static struct resource s3c_camif_resource[] = { | ||
439 | [0] = { | ||
440 | .start = S3C2440_PA_CAMIF, | ||
441 | .end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1, | ||
442 | .flags = IORESOURCE_MEM, | ||
443 | }, | ||
444 | [1] = { | ||
445 | .start = IRQ_CAM, | ||
446 | .end = IRQ_CAM, | ||
447 | .flags = IORESOURCE_IRQ, | ||
448 | } | ||
449 | |||
450 | }; | ||
451 | |||
452 | static u64 s3c_device_camif_dmamask = 0xffffffffUL; | ||
453 | |||
454 | struct platform_device s3c_device_camif = { | ||
455 | .name = "s3c2440-camif", | ||
456 | .id = -1, | ||
457 | .num_resources = ARRAY_SIZE(s3c_camif_resource), | ||
458 | .resource = s3c_camif_resource, | ||
459 | .dev = { | ||
460 | .dma_mask = &s3c_device_camif_dmamask, | ||
461 | .coherent_dma_mask = 0xffffffffUL | ||
462 | } | ||
463 | }; | ||
464 | |||
465 | EXPORT_SYMBOL(s3c_device_camif); | ||
466 | |||
467 | /* AC97 */ | ||
468 | |||
469 | static struct resource s3c_ac97_resource[] = { | ||
470 | [0] = { | ||
471 | .start = S3C2440_PA_AC97, | ||
472 | .end = S3C2440_PA_AC97 + S3C2440_SZ_AC97 -1, | ||
473 | .flags = IORESOURCE_MEM, | ||
474 | }, | ||
475 | [1] = { | ||
476 | .start = IRQ_S3C244x_AC97, | ||
477 | .end = IRQ_S3C244x_AC97, | ||
478 | .flags = IORESOURCE_IRQ, | ||
479 | }, | ||
480 | [2] = { | ||
481 | .name = "PCM out", | ||
482 | .start = DMACH_PCM_OUT, | ||
483 | .end = DMACH_PCM_OUT, | ||
484 | .flags = IORESOURCE_DMA, | ||
485 | }, | ||
486 | [3] = { | ||
487 | .name = "PCM in", | ||
488 | .start = DMACH_PCM_IN, | ||
489 | .end = DMACH_PCM_IN, | ||
490 | .flags = IORESOURCE_DMA, | ||
491 | }, | ||
492 | [4] = { | ||
493 | .name = "Mic in", | ||
494 | .start = DMACH_MIC_IN, | ||
495 | .end = DMACH_MIC_IN, | ||
496 | .flags = IORESOURCE_DMA, | ||
497 | }, | ||
498 | }; | ||
499 | |||
500 | static u64 s3c_device_audio_dmamask = 0xffffffffUL; | ||
501 | |||
502 | struct platform_device s3c_device_ac97 = { | ||
503 | .name = "samsung-ac97", | ||
504 | .id = -1, | ||
505 | .num_resources = ARRAY_SIZE(s3c_ac97_resource), | ||
506 | .resource = s3c_ac97_resource, | ||
507 | .dev = { | ||
508 | .dma_mask = &s3c_device_audio_dmamask, | ||
509 | .coherent_dma_mask = 0xffffffffUL | ||
510 | } | ||
511 | }; | ||
512 | |||
513 | EXPORT_SYMBOL(s3c_device_ac97); | ||
514 | |||
515 | /* ASoC I2S */ | ||
516 | |||
517 | struct platform_device s3c2412_device_iis = { | ||
518 | .name = "s3c2412-iis", | ||
519 | .id = -1, | ||
520 | .dev = { | ||
521 | .dma_mask = &s3c_device_audio_dmamask, | ||
522 | .coherent_dma_mask = 0xffffffffUL | ||
523 | } | ||
524 | }; | ||
525 | |||
526 | EXPORT_SYMBOL(s3c2412_device_iis); | ||
527 | |||
528 | #endif // CONFIG_CPU_S32440 | ||
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c new file mode 100644 index 00000000000..2f3d7c089df --- /dev/null +++ b/arch/arm/plat-s3c24xx/gpio.c | |||
@@ -0,0 +1,96 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/gpio.c | ||
2 | * | ||
3 | * Copyright (c) 2004-2010 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C24XX GPIO support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
21 | */ | ||
22 | |||
23 | #include <linux/kernel.h> | ||
24 | #include <linux/init.h> | ||
25 | #include <linux/module.h> | ||
26 | #include <linux/interrupt.h> | ||
27 | #include <linux/ioport.h> | ||
28 | #include <linux/gpio.h> | ||
29 | #include <linux/io.h> | ||
30 | |||
31 | #include <mach/hardware.h> | ||
32 | #include <mach/gpio-fns.h> | ||
33 | #include <asm/irq.h> | ||
34 | |||
35 | #include <mach/regs-gpio.h> | ||
36 | |||
37 | #include <plat/gpio-core.h> | ||
38 | |||
39 | /* gpiolib wrappers until these are totally eliminated */ | ||
40 | |||
41 | void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) | ||
42 | { | ||
43 | int ret; | ||
44 | |||
45 | WARN_ON(to); /* should be none of these left */ | ||
46 | |||
47 | if (!to) { | ||
48 | /* if pull is enabled, try first with up, and if that | ||
49 | * fails, try using down */ | ||
50 | |||
51 | ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP); | ||
52 | if (ret) | ||
53 | s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN); | ||
54 | } else { | ||
55 | s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE); | ||
56 | } | ||
57 | } | ||
58 | EXPORT_SYMBOL(s3c2410_gpio_pullup); | ||
59 | |||
60 | void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) | ||
61 | { | ||
62 | /* do this via gpiolib until all users removed */ | ||
63 | |||
64 | gpio_request(pin, "temporary"); | ||
65 | gpio_set_value(pin, to); | ||
66 | gpio_free(pin); | ||
67 | } | ||
68 | |||
69 | EXPORT_SYMBOL(s3c2410_gpio_setpin); | ||
70 | |||
71 | unsigned int s3c2410_gpio_getpin(unsigned int pin) | ||
72 | { | ||
73 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
74 | unsigned long offs = pin - chip->chip.base; | ||
75 | |||
76 | return __raw_readl(chip->base + 0x04) & (1<< offs); | ||
77 | } | ||
78 | |||
79 | EXPORT_SYMBOL(s3c2410_gpio_getpin); | ||
80 | |||
81 | unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change) | ||
82 | { | ||
83 | unsigned long flags; | ||
84 | unsigned long misccr; | ||
85 | |||
86 | local_irq_save(flags); | ||
87 | misccr = __raw_readl(S3C24XX_MISCCR); | ||
88 | misccr &= ~clear; | ||
89 | misccr ^= change; | ||
90 | __raw_writel(misccr, S3C24XX_MISCCR); | ||
91 | local_irq_restore(flags); | ||
92 | |||
93 | return misccr; | ||
94 | } | ||
95 | |||
96 | EXPORT_SYMBOL(s3c2410_modify_misccr); | ||
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c new file mode 100644 index 00000000000..243b6411050 --- /dev/null +++ b/arch/arm/plat-s3c24xx/gpiolib.c | |||
@@ -0,0 +1,229 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/gpiolib.c | ||
2 | * | ||
3 | * Copyright (c) 2008-2010 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX GPIOlib support | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/init.h> | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/sysdev.h> | ||
19 | #include <linux/ioport.h> | ||
20 | #include <linux/io.h> | ||
21 | #include <linux/gpio.h> | ||
22 | |||
23 | #include <plat/gpio-core.h> | ||
24 | #include <plat/gpio-cfg.h> | ||
25 | #include <plat/gpio-cfg-helpers.h> | ||
26 | #include <mach/hardware.h> | ||
27 | #include <asm/irq.h> | ||
28 | #include <plat/pm.h> | ||
29 | |||
30 | #include <mach/regs-gpio.h> | ||
31 | |||
32 | static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) | ||
33 | { | ||
34 | return -EINVAL; | ||
35 | } | ||
36 | |||
37 | static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, | ||
38 | unsigned offset, int value) | ||
39 | { | ||
40 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
41 | void __iomem *base = ourchip->base; | ||
42 | unsigned long flags; | ||
43 | unsigned long dat; | ||
44 | unsigned long con; | ||
45 | |||
46 | local_irq_save(flags); | ||
47 | |||
48 | con = __raw_readl(base + 0x00); | ||
49 | dat = __raw_readl(base + 0x04); | ||
50 | |||
51 | dat &= ~(1 << offset); | ||
52 | if (value) | ||
53 | dat |= 1 << offset; | ||
54 | |||
55 | __raw_writel(dat, base + 0x04); | ||
56 | |||
57 | con &= ~(1 << offset); | ||
58 | |||
59 | __raw_writel(con, base + 0x00); | ||
60 | __raw_writel(dat, base + 0x04); | ||
61 | |||
62 | local_irq_restore(flags); | ||
63 | return 0; | ||
64 | } | ||
65 | |||
66 | static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset) | ||
67 | { | ||
68 | if (offset < 4) | ||
69 | return IRQ_EINT0 + offset; | ||
70 | |||
71 | if (offset < 8) | ||
72 | return IRQ_EINT4 + offset - 4; | ||
73 | |||
74 | return -EINVAL; | ||
75 | } | ||
76 | |||
77 | static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = { | ||
78 | .set_config = s3c_gpio_setcfg_s3c24xx_a, | ||
79 | .get_config = s3c_gpio_getcfg_s3c24xx_a, | ||
80 | }; | ||
81 | |||
82 | struct s3c_gpio_cfg s3c24xx_gpiocfg_default = { | ||
83 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
84 | .get_config = s3c_gpio_getcfg_s3c24xx, | ||
85 | }; | ||
86 | |||
87 | struct s3c_gpio_chip s3c24xx_gpios[] = { | ||
88 | [0] = { | ||
89 | .base = S3C2410_GPACON, | ||
90 | .pm = __gpio_pm(&s3c_gpio_pm_1bit), | ||
91 | .config = &s3c24xx_gpiocfg_banka, | ||
92 | .chip = { | ||
93 | .base = S3C2410_GPA(0), | ||
94 | .owner = THIS_MODULE, | ||
95 | .label = "GPIOA", | ||
96 | .ngpio = 24, | ||
97 | .direction_input = s3c24xx_gpiolib_banka_input, | ||
98 | .direction_output = s3c24xx_gpiolib_banka_output, | ||
99 | }, | ||
100 | }, | ||
101 | [1] = { | ||
102 | .base = S3C2410_GPBCON, | ||
103 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
104 | .chip = { | ||
105 | .base = S3C2410_GPB(0), | ||
106 | .owner = THIS_MODULE, | ||
107 | .label = "GPIOB", | ||
108 | .ngpio = 16, | ||
109 | }, | ||
110 | }, | ||
111 | [2] = { | ||
112 | .base = S3C2410_GPCCON, | ||
113 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
114 | .chip = { | ||
115 | .base = S3C2410_GPC(0), | ||
116 | .owner = THIS_MODULE, | ||
117 | .label = "GPIOC", | ||
118 | .ngpio = 16, | ||
119 | }, | ||
120 | }, | ||
121 | [3] = { | ||
122 | .base = S3C2410_GPDCON, | ||
123 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
124 | .chip = { | ||
125 | .base = S3C2410_GPD(0), | ||
126 | .owner = THIS_MODULE, | ||
127 | .label = "GPIOD", | ||
128 | .ngpio = 16, | ||
129 | }, | ||
130 | }, | ||
131 | [4] = { | ||
132 | .base = S3C2410_GPECON, | ||
133 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
134 | .chip = { | ||
135 | .base = S3C2410_GPE(0), | ||
136 | .label = "GPIOE", | ||
137 | .owner = THIS_MODULE, | ||
138 | .ngpio = 16, | ||
139 | }, | ||
140 | }, | ||
141 | [5] = { | ||
142 | .base = S3C2410_GPFCON, | ||
143 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
144 | .chip = { | ||
145 | .base = S3C2410_GPF(0), | ||
146 | .owner = THIS_MODULE, | ||
147 | .label = "GPIOF", | ||
148 | .ngpio = 8, | ||
149 | .to_irq = s3c24xx_gpiolib_bankf_toirq, | ||
150 | }, | ||
151 | }, | ||
152 | [6] = { | ||
153 | .base = S3C2410_GPGCON, | ||
154 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
155 | .irq_base = IRQ_EINT8, | ||
156 | .chip = { | ||
157 | .base = S3C2410_GPG(0), | ||
158 | .owner = THIS_MODULE, | ||
159 | .label = "GPIOG", | ||
160 | .ngpio = 16, | ||
161 | .to_irq = samsung_gpiolib_to_irq, | ||
162 | }, | ||
163 | }, { | ||
164 | .base = S3C2410_GPHCON, | ||
165 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
166 | .chip = { | ||
167 | .base = S3C2410_GPH(0), | ||
168 | .owner = THIS_MODULE, | ||
169 | .label = "GPIOH", | ||
170 | .ngpio = 11, | ||
171 | }, | ||
172 | }, | ||
173 | /* GPIOS for the S3C2443 and later devices. */ | ||
174 | { | ||
175 | .base = S3C2440_GPJCON, | ||
176 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
177 | .chip = { | ||
178 | .base = S3C2410_GPJ(0), | ||
179 | .owner = THIS_MODULE, | ||
180 | .label = "GPIOJ", | ||
181 | .ngpio = 16, | ||
182 | }, | ||
183 | }, { | ||
184 | .base = S3C2443_GPKCON, | ||
185 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
186 | .chip = { | ||
187 | .base = S3C2410_GPK(0), | ||
188 | .owner = THIS_MODULE, | ||
189 | .label = "GPIOK", | ||
190 | .ngpio = 16, | ||
191 | }, | ||
192 | }, { | ||
193 | .base = S3C2443_GPLCON, | ||
194 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
195 | .chip = { | ||
196 | .base = S3C2410_GPL(0), | ||
197 | .owner = THIS_MODULE, | ||
198 | .label = "GPIOL", | ||
199 | .ngpio = 15, | ||
200 | }, | ||
201 | }, { | ||
202 | .base = S3C2443_GPMCON, | ||
203 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
204 | .chip = { | ||
205 | .base = S3C2410_GPM(0), | ||
206 | .owner = THIS_MODULE, | ||
207 | .label = "GPIOM", | ||
208 | .ngpio = 2, | ||
209 | }, | ||
210 | }, | ||
211 | }; | ||
212 | |||
213 | |||
214 | static __init int s3c24xx_gpiolib_init(void) | ||
215 | { | ||
216 | struct s3c_gpio_chip *chip = s3c24xx_gpios; | ||
217 | int gpn; | ||
218 | |||
219 | for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) { | ||
220 | if (!chip->config) | ||
221 | chip->config = &s3c24xx_gpiocfg_default; | ||
222 | |||
223 | s3c_gpiolib_add(chip); | ||
224 | } | ||
225 | |||
226 | return 0; | ||
227 | } | ||
228 | |||
229 | core_initcall(s3c24xx_gpiolib_init); | ||
diff --git a/arch/arm/plat-s3c24xx/include/mach/clkdev.h b/arch/arm/plat-s3c24xx/include/mach/clkdev.h new file mode 100644 index 00000000000..7dffa83d23f --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/mach/clkdev.h | |||
@@ -0,0 +1,7 @@ | |||
1 | #ifndef __MACH_CLKDEV_H__ | ||
2 | #define __MACH_CLKDEV_H__ | ||
3 | |||
4 | #define __clk_get(clk) ({ 1; }) | ||
5 | #define __clk_put(clk) do {} while (0) | ||
6 | |||
7 | #endif | ||
diff --git a/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h new file mode 100644 index 00000000000..a087de21bc2 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h | |||
@@ -0,0 +1,55 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C24xx - pwm clock and timer support | ||
8 | */ | ||
9 | |||
10 | /** | ||
11 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk | ||
12 | * @cfg: The timer TCFG1 register bits shifted down to 0. | ||
13 | * | ||
14 | * Return true if the given configuration from TCFG1 is a TCLK instead | ||
15 | * any of the TDIV clocks. | ||
16 | */ | ||
17 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | ||
18 | { | ||
19 | return tcfg == S3C2410_TCFG1_MUX_TCLK; | ||
20 | } | ||
21 | |||
22 | /** | ||
23 | * tcfg_to_divisor() - convert tcfg1 setting to a divisor | ||
24 | * @tcfg1: The tcfg1 setting, shifted down. | ||
25 | * | ||
26 | * Get the divisor value for the given tcfg1 setting. We assume the | ||
27 | * caller has already checked to see if this is not a TCLK source. | ||
28 | */ | ||
29 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | ||
30 | { | ||
31 | return 1 << (1 + tcfg1); | ||
32 | } | ||
33 | |||
34 | /** | ||
35 | * pwm_tdiv_has_div1() - does the tdiv setting have a /1 | ||
36 | * | ||
37 | * Return true if we have a /1 in the tdiv setting. | ||
38 | */ | ||
39 | static inline unsigned int pwm_tdiv_has_div1(void) | ||
40 | { | ||
41 | return 0; | ||
42 | } | ||
43 | |||
44 | /** | ||
45 | * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. | ||
46 | * @div: The divisor to calculate the bit information for. | ||
47 | * | ||
48 | * Turn a divisor into the necessary bit field for TCFG1. | ||
49 | */ | ||
50 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) | ||
51 | { | ||
52 | return ilog2(div) - 1; | ||
53 | } | ||
54 | |||
55 | #define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h b/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h new file mode 100644 index 00000000000..de5e88fdcb3 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /* arch/arm/plat-s3c24xx/include/plat/audio-simtec.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * Simtec Audio support. | ||
12 | */ | ||
13 | |||
14 | /** | ||
15 | * struct s3c24xx_audio_simtec_pdata - platform data for simtec audio | ||
16 | * @use_mpllin: Select codec clock from MPLLin | ||
17 | * @output_cdclk: Need to output CDCLK to the codec | ||
18 | * @have_mic: Set if we have a MIC socket | ||
19 | * @have_lout: Set if we have a LineOut socket | ||
20 | * @amp_gpio: GPIO pin to enable the AMP | ||
21 | * @amp_gain: Option GPIO to control AMP gain | ||
22 | */ | ||
23 | struct s3c24xx_audio_simtec_pdata { | ||
24 | unsigned int use_mpllin:1; | ||
25 | unsigned int output_cdclk:1; | ||
26 | |||
27 | unsigned int have_mic:1; | ||
28 | unsigned int have_lout:1; | ||
29 | |||
30 | int amp_gpio; | ||
31 | int amp_gain[2]; | ||
32 | |||
33 | void (*startup)(void); | ||
34 | }; | ||
35 | |||
36 | extern int simtec_audio_add(const char *codec_name, bool has_lr_routing, | ||
37 | struct s3c24xx_audio_simtec_pdata *pdata); | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/common-smdk.h b/arch/arm/plat-s3c24xx/include/plat/common-smdk.h new file mode 100644 index 00000000000..58d9094c935 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/common-smdk.h | |||
@@ -0,0 +1,15 @@ | |||
1 | /* linux/include/asm-arm/plat-s3c24xx/common-smdk.h | ||
2 | * | ||
3 | * Copyright (c) 2006 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Common code for SMDK2410 and SMDK2440 boards | ||
7 | * | ||
8 | * http://www.fluff.org/ben/smdk2440/ | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | extern void smdk_machine_init(void); | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h new file mode 100644 index 00000000000..d623235ae96 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h | |||
@@ -0,0 +1,287 @@ | |||
1 | /* arch/arm/plat-s3c/include/plat/cpu-freq.h | ||
2 | * | ||
3 | * Copyright (c) 2006-2009 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C CPU frequency scaling support - core support | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <plat/cpu-freq.h> | ||
15 | |||
16 | struct seq_file; | ||
17 | |||
18 | #define MAX_BANKS (8) | ||
19 | #define S3C2412_MAX_IO (8) | ||
20 | |||
21 | /** | ||
22 | * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings | ||
23 | * @bankcon: The cached version of settings in this structure. | ||
24 | * @tacp: | ||
25 | * @tacs: Time from address valid to nCS asserted. | ||
26 | * @tcos: Time from nCS asserted to nOE or nWE asserted. | ||
27 | * @tacc: Time that nOE or nWE is asserted. | ||
28 | * @tcoh: Time nCS is held after nOE or nWE are released. | ||
29 | * @tcah: Time address is held for after | ||
30 | * @nwait_en: Whether nWAIT is enabled for this bank. | ||
31 | * | ||
32 | * This structure represents the IO timings for a S3C2410 style IO bank | ||
33 | * used by the CPU frequency support if it needs to change the settings | ||
34 | * of the IO. | ||
35 | */ | ||
36 | struct s3c2410_iobank_timing { | ||
37 | unsigned long bankcon; | ||
38 | unsigned int tacp; | ||
39 | unsigned int tacs; | ||
40 | unsigned int tcos; | ||
41 | unsigned int tacc; | ||
42 | unsigned int tcoh; /* nCS hold afrer nOE/nWE */ | ||
43 | unsigned int tcah; /* Address hold after nCS */ | ||
44 | unsigned char nwait_en; /* nWait enabled for bank. */ | ||
45 | }; | ||
46 | |||
47 | /** | ||
48 | * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO | ||
49 | * @idcy: The idle cycle time between transactions. | ||
50 | * @wstrd: nCS release to end of read cycle. | ||
51 | * @wstwr: nCS release to end of write cycle. | ||
52 | * @wstoen: nCS assertion to nOE assertion time. | ||
53 | * @wstwen: nCS assertion to nWE assertion time. | ||
54 | * @wstbrd: Burst ready delay. | ||
55 | * @smbidcyr: Register cache for smbidcyr value. | ||
56 | * @smbwstrd: Register cache for smbwstrd value. | ||
57 | * @smbwstwr: Register cache for smbwstwr value. | ||
58 | * @smbwstoen: Register cache for smbwstoen value. | ||
59 | * @smbwstwen: Register cache for smbwstwen value. | ||
60 | * @smbwstbrd: Register cache for smbwstbrd value. | ||
61 | * | ||
62 | * Timing information for a IO bank on an S3C2412 or similar system which | ||
63 | * uses a PL093 block. | ||
64 | */ | ||
65 | struct s3c2412_iobank_timing { | ||
66 | unsigned int idcy; | ||
67 | unsigned int wstrd; | ||
68 | unsigned int wstwr; | ||
69 | unsigned int wstoen; | ||
70 | unsigned int wstwen; | ||
71 | unsigned int wstbrd; | ||
72 | |||
73 | /* register cache */ | ||
74 | unsigned char smbidcyr; | ||
75 | unsigned char smbwstrd; | ||
76 | unsigned char smbwstwr; | ||
77 | unsigned char smbwstoen; | ||
78 | unsigned char smbwstwen; | ||
79 | unsigned char smbwstbrd; | ||
80 | }; | ||
81 | |||
82 | union s3c_iobank { | ||
83 | struct s3c2410_iobank_timing *io_2410; | ||
84 | struct s3c2412_iobank_timing *io_2412; | ||
85 | }; | ||
86 | |||
87 | /** | ||
88 | * struct s3c_iotimings - Chip IO timings holder | ||
89 | * @bank: The timings for each IO bank. | ||
90 | */ | ||
91 | struct s3c_iotimings { | ||
92 | union s3c_iobank bank[MAX_BANKS]; | ||
93 | }; | ||
94 | |||
95 | /** | ||
96 | * struct s3c_plltab - PLL table information. | ||
97 | * @vals: List of PLL values. | ||
98 | * @size: Size of the PLL table @vals. | ||
99 | */ | ||
100 | struct s3c_plltab { | ||
101 | struct s3c_pllval *vals; | ||
102 | int size; | ||
103 | }; | ||
104 | |||
105 | /** | ||
106 | * struct s3c_cpufreq_config - current cpu frequency configuration | ||
107 | * @freq: The current settings for the core clocks. | ||
108 | * @max: Maxium settings, derived from core, board and user settings. | ||
109 | * @pll: The PLL table entry for the current PLL settings. | ||
110 | * @divs: The divisor settings for the core clocks. | ||
111 | * @info: The current core driver information. | ||
112 | * @board: The information for the board we are running on. | ||
113 | * @lock_pll: Set if the PLL settings cannot be changed. | ||
114 | * | ||
115 | * This is for the core drivers that need to know information about | ||
116 | * the current settings and values. It should not be needed by any | ||
117 | * device drivers. | ||
118 | */ | ||
119 | struct s3c_cpufreq_config { | ||
120 | struct s3c_freq freq; | ||
121 | struct s3c_freq max; | ||
122 | struct cpufreq_frequency_table pll; | ||
123 | struct s3c_clkdivs divs; | ||
124 | struct s3c_cpufreq_info *info; /* for core, not drivers */ | ||
125 | struct s3c_cpufreq_board *board; | ||
126 | |||
127 | unsigned int lock_pll:1; | ||
128 | }; | ||
129 | |||
130 | /** | ||
131 | * struct s3c_cpufreq_info - Information for the CPU frequency driver. | ||
132 | * @name: The name of this implementation. | ||
133 | * @max: The maximum frequencies for the system. | ||
134 | * @latency: Transition latency to give to cpufreq. | ||
135 | * @locktime_m: The lock-time in uS for the MPLL. | ||
136 | * @locktime_u: The lock-time in uS for the UPLL. | ||
137 | * @locttime_bits: The number of bits each LOCKTIME field. | ||
138 | * @need_pll: Set if this driver needs to change the PLL values to achieve | ||
139 | * any frequency changes. This is really only need by devices like the | ||
140 | * S3C2410 where there is no or limited divider between the PLL and the | ||
141 | * ARMCLK. | ||
142 | * @resume_clocks: Update the clocks on resume. | ||
143 | * @get_iotiming: Get the current IO timing data, mainly for use at start. | ||
144 | * @set_iotiming: Update the IO timings from the cached copies calculated | ||
145 | * from the @calc_iotiming entry when changing the frequency. | ||
146 | * @calc_iotiming: Calculate and update the cached copies of the IO timings | ||
147 | * from the newly calculated frequencies. | ||
148 | * @calc_freqtable: Calculate (fill in) the given frequency table from the | ||
149 | * current frequency configuration. If the table passed in is NULL, | ||
150 | * then the return is the number of elements to be filled for allocation | ||
151 | * of the table. | ||
152 | * @set_refresh: Set the memory refresh configuration. | ||
153 | * @set_fvco: Set the PLL frequencies. | ||
154 | * @set_divs: Update the clock divisors. | ||
155 | * @calc_divs: Calculate the clock divisors. | ||
156 | */ | ||
157 | struct s3c_cpufreq_info { | ||
158 | const char *name; | ||
159 | struct s3c_freq max; | ||
160 | |||
161 | unsigned int latency; | ||
162 | |||
163 | unsigned int locktime_m; | ||
164 | unsigned int locktime_u; | ||
165 | unsigned char locktime_bits; | ||
166 | |||
167 | unsigned int need_pll:1; | ||
168 | |||
169 | /* driver routines */ | ||
170 | |||
171 | void (*resume_clocks)(void); | ||
172 | |||
173 | int (*get_iotiming)(struct s3c_cpufreq_config *cfg, | ||
174 | struct s3c_iotimings *timings); | ||
175 | |||
176 | void (*set_iotiming)(struct s3c_cpufreq_config *cfg, | ||
177 | struct s3c_iotimings *timings); | ||
178 | |||
179 | int (*calc_iotiming)(struct s3c_cpufreq_config *cfg, | ||
180 | struct s3c_iotimings *timings); | ||
181 | |||
182 | int (*calc_freqtable)(struct s3c_cpufreq_config *cfg, | ||
183 | struct cpufreq_frequency_table *t, | ||
184 | size_t table_size); | ||
185 | |||
186 | void (*debug_io_show)(struct seq_file *seq, | ||
187 | struct s3c_cpufreq_config *cfg, | ||
188 | union s3c_iobank *iob); | ||
189 | |||
190 | void (*set_refresh)(struct s3c_cpufreq_config *cfg); | ||
191 | void (*set_fvco)(struct s3c_cpufreq_config *cfg); | ||
192 | void (*set_divs)(struct s3c_cpufreq_config *cfg); | ||
193 | int (*calc_divs)(struct s3c_cpufreq_config *cfg); | ||
194 | }; | ||
195 | |||
196 | extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info); | ||
197 | |||
198 | extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no); | ||
199 | |||
200 | /* exports and utilities for debugfs */ | ||
201 | extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void); | ||
202 | extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void); | ||
203 | |||
204 | extern void s3c2410_iotiming_debugfs(struct seq_file *seq, | ||
205 | struct s3c_cpufreq_config *cfg, | ||
206 | union s3c_iobank *iob); | ||
207 | |||
208 | extern void s3c2412_iotiming_debugfs(struct seq_file *seq, | ||
209 | struct s3c_cpufreq_config *cfg, | ||
210 | union s3c_iobank *iob); | ||
211 | |||
212 | #ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS | ||
213 | #define s3c_cpufreq_debugfs_call(x) x | ||
214 | #else | ||
215 | #define s3c_cpufreq_debugfs_call(x) NULL | ||
216 | #endif | ||
217 | |||
218 | /* Useful utility functions. */ | ||
219 | |||
220 | extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *); | ||
221 | |||
222 | /* S3C2410 and compatible exported functions */ | ||
223 | |||
224 | extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg); | ||
225 | extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg); | ||
226 | |||
227 | #ifdef CONFIG_S3C2410_IOTIMING | ||
228 | extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg, | ||
229 | struct s3c_iotimings *iot); | ||
230 | |||
231 | extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg, | ||
232 | struct s3c_iotimings *timings); | ||
233 | |||
234 | extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg, | ||
235 | struct s3c_iotimings *iot); | ||
236 | #else | ||
237 | #define s3c2410_iotiming_calc NULL | ||
238 | #define s3c2410_iotiming_get NULL | ||
239 | #define s3c2410_iotiming_set NULL | ||
240 | #endif /* CONFIG_S3C2410_IOTIMING */ | ||
241 | |||
242 | /* S3C2412 compatible routines */ | ||
243 | |||
244 | extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, | ||
245 | struct s3c_iotimings *timings); | ||
246 | |||
247 | extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, | ||
248 | struct s3c_iotimings *timings); | ||
249 | |||
250 | extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg, | ||
251 | struct s3c_iotimings *iot); | ||
252 | |||
253 | extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, | ||
254 | struct s3c_iotimings *iot); | ||
255 | |||
256 | #ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG | ||
257 | #define s3c_freq_dbg(x...) printk(KERN_INFO x) | ||
258 | #else | ||
259 | #define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0) | ||
260 | #endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */ | ||
261 | |||
262 | #ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG | ||
263 | #define s3c_freq_iodbg(x...) printk(KERN_INFO x) | ||
264 | #else | ||
265 | #define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0) | ||
266 | #endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */ | ||
267 | |||
268 | static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table, | ||
269 | int index, size_t table_size, | ||
270 | unsigned int freq) | ||
271 | { | ||
272 | if (index < 0) | ||
273 | return index; | ||
274 | |||
275 | if (table) { | ||
276 | if (index >= table_size) | ||
277 | return -ENOMEM; | ||
278 | |||
279 | s3c_freq_dbg("%s: { %d = %u kHz }\n", | ||
280 | __func__, index, freq); | ||
281 | |||
282 | table[index].index = index; | ||
283 | table[index].frequency = freq; | ||
284 | } | ||
285 | |||
286 | return index + 1; | ||
287 | } | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/fiq.h b/arch/arm/plat-s3c24xx/include/plat/fiq.h new file mode 100644 index 00000000000..8521b8372c5 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/fiq.h | |||
@@ -0,0 +1,13 @@ | |||
1 | /* linux/include/asm-arm/plat-s3c24xx/fiq.h | ||
2 | * | ||
3 | * Copyright (c) 2009 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Header file for S3C24XX CPU FIQ support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | extern int s3c24xx_set_fiq(unsigned int irq, bool on); | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-s3c24xx/include/plat/irq.h new file mode 100644 index 00000000000..ec087d6054b --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/irq.h | |||
@@ -0,0 +1,115 @@ | |||
1 | /* linux/include/asm-arm/plat-s3c24xx/irq.h | ||
2 | * | ||
3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Header file for S3C24XX CPU IRQ support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/io.h> | ||
14 | |||
15 | #include <mach/hardware.h> | ||
16 | #include <mach/regs-irq.h> | ||
17 | #include <mach/regs-gpio.h> | ||
18 | |||
19 | #define irqdbf(x...) | ||
20 | #define irqdbf2(x...) | ||
21 | |||
22 | #define EXTINT_OFF (IRQ_EINT4 - 4) | ||
23 | |||
24 | /* these are exported for arch/arm/mach-* usage */ | ||
25 | extern struct irq_chip s3c_irq_level_chip; | ||
26 | extern struct irq_chip s3c_irq_chip; | ||
27 | |||
28 | static inline void | ||
29 | s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, | ||
30 | int subcheck) | ||
31 | { | ||
32 | unsigned long mask; | ||
33 | unsigned long submask; | ||
34 | |||
35 | submask = __raw_readl(S3C2410_INTSUBMSK); | ||
36 | mask = __raw_readl(S3C2410_INTMSK); | ||
37 | |||
38 | submask |= (1UL << (irqno - IRQ_S3CUART_RX0)); | ||
39 | |||
40 | /* check to see if we need to mask the parent IRQ */ | ||
41 | |||
42 | if ((submask & subcheck) == subcheck) { | ||
43 | __raw_writel(mask | parentbit, S3C2410_INTMSK); | ||
44 | } | ||
45 | |||
46 | /* write back masks */ | ||
47 | __raw_writel(submask, S3C2410_INTSUBMSK); | ||
48 | |||
49 | } | ||
50 | |||
51 | static inline void | ||
52 | s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit) | ||
53 | { | ||
54 | unsigned long mask; | ||
55 | unsigned long submask; | ||
56 | |||
57 | submask = __raw_readl(S3C2410_INTSUBMSK); | ||
58 | mask = __raw_readl(S3C2410_INTMSK); | ||
59 | |||
60 | submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0)); | ||
61 | mask &= ~parentbit; | ||
62 | |||
63 | /* write back masks */ | ||
64 | __raw_writel(submask, S3C2410_INTSUBMSK); | ||
65 | __raw_writel(mask, S3C2410_INTMSK); | ||
66 | } | ||
67 | |||
68 | |||
69 | static inline void | ||
70 | s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group) | ||
71 | { | ||
72 | unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); | ||
73 | |||
74 | s3c_irqsub_mask(irqno, parentmask, group); | ||
75 | |||
76 | __raw_writel(bit, S3C2410_SUBSRCPND); | ||
77 | |||
78 | /* only ack parent if we've got all the irqs (seems we must | ||
79 | * ack, all and hope that the irq system retriggers ok when | ||
80 | * the interrupt goes off again) | ||
81 | */ | ||
82 | |||
83 | if (1) { | ||
84 | __raw_writel(parentmask, S3C2410_SRCPND); | ||
85 | __raw_writel(parentmask, S3C2410_INTPND); | ||
86 | } | ||
87 | } | ||
88 | |||
89 | static inline void | ||
90 | s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group) | ||
91 | { | ||
92 | unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); | ||
93 | |||
94 | __raw_writel(bit, S3C2410_SUBSRCPND); | ||
95 | |||
96 | /* only ack parent if we've got all the irqs (seems we must | ||
97 | * ack, all and hope that the irq system retriggers ok when | ||
98 | * the interrupt goes off again) | ||
99 | */ | ||
100 | |||
101 | if (1) { | ||
102 | __raw_writel(parentmask, S3C2410_SRCPND); | ||
103 | __raw_writel(parentmask, S3C2410_INTPND); | ||
104 | } | ||
105 | } | ||
106 | |||
107 | /* exported for use in arch/arm/mach-s3c2410 */ | ||
108 | |||
109 | #ifdef CONFIG_PM | ||
110 | extern int s3c_irq_wake(struct irq_data *data, unsigned int state); | ||
111 | #else | ||
112 | #define s3c_irq_wake NULL | ||
113 | #endif | ||
114 | |||
115 | extern int s3c_irqext_type(struct irq_data *d, unsigned int type); | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h new file mode 100644 index 00000000000..bd534d32b99 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/map.h | |||
@@ -0,0 +1,100 @@ | |||
1 | /* linux/include/asm-arm/plat-s3c24xx/map.h | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C24XX - Memory map definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_PLAT_S3C24XX_MAP_H | ||
14 | #define __ASM_PLAT_S3C24XX_MAP_H | ||
15 | |||
16 | /* interrupt controller is the first thing we put in, to make | ||
17 | * the assembly code for the irq detection easier | ||
18 | */ | ||
19 | #define S3C24XX_VA_IRQ S3C_VA_IRQ | ||
20 | #define S3C2410_PA_IRQ (0x4A000000) | ||
21 | #define S3C24XX_SZ_IRQ SZ_1M | ||
22 | |||
23 | /* memory controller registers */ | ||
24 | #define S3C24XX_VA_MEMCTRL S3C_VA_MEM | ||
25 | #define S3C2410_PA_MEMCTRL (0x48000000) | ||
26 | #define S3C24XX_SZ_MEMCTRL SZ_1M | ||
27 | |||
28 | /* UARTs */ | ||
29 | #define S3C24XX_VA_UART S3C_VA_UART | ||
30 | #define S3C2410_PA_UART (0x50000000) | ||
31 | #define S3C24XX_SZ_UART SZ_1M | ||
32 | #define S3C_UART_OFFSET (0x4000) | ||
33 | |||
34 | #define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET))) | ||
35 | |||
36 | /* Timers */ | ||
37 | #define S3C24XX_VA_TIMER S3C_VA_TIMER | ||
38 | #define S3C2410_PA_TIMER (0x51000000) | ||
39 | #define S3C24XX_SZ_TIMER SZ_1M | ||
40 | |||
41 | /* Clock and Power management */ | ||
42 | #define S3C24XX_VA_CLKPWR S3C_VA_SYS | ||
43 | #define S3C24XX_SZ_CLKPWR SZ_1M | ||
44 | |||
45 | /* USB Device port */ | ||
46 | #define S3C2410_PA_USBDEV (0x52000000) | ||
47 | #define S3C24XX_SZ_USBDEV SZ_1M | ||
48 | |||
49 | /* Watchdog */ | ||
50 | #define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG | ||
51 | #define S3C2410_PA_WATCHDOG (0x53000000) | ||
52 | #define S3C24XX_SZ_WATCHDOG SZ_1M | ||
53 | |||
54 | /* Standard size definitions for peripheral blocks. */ | ||
55 | |||
56 | #define S3C24XX_SZ_IIS SZ_1M | ||
57 | #define S3C24XX_SZ_ADC SZ_1M | ||
58 | #define S3C24XX_SZ_SPI SZ_1M | ||
59 | #define S3C24XX_SZ_SDI SZ_1M | ||
60 | #define S3C24XX_SZ_NAND SZ_1M | ||
61 | |||
62 | /* GPIO ports */ | ||
63 | |||
64 | /* the calculation for the VA of this must ensure that | ||
65 | * it is the same distance apart from the UART in the | ||
66 | * phsyical address space, as the initial mapping for the IO | ||
67 | * is done as a 1:1 mapping. This puts it (currently) at | ||
68 | * 0xFA800000, which is not in the way of any current mapping | ||
69 | * by the base system. | ||
70 | */ | ||
71 | |||
72 | #define S3C2410_PA_GPIO (0x56000000) | ||
73 | #define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) | ||
74 | #define S3C24XX_SZ_GPIO SZ_1M | ||
75 | |||
76 | |||
77 | /* ISA style IO, for each machine to sort out mappings for, if it | ||
78 | * implements it. We reserve two 16M regions for ISA. | ||
79 | */ | ||
80 | |||
81 | #define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) | ||
82 | #define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) | ||
83 | |||
84 | /* deal with the registers that move under the 2412/2413 */ | ||
85 | |||
86 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | ||
87 | #ifndef __ASSEMBLY__ | ||
88 | extern void __iomem *s3c24xx_va_gpio2; | ||
89 | #endif | ||
90 | #ifdef CONFIG_CPU_S3C2412_ONLY | ||
91 | #define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) | ||
92 | #else | ||
93 | #define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 | ||
94 | #endif | ||
95 | #else | ||
96 | #define s3c24xx_va_gpio2 S3C24XX_VA_GPIO | ||
97 | #define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO | ||
98 | #endif | ||
99 | |||
100 | #endif /* __ASM_PLAT_S3C24XX_MAP_H */ | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h new file mode 100644 index 00000000000..2ac2b21ec49 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/mci.h | |||
@@ -0,0 +1,52 @@ | |||
1 | #ifndef _ARCH_MCI_H | ||
2 | #define _ARCH_MCI_H | ||
3 | |||
4 | /** | ||
5 | * struct s3c24xx_mci_pdata - sd/mmc controller platform data | ||
6 | * @no_wprotect: Set this to indicate there is no write-protect switch. | ||
7 | * @no_detect: Set this if there is no detect switch. | ||
8 | * @wprotect_invert: Invert the default sense of the write protect switch. | ||
9 | * @detect_invert: Invert the default sense of the write protect switch. | ||
10 | * @use_dma: Set to allow the use of DMA. | ||
11 | * @gpio_detect: GPIO number for the card detect line. | ||
12 | * @gpio_wprotect: GPIO number for the write protect line. | ||
13 | * @ocr_avail: The mask of the available power states, non-zero to use. | ||
14 | * @set_power: Callback to control the power mode. | ||
15 | * | ||
16 | * The @gpio_detect is used for card detection when @no_wprotect is unset, | ||
17 | * and the default sense is that 0 returned from gpio_get_value() means | ||
18 | * that a card is inserted. If @detect_invert is set, then the value from | ||
19 | * gpio_get_value() is inverted, which makes 1 mean card inserted. | ||
20 | * | ||
21 | * The driver will use @gpio_wprotect to signal whether the card is write | ||
22 | * protected if @no_wprotect is not set. A 0 returned from gpio_get_value() | ||
23 | * means the card is read/write, and 1 means read-only. The @wprotect_invert | ||
24 | * will invert the value returned from gpio_get_value(). | ||
25 | * | ||
26 | * Card power is set by @ocr_availa, using MCC_VDD_ constants if it is set | ||
27 | * to a non-zero value, otherwise the default of 3.2-3.4V is used. | ||
28 | */ | ||
29 | struct s3c24xx_mci_pdata { | ||
30 | unsigned int no_wprotect : 1; | ||
31 | unsigned int no_detect : 1; | ||
32 | unsigned int wprotect_invert : 1; | ||
33 | unsigned int detect_invert : 1; /* set => detect active high. */ | ||
34 | unsigned int use_dma : 1; | ||
35 | |||
36 | unsigned int gpio_detect; | ||
37 | unsigned int gpio_wprotect; | ||
38 | unsigned long ocr_avail; | ||
39 | void (*set_power)(unsigned char power_mode, | ||
40 | unsigned short vdd); | ||
41 | }; | ||
42 | |||
43 | /** | ||
44 | * s3c24xx_mci_set_platdata - set platform data for mmc/sdi device | ||
45 | * @pdata: The platform data | ||
46 | * | ||
47 | * Copy the platform data supplied by @pdata so that this can be marked | ||
48 | * __initdata. | ||
49 | */ | ||
50 | extern void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata); | ||
51 | |||
52 | #endif /* _ARCH_NCI_H */ | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h new file mode 100644 index 00000000000..005729a1077 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/pll.h | |||
@@ -0,0 +1,62 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/include/plat/pll.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C24xx - common pll registers and code | ||
8 | */ | ||
9 | |||
10 | #define S3C24XX_PLLCON_MDIVSHIFT 12 | ||
11 | #define S3C24XX_PLLCON_PDIVSHIFT 4 | ||
12 | #define S3C24XX_PLLCON_SDIVSHIFT 0 | ||
13 | #define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) | ||
14 | #define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1) | ||
15 | #define S3C24XX_PLLCON_SDIVMASK 3 | ||
16 | |||
17 | #include <asm/div64.h> | ||
18 | |||
19 | static inline unsigned int | ||
20 | s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk) | ||
21 | { | ||
22 | unsigned int mdiv, pdiv, sdiv; | ||
23 | uint64_t fvco; | ||
24 | |||
25 | mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT; | ||
26 | pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT; | ||
27 | sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT; | ||
28 | |||
29 | mdiv &= S3C24XX_PLLCON_MDIVMASK; | ||
30 | pdiv &= S3C24XX_PLLCON_PDIVMASK; | ||
31 | sdiv &= S3C24XX_PLLCON_SDIVMASK; | ||
32 | |||
33 | fvco = (uint64_t)baseclk * (mdiv + 8); | ||
34 | do_div(fvco, (pdiv + 2) << sdiv); | ||
35 | |||
36 | return (unsigned int)fvco; | ||
37 | } | ||
38 | |||
39 | #define S3C2416_PLL_M_SHIFT (14) | ||
40 | #define S3C2416_PLL_P_SHIFT (5) | ||
41 | #define S3C2416_PLL_S_MASK (7) | ||
42 | #define S3C2416_PLL_M_MASK ((1 << 10) - 1) | ||
43 | #define S3C2416_PLL_P_MASK (63) | ||
44 | |||
45 | static inline unsigned int | ||
46 | s3c2416_get_pll(unsigned int pllval, unsigned int baseclk) | ||
47 | { | ||
48 | unsigned int m, p, s; | ||
49 | uint64_t fvco; | ||
50 | |||
51 | m = pllval >> S3C2416_PLL_M_SHIFT; | ||
52 | p = pllval >> S3C2416_PLL_P_SHIFT; | ||
53 | |||
54 | s = pllval & S3C2416_PLL_S_MASK; | ||
55 | m &= S3C2416_PLL_M_MASK; | ||
56 | p &= S3C2416_PLL_P_MASK; | ||
57 | |||
58 | fvco = (uint64_t)baseclk * m; | ||
59 | do_div(fvco, (p << s)); | ||
60 | |||
61 | return (unsigned int)fvco; | ||
62 | } | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h new file mode 100644 index 00000000000..1b0f4c36d38 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h | |||
@@ -0,0 +1,145 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/dma.h | ||
2 | * | ||
3 | * Copyright (C) 2003-2006 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Samsung S3C24XX DMA support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | /* DMA Register definitions */ | ||
14 | |||
15 | #define S3C2410_DMA_DISRC (0x00) | ||
16 | #define S3C2410_DMA_DISRCC (0x04) | ||
17 | #define S3C2410_DMA_DIDST (0x08) | ||
18 | #define S3C2410_DMA_DIDSTC (0x0C) | ||
19 | #define S3C2410_DMA_DCON (0x10) | ||
20 | #define S3C2410_DMA_DSTAT (0x14) | ||
21 | #define S3C2410_DMA_DCSRC (0x18) | ||
22 | #define S3C2410_DMA_DCDST (0x1C) | ||
23 | #define S3C2410_DMA_DMASKTRIG (0x20) | ||
24 | #define S3C2412_DMA_DMAREQSEL (0x24) | ||
25 | #define S3C2443_DMA_DMAREQSEL (0x24) | ||
26 | |||
27 | #define S3C2410_DISRCC_INC (1<<0) | ||
28 | #define S3C2410_DISRCC_APB (1<<1) | ||
29 | |||
30 | #define S3C2410_DMASKTRIG_STOP (1<<2) | ||
31 | #define S3C2410_DMASKTRIG_ON (1<<1) | ||
32 | #define S3C2410_DMASKTRIG_SWTRIG (1<<0) | ||
33 | |||
34 | #define S3C2410_DCON_DEMAND (0<<31) | ||
35 | #define S3C2410_DCON_HANDSHAKE (1<<31) | ||
36 | #define S3C2410_DCON_SYNC_PCLK (0<<30) | ||
37 | #define S3C2410_DCON_SYNC_HCLK (1<<30) | ||
38 | |||
39 | #define S3C2410_DCON_INTREQ (1<<29) | ||
40 | |||
41 | #define S3C2410_DCON_CH0_XDREQ0 (0<<24) | ||
42 | #define S3C2410_DCON_CH0_UART0 (1<<24) | ||
43 | #define S3C2410_DCON_CH0_SDI (2<<24) | ||
44 | #define S3C2410_DCON_CH0_TIMER (3<<24) | ||
45 | #define S3C2410_DCON_CH0_USBEP1 (4<<24) | ||
46 | |||
47 | #define S3C2410_DCON_CH1_XDREQ1 (0<<24) | ||
48 | #define S3C2410_DCON_CH1_UART1 (1<<24) | ||
49 | #define S3C2410_DCON_CH1_I2SSDI (2<<24) | ||
50 | #define S3C2410_DCON_CH1_SPI (3<<24) | ||
51 | #define S3C2410_DCON_CH1_USBEP2 (4<<24) | ||
52 | |||
53 | #define S3C2410_DCON_CH2_I2SSDO (0<<24) | ||
54 | #define S3C2410_DCON_CH2_I2SSDI (1<<24) | ||
55 | #define S3C2410_DCON_CH2_SDI (2<<24) | ||
56 | #define S3C2410_DCON_CH2_TIMER (3<<24) | ||
57 | #define S3C2410_DCON_CH2_USBEP3 (4<<24) | ||
58 | |||
59 | #define S3C2410_DCON_CH3_UART2 (0<<24) | ||
60 | #define S3C2410_DCON_CH3_SDI (1<<24) | ||
61 | #define S3C2410_DCON_CH3_SPI (2<<24) | ||
62 | #define S3C2410_DCON_CH3_TIMER (3<<24) | ||
63 | #define S3C2410_DCON_CH3_USBEP4 (4<<24) | ||
64 | |||
65 | #define S3C2410_DCON_SRCSHIFT (24) | ||
66 | #define S3C2410_DCON_SRCMASK (7<<24) | ||
67 | |||
68 | #define S3C2410_DCON_BYTE (0<<20) | ||
69 | #define S3C2410_DCON_HALFWORD (1<<20) | ||
70 | #define S3C2410_DCON_WORD (2<<20) | ||
71 | |||
72 | #define S3C2410_DCON_AUTORELOAD (0<<22) | ||
73 | #define S3C2410_DCON_NORELOAD (1<<22) | ||
74 | #define S3C2410_DCON_HWTRIG (1<<23) | ||
75 | |||
76 | #ifdef CONFIG_CPU_S3C2440 | ||
77 | #define S3C2440_DIDSTC_CHKINT (1<<2) | ||
78 | |||
79 | #define S3C2440_DCON_CH0_I2SSDO (5<<24) | ||
80 | #define S3C2440_DCON_CH0_PCMIN (6<<24) | ||
81 | |||
82 | #define S3C2440_DCON_CH1_PCMOUT (5<<24) | ||
83 | #define S3C2440_DCON_CH1_SDI (6<<24) | ||
84 | |||
85 | #define S3C2440_DCON_CH2_PCMIN (5<<24) | ||
86 | #define S3C2440_DCON_CH2_MICIN (6<<24) | ||
87 | |||
88 | #define S3C2440_DCON_CH3_MICIN (5<<24) | ||
89 | #define S3C2440_DCON_CH3_PCMOUT (6<<24) | ||
90 | #endif | ||
91 | |||
92 | #ifdef CONFIG_CPU_S3C2412 | ||
93 | |||
94 | #define S3C2412_DMAREQSEL_SRC(x) ((x)<<1) | ||
95 | |||
96 | #define S3C2412_DMAREQSEL_HW (1) | ||
97 | |||
98 | #define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0) | ||
99 | #define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1) | ||
100 | #define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2) | ||
101 | #define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3) | ||
102 | #define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4) | ||
103 | #define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5) | ||
104 | #define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9) | ||
105 | #define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10) | ||
106 | #define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13) | ||
107 | #define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14) | ||
108 | #define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15) | ||
109 | #define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16) | ||
110 | #define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17) | ||
111 | #define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18) | ||
112 | #define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19) | ||
113 | #define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20) | ||
114 | #define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21) | ||
115 | #define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22) | ||
116 | #define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23) | ||
117 | #define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) | ||
118 | |||
119 | #endif | ||
120 | |||
121 | #define S3C2443_DMAREQSEL_SRC(x) ((x)<<1) | ||
122 | |||
123 | #define S3C2443_DMAREQSEL_HW (1) | ||
124 | |||
125 | #define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0) | ||
126 | #define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1) | ||
127 | #define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2) | ||
128 | #define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3) | ||
129 | #define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4) | ||
130 | #define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5) | ||
131 | #define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9) | ||
132 | #define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10) | ||
133 | #define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17) | ||
134 | #define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18) | ||
135 | #define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19) | ||
136 | #define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20) | ||
137 | #define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21) | ||
138 | #define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22) | ||
139 | #define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23) | ||
140 | #define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24) | ||
141 | #define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25) | ||
142 | #define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26) | ||
143 | #define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27) | ||
144 | #define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28) | ||
145 | #define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29) | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h b/arch/arm/plat-s3c24xx/include/plat/regs-iis.h new file mode 100644 index 00000000000..cc44e0e931e --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/regs-iis.h | |||
@@ -0,0 +1,68 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-iis.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 IIS register definition | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_IIS_H | ||
14 | #define __ASM_ARCH_REGS_IIS_H | ||
15 | |||
16 | #define S3C2410_IISCON (0x00) | ||
17 | |||
18 | #define S3C2410_IISCON_LRINDEX (1<<8) | ||
19 | #define S3C2410_IISCON_TXFIFORDY (1<<7) | ||
20 | #define S3C2410_IISCON_RXFIFORDY (1<<6) | ||
21 | #define S3C2410_IISCON_TXDMAEN (1<<5) | ||
22 | #define S3C2410_IISCON_RXDMAEN (1<<4) | ||
23 | #define S3C2410_IISCON_TXIDLE (1<<3) | ||
24 | #define S3C2410_IISCON_RXIDLE (1<<2) | ||
25 | #define S3C2410_IISCON_PSCEN (1<<1) | ||
26 | #define S3C2410_IISCON_IISEN (1<<0) | ||
27 | |||
28 | #define S3C2410_IISMOD (0x04) | ||
29 | |||
30 | #define S3C2440_IISMOD_MPLL (1<<9) | ||
31 | #define S3C2410_IISMOD_SLAVE (1<<8) | ||
32 | #define S3C2410_IISMOD_NOXFER (0<<6) | ||
33 | #define S3C2410_IISMOD_RXMODE (1<<6) | ||
34 | #define S3C2410_IISMOD_TXMODE (2<<6) | ||
35 | #define S3C2410_IISMOD_TXRXMODE (3<<6) | ||
36 | #define S3C2410_IISMOD_LR_LLOW (0<<5) | ||
37 | #define S3C2410_IISMOD_LR_RLOW (1<<5) | ||
38 | #define S3C2410_IISMOD_IIS (0<<4) | ||
39 | #define S3C2410_IISMOD_MSB (1<<4) | ||
40 | #define S3C2410_IISMOD_8BIT (0<<3) | ||
41 | #define S3C2410_IISMOD_16BIT (1<<3) | ||
42 | #define S3C2410_IISMOD_BITMASK (1<<3) | ||
43 | #define S3C2410_IISMOD_256FS (0<<2) | ||
44 | #define S3C2410_IISMOD_384FS (1<<2) | ||
45 | #define S3C2410_IISMOD_16FS (0<<0) | ||
46 | #define S3C2410_IISMOD_32FS (1<<0) | ||
47 | #define S3C2410_IISMOD_48FS (2<<0) | ||
48 | #define S3C2410_IISMOD_FS_MASK (3<<0) | ||
49 | |||
50 | #define S3C2410_IISPSR (0x08) | ||
51 | #define S3C2410_IISPSR_INTMASK (31<<5) | ||
52 | #define S3C2410_IISPSR_INTSHIFT (5) | ||
53 | #define S3C2410_IISPSR_EXTMASK (31<<0) | ||
54 | #define S3C2410_IISPSR_EXTSHFIT (0) | ||
55 | |||
56 | #define S3C2410_IISFCON (0x0c) | ||
57 | |||
58 | #define S3C2410_IISFCON_TXDMA (1<<15) | ||
59 | #define S3C2410_IISFCON_RXDMA (1<<14) | ||
60 | #define S3C2410_IISFCON_TXENABLE (1<<13) | ||
61 | #define S3C2410_IISFCON_RXENABLE (1<<12) | ||
62 | #define S3C2410_IISFCON_TXMASK (0x3f << 6) | ||
63 | #define S3C2410_IISFCON_TXSHIFT (6) | ||
64 | #define S3C2410_IISFCON_RXMASK (0x3f) | ||
65 | #define S3C2410_IISFCON_RXSHIFT (0) | ||
66 | |||
67 | #define S3C2410_IISFIFO (0x10) | ||
68 | #endif /* __ASM_ARCH_REGS_IIS_H */ | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h new file mode 100644 index 00000000000..892e2f680fc --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h | |||
@@ -0,0 +1,81 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-spi.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Fetron GmbH | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | * | ||
9 | * S3C2410 SPI register definition | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARCH_REGS_SPI_H | ||
13 | #define __ASM_ARCH_REGS_SPI_H | ||
14 | |||
15 | #define S3C2410_SPI1 (0x20) | ||
16 | #define S3C2412_SPI1 (0x100) | ||
17 | |||
18 | #define S3C2410_SPCON (0x00) | ||
19 | |||
20 | #define S3C2412_SPCON_RXFIFO_RB2 (0<<14) | ||
21 | #define S3C2412_SPCON_RXFIFO_RB4 (1<<14) | ||
22 | #define S3C2412_SPCON_RXFIFO_RB12 (2<<14) | ||
23 | #define S3C2412_SPCON_RXFIFO_RB14 (3<<14) | ||
24 | #define S3C2412_SPCON_TXFIFO_RB2 (0<<12) | ||
25 | #define S3C2412_SPCON_TXFIFO_RB4 (1<<12) | ||
26 | #define S3C2412_SPCON_TXFIFO_RB12 (2<<12) | ||
27 | #define S3C2412_SPCON_TXFIFO_RB14 (3<<12) | ||
28 | #define S3C2412_SPCON_RXFIFO_RESET (1<<11) /* RxFIFO reset */ | ||
29 | #define S3C2412_SPCON_TXFIFO_RESET (1<<10) /* TxFIFO reset */ | ||
30 | #define S3C2412_SPCON_RXFIFO_EN (1<<9) /* RxFIFO Enable */ | ||
31 | #define S3C2412_SPCON_TXFIFO_EN (1<<8) /* TxFIFO Enable */ | ||
32 | |||
33 | #define S3C2412_SPCON_DIRC_RX (1<<7) | ||
34 | |||
35 | #define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */ | ||
36 | #define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */ | ||
37 | #define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */ | ||
38 | #define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */ | ||
39 | #define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select | ||
40 | 0: slave, 1: master */ | ||
41 | #define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */ | ||
42 | #define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */ | ||
43 | |||
44 | #define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */ | ||
45 | #define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */ | ||
46 | |||
47 | #define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */ | ||
48 | |||
49 | |||
50 | #define S3C2410_SPSTA (0x04) | ||
51 | |||
52 | #define S3C2412_SPSTA_RXFIFO_AE (1<<11) | ||
53 | #define S3C2412_SPSTA_TXFIFO_AE (1<<10) | ||
54 | #define S3C2412_SPSTA_RXFIFO_ERROR (1<<9) | ||
55 | #define S3C2412_SPSTA_TXFIFO_ERROR (1<<8) | ||
56 | #define S3C2412_SPSTA_RXFIFO_FIFO (1<<7) | ||
57 | #define S3C2412_SPSTA_RXFIFO_EMPTY (1<<6) | ||
58 | #define S3C2412_SPSTA_TXFIFO_NFULL (1<<5) | ||
59 | #define S3C2412_SPSTA_TXFIFO_EMPTY (1<<4) | ||
60 | |||
61 | #define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */ | ||
62 | #define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */ | ||
63 | #define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */ | ||
64 | #define S3C2412_SPSTA_READY_ORG (1<<3) | ||
65 | |||
66 | #define S3C2410_SPPIN (0x08) | ||
67 | |||
68 | #define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */ | ||
69 | #define S3C2410_SPPIN_RESERVED (1<<1) | ||
70 | #define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */ | ||
71 | |||
72 | #define S3C2410_SPPRE (0x0C) | ||
73 | #define S3C2410_SPTDAT (0x10) | ||
74 | #define S3C2410_SPRDAT (0x14) | ||
75 | |||
76 | #define S3C2412_TXFIFO (0x18) | ||
77 | #define S3C2412_RXFIFO (0x18) | ||
78 | #define S3C2412_SPFIC (0x24) | ||
79 | |||
80 | |||
81 | #endif /* __ASM_ARCH_REGS_SPI_H */ | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-udc.h b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h new file mode 100644 index 00000000000..f0dd4a41b37 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h | |||
@@ -0,0 +1,153 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-udc.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at> | ||
4 | * | ||
5 | * This include file is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License as | ||
7 | * published by the Free Software Foundation; either version 2 of | ||
8 | * the License, or (at your option) any later version. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_REGS_UDC_H | ||
12 | #define __ASM_ARCH_REGS_UDC_H | ||
13 | |||
14 | #define S3C2410_USBDREG(x) (x) | ||
15 | |||
16 | #define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140) | ||
17 | #define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144) | ||
18 | #define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148) | ||
19 | |||
20 | #define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158) | ||
21 | #define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c) | ||
22 | |||
23 | #define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c) | ||
24 | |||
25 | #define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170) | ||
26 | #define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174) | ||
27 | |||
28 | #define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0) | ||
29 | #define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4) | ||
30 | #define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8) | ||
31 | #define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc) | ||
32 | #define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0) | ||
33 | |||
34 | #define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200) | ||
35 | #define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204) | ||
36 | #define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208) | ||
37 | #define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c) | ||
38 | #define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210) | ||
39 | #define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214) | ||
40 | |||
41 | #define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218) | ||
42 | #define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c) | ||
43 | #define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220) | ||
44 | #define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224) | ||
45 | #define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228) | ||
46 | #define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c) | ||
47 | |||
48 | #define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240) | ||
49 | #define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244) | ||
50 | #define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248) | ||
51 | #define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c) | ||
52 | #define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250) | ||
53 | #define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254) | ||
54 | |||
55 | #define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258) | ||
56 | #define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c) | ||
57 | #define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260) | ||
58 | #define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264) | ||
59 | #define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268) | ||
60 | #define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c) | ||
61 | |||
62 | #define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178) | ||
63 | |||
64 | /* indexed registers */ | ||
65 | |||
66 | #define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180) | ||
67 | |||
68 | #define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184) | ||
69 | |||
70 | #define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184) | ||
71 | #define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188) | ||
72 | |||
73 | #define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190) | ||
74 | #define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194) | ||
75 | #define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198) | ||
76 | #define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c) | ||
77 | |||
78 | #define S3C2410_UDC_FUNCADDR_UPDATE (1<<7) | ||
79 | |||
80 | #define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W | ||
81 | #define S3C2410_UDC_PWR_RESET (1<<3) // R | ||
82 | #define S3C2410_UDC_PWR_RESUME (1<<2) // R/W | ||
83 | #define S3C2410_UDC_PWR_SUSPEND (1<<1) // R | ||
84 | #define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W | ||
85 | |||
86 | #define S3C2410_UDC_PWR_DEFAULT 0x00 | ||
87 | |||
88 | #define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only) | ||
89 | #define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only) | ||
90 | #define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only) | ||
91 | #define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only) | ||
92 | #define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only) | ||
93 | |||
94 | #define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only) | ||
95 | #define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only) | ||
96 | #define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only) | ||
97 | |||
98 | #define S3C2410_UDC_INTE_EP4 (1<<4) // R/W | ||
99 | #define S3C2410_UDC_INTE_EP3 (1<<3) // R/W | ||
100 | #define S3C2410_UDC_INTE_EP2 (1<<2) // R/W | ||
101 | #define S3C2410_UDC_INTE_EP1 (1<<1) // R/W | ||
102 | #define S3C2410_UDC_INTE_EP0 (1<<0) // R/W | ||
103 | |||
104 | #define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W | ||
105 | #define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W | ||
106 | |||
107 | |||
108 | #define S3C2410_UDC_INDEX_EP0 (0x00) | ||
109 | #define S3C2410_UDC_INDEX_EP1 (0x01) // ?? | ||
110 | #define S3C2410_UDC_INDEX_EP2 (0x02) // ?? | ||
111 | #define S3C2410_UDC_INDEX_EP3 (0x03) // ?? | ||
112 | #define S3C2410_UDC_INDEX_EP4 (0x04) // ?? | ||
113 | |||
114 | #define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W | ||
115 | #define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only) | ||
116 | #define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W | ||
117 | #define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only) | ||
118 | #define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only) | ||
119 | #define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only) | ||
120 | |||
121 | #define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W | ||
122 | #define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W | ||
123 | #define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W | ||
124 | #define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W | ||
125 | |||
126 | #define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W | ||
127 | #define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only) | ||
128 | #define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W | ||
129 | #define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W | ||
130 | #define S3C2410_UDC_OCSR1_DERROR (1<<3) // R | ||
131 | #define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only) | ||
132 | #define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only) | ||
133 | |||
134 | #define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W | ||
135 | #define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W | ||
136 | #define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W | ||
137 | |||
138 | #define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0) | ||
139 | #define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1) | ||
140 | #define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2) | ||
141 | #define S3C2410_UDC_EP0_CSR_DE (1<<3) | ||
142 | #define S3C2410_UDC_EP0_CSR_SE (1<<4) | ||
143 | #define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5) | ||
144 | #define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6) | ||
145 | #define S3C2410_UDC_EP0_CSR_SSE (1<<7) | ||
146 | |||
147 | #define S3C2410_UDC_MAXP_8 (1<<0) | ||
148 | #define S3C2410_UDC_MAXP_16 (1<<1) | ||
149 | #define S3C2410_UDC_MAXP_32 (1<<2) | ||
150 | #define S3C2410_UDC_MAXP_64 (1<<3) | ||
151 | |||
152 | |||
153 | #endif | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h new file mode 100644 index 00000000000..82ab4aad1bb --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /* linux/include/asm-arm/plat-s3c24xx/s3c2410.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Header file for s3c2410 machine directory | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #ifdef CONFIG_CPU_S3C2410 | ||
15 | |||
16 | extern int s3c2410_init(void); | ||
17 | extern int s3c2410a_init(void); | ||
18 | |||
19 | extern void s3c2410_map_io(void); | ||
20 | |||
21 | extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
22 | |||
23 | extern void s3c2410_init_clocks(int xtal); | ||
24 | |||
25 | #else | ||
26 | #define s3c2410_init_clocks NULL | ||
27 | #define s3c2410_init_uarts NULL | ||
28 | #define s3c2410_map_io NULL | ||
29 | #define s3c2410_init NULL | ||
30 | #define s3c2410a_init NULL | ||
31 | #endif | ||
32 | |||
33 | extern int s3c2410_baseclk_add(void); | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h b/arch/arm/plat-s3c24xx/include/plat/s3c2412.h new file mode 100644 index 00000000000..bb15d3b68be --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2412.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* linux/include/asm-arm/plat-s3c24xx/s3c2412.h | ||
2 | * | ||
3 | * Copyright (c) 2006 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Header file for s3c2412 cpu support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifdef CONFIG_CPU_S3C2412 | ||
14 | |||
15 | extern int s3c2412_init(void); | ||
16 | |||
17 | extern void s3c2412_map_io(void); | ||
18 | |||
19 | extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
20 | |||
21 | extern void s3c2412_init_clocks(int xtal); | ||
22 | |||
23 | extern int s3c2412_baseclk_add(void); | ||
24 | #else | ||
25 | #define s3c2412_init_clocks NULL | ||
26 | #define s3c2412_init_uarts NULL | ||
27 | #define s3c2412_map_io NULL | ||
28 | #define s3c2412_init NULL | ||
29 | #endif | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2416.h b/arch/arm/plat-s3c24xx/include/plat/s3c2416.h new file mode 100644 index 00000000000..dc3c0907d22 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2416.h | |||
@@ -0,0 +1,31 @@ | |||
1 | /* linux/include/asm-arm/plat-s3c24xx/s3c2443.h | ||
2 | * | ||
3 | * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com> | ||
4 | * | ||
5 | * Header file for s3c2416 cpu support | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #ifdef CONFIG_CPU_S3C2416 | ||
13 | |||
14 | struct s3c2410_uartcfg; | ||
15 | |||
16 | extern int s3c2416_init(void); | ||
17 | |||
18 | extern void s3c2416_map_io(void); | ||
19 | |||
20 | extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
21 | |||
22 | extern void s3c2416_init_clocks(int xtal); | ||
23 | |||
24 | extern int s3c2416_baseclk_add(void); | ||
25 | |||
26 | #else | ||
27 | #define s3c2416_init_clocks NULL | ||
28 | #define s3c2416_init_uarts NULL | ||
29 | #define s3c2416_map_io NULL | ||
30 | #define s3c2416_init NULL | ||
31 | #endif | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h new file mode 100644 index 00000000000..a19715feb79 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h | |||
@@ -0,0 +1,51 @@ | |||
1 | /* linux/include/asm-arm/plat-s3c24xx/s3c2443.h | ||
2 | * | ||
3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Header file for s3c2443 cpu support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifdef CONFIG_CPU_S3C2443 | ||
14 | |||
15 | struct s3c2410_uartcfg; | ||
16 | |||
17 | extern int s3c2443_init(void); | ||
18 | |||
19 | extern void s3c2443_map_io(void); | ||
20 | |||
21 | extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
22 | |||
23 | extern void s3c2443_init_clocks(int xtal); | ||
24 | |||
25 | extern int s3c2443_baseclk_add(void); | ||
26 | |||
27 | #else | ||
28 | #define s3c2443_init_clocks NULL | ||
29 | #define s3c2443_init_uarts NULL | ||
30 | #define s3c2443_map_io NULL | ||
31 | #define s3c2443_init NULL | ||
32 | #endif | ||
33 | |||
34 | /* common code used by s3c2443 and others. | ||
35 | * note, not to be used outside of arch/arm/mach-s3c* */ | ||
36 | |||
37 | struct clk; /* some files don't need clk.h otherwise */ | ||
38 | |||
39 | typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base); | ||
40 | typedef unsigned int (*fdiv_fn)(unsigned long clkcon0); | ||
41 | |||
42 | extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv); | ||
43 | extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv); | ||
44 | |||
45 | extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable); | ||
46 | extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable); | ||
47 | extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable); | ||
48 | |||
49 | extern struct clksrc_clk clk_epllref; | ||
50 | extern struct clksrc_clk clk_esysclk; | ||
51 | extern struct clksrc_clk clk_msysclk; | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c244x.h b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h new file mode 100644 index 00000000000..89e8d0a25f8 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/include/plat/s3c244x.h | ||
2 | * | ||
3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Header file for S3C2440 and S3C2442 cpu support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) | ||
14 | |||
15 | extern void s3c244x_map_io(void); | ||
16 | |||
17 | extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
18 | |||
19 | extern void s3c244x_init_clocks(int xtal); | ||
20 | |||
21 | #else | ||
22 | #define s3c244x_init_clocks NULL | ||
23 | #define s3c244x_init_uarts NULL | ||
24 | #endif | ||
25 | |||
26 | #ifdef CONFIG_CPU_S3C2440 | ||
27 | extern int s3c2440_init(void); | ||
28 | |||
29 | extern void s3c2440_map_io(void); | ||
30 | #else | ||
31 | #define s3c2440_init NULL | ||
32 | #define s3c2440_map_io NULL | ||
33 | #endif | ||
34 | |||
35 | #ifdef CONFIG_CPU_S3C2442 | ||
36 | extern int s3c2442_init(void); | ||
37 | |||
38 | extern void s3c2442_map_io(void); | ||
39 | #else | ||
40 | #define s3c2442_init NULL | ||
41 | #define s3c2442_map_io NULL | ||
42 | #endif | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/udc.h b/arch/arm/plat-s3c24xx/include/plat/udc.h new file mode 100644 index 00000000000..f6388424250 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/udc.h | |||
@@ -0,0 +1,57 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/udc.h | ||
2 | * | ||
3 | * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org> | ||
4 | * | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * | ||
11 | * Changelog: | ||
12 | * 14-Mar-2005 RTP Created file | ||
13 | * 02-Aug-2005 RTP File rename | ||
14 | * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum | ||
15 | * 18-Jan-2007 HMW Add per-platform vbus_draw function | ||
16 | */ | ||
17 | |||
18 | #ifndef __ASM_ARM_ARCH_UDC_H | ||
19 | #define __ASM_ARM_ARCH_UDC_H | ||
20 | |||
21 | enum s3c2410_udc_cmd_e { | ||
22 | S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */ | ||
23 | S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */ | ||
24 | S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */ | ||
25 | }; | ||
26 | |||
27 | struct s3c2410_udc_mach_info { | ||
28 | void (*udc_command)(enum s3c2410_udc_cmd_e); | ||
29 | void (*vbus_draw)(unsigned int ma); | ||
30 | |||
31 | unsigned int pullup_pin; | ||
32 | unsigned int pullup_pin_inverted; | ||
33 | |||
34 | unsigned int vbus_pin; | ||
35 | unsigned char vbus_pin_inverted; | ||
36 | }; | ||
37 | |||
38 | extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *); | ||
39 | |||
40 | /** | ||
41 | * s3c24xx_hsudc_platdata - Platform data for USB High-Speed gadget controller. | ||
42 | * @epnum: Number of endpoints to be instantiated by the controller driver. | ||
43 | * @gpio_init: Platform specific USB related GPIO initialization. | ||
44 | * @gpio_uninit: Platform specific USB releted GPIO uninitialzation. | ||
45 | * | ||
46 | * Representation of platform data for the S3C24XX USB 2.0 High Speed gadget | ||
47 | * controllers. | ||
48 | */ | ||
49 | struct s3c24xx_hsudc_platdata { | ||
50 | unsigned int epnum; | ||
51 | void (*gpio_init)(void); | ||
52 | void (*gpio_uninit)(void); | ||
53 | }; | ||
54 | |||
55 | extern void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd); | ||
56 | |||
57 | #endif /* __ASM_ARM_ARCH_UDC_H */ | ||
diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c new file mode 100644 index 00000000000..0efb2e2848c --- /dev/null +++ b/arch/arm/plat-s3c24xx/irq-pm.c | |||
@@ -0,0 +1,95 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/irq-om.c | ||
2 | * | ||
3 | * Copyright (c) 2003-2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C24XX - IRQ PM code | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/irq.h> | ||
18 | |||
19 | #include <plat/cpu.h> | ||
20 | #include <plat/pm.h> | ||
21 | #include <plat/irq.h> | ||
22 | |||
23 | #include <asm/irq.h> | ||
24 | |||
25 | /* state for IRQs over sleep */ | ||
26 | |||
27 | /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources | ||
28 | * | ||
29 | * set bit to 1 in allow bitfield to enable the wakeup settings on it | ||
30 | */ | ||
31 | |||
32 | unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; | ||
33 | unsigned long s3c_irqwake_eintallow = 0x0000fff0L; | ||
34 | |||
35 | int s3c_irq_wake(struct irq_data *data, unsigned int state) | ||
36 | { | ||
37 | unsigned long irqbit = 1 << (data->irq - IRQ_EINT0); | ||
38 | |||
39 | if (!(s3c_irqwake_intallow & irqbit)) | ||
40 | return -ENOENT; | ||
41 | |||
42 | printk(KERN_INFO "wake %s for irq %d\n", | ||
43 | state ? "enabled" : "disabled", data->irq); | ||
44 | |||
45 | if (!state) | ||
46 | s3c_irqwake_intmask |= irqbit; | ||
47 | else | ||
48 | s3c_irqwake_intmask &= ~irqbit; | ||
49 | |||
50 | return 0; | ||
51 | } | ||
52 | |||
53 | static struct sleep_save irq_save[] = { | ||
54 | SAVE_ITEM(S3C2410_INTMSK), | ||
55 | SAVE_ITEM(S3C2410_INTSUBMSK), | ||
56 | }; | ||
57 | |||
58 | /* the extint values move between the s3c2410/s3c2440 and the s3c2412 | ||
59 | * so we use an array to hold them, and to calculate the address of | ||
60 | * the register at run-time | ||
61 | */ | ||
62 | |||
63 | static unsigned long save_extint[3]; | ||
64 | static unsigned long save_eintflt[4]; | ||
65 | static unsigned long save_eintmask; | ||
66 | |||
67 | int s3c24xx_irq_suspend(void) | ||
68 | { | ||
69 | unsigned int i; | ||
70 | |||
71 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | ||
72 | save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); | ||
73 | |||
74 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | ||
75 | save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); | ||
76 | |||
77 | s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); | ||
78 | save_eintmask = __raw_readl(S3C24XX_EINTMASK); | ||
79 | |||
80 | return 0; | ||
81 | } | ||
82 | |||
83 | void s3c24xx_irq_resume(void) | ||
84 | { | ||
85 | unsigned int i; | ||
86 | |||
87 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | ||
88 | __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4)); | ||
89 | |||
90 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | ||
91 | __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4)); | ||
92 | |||
93 | s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); | ||
94 | __raw_writel(save_eintmask, S3C24XX_EINTMASK); | ||
95 | } | ||
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c new file mode 100644 index 00000000000..663b280d65d --- /dev/null +++ b/arch/arm/plat-s3c24xx/pm-simtec.c | |||
@@ -0,0 +1,67 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/pm-simtec.c | ||
2 | * | ||
3 | * Copyright 2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * Power Management helpers for Simtec S3C24XX implementations | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/list.h> | ||
19 | #include <linux/timer.h> | ||
20 | #include <linux/init.h> | ||
21 | #include <linux/sysdev.h> | ||
22 | #include <linux/device.h> | ||
23 | #include <linux/io.h> | ||
24 | |||
25 | #include <asm/mach/arch.h> | ||
26 | #include <asm/mach/map.h> | ||
27 | |||
28 | #include <mach/hardware.h> | ||
29 | |||
30 | #include <mach/map.h> | ||
31 | #include <mach/regs-gpio.h> | ||
32 | #include <mach/regs-mem.h> | ||
33 | |||
34 | #include <asm/mach-types.h> | ||
35 | |||
36 | #include <plat/pm.h> | ||
37 | |||
38 | #define COPYRIGHT ", Copyright 2005 Simtec Electronics" | ||
39 | |||
40 | /* pm_simtec_init | ||
41 | * | ||
42 | * enable the power management functions | ||
43 | */ | ||
44 | |||
45 | static __init int pm_simtec_init(void) | ||
46 | { | ||
47 | unsigned long gstatus4; | ||
48 | |||
49 | /* check which machine we are running on */ | ||
50 | |||
51 | if (!machine_is_bast() && !machine_is_vr1000() && | ||
52 | !machine_is_anubis() && !machine_is_osiris() && | ||
53 | !machine_is_aml_m5900()) | ||
54 | return 0; | ||
55 | |||
56 | printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n"); | ||
57 | |||
58 | gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30; | ||
59 | gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28; | ||
60 | gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK); | ||
61 | |||
62 | __raw_writel(gstatus4, S3C2410_GSTATUS4); | ||
63 | |||
64 | return s3c_pm_init(); | ||
65 | } | ||
66 | |||
67 | arch_initcall(pm_simtec_init); | ||
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c new file mode 100644 index 00000000000..60627e63a25 --- /dev/null +++ b/arch/arm/plat-s3c24xx/pm.c | |||
@@ -0,0 +1,149 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/pm.c | ||
2 | * | ||
3 | * Copyright (c) 2004-2006 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C24XX Power Manager (Suspend-To-RAM) support | ||
7 | * | ||
8 | * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
23 | * | ||
24 | * Parts based on arch/arm/mach-pxa/pm.c | ||
25 | * | ||
26 | * Thanks to Dimitry Andric for debugging | ||
27 | */ | ||
28 | |||
29 | #include <linux/init.h> | ||
30 | #include <linux/suspend.h> | ||
31 | #include <linux/errno.h> | ||
32 | #include <linux/time.h> | ||
33 | #include <linux/gpio.h> | ||
34 | #include <linux/interrupt.h> | ||
35 | #include <linux/serial_core.h> | ||
36 | #include <linux/io.h> | ||
37 | |||
38 | #include <plat/regs-serial.h> | ||
39 | #include <mach/regs-clock.h> | ||
40 | #include <mach/regs-gpio.h> | ||
41 | #include <mach/regs-mem.h> | ||
42 | #include <mach/regs-irq.h> | ||
43 | |||
44 | #include <asm/mach/time.h> | ||
45 | |||
46 | #include <plat/gpio-cfg.h> | ||
47 | #include <plat/pm.h> | ||
48 | |||
49 | #define PFX "s3c24xx-pm: " | ||
50 | |||
51 | static struct sleep_save core_save[] = { | ||
52 | SAVE_ITEM(S3C2410_LOCKTIME), | ||
53 | SAVE_ITEM(S3C2410_CLKCON), | ||
54 | |||
55 | /* we restore the timings here, with the proviso that the board | ||
56 | * brings the system up in an slower, or equal frequency setting | ||
57 | * to the original system. | ||
58 | * | ||
59 | * if we cannot guarantee this, then things are going to go very | ||
60 | * wrong here, as we modify the refresh and both pll settings. | ||
61 | */ | ||
62 | |||
63 | SAVE_ITEM(S3C2410_BWSCON), | ||
64 | SAVE_ITEM(S3C2410_BANKCON0), | ||
65 | SAVE_ITEM(S3C2410_BANKCON1), | ||
66 | SAVE_ITEM(S3C2410_BANKCON2), | ||
67 | SAVE_ITEM(S3C2410_BANKCON3), | ||
68 | SAVE_ITEM(S3C2410_BANKCON4), | ||
69 | SAVE_ITEM(S3C2410_BANKCON5), | ||
70 | |||
71 | #ifndef CONFIG_CPU_FREQ | ||
72 | SAVE_ITEM(S3C2410_CLKDIVN), | ||
73 | SAVE_ITEM(S3C2410_MPLLCON), | ||
74 | SAVE_ITEM(S3C2410_REFRESH), | ||
75 | #endif | ||
76 | SAVE_ITEM(S3C2410_UPLLCON), | ||
77 | SAVE_ITEM(S3C2410_CLKSLOW), | ||
78 | }; | ||
79 | |||
80 | static struct sleep_save misc_save[] = { | ||
81 | SAVE_ITEM(S3C2410_DCLKCON), | ||
82 | }; | ||
83 | |||
84 | /* s3c_pm_check_resume_pin | ||
85 | * | ||
86 | * check to see if the pin is configured correctly for sleep mode, and | ||
87 | * make any necessary adjustments if it is not | ||
88 | */ | ||
89 | |||
90 | static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) | ||
91 | { | ||
92 | unsigned long irqstate; | ||
93 | unsigned long pinstate; | ||
94 | int irq = gpio_to_irq(pin); | ||
95 | |||
96 | if (irqoffs < 4) | ||
97 | irqstate = s3c_irqwake_intmask & (1L<<irqoffs); | ||
98 | else | ||
99 | irqstate = s3c_irqwake_eintmask & (1L<<irqoffs); | ||
100 | |||
101 | pinstate = s3c_gpio_getcfg(pin); | ||
102 | |||
103 | if (!irqstate) { | ||
104 | if (pinstate == S3C2410_GPIO_IRQ) | ||
105 | S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin); | ||
106 | } else { | ||
107 | if (pinstate == S3C2410_GPIO_IRQ) { | ||
108 | S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); | ||
109 | s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); | ||
110 | } | ||
111 | } | ||
112 | } | ||
113 | |||
114 | /* s3c_pm_configure_extint | ||
115 | * | ||
116 | * configure all external interrupt pins | ||
117 | */ | ||
118 | |||
119 | void s3c_pm_configure_extint(void) | ||
120 | { | ||
121 | int pin; | ||
122 | |||
123 | /* for each of the external interrupts (EINT0..EINT15) we | ||
124 | * need to check wether it is an external interrupt source, | ||
125 | * and then configure it as an input if it is not | ||
126 | */ | ||
127 | |||
128 | for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) { | ||
129 | s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0)); | ||
130 | } | ||
131 | |||
132 | for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) { | ||
133 | s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8); | ||
134 | } | ||
135 | } | ||
136 | |||
137 | |||
138 | void s3c_pm_restore_core(void) | ||
139 | { | ||
140 | s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); | ||
141 | s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); | ||
142 | } | ||
143 | |||
144 | void s3c_pm_save_core(void) | ||
145 | { | ||
146 | s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); | ||
147 | s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); | ||
148 | } | ||
149 | |||
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c new file mode 100644 index 00000000000..59552c0ea5f --- /dev/null +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c | |||
@@ -0,0 +1,441 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c | ||
2 | * | ||
3 | * Copyright (c) 2007, 2010 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2443 Clock control suport - common code | ||
7 | */ | ||
8 | |||
9 | #include <linux/init.h> | ||
10 | #include <linux/clk.h> | ||
11 | #include <linux/io.h> | ||
12 | |||
13 | #include <mach/regs-s3c2443-clock.h> | ||
14 | |||
15 | #include <plat/s3c2443.h> | ||
16 | #include <plat/clock.h> | ||
17 | #include <plat/clock-clksrc.h> | ||
18 | #include <plat/cpu.h> | ||
19 | |||
20 | #include <plat/cpu-freq.h> | ||
21 | |||
22 | |||
23 | static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable) | ||
24 | { | ||
25 | u32 ctrlbit = clk->ctrlbit; | ||
26 | u32 con = __raw_readl(reg); | ||
27 | |||
28 | if (enable) | ||
29 | con |= ctrlbit; | ||
30 | else | ||
31 | con &= ~ctrlbit; | ||
32 | |||
33 | __raw_writel(con, reg); | ||
34 | return 0; | ||
35 | } | ||
36 | |||
37 | int s3c2443_clkcon_enable_h(struct clk *clk, int enable) | ||
38 | { | ||
39 | return s3c2443_gate(S3C2443_HCLKCON, clk, enable); | ||
40 | } | ||
41 | |||
42 | int s3c2443_clkcon_enable_p(struct clk *clk, int enable) | ||
43 | { | ||
44 | return s3c2443_gate(S3C2443_PCLKCON, clk, enable); | ||
45 | } | ||
46 | |||
47 | int s3c2443_clkcon_enable_s(struct clk *clk, int enable) | ||
48 | { | ||
49 | return s3c2443_gate(S3C2443_SCLKCON, clk, enable); | ||
50 | } | ||
51 | |||
52 | /* mpllref is a direct descendant of clk_xtal by default, but it is not | ||
53 | * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as | ||
54 | * such directly equating the two source clocks is impossible. | ||
55 | */ | ||
56 | struct clk clk_mpllref = { | ||
57 | .name = "mpllref", | ||
58 | .parent = &clk_xtal, | ||
59 | }; | ||
60 | |||
61 | static struct clk *clk_epllref_sources[] = { | ||
62 | [0] = &clk_mpllref, | ||
63 | [1] = &clk_mpllref, | ||
64 | [2] = &clk_xtal, | ||
65 | [3] = &clk_ext, | ||
66 | }; | ||
67 | |||
68 | struct clksrc_clk clk_epllref = { | ||
69 | .clk = { | ||
70 | .name = "epllref", | ||
71 | }, | ||
72 | .sources = &(struct clksrc_sources) { | ||
73 | .sources = clk_epllref_sources, | ||
74 | .nr_sources = ARRAY_SIZE(clk_epllref_sources), | ||
75 | }, | ||
76 | .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 }, | ||
77 | }; | ||
78 | |||
79 | /* esysclk | ||
80 | * | ||
81 | * this is sourced from either the EPLL or the EPLLref clock | ||
82 | */ | ||
83 | |||
84 | static struct clk *clk_sysclk_sources[] = { | ||
85 | [0] = &clk_epllref.clk, | ||
86 | [1] = &clk_epll, | ||
87 | }; | ||
88 | |||
89 | struct clksrc_clk clk_esysclk = { | ||
90 | .clk = { | ||
91 | .name = "esysclk", | ||
92 | .parent = &clk_epll, | ||
93 | }, | ||
94 | .sources = &(struct clksrc_sources) { | ||
95 | .sources = clk_sysclk_sources, | ||
96 | .nr_sources = ARRAY_SIZE(clk_sysclk_sources), | ||
97 | }, | ||
98 | .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 }, | ||
99 | }; | ||
100 | |||
101 | static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) | ||
102 | { | ||
103 | unsigned long parent_rate = clk_get_rate(clk->parent); | ||
104 | unsigned long div = __raw_readl(S3C2443_CLKDIV0); | ||
105 | |||
106 | div &= S3C2443_CLKDIV0_EXTDIV_MASK; | ||
107 | div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */ | ||
108 | |||
109 | return parent_rate / (div + 1); | ||
110 | } | ||
111 | |||
112 | static struct clk clk_mdivclk = { | ||
113 | .name = "mdivclk", | ||
114 | .parent = &clk_mpllref, | ||
115 | .ops = &(struct clk_ops) { | ||
116 | .get_rate = s3c2443_getrate_mdivclk, | ||
117 | }, | ||
118 | }; | ||
119 | |||
120 | static struct clk *clk_msysclk_sources[] = { | ||
121 | [0] = &clk_mpllref, | ||
122 | [1] = &clk_mpll, | ||
123 | [2] = &clk_mdivclk, | ||
124 | [3] = &clk_mpllref, | ||
125 | }; | ||
126 | |||
127 | struct clksrc_clk clk_msysclk = { | ||
128 | .clk = { | ||
129 | .name = "msysclk", | ||
130 | .parent = &clk_xtal, | ||
131 | }, | ||
132 | .sources = &(struct clksrc_sources) { | ||
133 | .sources = clk_msysclk_sources, | ||
134 | .nr_sources = ARRAY_SIZE(clk_msysclk_sources), | ||
135 | }, | ||
136 | .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 }, | ||
137 | }; | ||
138 | |||
139 | /* prediv | ||
140 | * | ||
141 | * this divides the msysclk down to pass to h/p/etc. | ||
142 | */ | ||
143 | |||
144 | static unsigned long s3c2443_prediv_getrate(struct clk *clk) | ||
145 | { | ||
146 | unsigned long rate = clk_get_rate(clk->parent); | ||
147 | unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); | ||
148 | |||
149 | clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK; | ||
150 | clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT; | ||
151 | |||
152 | return rate / (clkdiv0 + 1); | ||
153 | } | ||
154 | |||
155 | static struct clk clk_prediv = { | ||
156 | .name = "prediv", | ||
157 | .parent = &clk_msysclk.clk, | ||
158 | .ops = &(struct clk_ops) { | ||
159 | .get_rate = s3c2443_prediv_getrate, | ||
160 | }, | ||
161 | }; | ||
162 | |||
163 | /* usbhost | ||
164 | * | ||
165 | * usb host bus-clock, usually 48MHz to provide USB bus clock timing | ||
166 | */ | ||
167 | |||
168 | static struct clksrc_clk clk_usb_bus_host = { | ||
169 | .clk = { | ||
170 | .name = "usb-bus-host-parent", | ||
171 | .parent = &clk_esysclk.clk, | ||
172 | .ctrlbit = S3C2443_SCLKCON_USBHOST, | ||
173 | .enable = s3c2443_clkcon_enable_s, | ||
174 | }, | ||
175 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, | ||
176 | }; | ||
177 | |||
178 | /* common clksrc clocks */ | ||
179 | |||
180 | static struct clksrc_clk clksrc_clks[] = { | ||
181 | { | ||
182 | /* ART baud-rate clock sourced from esysclk via a divisor */ | ||
183 | .clk = { | ||
184 | .name = "uartclk", | ||
185 | .parent = &clk_esysclk.clk, | ||
186 | }, | ||
187 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, | ||
188 | }, { | ||
189 | /* camera interface bus-clock, divided down from esysclk */ | ||
190 | .clk = { | ||
191 | .name = "camif-upll", /* same as 2440 name */ | ||
192 | .parent = &clk_esysclk.clk, | ||
193 | .ctrlbit = S3C2443_SCLKCON_CAMCLK, | ||
194 | .enable = s3c2443_clkcon_enable_s, | ||
195 | }, | ||
196 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 }, | ||
197 | }, { | ||
198 | .clk = { | ||
199 | .name = "display-if", | ||
200 | .parent = &clk_esysclk.clk, | ||
201 | .ctrlbit = S3C2443_SCLKCON_DISPCLK, | ||
202 | .enable = s3c2443_clkcon_enable_s, | ||
203 | }, | ||
204 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 }, | ||
205 | }, | ||
206 | }; | ||
207 | |||
208 | |||
209 | static struct clk init_clocks_off[] = { | ||
210 | { | ||
211 | .name = "adc", | ||
212 | .parent = &clk_p, | ||
213 | .enable = s3c2443_clkcon_enable_p, | ||
214 | .ctrlbit = S3C2443_PCLKCON_ADC, | ||
215 | }, { | ||
216 | .name = "i2c", | ||
217 | .parent = &clk_p, | ||
218 | .enable = s3c2443_clkcon_enable_p, | ||
219 | .ctrlbit = S3C2443_PCLKCON_IIC, | ||
220 | } | ||
221 | }; | ||
222 | |||
223 | static struct clk init_clocks[] = { | ||
224 | { | ||
225 | .name = "dma", | ||
226 | .parent = &clk_h, | ||
227 | .enable = s3c2443_clkcon_enable_h, | ||
228 | .ctrlbit = S3C2443_HCLKCON_DMA0, | ||
229 | }, { | ||
230 | .name = "dma", | ||
231 | .parent = &clk_h, | ||
232 | .enable = s3c2443_clkcon_enable_h, | ||
233 | .ctrlbit = S3C2443_HCLKCON_DMA1, | ||
234 | }, { | ||
235 | .name = "dma", | ||
236 | .parent = &clk_h, | ||
237 | .enable = s3c2443_clkcon_enable_h, | ||
238 | .ctrlbit = S3C2443_HCLKCON_DMA2, | ||
239 | }, { | ||
240 | .name = "dma", | ||
241 | .parent = &clk_h, | ||
242 | .enable = s3c2443_clkcon_enable_h, | ||
243 | .ctrlbit = S3C2443_HCLKCON_DMA3, | ||
244 | }, { | ||
245 | .name = "dma", | ||
246 | .parent = &clk_h, | ||
247 | .enable = s3c2443_clkcon_enable_h, | ||
248 | .ctrlbit = S3C2443_HCLKCON_DMA4, | ||
249 | }, { | ||
250 | .name = "dma", | ||
251 | .parent = &clk_h, | ||
252 | .enable = s3c2443_clkcon_enable_h, | ||
253 | .ctrlbit = S3C2443_HCLKCON_DMA5, | ||
254 | }, { | ||
255 | .name = "hsmmc", | ||
256 | .parent = &clk_h, | ||
257 | .enable = s3c2443_clkcon_enable_h, | ||
258 | .ctrlbit = S3C2443_HCLKCON_HSMMC, | ||
259 | }, { | ||
260 | .name = "gpio", | ||
261 | .parent = &clk_p, | ||
262 | .enable = s3c2443_clkcon_enable_p, | ||
263 | .ctrlbit = S3C2443_PCLKCON_GPIO, | ||
264 | }, { | ||
265 | .name = "usb-host", | ||
266 | .parent = &clk_h, | ||
267 | .enable = s3c2443_clkcon_enable_h, | ||
268 | .ctrlbit = S3C2443_HCLKCON_USBH, | ||
269 | }, { | ||
270 | .name = "usb-device", | ||
271 | .parent = &clk_h, | ||
272 | .enable = s3c2443_clkcon_enable_h, | ||
273 | .ctrlbit = S3C2443_HCLKCON_USBD, | ||
274 | }, { | ||
275 | .name = "lcd", | ||
276 | .parent = &clk_h, | ||
277 | .enable = s3c2443_clkcon_enable_h, | ||
278 | .ctrlbit = S3C2443_HCLKCON_LCDC, | ||
279 | |||
280 | }, { | ||
281 | .name = "timers", | ||
282 | .parent = &clk_p, | ||
283 | .enable = s3c2443_clkcon_enable_p, | ||
284 | .ctrlbit = S3C2443_PCLKCON_PWMT, | ||
285 | }, { | ||
286 | .name = "cfc", | ||
287 | .parent = &clk_h, | ||
288 | .enable = s3c2443_clkcon_enable_h, | ||
289 | .ctrlbit = S3C2443_HCLKCON_CFC, | ||
290 | }, { | ||
291 | .name = "ssmc", | ||
292 | .parent = &clk_h, | ||
293 | .enable = s3c2443_clkcon_enable_h, | ||
294 | .ctrlbit = S3C2443_HCLKCON_SSMC, | ||
295 | }, { | ||
296 | .name = "uart", | ||
297 | .devname = "s3c2440-uart.0", | ||
298 | .parent = &clk_p, | ||
299 | .enable = s3c2443_clkcon_enable_p, | ||
300 | .ctrlbit = S3C2443_PCLKCON_UART0, | ||
301 | }, { | ||
302 | .name = "uart", | ||
303 | .devname = "s3c2440-uart.1", | ||
304 | .parent = &clk_p, | ||
305 | .enable = s3c2443_clkcon_enable_p, | ||
306 | .ctrlbit = S3C2443_PCLKCON_UART1, | ||
307 | }, { | ||
308 | .name = "uart", | ||
309 | .devname = "s3c2440-uart.2", | ||
310 | .parent = &clk_p, | ||
311 | .enable = s3c2443_clkcon_enable_p, | ||
312 | .ctrlbit = S3C2443_PCLKCON_UART2, | ||
313 | }, { | ||
314 | .name = "uart", | ||
315 | .devname = "s3c2440-uart.3", | ||
316 | .parent = &clk_p, | ||
317 | .enable = s3c2443_clkcon_enable_p, | ||
318 | .ctrlbit = S3C2443_PCLKCON_UART3, | ||
319 | }, { | ||
320 | .name = "rtc", | ||
321 | .parent = &clk_p, | ||
322 | .enable = s3c2443_clkcon_enable_p, | ||
323 | .ctrlbit = S3C2443_PCLKCON_RTC, | ||
324 | }, { | ||
325 | .name = "watchdog", | ||
326 | .parent = &clk_p, | ||
327 | .ctrlbit = S3C2443_PCLKCON_WDT, | ||
328 | }, { | ||
329 | .name = "ac97", | ||
330 | .parent = &clk_p, | ||
331 | .ctrlbit = S3C2443_PCLKCON_AC97, | ||
332 | }, { | ||
333 | .name = "nand", | ||
334 | .parent = &clk_h, | ||
335 | }, { | ||
336 | .name = "usb-bus-host", | ||
337 | .parent = &clk_usb_bus_host.clk, | ||
338 | } | ||
339 | }; | ||
340 | |||
341 | static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) | ||
342 | { | ||
343 | clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; | ||
344 | |||
345 | return clkcon0 + 1; | ||
346 | } | ||
347 | |||
348 | /* EPLLCON compatible enough to get on/off information */ | ||
349 | |||
350 | void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll, | ||
351 | fdiv_fn get_fdiv) | ||
352 | { | ||
353 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); | ||
354 | unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); | ||
355 | unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); | ||
356 | struct clk *xtal_clk; | ||
357 | unsigned long xtal; | ||
358 | unsigned long pll; | ||
359 | unsigned long fclk; | ||
360 | unsigned long hclk; | ||
361 | unsigned long pclk; | ||
362 | int ptr; | ||
363 | |||
364 | xtal_clk = clk_get(NULL, "xtal"); | ||
365 | xtal = clk_get_rate(xtal_clk); | ||
366 | clk_put(xtal_clk); | ||
367 | |||
368 | pll = get_mpll(mpllcon, xtal); | ||
369 | clk_msysclk.clk.rate = pll; | ||
370 | |||
371 | fclk = pll / get_fdiv(clkdiv0); | ||
372 | hclk = s3c2443_prediv_getrate(&clk_prediv); | ||
373 | hclk /= s3c2443_get_hdiv(clkdiv0); | ||
374 | pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); | ||
375 | |||
376 | s3c24xx_setup_clocks(fclk, hclk, pclk); | ||
377 | |||
378 | printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", | ||
379 | (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", | ||
380 | print_mhz(pll), print_mhz(fclk), | ||
381 | print_mhz(hclk), print_mhz(pclk)); | ||
382 | |||
383 | for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++) | ||
384 | s3c_set_clksrc(&clksrc_clks[ptr], true); | ||
385 | |||
386 | /* ensure usb bus clock is within correct rate of 48MHz */ | ||
387 | |||
388 | if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) { | ||
389 | printk(KERN_INFO "Warning: USB host bus not at 48MHz\n"); | ||
390 | clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000); | ||
391 | } | ||
392 | |||
393 | printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", | ||
394 | (epllcon & S3C2443_PLLCON_OFF) ? "off":"on", | ||
395 | print_mhz(clk_get_rate(&clk_epll)), | ||
396 | print_mhz(clk_get_rate(&clk_usb_bus))); | ||
397 | } | ||
398 | |||
399 | static struct clk *clks[] __initdata = { | ||
400 | &clk_prediv, | ||
401 | &clk_mpllref, | ||
402 | &clk_mdivclk, | ||
403 | &clk_ext, | ||
404 | &clk_epll, | ||
405 | &clk_usb_bus, | ||
406 | }; | ||
407 | |||
408 | static struct clksrc_clk *clksrcs[] __initdata = { | ||
409 | &clk_usb_bus_host, | ||
410 | &clk_epllref, | ||
411 | &clk_esysclk, | ||
412 | &clk_msysclk, | ||
413 | }; | ||
414 | |||
415 | void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, | ||
416 | fdiv_fn get_fdiv) | ||
417 | { | ||
418 | int ptr; | ||
419 | |||
420 | /* s3c2443 parents h and p clocks from prediv */ | ||
421 | clk_h.parent = &clk_prediv; | ||
422 | clk_p.parent = &clk_prediv; | ||
423 | |||
424 | clk_usb_bus.parent = &clk_usb_bus_host.clk; | ||
425 | clk_epll.parent = &clk_epllref.clk; | ||
426 | |||
427 | s3c24xx_register_baseclocks(xtal); | ||
428 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | ||
429 | |||
430 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | ||
431 | s3c_register_clksrc(clksrcs[ptr], 1); | ||
432 | |||
433 | s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks)); | ||
434 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | ||
435 | |||
436 | /* See s3c2443/etc notes on disabling clocks at init time */ | ||
437 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | ||
438 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | ||
439 | |||
440 | s3c2443_common_setup_clocks(get_mpll, get_fdiv); | ||
441 | } | ||
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c new file mode 100644 index 00000000000..9e90a7cbd1d --- /dev/null +++ b/arch/arm/plat-s3c24xx/setup-i2c.c | |||
@@ -0,0 +1,27 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/setup-i2c.c | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C24XX Base setup for i2c device | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/gpio.h> | ||
15 | |||
16 | struct platform_device; | ||
17 | |||
18 | #include <plat/gpio-cfg.h> | ||
19 | #include <plat/iic.h> | ||
20 | #include <mach/hardware.h> | ||
21 | #include <mach/regs-gpio.h> | ||
22 | |||
23 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) | ||
24 | { | ||
25 | s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA); | ||
26 | s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL); | ||
27 | } | ||
diff --git a/arch/arm/plat-s3c24xx/setup-ts.c b/arch/arm/plat-s3c24xx/setup-ts.c new file mode 100644 index 00000000000..ed263866367 --- /dev/null +++ b/arch/arm/plat-s3c24xx/setup-ts.c | |||
@@ -0,0 +1,34 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/setup-ts.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * Based on S3C24XX setup for i2c device | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/gpio.h> | ||
15 | |||
16 | struct platform_device; /* don't need the contents */ | ||
17 | |||
18 | #include <mach/hardware.h> | ||
19 | #include <mach/regs-gpio.h> | ||
20 | |||
21 | /** | ||
22 | * s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems | ||
23 | * | ||
24 | * Configure the GPIO for the S3C2410 system, where we have external FETs | ||
25 | * connected to the device (later systems such as the S3C2440 integrate | ||
26 | * these into the device). | ||
27 | */ | ||
28 | void s3c24xx_ts_cfg_gpio(struct platform_device *dev) | ||
29 | { | ||
30 | s3c2410_gpio_cfgpin(S3C2410_GPG(12), S3C2410_GPG12_XMON); | ||
31 | s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPG13_nXPON); | ||
32 | s3c2410_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPG14_YMON); | ||
33 | s3c2410_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPG15_nYPON); | ||
34 | } | ||
diff --git a/arch/arm/plat-s3c24xx/simtec-audio.c b/arch/arm/plat-s3c24xx/simtec-audio.c new file mode 100644 index 00000000000..6bc832e0d8e --- /dev/null +++ b/arch/arm/plat-s3c24xx/simtec-audio.c | |||
@@ -0,0 +1,77 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/simtec-audio.c | ||
2 | * | ||
3 | * Copyright (c) 2009 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * Audio setup for various Simtec S3C24XX implementations | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/interrupt.h> | ||
16 | #include <linux/init.h> | ||
17 | #include <linux/device.h> | ||
18 | #include <linux/io.h> | ||
19 | |||
20 | #include <mach/bast-map.h> | ||
21 | #include <mach/bast-irq.h> | ||
22 | #include <mach/bast-cpld.h> | ||
23 | |||
24 | #include <mach/hardware.h> | ||
25 | #include <mach/regs-gpio.h> | ||
26 | |||
27 | #include <plat/audio-simtec.h> | ||
28 | #include <plat/devs.h> | ||
29 | |||
30 | /* platform ops for audio */ | ||
31 | |||
32 | static void simtec_audio_startup_lrroute(void) | ||
33 | { | ||
34 | unsigned int tmp; | ||
35 | unsigned long flags; | ||
36 | |||
37 | local_irq_save(flags); | ||
38 | |||
39 | tmp = __raw_readb(BAST_VA_CTRL1); | ||
40 | tmp &= ~BAST_CPLD_CTRL1_LRMASK; | ||
41 | tmp |= BAST_CPLD_CTRL1_LRCDAC; | ||
42 | __raw_writeb(tmp, BAST_VA_CTRL1); | ||
43 | |||
44 | local_irq_restore(flags); | ||
45 | } | ||
46 | |||
47 | static struct s3c24xx_audio_simtec_pdata simtec_audio_platdata; | ||
48 | static char our_name[32]; | ||
49 | |||
50 | static struct platform_device simtec_audio_dev = { | ||
51 | .name = our_name, | ||
52 | .id = -1, | ||
53 | .dev = { | ||
54 | .parent = &s3c_device_iis.dev, | ||
55 | .platform_data = &simtec_audio_platdata, | ||
56 | }, | ||
57 | }; | ||
58 | |||
59 | int __init simtec_audio_add(const char *name, bool has_lr_routing, | ||
60 | struct s3c24xx_audio_simtec_pdata *spd) | ||
61 | { | ||
62 | if (!name) | ||
63 | name = "tlv320aic23"; | ||
64 | |||
65 | snprintf(our_name, sizeof(our_name)-1, "s3c24xx-simtec-%s", name); | ||
66 | |||
67 | /* copy platform data so the source can be __initdata */ | ||
68 | if (spd) | ||
69 | simtec_audio_platdata = *spd; | ||
70 | |||
71 | if (has_lr_routing) | ||
72 | simtec_audio_platdata.startup = simtec_audio_startup_lrroute; | ||
73 | |||
74 | platform_device_register(&s3c_device_iis); | ||
75 | platform_device_register(&simtec_audio_dev); | ||
76 | return 0; | ||
77 | } | ||
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S new file mode 100644 index 00000000000..c56612569b4 --- /dev/null +++ b/arch/arm/plat-s3c24xx/sleep.S | |||
@@ -0,0 +1,84 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/sleep.S | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 Power Manager (Suspend-To-RAM) support | ||
7 | * | ||
8 | * Based on PXA/SA1100 sleep code by: | ||
9 | * Nicolas Pitre, (c) 2002 Monta Vista Software Inc | ||
10 | * Cliff Brake, (c) 2001 | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or modify | ||
13 | * it under the terms of the GNU General Public License as published by | ||
14 | * the Free Software Foundation; either version 2 of the License, or | ||
15 | * (at your option) any later version. | ||
16 | * | ||
17 | * This program is distributed in the hope that it will be useful, | ||
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
20 | * GNU General Public License for more details. | ||
21 | * | ||
22 | * You should have received a copy of the GNU General Public License | ||
23 | * along with this program; if not, write to the Free Software | ||
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
25 | */ | ||
26 | |||
27 | #include <linux/linkage.h> | ||
28 | #include <asm/assembler.h> | ||
29 | #include <mach/hardware.h> | ||
30 | #include <mach/map.h> | ||
31 | |||
32 | #include <mach/regs-gpio.h> | ||
33 | #include <mach/regs-clock.h> | ||
34 | #include <mach/regs-mem.h> | ||
35 | #include <plat/regs-serial.h> | ||
36 | |||
37 | /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not | ||
38 | * reset the UART configuration, only enable if you really need this! | ||
39 | */ | ||
40 | //#define CONFIG_DEBUG_RESUME | ||
41 | |||
42 | .text | ||
43 | |||
44 | /* sleep magic, to allow the bootloader to check for an valid | ||
45 | * image to resume to. Must be the first word before the | ||
46 | * s3c_cpu_resume entry. | ||
47 | */ | ||
48 | |||
49 | .word 0x2bedf00d | ||
50 | |||
51 | /* s3c_cpu_resume | ||
52 | * | ||
53 | * resume code entry for bootloader to call | ||
54 | */ | ||
55 | |||
56 | ENTRY(s3c_cpu_resume) | ||
57 | mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE | ||
58 | msr cpsr_c, r0 | ||
59 | |||
60 | @@ load UART to allow us to print the two characters for | ||
61 | @@ resume debug | ||
62 | |||
63 | mov r2, #S3C24XX_PA_UART & 0xff000000 | ||
64 | orr r2, r2, #S3C24XX_PA_UART & 0xff000 | ||
65 | |||
66 | #if 0 | ||
67 | /* SMDK2440 LED set */ | ||
68 | mov r14, #S3C24XX_PA_GPIO | ||
69 | ldr r12, [ r14, #0x54 ] | ||
70 | bic r12, r12, #3<<4 | ||
71 | orr r12, r12, #1<<7 | ||
72 | str r12, [ r14, #0x54 ] | ||
73 | #endif | ||
74 | |||
75 | #ifdef CONFIG_DEBUG_RESUME | ||
76 | mov r3, #'L' | ||
77 | strb r3, [ r2, #S3C2410_UTXH ] | ||
78 | 1001: | ||
79 | ldrb r14, [ r3, #S3C2410_UTRSTAT ] | ||
80 | tst r14, #S3C2410_UTRSTAT_TXE | ||
81 | beq 1001b | ||
82 | #endif /* CONFIG_DEBUG_RESUME */ | ||
83 | |||
84 | b cpu_resume | ||
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c new file mode 100644 index 00000000000..704175b0573 --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c | |||
@@ -0,0 +1,36 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13 | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/gpio.h> | ||
16 | |||
17 | #include <mach/spi.h> | ||
18 | #include <mach/regs-gpio.h> | ||
19 | |||
20 | void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, | ||
21 | int enable) | ||
22 | { | ||
23 | if (enable) { | ||
24 | s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0); | ||
25 | s3c_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0); | ||
26 | s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0); | ||
27 | s3c2410_gpio_pullup(S3C2410_GPE(11), 0); | ||
28 | s3c2410_gpio_pullup(S3C2410_GPE(13), 0); | ||
29 | } else { | ||
30 | s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT); | ||
31 | s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT); | ||
32 | s3c_gpio_setpull(S3C2410_GPE(11), S3C_GPIO_PULL_NONE); | ||
33 | s3c_gpio_setpull(S3C2410_GPE(12), S3C_GPIO_PULL_NONE); | ||
34 | s3c_gpio_setpull(S3C2410_GPE(13), S3C_GPIO_PULL_NONE); | ||
35 | } | ||
36 | } | ||
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c new file mode 100644 index 00000000000..72457afd625 --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c | |||
@@ -0,0 +1,38 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/spi-bus0-gpd8_9_10.c | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX SPI - gpio configuration for bus 1 on gpd8,9,10 | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/gpio.h> | ||
16 | |||
17 | #include <mach/spi.h> | ||
18 | #include <mach/regs-gpio.h> | ||
19 | |||
20 | void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi, | ||
21 | int enable) | ||
22 | { | ||
23 | |||
24 | printk(KERN_INFO "%s(%d)\n", __func__, enable); | ||
25 | if (enable) { | ||
26 | s3c_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1); | ||
27 | s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1); | ||
28 | s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1); | ||
29 | s3c2410_gpio_pullup(S3C2410_GPD(10), 0); | ||
30 | s3c2410_gpio_pullup(S3C2410_GPD(9), 0); | ||
31 | } else { | ||
32 | s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT); | ||
33 | s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT); | ||
34 | s3c_gpio_setpull(S3C2410_GPD(10), S3C_GPIO_PULL_NONE); | ||
35 | s3c_gpio_setpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE); | ||
36 | s3c_gpio_setpull(S3C2410_GPD(8), S3C_GPIO_PULL_NONE); | ||
37 | } | ||
38 | } | ||
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c new file mode 100644 index 00000000000..c3972b645d1 --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c | |||
@@ -0,0 +1,36 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7 | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/gpio.h> | ||
16 | |||
17 | #include <mach/spi.h> | ||
18 | #include <mach/regs-gpio.h> | ||
19 | |||
20 | void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, | ||
21 | int enable) | ||
22 | { | ||
23 | if (enable) { | ||
24 | s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1); | ||
25 | s3c_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1); | ||
26 | s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1); | ||
27 | s3c2410_gpio_pullup(S3C2410_GPG(5), 0); | ||
28 | s3c2410_gpio_pullup(S3C2410_GPG(6), 0); | ||
29 | } else { | ||
30 | s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT); | ||
31 | s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT); | ||
32 | s3c_gpio_setpull(S3C2410_GPG(5), S3C_GPIO_PULL_NONE); | ||
33 | s3c_gpio_setpull(S3C2410_GPG(6), S3C_GPIO_PULL_NONE); | ||
34 | s3c_gpio_setpull(S3C2410_GPG(7), S3C_GPIO_PULL_NONE); | ||
35 | } | ||
36 | } | ||