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authorLinus Torvalds <torvalds@linux-foundation.org>2010-08-08 13:01:46 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-08 13:01:46 -0400
commitd71048e22f47725a5808ea2e4e1e72fa36c1a788 (patch)
tree65debebb2964cb4cbde4d29e15730527d686a540 /arch/arm/plat-omap
parent44d51a029f95d49c5c7ccd7808f81904c20c3abd (diff)
parentd21872b3683ff37f73c68993749a6e6aeeaed265 (diff)
Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (143 commits) omap: mailbox: reorganize headers omap: mailbox: standarize on 'omap-mailbox' omap: mailbox: only compile for configured archs omap: mailbox: simplify omap_mbox_register() omap: mailbox: reorganize registering omap: mailbox: add IRQ names omap: mailbox: remove unecessary fields omap: mailbox: don't export unecessary symbols omap: mailbox: update omap1 probing omap: mailbox: use correct config for omap1 omap: mailbox: 2420 should be detected at run-time omap: mailbox: reorganize structures omap: mailbox: trivial cleanups omap mailbox: Set a device in logical mbox instance for traceability omap: mailbox: convert block api to kfifo omap: mailbox: remove (un)likely macros from cold paths omap: mailbox cleanup: split MODULE_AUTHOR line omap: mailbox: convert rwlocks to spinlock Mailbox: disable mailbox interrupt when request queue Mailbox: new mutext lock for h/w mailbox configuration ...
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/Kconfig33
-rw-r--r--arch/arm/plat-omap/Makefile1
-rw-r--r--arch/arm/plat-omap/common.c10
-rw-r--r--arch/arm/plat-omap/debug-leds.c2
-rw-r--r--arch/arm/plat-omap/devices.c124
-rw-r--r--arch/arm/plat-omap/dma.c11
-rw-r--r--arch/arm/plat-omap/gpio.c4
-rw-r--r--arch/arm/plat-omap/i2c.c12
-rw-r--r--arch/arm/plat-omap/include/plat/board.h8
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h130
-rw-r--r--arch/arm/plat-omap/include/plat/common.h9
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h17
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h1
-rw-r--r--arch/arm/plat-omap/include/plat/dsp_common.h40
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h42
-rw-r--r--arch/arm/plat-omap/include/plat/iommu.h2
-rw-r--r--arch/arm/plat-omap/include/plat/mailbox.h20
-rw-r--r--arch/arm/plat-omap/include/plat/mux.h224
-rw-r--r--arch/arm/plat-omap/include/plat/nand.h6
-rw-r--r--arch/arm/plat-omap/include/plat/omap-pm.h130
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h2
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h14
-rw-r--r--arch/arm/plat-omap/include/plat/smp.h1
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h6
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h49
-rw-r--r--arch/arm/plat-omap/iommu.c27
-rw-r--r--arch/arm/plat-omap/iopgtable.h8
-rw-r--r--arch/arm/plat-omap/mailbox.c248
-rw-r--r--arch/arm/plat-omap/mux.c2
-rw-r--r--arch/arm/plat-omap/omap-pm-noop.c61
-rw-r--r--arch/arm/plat-omap/omap_device.c37
-rw-r--r--arch/arm/plat-omap/usb.c644
32 files changed, 634 insertions, 1291 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 78b49a626d0..e39a417a368 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -1,6 +1,6 @@
1if ARCH_OMAP 1if ARCH_OMAP
2 2
3menu "TI OMAP Implementations" 3menu "TI OMAP Common Features"
4 4
5config ARCH_OMAP_OTG 5config ARCH_OMAP_OTG
6 bool 6 bool
@@ -21,24 +21,6 @@ config ARCH_OMAP2PLUS
21 help 21 help
22 "Systems based on omap24xx, omap34xx or omap44xx" 22 "Systems based on omap24xx, omap34xx or omap44xx"
23 23
24config ARCH_OMAP2
25 bool "TI OMAP2"
26 depends on ARCH_OMAP2PLUS
27 select CPU_V6
28
29config ARCH_OMAP3
30 bool "TI OMAP3"
31 depends on ARCH_OMAP2PLUS
32 select CPU_V7
33 select USB_ARCH_HAS_EHCI
34 select ARM_L1_CACHE_SHIFT_6
35
36config ARCH_OMAP4
37 bool "TI OMAP4"
38 depends on ARCH_OMAP2PLUS
39 select CPU_V7
40 select ARM_GIC
41
42endchoice 24endchoice
43 25
44comment "OMAP Feature Selections" 26comment "OMAP Feature Selections"
@@ -51,7 +33,7 @@ config OMAP_DEBUG_DEVICES
51config OMAP_DEBUG_LEDS 33config OMAP_DEBUG_LEDS
52 bool 34 bool
53 depends on OMAP_DEBUG_DEVICES 35 depends on OMAP_DEBUG_DEVICES
54 default y if LEDS || LEDS_OMAP_DEBUG 36 default y if LEDS
55 37
56config OMAP_RESET_CLOCKS 38config OMAP_RESET_CLOCKS
57 bool "Reset unused clocks during boot" 39 bool "Reset unused clocks during boot"
@@ -106,6 +88,15 @@ config OMAP_MBOX_FWK
106 Say Y here if you want to use OMAP Mailbox framework support for 88 Say Y here if you want to use OMAP Mailbox framework support for
107 DSP, IVA1.0 and IVA2 in OMAP1/2/3. 89 DSP, IVA1.0 and IVA2 in OMAP1/2/3.
108 90
91config OMAP_MBOX_KFIFO_SIZE
92 int "Mailbox kfifo default buffer size (bytes)"
93 depends on OMAP_MBOX_FWK
94 default 256
95 help
96 Specify the default size of mailbox's kfifo buffers (bytes).
97 This can also be changed at runtime (via the mbox_kfifo_size
98 module parameter).
99
109config OMAP_IOMMU 100config OMAP_IOMMU
110 tristate 101 tristate
111 102
@@ -120,7 +111,7 @@ config OMAP_IOMMU_DEBUG
120 111
121choice 112choice
122 prompt "System timer" 113 prompt "System timer"
123 default OMAP_MPU_TIMER 114 default OMAP_32K_TIMER if !ARCH_OMAP15XX
124 115
125config OMAP_MPU_TIMER 116config OMAP_MPU_TIMER
126 bool "Use mpu timer" 117 bool "Use mpu timer"
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 98f01910c2c..9405831b746 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
15# omap_device support (OMAP2+ only at the moment) 15# omap_device support (OMAP2+ only at the moment)
16obj-$(CONFIG_ARCH_OMAP2) += omap_device.o 16obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
17obj-$(CONFIG_ARCH_OMAP3) += omap_device.o 17obj-$(CONFIG_ARCH_OMAP3) += omap_device.o
18obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
18 19
19obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o 20obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
20obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o 21obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index ebed82699eb..3008e710448 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -317,18 +317,18 @@ static struct omap_globals omap3_globals = {
317 .uart1_phys = OMAP3_UART1_BASE, 317 .uart1_phys = OMAP3_UART1_BASE,
318 .uart2_phys = OMAP3_UART2_BASE, 318 .uart2_phys = OMAP3_UART2_BASE,
319 .uart3_phys = OMAP3_UART3_BASE, 319 .uart3_phys = OMAP3_UART3_BASE,
320 .uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */
320}; 321};
321 322
322void __init omap2_set_globals_343x(void) 323void __init omap2_set_globals_3xxx(void)
323{ 324{
324 __omap2_set_globals(&omap3_globals); 325 __omap2_set_globals(&omap3_globals);
325} 326}
326 327
327void __init omap2_set_globals_36xx(void) 328void __init omap3_map_io(void)
328{ 329{
329 omap3_globals.uart4_phys = OMAP3_UART4_BASE; 330 omap2_set_globals_3xxx();
330 331 omap34xx_map_common_io();
331 __omap2_set_globals(&omap3_globals);
332} 332}
333#endif 333#endif
334 334
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 53fcef7c520..fc05b102260 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -39,7 +39,7 @@ static struct h2p2_dbg_fpga __iomem *fpga;
39static u16 led_state, hw_led_state; 39static u16 led_state, hw_led_state;
40 40
41 41
42#ifdef CONFIG_LEDS_OMAP_DEBUG 42#ifdef CONFIG_OMAP_DEBUG_LEDS
43#define new_led_api() 1 43#define new_led_api() 1
44#else 44#else
45#define new_led_api() 0 45#define new_led_api() 0
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 95677d17cd1..d1920be7833 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -24,135 +24,13 @@
24#include <plat/control.h> 24#include <plat/control.h>
25#include <plat/board.h> 25#include <plat/board.h>
26#include <plat/mmc.h> 26#include <plat/mmc.h>
27#include <plat/mux.h>
28#include <mach/gpio.h> 27#include <mach/gpio.h>
29#include <plat/menelaus.h> 28#include <plat/menelaus.h>
30#include <plat/mcbsp.h> 29#include <plat/mcbsp.h>
31#include <plat/dsp_common.h>
32#include <plat/omap44xx.h> 30#include <plat/omap44xx.h>
33 31
34#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
35
36static struct dsp_platform_data dsp_pdata = {
37 .kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
38};
39
40static struct resource omap_dsp_resources[] = {
41 {
42 .name = "dsp_mmu",
43 .start = -1,
44 .flags = IORESOURCE_IRQ,
45 },
46};
47
48static struct platform_device omap_dsp_device = {
49 .name = "dsp",
50 .id = -1,
51 .num_resources = ARRAY_SIZE(omap_dsp_resources),
52 .resource = omap_dsp_resources,
53 .dev = {
54 .platform_data = &dsp_pdata,
55 },
56};
57
58static inline void omap_init_dsp(void)
59{
60 struct resource *res;
61 int irq;
62
63 if (cpu_is_omap15xx())
64 irq = INT_1510_DSP_MMU;
65 else if (cpu_is_omap16xx())
66 irq = INT_1610_DSP_MMU;
67 else if (cpu_is_omap24xx())
68 irq = INT_24XX_DSP_MMU;
69
70 res = platform_get_resource_byname(&omap_dsp_device,
71 IORESOURCE_IRQ, "dsp_mmu");
72 res->start = irq;
73
74 platform_device_register(&omap_dsp_device);
75}
76
77int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev)
78{
79 static DEFINE_MUTEX(dsp_pdata_lock);
80
81 spin_lock_init(&kdev->lock);
82
83 mutex_lock(&dsp_pdata_lock);
84 list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
85 mutex_unlock(&dsp_pdata_lock);
86
87 return 0;
88}
89EXPORT_SYMBOL(dsp_kfunc_device_register);
90
91#else
92static inline void omap_init_dsp(void) { }
93#endif /* CONFIG_OMAP_DSP */
94
95/*-------------------------------------------------------------------------*/ 32/*-------------------------------------------------------------------------*/
96#if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
97
98static void omap_init_kp(void)
99{
100 /* 2430 and 34xx keypad is on TWL4030 */
101 if (cpu_is_omap2430() || cpu_is_omap34xx())
102 return;
103 33
104 if (machine_is_omap_h2() || machine_is_omap_h3()) {
105 omap_cfg_reg(F18_1610_KBC0);
106 omap_cfg_reg(D20_1610_KBC1);
107 omap_cfg_reg(D19_1610_KBC2);
108 omap_cfg_reg(E18_1610_KBC3);
109 omap_cfg_reg(C21_1610_KBC4);
110
111 omap_cfg_reg(G18_1610_KBR0);
112 omap_cfg_reg(F19_1610_KBR1);
113 omap_cfg_reg(H14_1610_KBR2);
114 omap_cfg_reg(E20_1610_KBR3);
115 omap_cfg_reg(E19_1610_KBR4);
116 omap_cfg_reg(N19_1610_KBR5);
117 } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
118 omap_cfg_reg(E2_7XX_KBR0);
119 omap_cfg_reg(J7_7XX_KBR1);
120 omap_cfg_reg(E1_7XX_KBR2);
121 omap_cfg_reg(F3_7XX_KBR3);
122 omap_cfg_reg(D2_7XX_KBR4);
123
124 omap_cfg_reg(C2_7XX_KBC0);
125 omap_cfg_reg(D3_7XX_KBC1);
126 omap_cfg_reg(E4_7XX_KBC2);
127 omap_cfg_reg(F4_7XX_KBC3);
128 omap_cfg_reg(E3_7XX_KBC4);
129 } else if (machine_is_omap_h4()) {
130 omap_cfg_reg(T19_24XX_KBR0);
131 omap_cfg_reg(R19_24XX_KBR1);
132 omap_cfg_reg(V18_24XX_KBR2);
133 omap_cfg_reg(M21_24XX_KBR3);
134 omap_cfg_reg(E5__24XX_KBR4);
135 if (omap_has_menelaus()) {
136 omap_cfg_reg(B3__24XX_KBR5);
137 omap_cfg_reg(AA4_24XX_KBC2);
138 omap_cfg_reg(B13_24XX_KBC6);
139 } else {
140 omap_cfg_reg(M18_24XX_KBR5);
141 omap_cfg_reg(H19_24XX_KBC2);
142 omap_cfg_reg(N19_24XX_KBC6);
143 }
144 omap_cfg_reg(R20_24XX_KBC0);
145 omap_cfg_reg(M14_24XX_KBC1);
146 omap_cfg_reg(V17_24XX_KBC3);
147 omap_cfg_reg(P21_24XX_KBC4);
148 omap_cfg_reg(L14_24XX_KBC5);
149 }
150}
151#else
152static inline void omap_init_kp(void) {}
153#endif
154
155/*-------------------------------------------------------------------------*/
156#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE) 34#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
157 35
158static struct platform_device **omap_mcbsp_devices; 36static struct platform_device **omap_mcbsp_devices;
@@ -419,8 +297,6 @@ static int __init omap_init_devices(void)
419 /* please keep these calls, and their implementations above, 297 /* please keep these calls, and their implementations above,
420 * in alphabetical order so they're easier to sort through. 298 * in alphabetical order so they're easier to sort through.
421 */ 299 */
422 omap_init_dsp();
423 omap_init_kp();
424 omap_init_rng(); 300 omap_init_rng();
425 omap_init_mcpdm(); 301 omap_init_mcpdm();
426 omap_init_uwire(); 302 omap_init_uwire();
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index f7f571e7987..ec7eddf9e52 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -290,7 +290,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
290 val = dma_read(CCR(lch)); 290 val = dma_read(CCR(lch));
291 291
292 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ 292 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
293 val &= ~((3 << 19) | 0x1f); 293 val &= ~((1 << 23) | (3 << 19) | 0x1f);
294 val |= (dma_trigger & ~0x1f) << 14; 294 val |= (dma_trigger & ~0x1f) << 14;
295 val |= dma_trigger & 0x1f; 295 val |= dma_trigger & 0x1f;
296 296
@@ -304,11 +304,14 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
304 else 304 else
305 val &= ~(1 << 18); 305 val &= ~(1 << 18);
306 306
307 if (src_or_dst_synch) 307 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
308 val &= ~(1 << 24); /* dest synch */
309 val |= (1 << 23); /* Prefetch */
310 } else if (src_or_dst_synch) {
308 val |= 1 << 24; /* source synch */ 311 val |= 1 << 24; /* source synch */
309 else 312 } else {
310 val &= ~(1 << 24); /* dest synch */ 313 val &= ~(1 << 24); /* dest synch */
311 314 }
312 dma_write(val, CCR(lch)); 315 dma_write(val, CCR(lch));
313 } 316 }
314 317
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 9b7e3545f32..7951eefe1a0 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -390,7 +390,9 @@ static inline int gpio_valid(int gpio)
390 return 0; 390 return 0;
391 if (cpu_is_omap7xx() && gpio < 192) 391 if (cpu_is_omap7xx() && gpio < 192)
392 return 0; 392 return 0;
393 if (cpu_is_omap24xx() && gpio < 128) 393 if (cpu_is_omap2420() && gpio < 128)
394 return 0;
395 if (cpu_is_omap2430() && gpio < 160)
394 return 0; 396 return 0;
395 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) 397 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
396 return 0; 398 return 0;
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index eec2b4993c6..a5ce4f0aad3 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -138,6 +138,16 @@ static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
138 return platform_device_register(pdev); 138 return platform_device_register(pdev);
139} 139}
140 140
141/*
142 * XXX This function is a temporary compatibility wrapper - only
143 * needed until the I2C driver can be converted to call
144 * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
145 */
146static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
147{
148 omap_pm_set_max_mpu_wakeup_lat(dev, t);
149}
150
141static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id) 151static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
142{ 152{
143 struct resource *res; 153 struct resource *res;
@@ -168,7 +178,7 @@ static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
168 struct omap_i2c_bus_platform_data *pd; 178 struct omap_i2c_bus_platform_data *pd;
169 179
170 pd = pdev->dev.platform_data; 180 pd = pdev->dev.platform_data;
171 pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat; 181 pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
172 } 182 }
173 183
174 return platform_device_register(pdev); 184 return platform_device_register(pdev);
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 5cd622039da..3cf4fa25ab3 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -85,6 +85,14 @@ struct omap_usb_config {
85 * 6 == 6 wire unidirectional (or TLL) 85 * 6 == 6 wire unidirectional (or TLL)
86 */ 86 */
87 u8 pins[3]; 87 u8 pins[3];
88
89 struct platform_device *udc_device;
90 struct platform_device *ohci_device;
91 struct platform_device *otg_device;
92
93 u32 (*usb0_init)(unsigned nwires, unsigned is_device);
94 u32 (*usb1_init)(unsigned nwires);
95 u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
88}; 96};
89 97
90struct omap_lcd_config { 98struct omap_lcd_config {
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index dfc472ca0cc..fef4696dcf6 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -19,6 +19,22 @@ struct module;
19struct clk; 19struct clk;
20struct clockdomain; 20struct clockdomain;
21 21
22/**
23 * struct clkops - some clock function pointers
24 * @enable: fn ptr that enables the current clock in hardware
25 * @disable: fn ptr that enables the current clock in hardware
26 * @find_idlest: function returning the IDLEST register for the clock's IP blk
27 * @find_companion: function returning the "companion" clk reg for the clock
28 *
29 * A "companion" clk is an accompanying clock to the one being queried
30 * that must be enabled for the IP module connected to the clock to
31 * become accessible by the hardware. Neither @find_idlest nor
32 * @find_companion should be needed; that information is IP
33 * block-specific; the hwmod code has been created to handle this, but
34 * until hwmod data is ready and drivers have been converted to use PM
35 * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
36 * @find_companion must, unfortunately, remain.
37 */
22struct clkops { 38struct clkops {
23 int (*enable)(struct clk *); 39 int (*enable)(struct clk *);
24 void (*disable)(struct clk *); 40 void (*disable)(struct clk *);
@@ -30,12 +46,45 @@ struct clkops {
30 46
31#ifdef CONFIG_ARCH_OMAP2PLUS 47#ifdef CONFIG_ARCH_OMAP2PLUS
32 48
49/* struct clksel_rate.flags possibilities */
50#define RATE_IN_242X (1 << 0)
51#define RATE_IN_243X (1 << 1)
52#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */
53#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */
54#define RATE_IN_36XX (1 << 4)
55#define RATE_IN_4430 (1 << 5)
56
57#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
58#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX)
59
60/**
61 * struct clksel_rate - register bitfield values corresponding to clk divisors
62 * @val: register bitfield value (shifted to bit 0)
63 * @div: clock divisor corresponding to @val
64 * @flags: (see "struct clksel_rate.flags possibilities" above)
65 *
66 * @val should match the value of a read from struct clk.clksel_reg
67 * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
68 *
69 * @div is the divisor that should be applied to the parent clock's rate
70 * to produce the current clock's rate.
71 *
72 * XXX @flags probably should be replaced with an struct omap_chip.
73 */
33struct clksel_rate { 74struct clksel_rate {
34 u32 val; 75 u32 val;
35 u8 div; 76 u8 div;
36 u8 flags; 77 u8 flags;
37}; 78};
38 79
80/**
81 * struct clksel - available parent clocks, and a pointer to their divisors
82 * @parent: struct clk * to a possible parent clock
83 * @rates: available divisors for this parent clock
84 *
85 * A struct clksel is always associated with one or more struct clks
86 * and one or more struct clksel_rates.
87 */
39struct clksel { 88struct clksel {
40 struct clk *parent; 89 struct clk *parent;
41 const struct clksel_rate *rates; 90 const struct clksel_rate *rates;
@@ -116,6 +165,60 @@ struct dpll_data {
116 165
117#endif 166#endif
118 167
168/* struct clk.flags possibilities */
169#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
170#define CLOCK_IDLE_CONTROL (1 << 1)
171#define CLOCK_NO_IDLE_PARENT (1 << 2)
172#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
173#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
174
175/**
176 * struct clk - OMAP struct clk
177 * @node: list_head connecting this clock into the full clock list
178 * @ops: struct clkops * for this clock
179 * @name: the name of the clock in the hardware (used in hwmod data and debug)
180 * @parent: pointer to this clock's parent struct clk
181 * @children: list_head connecting to the child clks' @sibling list_heads
182 * @sibling: list_head connecting this clk to its parent clk's @children
183 * @rate: current clock rate
184 * @enable_reg: register to write to enable the clock (see @enable_bit)
185 * @recalc: fn ptr that returns the clock's current rate
186 * @set_rate: fn ptr that can change the clock's current rate
187 * @round_rate: fn ptr that can round the clock's current rate
188 * @init: fn ptr to do clock-specific initialization
189 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
190 * @usecount: number of users that have requested this clock to be enabled
191 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
192 * @flags: see "struct clk.flags possibilities" above
193 * @clksel_reg: for clksel clks, register va containing src/divisor select
194 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
195 * @clksel: for clksel clks, pointer to struct clksel for this clock
196 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
197 * @clkdm_name: clockdomain name that this clock is contained in
198 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
199 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
200 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
201 *
202 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
203 * clock code converted to use clksel.
204 *
205 * XXX @usecount is poorly named. It should be "enable_count" or
206 * something similar. "users" in the description refers to kernel
207 * code (core code or drivers) that have called clk_enable() and not
208 * yet called clk_disable(); the usecount of parent clocks is also
209 * incremented by the clock code when clk_enable() is called on child
210 * clocks and decremented by the clock code when clk_disable() is
211 * called on child clocks.
212 *
213 * XXX @clkdm, @usecount, @children, @sibling should be marked for
214 * internal use only.
215 *
216 * @children and @sibling are used to optimize parent-to-child clock
217 * tree traversals. (child-to-parent traversals use @parent.)
218 *
219 * XXX The notion of the clock's current rate probably needs to be
220 * separated from the clock's target rate.
221 */
119struct clk { 222struct clk {
120 struct list_head node; 223 struct list_head node;
121 const struct clkops *ops; 224 const struct clkops *ops;
@@ -129,8 +232,8 @@ struct clk {
129 int (*set_rate)(struct clk *, unsigned long); 232 int (*set_rate)(struct clk *, unsigned long);
130 long (*round_rate)(struct clk *, unsigned long); 233 long (*round_rate)(struct clk *, unsigned long);
131 void (*init)(struct clk *); 234 void (*init)(struct clk *);
132 __u8 enable_bit; 235 u8 enable_bit;
133 __s8 usecount; 236 s8 usecount;
134 u8 fixed_div; 237 u8 fixed_div;
135 u8 flags; 238 u8 flags;
136#ifdef CONFIG_ARCH_OMAP2PLUS 239#ifdef CONFIG_ARCH_OMAP2PLUS
@@ -141,8 +244,8 @@ struct clk {
141 const char *clkdm_name; 244 const char *clkdm_name;
142 struct clockdomain *clkdm; 245 struct clockdomain *clkdm;
143#else 246#else
144 __u8 rate_offset; 247 u8 rate_offset;
145 __u8 src_offset; 248 u8 src_offset;
146#endif 249#endif
147#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) 250#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
148 struct dentry *dent; /* For visible tree hierarchy */ 251 struct dentry *dent; /* For visible tree hierarchy */
@@ -188,23 +291,4 @@ extern const struct clkops clkops_null;
188 291
189extern struct clk dummy_ck; 292extern struct clk dummy_ck;
190 293
191/* Clock flags */
192#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
193#define CLOCK_IDLE_CONTROL (1 << 1)
194#define CLOCK_NO_IDLE_PARENT (1 << 2)
195#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
196#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
197
198/* Clksel_rate flags */
199#define RATE_IN_242X (1 << 0)
200#define RATE_IN_243X (1 << 1)
201#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */
202#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */
203#define RATE_IN_36XX (1 << 4)
204#define RATE_IN_4430 (1 << 5)
205
206#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
207
208#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX)
209
210#endif 294#endif
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 5e4afbee0fd..9776b41ad76 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -58,8 +58,7 @@ struct omap_globals {
58 58
59void omap2_set_globals_242x(void); 59void omap2_set_globals_242x(void);
60void omap2_set_globals_243x(void); 60void omap2_set_globals_243x(void);
61void omap2_set_globals_343x(void); 61void omap2_set_globals_3xxx(void);
62void omap2_set_globals_36xx(void);
63void omap2_set_globals_443x(void); 62void omap2_set_globals_443x(void);
64 63
65/* These get called from omap2_set_globals_xxxx(), do not call these */ 64/* These get called from omap2_set_globals_xxxx(), do not call these */
@@ -69,6 +68,8 @@ void omap2_set_globals_control(struct omap_globals *);
69void omap2_set_globals_prcm(struct omap_globals *); 68void omap2_set_globals_prcm(struct omap_globals *);
70void omap2_set_globals_uart(struct omap_globals *); 69void omap2_set_globals_uart(struct omap_globals *);
71 70
71void omap3_map_io(void);
72
72/** 73/**
73 * omap_test_timeout - busy-loop, testing a condition 74 * omap_test_timeout - busy-loop, testing a condition
74 * @cond: condition to test until it evaluates to true 75 * @cond: condition to test until it evaluates to true
@@ -89,4 +90,8 @@ void omap2_set_globals_uart(struct omap_globals *);
89 } \ 90 } \
90}) 91})
91 92
93extern struct device *omap2_get_mpuss_device(void);
94extern struct device *omap2_get_dsp_device(void);
95extern struct device *omap2_get_l3_device(void);
96
92#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ 97#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 75141742300..2e2ae530fce 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -66,6 +66,8 @@ unsigned int omap_rev(void);
66 * family. This difference can be handled separately. 66 * family. This difference can be handled separately.
67 */ 67 */
68#define OMAP_REVBITS_00 0x00 68#define OMAP_REVBITS_00 0x00
69#define OMAP_REVBITS_01 0x01
70#define OMAP_REVBITS_02 0x02
69#define OMAP_REVBITS_10 0x10 71#define OMAP_REVBITS_10 0x10
70#define OMAP_REVBITS_20 0x20 72#define OMAP_REVBITS_20 0x20
71#define OMAP_REVBITS_30 0x30 73#define OMAP_REVBITS_30 0x30
@@ -376,6 +378,8 @@ IS_OMAP_TYPE(3517, 0x3517)
376#define OMAP3430_REV_ES3_1_2 0x34305034 378#define OMAP3430_REV_ES3_1_2 0x34305034
377 379
378#define OMAP3630_REV_ES1_0 0x36300034 380#define OMAP3630_REV_ES1_0 0x36300034
381#define OMAP3630_REV_ES1_1 0x36300134
382#define OMAP3630_REV_ES1_2 0x36300234
379 383
380#define OMAP35XX_CLASS 0x35000034 384#define OMAP35XX_CLASS 0x35000034
381#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) 385#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
@@ -411,6 +415,8 @@ IS_OMAP_TYPE(3517, 0x3517)
411#define CHIP_IS_OMAP3430ES3_1 (1 << 6) 415#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
412#define CHIP_IS_OMAP3630ES1 (1 << 7) 416#define CHIP_IS_OMAP3630ES1 (1 << 7)
413#define CHIP_IS_OMAP4430ES1 (1 << 8) 417#define CHIP_IS_OMAP4430ES1 (1 << 8)
418#define CHIP_IS_OMAP3630ES1_1 (1 << 9)
419#define CHIP_IS_OMAP3630ES1_2 (1 << 10)
414 420
415#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) 421#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
416 422
@@ -424,11 +430,12 @@ IS_OMAP_TYPE(3517, 0x3517)
424 */ 430 */
425#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ 431#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
426 CHIP_IS_OMAP3430ES3_0 | \ 432 CHIP_IS_OMAP3430ES3_0 | \
427 CHIP_IS_OMAP3430ES3_1 | \ 433 CHIP_GE_OMAP3430ES3_1)
428 CHIP_IS_OMAP3630ES1)
429#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \ 434#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \
430 CHIP_IS_OMAP3630ES1) 435 CHIP_IS_OMAP3630ES1 | \
431 436 CHIP_GE_OMAP3630ES1_1)
437#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \
438 CHIP_IS_OMAP3630ES1_2)
432 439
433int omap_chip_is(struct omap_chip_id oci); 440int omap_chip_is(struct omap_chip_id oci);
434void omap2_check_revision(void); 441void omap2_check_revision(void);
@@ -444,6 +451,7 @@ extern u32 omap3_features;
444#define OMAP3_HAS_NEON BIT(3) 451#define OMAP3_HAS_NEON BIT(3)
445#define OMAP3_HAS_ISP BIT(4) 452#define OMAP3_HAS_ISP BIT(4)
446#define OMAP3_HAS_192MHZ_CLK BIT(5) 453#define OMAP3_HAS_192MHZ_CLK BIT(5)
454#define OMAP3_HAS_IO_WAKEUP BIT(6)
447 455
448#define OMAP3_HAS_FEATURE(feat,flag) \ 456#define OMAP3_HAS_FEATURE(feat,flag) \
449static inline unsigned int omap3_has_ ##feat(void) \ 457static inline unsigned int omap3_has_ ##feat(void) \
@@ -457,5 +465,6 @@ OMAP3_HAS_FEATURE(iva, IVA)
457OMAP3_HAS_FEATURE(neon, NEON) 465OMAP3_HAS_FEATURE(neon, NEON)
458OMAP3_HAS_FEATURE(isp, ISP) 466OMAP3_HAS_FEATURE(isp, ISP)
459OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) 467OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
468OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
460 469
461#endif 470#endif
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 02232ca2c37..af3a03941ad 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -345,6 +345,7 @@
345#define OMAP_DMA_SYNC_BLOCK 0x02 345#define OMAP_DMA_SYNC_BLOCK 0x02
346#define OMAP_DMA_SYNC_PACKET 0x03 346#define OMAP_DMA_SYNC_PACKET 0x03
347 347
348#define OMAP_DMA_DST_SYNC_PREFETCH 0x02
348#define OMAP_DMA_SRC_SYNC 0x01 349#define OMAP_DMA_SRC_SYNC 0x01
349#define OMAP_DMA_DST_SYNC 0x00 350#define OMAP_DMA_DST_SYNC 0x00
350 351
diff --git a/arch/arm/plat-omap/include/plat/dsp_common.h b/arch/arm/plat-omap/include/plat/dsp_common.h
deleted file mode 100644
index da97736f3ef..00000000000
--- a/arch/arm/plat-omap/include/plat/dsp_common.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
3 *
4 * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
5 *
6 * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#ifndef ASM_ARCH_DSP_COMMON_H
25#define ASM_ARCH_DSP_COMMON_H
26
27#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
28extern void omap_dsp_request_mpui(void);
29extern void omap_dsp_release_mpui(void);
30extern int omap_dsp_request_mem(void);
31extern int omap_dsp_release_mem(void);
32#else
33static inline int omap_dsp_request_mem(void)
34{
35 return 0;
36}
37#define omap_dsp_release_mem() do {} while (0)
38#endif
39
40#endif /* ASM_ARCH_DSP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 145838a81ef..9fd99b9e40a 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -25,10 +25,26 @@
25#define GPMC_CS_NAND_ADDRESS 0x20 25#define GPMC_CS_NAND_ADDRESS 0x20
26#define GPMC_CS_NAND_DATA 0x24 26#define GPMC_CS_NAND_DATA 0x24
27 27
28#define GPMC_CONFIG 0x50 28/* Control Commands */
29#define GPMC_STATUS 0x54 29#define GPMC_CONFIG_RDY_BSY 0x00000001
30#define GPMC_CS0_BASE 0x60 30#define GPMC_CONFIG_DEV_SIZE 0x00000002
31#define GPMC_CS_SIZE 0x30 31#define GPMC_CONFIG_DEV_TYPE 0x00000003
32#define GPMC_SET_IRQ_STATUS 0x00000004
33#define GPMC_CONFIG_WP 0x00000005
34
35#define GPMC_GET_IRQ_STATUS 0x00000006
36#define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */
37#define GPMC_PREFETCH_COUNT 0x00000008 /* remaining bytes to be read/write*/
38#define GPMC_STATUS_BUFFER 0x00000009 /* 1: buffer is available to write */
39
40#define GPMC_NAND_COMMAND 0x0000000a
41#define GPMC_NAND_ADDRESS 0x0000000b
42#define GPMC_NAND_DATA 0x0000000c
43
44/* ECC commands */
45#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
46#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
47#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
32 48
33#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 49#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
34#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) 50#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
@@ -47,7 +63,6 @@
47#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) 63#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
48#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) 64#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
49#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) 65#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
50#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2)
51#define GPMC_CONFIG1_MUXADDDATA (1 << 9) 66#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
52#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) 67#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
53#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) 68#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
@@ -56,6 +71,14 @@
56#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) 71#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
57#define GPMC_CONFIG7_CSVALID (1 << 6) 72#define GPMC_CONFIG7_CSVALID (1 << 6)
58 73
74#define GPMC_DEVICETYPE_NOR 0
75#define GPMC_DEVICETYPE_NAND 2
76#define GPMC_CONFIG_WRITEPROTECT 0x00000010
77#define GPMC_STATUS_BUFF_EMPTY 0x00000001
78#define WR_RD_PIN_MONITORING 0x00600000
79#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
80#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
81
59/* 82/*
60 * Note that all values in this struct are in nanoseconds, while 83 * Note that all values in this struct are in nanoseconds, while
61 * the register values are in gpmc_fck cycles. 84 * the register values are in gpmc_fck cycles.
@@ -108,10 +131,15 @@ extern int gpmc_cs_set_reserved(int cs, int reserved);
108extern int gpmc_cs_reserved(int cs); 131extern int gpmc_cs_reserved(int cs);
109extern int gpmc_prefetch_enable(int cs, int dma_mode, 132extern int gpmc_prefetch_enable(int cs, int dma_mode,
110 unsigned int u32_count, int is_write); 133 unsigned int u32_count, int is_write);
111extern void gpmc_prefetch_reset(void); 134extern int gpmc_prefetch_reset(int cs);
112extern int gpmc_prefetch_status(void);
113extern void omap3_gpmc_save_context(void); 135extern void omap3_gpmc_save_context(void);
114extern void omap3_gpmc_restore_context(void); 136extern void omap3_gpmc_restore_context(void);
115extern void gpmc_init(void); 137extern void gpmc_init(void);
138extern int gpmc_read_status(int cmd);
139extern int gpmc_cs_configure(int cs, int cmd, int wval);
140extern int gpmc_nand_read(int cs, int cmd);
141extern int gpmc_nand_write(int cs, int cmd, int wval);
116 142
143int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size);
144int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code);
117#endif 145#endif
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 0752af9d099..33c7d41cb6a 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -80,6 +80,7 @@ struct iommu_functions {
80 80
81 int (*enable)(struct iommu *obj); 81 int (*enable)(struct iommu *obj);
82 void (*disable)(struct iommu *obj); 82 void (*disable)(struct iommu *obj);
83 void (*set_twl)(struct iommu *obj, bool on);
83 u32 (*fault_isr)(struct iommu *obj, u32 *ra); 84 u32 (*fault_isr)(struct iommu *obj, u32 *ra);
84 85
85 void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); 86 void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
@@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
143extern u32 iotlb_cr_to_virt(struct cr_regs *cr); 144extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
144 145
145extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); 146extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
147extern void iommu_set_twl(struct iommu *obj, bool on);
146extern void flush_iotlb_page(struct iommu *obj, u32 da); 148extern void flush_iotlb_page(struct iommu *obj, u32 da);
147extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); 149extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
148extern void flush_iotlb_all(struct iommu *obj); 150extern void flush_iotlb_all(struct iommu *obj);
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index 729166b76a7..99765655210 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -3,10 +3,11 @@
3#ifndef MAILBOX_H 3#ifndef MAILBOX_H
4#define MAILBOX_H 4#define MAILBOX_H
5 5
6#include <linux/wait.h> 6#include <linux/spinlock.h>
7#include <linux/workqueue.h> 7#include <linux/workqueue.h>
8#include <linux/blkdev.h>
9#include <linux/interrupt.h> 8#include <linux/interrupt.h>
9#include <linux/device.h>
10#include <linux/kfifo.h>
10 11
11typedef u32 mbox_msg_t; 12typedef u32 mbox_msg_t;
12struct omap_mbox; 13struct omap_mbox;
@@ -42,7 +43,7 @@ struct omap_mbox_ops {
42 43
43struct omap_mbox_queue { 44struct omap_mbox_queue {
44 spinlock_t lock; 45 spinlock_t lock;
45 struct request_queue *queue; 46 struct kfifo fifo;
46 struct work_struct work; 47 struct work_struct work;
47 struct tasklet_struct tasklet; 48 struct tasklet_struct tasklet;
48 int (*callback)(void *); 49 int (*callback)(void *);
@@ -52,19 +53,10 @@ struct omap_mbox_queue {
52struct omap_mbox { 53struct omap_mbox {
53 char *name; 54 char *name;
54 unsigned int irq; 55 unsigned int irq;
55
56 struct omap_mbox_queue *txq, *rxq; 56 struct omap_mbox_queue *txq, *rxq;
57
58 struct omap_mbox_ops *ops; 57 struct omap_mbox_ops *ops;
59
60 mbox_msg_t seq_snd, seq_rcv;
61
62 struct device *dev; 58 struct device *dev;
63
64 struct omap_mbox *next;
65 void *priv; 59 void *priv;
66
67 void (*err_notify)(void);
68}; 60};
69 61
70int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg); 62int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
@@ -73,8 +65,8 @@ void omap_mbox_init_seq(struct omap_mbox *);
73struct omap_mbox *omap_mbox_get(const char *); 65struct omap_mbox *omap_mbox_get(const char *);
74void omap_mbox_put(struct omap_mbox *); 66void omap_mbox_put(struct omap_mbox *);
75 67
76int omap_mbox_register(struct device *parent, struct omap_mbox *); 68int omap_mbox_register(struct device *parent, struct omap_mbox **);
77int omap_mbox_unregister(struct omap_mbox *); 69int omap_mbox_unregister(void);
78 70
79static inline void omap_mbox_save_ctx(struct omap_mbox *mbox) 71static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
80{ 72{
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index c7472a28ce2..aeba71796ad 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -114,28 +114,11 @@
114 PU_PD_REG(NA, 0) \ 114 PU_PD_REG(NA, 0) \
115}, 115},
116 116
117#define MUX_CFG_24XX(desc, reg_offset, mode, \
118 pull_en, pull_mode, dbg) \
119{ \
120 .name = desc, \
121 .debug = dbg, \
122 .mux_reg = reg_offset, \
123 .mask = mode, \
124 .pull_val = pull_en, \
125 .pu_pd_val = pull_mode, \
126},
127
128/* 24xx/34xx mux bit defines */
129#define OMAP2_PULL_ENA (1 << 3)
130#define OMAP2_PULL_UP (1 << 4)
131#define OMAP2_ALTELECTRICALSEL (1 << 5)
132
133struct pin_config { 117struct pin_config {
134 char *name; 118 char *name;
135 const unsigned int mux_reg; 119 const unsigned int mux_reg;
136 unsigned char debug; 120 unsigned char debug;
137 121
138#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
139 const unsigned char mask_offset; 122 const unsigned char mask_offset;
140 const unsigned char mask; 123 const unsigned char mask;
141 124
@@ -147,7 +130,6 @@ struct pin_config {
147 const char *pu_pd_name; 130 const char *pu_pd_name;
148 const unsigned int pu_pd_reg; 131 const unsigned int pu_pd_reg;
149 const unsigned char pu_pd_val; 132 const unsigned char pu_pd_val;
150#endif
151 133
152#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) 134#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
153 const char *mux_reg_name; 135 const char *mux_reg_name;
@@ -191,6 +173,10 @@ enum omap7xx_index {
191 SPI_7XX_4, 173 SPI_7XX_4,
192 SPI_7XX_5, 174 SPI_7XX_5,
193 SPI_7XX_6, 175 SPI_7XX_6,
176
177 /* UART */
178 UART_7XX_1,
179 UART_7XX_2,
194}; 180};
195 181
196enum omap1xxx_index { 182enum omap1xxx_index {
@@ -446,208 +432,6 @@ enum omap1xxx_index {
446 432
447}; 433};
448 434
449enum omap24xx_index {
450 /* 24xx I2C */
451 M19_24XX_I2C1_SCL,
452 L15_24XX_I2C1_SDA,
453 J15_24XX_I2C2_SCL,
454 H19_24XX_I2C2_SDA,
455
456 /* 24xx Menelaus interrupt */
457 W19_24XX_SYS_NIRQ,
458
459 /* 24xx clock */
460 W14_24XX_SYS_CLKOUT,
461
462 /* 24xx GPMC chipselects, wait pin monitoring */
463 E2_GPMC_NCS2,
464 L2_GPMC_NCS7,
465 L3_GPMC_WAIT0,
466 N7_GPMC_WAIT1,
467 M1_GPMC_WAIT2,
468 P1_GPMC_WAIT3,
469
470 /* 242X McBSP */
471 Y15_24XX_MCBSP2_CLKX,
472 R14_24XX_MCBSP2_FSX,
473 W15_24XX_MCBSP2_DR,
474 V15_24XX_MCBSP2_DX,
475
476 /* 24xx GPIO */
477 M21_242X_GPIO11,
478 P21_242X_GPIO12,
479 AA10_242X_GPIO13,
480 AA6_242X_GPIO14,
481 AA4_242X_GPIO15,
482 Y11_242X_GPIO16,
483 AA12_242X_GPIO17,
484 AA8_242X_GPIO58,
485 Y20_24XX_GPIO60,
486 W4__24XX_GPIO74,
487 N15_24XX_GPIO85,
488 M15_24XX_GPIO92,
489 P20_24XX_GPIO93,
490 P18_24XX_GPIO95,
491 M18_24XX_GPIO96,
492 L14_24XX_GPIO97,
493 J15_24XX_GPIO99,
494 V14_24XX_GPIO117,
495 P14_24XX_GPIO125,
496
497 /* 242x DBG GPIO */
498 V4_242X_GPIO49,
499 W2_242X_GPIO50,
500 U4_242X_GPIO51,
501 V3_242X_GPIO52,
502 V2_242X_GPIO53,
503 V6_242X_GPIO53,
504 T4_242X_GPIO54,
505 Y4_242X_GPIO54,
506 T3_242X_GPIO55,
507 U2_242X_GPIO56,
508
509 /* 24xx external DMA requests */
510 AA10_242X_DMAREQ0,
511 AA6_242X_DMAREQ1,
512 E4_242X_DMAREQ2,
513 G4_242X_DMAREQ3,
514 D3_242X_DMAREQ4,
515 E3_242X_DMAREQ5,
516
517 /* UART3 */
518 K15_24XX_UART3_TX,
519 K14_24XX_UART3_RX,
520
521 /* MMC/SDIO */
522 G19_24XX_MMC_CLKO,
523 H18_24XX_MMC_CMD,
524 F20_24XX_MMC_DAT0,
525 H14_24XX_MMC_DAT1,
526 E19_24XX_MMC_DAT2,
527 D19_24XX_MMC_DAT3,
528 F19_24XX_MMC_DAT_DIR0,
529 E20_24XX_MMC_DAT_DIR1,
530 F18_24XX_MMC_DAT_DIR2,
531 E18_24XX_MMC_DAT_DIR3,
532 G18_24XX_MMC_CMD_DIR,
533 H15_24XX_MMC_CLKI,
534
535 /* Full speed USB */
536 J20_24XX_USB0_PUEN,
537 J19_24XX_USB0_VP,
538 K20_24XX_USB0_VM,
539 J18_24XX_USB0_RCV,
540 K19_24XX_USB0_TXEN,
541 J14_24XX_USB0_SE0,
542 K18_24XX_USB0_DAT,
543
544 N14_24XX_USB1_SE0,
545 W12_24XX_USB1_SE0,
546 P15_24XX_USB1_DAT,
547 R13_24XX_USB1_DAT,
548 W20_24XX_USB1_TXEN,
549 P13_24XX_USB1_TXEN,
550 V19_24XX_USB1_RCV,
551 V12_24XX_USB1_RCV,
552
553 AA10_24XX_USB2_SE0,
554 Y11_24XX_USB2_DAT,
555 AA12_24XX_USB2_TXEN,
556 AA6_24XX_USB2_RCV,
557 AA4_24XX_USB2_TLLSE0,
558
559 /* Keypad GPIO*/
560 T19_24XX_KBR0,
561 R19_24XX_KBR1,
562 V18_24XX_KBR2,
563 M21_24XX_KBR3,
564 E5__24XX_KBR4,
565 M18_24XX_KBR5,
566 R20_24XX_KBC0,
567 M14_24XX_KBC1,
568 H19_24XX_KBC2,
569 V17_24XX_KBC3,
570 P21_24XX_KBC4,
571 L14_24XX_KBC5,
572 N19_24XX_KBC6,
573
574 /* 24xx Menelaus Keypad GPIO */
575 B3__24XX_KBR5,
576 AA4_24XX_KBC2,
577 B13_24XX_KBC6,
578
579 /* 2430 USB */
580 AD9_2430_USB0_PUEN,
581 Y11_2430_USB0_VP,
582 AD7_2430_USB0_VM,
583 AE7_2430_USB0_RCV,
584 AD4_2430_USB0_TXEN,
585 AF9_2430_USB0_SE0,
586 AE6_2430_USB0_DAT,
587 AD24_2430_USB1_SE0,
588 AB24_2430_USB1_RCV,
589 Y25_2430_USB1_TXEN,
590 AA26_2430_USB1_DAT,
591
592 /* 2430 HS-USB */
593 AD9_2430_USB0HS_DATA3,
594 Y11_2430_USB0HS_DATA4,
595 AD7_2430_USB0HS_DATA5,
596 AE7_2430_USB0HS_DATA6,
597 AD4_2430_USB0HS_DATA2,
598 AF9_2430_USB0HS_DATA0,
599 AE6_2430_USB0HS_DATA1,
600 AE8_2430_USB0HS_CLK,
601 AD8_2430_USB0HS_DIR,
602 AE5_2430_USB0HS_STP,
603 AE9_2430_USB0HS_NXT,
604 AC7_2430_USB0HS_DATA7,
605
606 /* 2430 McBSP */
607 AD6_2430_MCBSP_CLKS,
608
609 AB2_2430_MCBSP1_CLKR,
610 AD5_2430_MCBSP1_FSR,
611 AA1_2430_MCBSP1_DX,
612 AF3_2430_MCBSP1_DR,
613 AB3_2430_MCBSP1_FSX,
614 Y9_2430_MCBSP1_CLKX,
615
616 AC10_2430_MCBSP2_FSX,
617 AD16_2430_MCBSP2_CLX,
618 AE13_2430_MCBSP2_DX,
619 AD13_2430_MCBSP2_DR,
620 AC10_2430_MCBSP2_FSX_OFF,
621 AD16_2430_MCBSP2_CLX_OFF,
622 AE13_2430_MCBSP2_DX_OFF,
623 AD13_2430_MCBSP2_DR_OFF,
624
625 AC9_2430_MCBSP3_CLKX,
626 AE4_2430_MCBSP3_FSX,
627 AE2_2430_MCBSP3_DR,
628 AF4_2430_MCBSP3_DX,
629
630 N3_2430_MCBSP4_CLKX,
631 AD23_2430_MCBSP4_DR,
632 AB25_2430_MCBSP4_DX,
633 AC25_2430_MCBSP4_FSX,
634
635 AE16_2430_MCBSP5_CLKX,
636 AF12_2430_MCBSP5_FSX,
637 K7_2430_MCBSP5_DX,
638 M1_2430_MCBSP5_DR,
639
640 /* 2430 McSPI*/
641 Y18_2430_MCSPI1_CLK,
642 AD15_2430_MCSPI1_SIMO,
643 AE17_2430_MCSPI1_SOMI,
644 U1_2430_MCSPI1_CS0,
645
646 /* Touchscreen GPIO */
647 AF19_2430_GPIO_85,
648
649};
650
651struct omap_mux_cfg { 435struct omap_mux_cfg {
652 struct pin_config *pins; 436 struct pin_config *pins;
653 unsigned long size; 437 unsigned long size;
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index f8efd5466b1..6562cd082bb 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -21,13 +21,11 @@ struct omap_nand_platform_data {
21 int (*dev_ready)(struct omap_nand_platform_data *); 21 int (*dev_ready)(struct omap_nand_platform_data *);
22 int dma_channel; 22 int dma_channel;
23 unsigned long phys_base; 23 unsigned long phys_base;
24 void __iomem *gpmc_cs_baseaddr;
25 void __iomem *gpmc_baseaddr;
26 int devsize; 24 int devsize;
27}; 25};
28 26
29/* size (4 KiB) for IO mapping */ 27/* minimum size for IO mapping */
30#define NAND_IO_SIZE SZ_4K 28#define NAND_IO_SIZE 4
31 29
32#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) 30#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
33extern int gpmc_nand_init(struct omap_nand_platform_data *d); 31extern int gpmc_nand_init(struct omap_nand_platform_data *d);
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index 3ee41d71149..728fbb9dd54 100644
--- a/arch/arm/plat-omap/include/plat/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * omap-pm.h - OMAP power management interface 2 * omap-pm.h - OMAP power management interface
3 * 3 *
4 * Copyright (C) 2008-2009 Texas Instruments, Inc. 4 * Copyright (C) 2008-2010 Texas Instruments, Inc.
5 * Copyright (C) 2008-2009 Nokia Corporation 5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Paul Walmsley 6 * Paul Walmsley
7 * 7 *
8 * Interface developed by (in alphabetical order): Karthik Dasu, Jouni 8 * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
@@ -16,6 +16,7 @@
16 16
17#include <linux/device.h> 17#include <linux/device.h>
18#include <linux/cpufreq.h> 18#include <linux/cpufreq.h>
19#include <linux/clk.h>
19 20
20#include "powerdomain.h" 21#include "powerdomain.h"
21 22
@@ -89,7 +90,7 @@ void omap_pm_if_exit(void);
89 * @t: maximum MPU wakeup latency in microseconds 90 * @t: maximum MPU wakeup latency in microseconds
90 * 91 *
91 * Request that the maximum interrupt latency for the MPU to be no 92 * Request that the maximum interrupt latency for the MPU to be no
92 * greater than 't' microseconds. "Interrupt latency" in this case is 93 * greater than @t microseconds. "Interrupt latency" in this case is
93 * defined as the elapsed time from the occurrence of a hardware or 94 * defined as the elapsed time from the occurrence of a hardware or
94 * timer interrupt to the time when the device driver's interrupt 95 * timer interrupt to the time when the device driver's interrupt
95 * service routine has been entered by the MPU. 96 * service routine has been entered by the MPU.
@@ -105,15 +106,19 @@ void omap_pm_if_exit(void);
105 * elapsed from when a device driver enables a hardware device with 106 * elapsed from when a device driver enables a hardware device with
106 * clk_enable(), to when the device is ready for register access or 107 * clk_enable(), to when the device is ready for register access or
107 * other use. To control this device wakeup latency, use 108 * other use. To control this device wakeup latency, use
108 * set_max_dev_wakeup_lat() 109 * omap_pm_set_max_dev_wakeup_lat()
109 * 110 *
110 * Multiple calls to set_max_mpu_wakeup_lat() will replace the 111 * Multiple calls to omap_pm_set_max_mpu_wakeup_lat() will replace the
111 * previous t value. To remove the latency target for the MPU, call 112 * previous t value. To remove the latency target for the MPU, call
112 * with t = -1. 113 * with t = -1.
113 * 114 *
114 * No return value. 115 * XXX This constraint will be deprecated soon in favor of the more
116 * general omap_pm_set_max_dev_wakeup_lat()
117 *
118 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
119 * is not satisfiable, or 0 upon success.
115 */ 120 */
116void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); 121int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
117 122
118 123
119/** 124/**
@@ -123,8 +128,8 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
123 * @r: minimum throughput (in KiB/s) 128 * @r: minimum throughput (in KiB/s)
124 * 129 *
125 * Request that the minimum data throughput on the OCP interconnect 130 * Request that the minimum data throughput on the OCP interconnect
126 * attached to device 'dev' interconnect agent 'tbus_id' be no less 131 * attached to device @dev interconnect agent @tbus_id be no less
127 * than 'r' KiB/s. 132 * than @r KiB/s.
128 * 133 *
129 * It is expected that the OMAP PM or bus code will use this 134 * It is expected that the OMAP PM or bus code will use this
130 * information to set the interconnect clock to run at the lowest 135 * information to set the interconnect clock to run at the lowest
@@ -138,40 +143,44 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
138 * code will also need to add an minimum L3 interconnect speed 143 * code will also need to add an minimum L3 interconnect speed
139 * constraint, 144 * constraint,
140 * 145 *
141 * Multiple calls to set_min_bus_tput() will replace the previous rate 146 * Multiple calls to omap_pm_set_min_bus_tput() will replace the
142 * value for this device. To remove the interconnect throughput 147 * previous rate value for this device. To remove the interconnect
143 * restriction for this device, call with r = 0. 148 * throughput restriction for this device, call with r = 0.
144 * 149 *
145 * No return value. 150 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
151 * is not satisfiable, or 0 upon success.
146 */ 152 */
147void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r); 153int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
148 154
149 155
150/** 156/**
151 * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency 157 * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
152 * @dev: struct device * 158 * @req_dev: struct device * requesting the constraint, or NULL if none
159 * @dev: struct device * to set the constraint one
153 * @t: maximum device wakeup latency in microseconds 160 * @t: maximum device wakeup latency in microseconds
154 * 161 *
155 * Request that the maximum amount of time necessary for a device to 162 * Request that the maximum amount of time necessary for a device @dev
156 * become accessible after its clocks are enabled should be no greater 163 * to become accessible after its clocks are enabled should be no
157 * than 't' microseconds. Specifically, this represents the time from 164 * greater than @t microseconds. Specifically, this represents the
158 * when a device driver enables device clocks with clk_enable(), to 165 * time from when a device driver enables device clocks with
159 * when the register reads and writes on the device will succeed. 166 * clk_enable(), to when the register reads and writes on the device
160 * This function should be called before clk_disable() is called, 167 * will succeed. This function should be called before clk_disable()
161 * since the power state transition decision may be made during 168 * is called, since the power state transition decision may be made
162 * clk_disable(). 169 * during clk_disable().
163 * 170 *
164 * It is intended that underlying PM code will use this information to 171 * It is intended that underlying PM code will use this information to
165 * determine what power state to put the powerdomain enclosing this 172 * determine what power state to put the powerdomain enclosing this
166 * device into. 173 * device into.
167 * 174 *
168 * Multiple calls to set_max_dev_wakeup_lat() will replace the 175 * Multiple calls to omap_pm_set_max_dev_wakeup_lat() will replace the
169 * previous wakeup latency values for this device. To remove the wakeup 176 * previous wakeup latency values for this device. To remove the
170 * latency restriction for this device, call with t = -1. 177 * wakeup latency restriction for this device, call with t = -1.
171 * 178 *
172 * No return value. 179 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
180 * is not satisfiable, or 0 upon success.
173 */ 181 */
174void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t); 182int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
183 long t);
175 184
176 185
177/** 186/**
@@ -198,10 +207,71 @@ void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
198 * value for this device. To remove the maximum DMA latency for this 207 * value for this device. To remove the maximum DMA latency for this
199 * device, call with t = -1. 208 * device, call with t = -1.
200 * 209 *
201 * No return value. 210 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
211 * is not satisfiable, or 0 upon success.
202 */ 212 */
203void omap_pm_set_max_sdma_lat(struct device *dev, long t); 213int omap_pm_set_max_sdma_lat(struct device *dev, long t);
214
204 215
216/**
217 * omap_pm_set_min_clk_rate - set minimum clock rate requested by @dev
218 * @dev: struct device * requesting the constraint
219 * @clk: struct clk * to set the minimum rate constraint on
220 * @r: minimum rate in Hz
221 *
222 * Request that the minimum clock rate on the device @dev's clk @clk
223 * be no less than @r Hz.
224 *
225 * It is expected that the OMAP PM code will use this information to
226 * find an OPP or clock setting that will satisfy this clock rate
227 * constraint, along with any other applicable system constraints on
228 * the clock rate or corresponding voltage, etc.
229 *
230 * omap_pm_set_min_clk_rate() differs from the clock code's
231 * clk_set_rate() in that it considers other constraints before taking
232 * any hardware action, and may change a system OPP rather than just a
233 * clock rate. clk_set_rate() is intended to be a low-level
234 * interface.
235 *
236 * omap_pm_set_min_clk_rate() is easily open to abuse. A better API
237 * would be something like "omap_pm_set_min_dev_performance()";
238 * however, there is no easily-generalizable concept of performance
239 * that applies to all devices. Only a device (and possibly the
240 * device subsystem) has both the subsystem-specific knowledge, and
241 * the hardware IP block-specific knowledge, to translate a constraint
242 * on "touchscreen sampling accuracy" or "number of pixels or polygons
243 * rendered per second" to a clock rate. This translation can be
244 * dependent on the hardware IP block's revision, or firmware version,
245 * and the driver is the only code on the system that has this
246 * information and can know how to translate that into a clock rate.
247 *
248 * The intended use-case for this function is for userspace or other
249 * kernel code to communicate a particular performance requirement to
250 * a subsystem; then for the subsystem to communicate that requirement
251 * to something that is meaningful to the device driver; then for the
252 * device driver to convert that requirement to a clock rate, and to
253 * then call omap_pm_set_min_clk_rate().
254 *
255 * Users of this function (such as device drivers) should not simply
256 * call this function with some high clock rate to ensure "high
257 * performance." Rather, the device driver should take a performance
258 * constraint from its subsystem, such as "render at least X polygons
259 * per second," and use some formula or table to convert that into a
260 * clock rate constraint given the hardware type and hardware
261 * revision. Device drivers or subsystems should not assume that they
262 * know how to make a power/performance tradeoff - some device use
263 * cases may tolerate a lower-fidelity device function for lower power
264 * consumption; others may demand a higher-fidelity device function,
265 * no matter what the power consumption.
266 *
267 * Multiple calls to omap_pm_set_min_clk_rate() will replace the
268 * previous rate value for the device @dev. To remove the minimum clock
269 * rate constraint for the device, call with r = 0.
270 *
271 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
272 * is not satisfiable, or 0 upon success.
273 */
274int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r);
205 275
206/* 276/*
207 * DSP Bridge-specific constraints 277 * DSP Bridge-specific constraints
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 3694b622c4a..25cd9ac3b09 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -101,6 +101,8 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
101int omap_device_register(struct omap_device *od); 101int omap_device_register(struct omap_device *od);
102int omap_early_device_register(struct omap_device *od); 102int omap_early_device_register(struct omap_device *od);
103 103
104void __iomem *omap_device_get_rt_va(struct omap_device *od);
105
104/* OMAP PM interface */ 106/* OMAP PM interface */
105int omap_device_align_pm_lat(struct platform_device *pdev, 107int omap_device_align_pm_lat(struct platform_device *pdev,
106 u32 new_wakeup_lat_limit); 108 u32 new_wakeup_lat_limit);
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 0eccc09ac4a..a4e508dfaba 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod macros, structures 2 * omap_hwmod macros, structures
3 * 3 *
4 * Copyright (C) 2009 Nokia Corporation 4 * Copyright (C) 2009-2010 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * Created in collaboration with (alphabetical order): Benoît Cousson, 7 * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -419,7 +419,7 @@ struct omap_hwmod_class {
419 * @slaves: ptr to array of OCP ifs that this hwmod can respond on 419 * @slaves: ptr to array of OCP ifs that this hwmod can respond on
420 * @dev_attr: arbitrary device attributes that can be passed to the driver 420 * @dev_attr: arbitrary device attributes that can be passed to the driver
421 * @_sysc_cache: internal-use hwmod flags 421 * @_sysc_cache: internal-use hwmod flags
422 * @_rt_va: cached register target start address (internal use) 422 * @_mpu_rt_va: cached register target start address (internal use)
423 * @_mpu_port_index: cached MPU register target slave ID (internal use) 423 * @_mpu_port_index: cached MPU register target slave ID (internal use)
424 * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) 424 * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
425 * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift 425 * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
@@ -460,7 +460,7 @@ struct omap_hwmod {
460 struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ 460 struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
461 void *dev_attr; 461 void *dev_attr;
462 u32 _sysc_cache; 462 u32 _sysc_cache;
463 void __iomem *_rt_va; 463 void __iomem *_mpu_rt_va;
464 struct list_head node; 464 struct list_head node;
465 u16 flags; 465 u16 flags;
466 u8 _mpu_port_index; 466 u8 _mpu_port_index;
@@ -482,11 +482,14 @@ int omap_hwmod_init(struct omap_hwmod **ohs);
482int omap_hwmod_register(struct omap_hwmod *oh); 482int omap_hwmod_register(struct omap_hwmod *oh);
483int omap_hwmod_unregister(struct omap_hwmod *oh); 483int omap_hwmod_unregister(struct omap_hwmod *oh);
484struct omap_hwmod *omap_hwmod_lookup(const char *name); 484struct omap_hwmod *omap_hwmod_lookup(const char *name);
485int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)); 485int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
486int omap_hwmod_late_init(void); 486 void *data);
487int omap_hwmod_late_init(u8 skip_setup_idle);
487 488
488int omap_hwmod_enable(struct omap_hwmod *oh); 489int omap_hwmod_enable(struct omap_hwmod *oh);
490int _omap_hwmod_enable(struct omap_hwmod *oh);
489int omap_hwmod_idle(struct omap_hwmod *oh); 491int omap_hwmod_idle(struct omap_hwmod *oh);
492int _omap_hwmod_idle(struct omap_hwmod *oh);
490int omap_hwmod_shutdown(struct omap_hwmod *oh); 493int omap_hwmod_shutdown(struct omap_hwmod *oh);
491 494
492int omap_hwmod_enable_clocks(struct omap_hwmod *oh); 495int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
@@ -504,6 +507,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh);
504int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); 507int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
505 508
506struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); 509struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
510void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
507 511
508int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, 512int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
509 struct omap_hwmod *init_oh); 513 struct omap_hwmod *init_oh);
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 8983d54c4fd..6a3ff65c030 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -30,6 +30,7 @@
30extern void omap_secondary_startup(void); 30extern void omap_secondary_startup(void);
31extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); 31extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
32extern void omap_auxcoreboot_addr(u32 cpu_addr); 32extern void omap_auxcoreboot_addr(u32 cpu_addr);
33extern u32 omap_read_auxcoreboot0(void);
33 34
34/* 35/*
35 * We use Soft IRQ1 as the IPI 36 * We use Soft IRQ1 as the IPI
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index bbedd71943f..ddf723be48d 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -25,6 +25,8 @@
25 25
26#include <plat/serial.h> 26#include <plat/serial.h>
27 27
28#define MDR1_MODE_MASK 0x07
29
28static volatile u8 *uart_base; 30static volatile u8 *uart_base;
29static int uart_shift; 31static int uart_shift;
30 32
@@ -42,6 +44,10 @@ static void putc(int c)
42 if (!uart_base) 44 if (!uart_base)
43 return; 45 return;
44 46
47 /* Check for UART 16x mode */
48 if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
49 return;
50
45 while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) 51 while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
46 barrier(); 52 barrier();
47 uart_base[UART_TX << uart_shift] = c; 53 uart_base[UART_TX << uart_shift] = c;
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 98eef5360e6..2a9427c8cc4 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -81,7 +81,34 @@ extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
81 81
82#endif 82#endif
83 83
84void omap_usb_init(struct omap_usb_config *pdata); 84
85/*
86 * FIXME correct answer depends on hmc_mode,
87 * as does (on omap1) any nonzero value for config->otg port number
88 */
89#ifdef CONFIG_USB_GADGET_OMAP
90#define is_usb0_device(config) 1
91#else
92#define is_usb0_device(config) 0
93#endif
94
95void omap_otg_init(struct omap_usb_config *config);
96
97#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
98void omap1_usb_init(struct omap_usb_config *pdata);
99#else
100static inline void omap1_usb_init(struct omap_usb_config *pdata)
101{
102}
103#endif
104
105#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
106void omap2_usbfs_init(struct omap_usb_config *pdata);
107#else
108static inline omap2_usbfs_init(struct omap_usb_config *pdata)
109{
110}
111#endif
85 112
86/*-------------------------------------------------------------------------*/ 113/*-------------------------------------------------------------------------*/
87 114
@@ -192,4 +219,24 @@ void omap_usb_init(struct omap_usb_config *pdata);
192# define USB0PUENACTLOI (1 << 16) 219# define USB0PUENACTLOI (1 << 16)
193# define USBSTANDBYCTRL (1 << 15) 220# define USBSTANDBYCTRL (1 << 15)
194 221
222#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
223u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
224u32 omap1_usb1_init(unsigned nwires);
225u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
226#else
227static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
228{
229 return 0;
230}
231static inline u32 omap1_usb1_init(unsigned nwires)
232{
233 return 0;
234
235}
236static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
237{
238 return 0;
239}
240#endif
241
195#endif /* __ASM_ARCH_OMAP_USB_H */ 242#endif /* __ASM_ARCH_OMAP_USB_H */
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index bc094dbacee..a202a2ce6e3 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -370,6 +370,23 @@ void flush_iotlb_all(struct iommu *obj)
370} 370}
371EXPORT_SYMBOL_GPL(flush_iotlb_all); 371EXPORT_SYMBOL_GPL(flush_iotlb_all);
372 372
373/**
374 * iommu_set_twl - enable/disable table walking logic
375 * @obj: target iommu
376 * @on: enable/disable
377 *
378 * Function used to enable/disable TWL. If one wants to work
379 * exclusively with locked TLB entries and receive notifications
380 * for TLB miss then call this function to disable TWL.
381 */
382void iommu_set_twl(struct iommu *obj, bool on)
383{
384 clk_enable(obj->clk);
385 arch_iommu->set_twl(obj, on);
386 clk_disable(obj->clk);
387}
388EXPORT_SYMBOL_GPL(iommu_set_twl);
389
373#if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) 390#if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
374 391
375ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes) 392ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
@@ -653,7 +670,7 @@ void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
653 if (!*iopgd) 670 if (!*iopgd)
654 goto out; 671 goto out;
655 672
656 if (*iopgd & IOPGD_TABLE) 673 if (iopgd_is_table(*iopgd))
657 iopte = iopte_offset(iopgd, da); 674 iopte = iopte_offset(iopgd, da);
658out: 675out:
659 *ppgd = iopgd; 676 *ppgd = iopgd;
@@ -670,7 +687,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da)
670 if (!*iopgd) 687 if (!*iopgd)
671 return 0; 688 return 0;
672 689
673 if (*iopgd & IOPGD_TABLE) { 690 if (iopgd_is_table(*iopgd)) {
674 int i; 691 int i;
675 u32 *iopte = iopte_offset(iopgd, da); 692 u32 *iopte = iopte_offset(iopgd, da);
676 693
@@ -745,7 +762,7 @@ static void iopgtable_clear_entry_all(struct iommu *obj)
745 if (!*iopgd) 762 if (!*iopgd)
746 continue; 763 continue;
747 764
748 if (*iopgd & IOPGD_TABLE) 765 if (iopgd_is_table(*iopgd))
749 iopte_free(iopte_offset(iopgd, 0)); 766 iopte_free(iopte_offset(iopgd, 0));
750 767
751 *iopgd = 0; 768 *iopgd = 0;
@@ -783,9 +800,11 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
783 if (!stat) 800 if (!stat)
784 return IRQ_HANDLED; 801 return IRQ_HANDLED;
785 802
803 iommu_disable(obj);
804
786 iopgd = iopgd_offset(obj, da); 805 iopgd = iopgd_offset(obj, da);
787 806
788 if (!(*iopgd & IOPGD_TABLE)) { 807 if (!iopgd_is_table(*iopgd)) {
789 dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__, 808 dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__,
790 da, iopgd, *iopgd); 809 da, iopgd, *iopgd);
791 return IRQ_NONE; 810 return IRQ_NONE;
diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h
index ab23b6a140f..c3e93bb0911 100644
--- a/arch/arm/plat-omap/iopgtable.h
+++ b/arch/arm/plat-omap/iopgtable.h
@@ -63,6 +63,8 @@
63#define IOPGD_SECTION (2 << 0) 63#define IOPGD_SECTION (2 << 0)
64#define IOPGD_SUPER (1 << 18 | 2 << 0) 64#define IOPGD_SUPER (1 << 18 | 2 << 0)
65 65
66#define iopgd_is_table(x) (((x) & 3) == IOPGD_TABLE)
67
66#define IOPTE_SMALL (2 << 0) 68#define IOPTE_SMALL (2 << 0)
67#define IOPTE_LARGE (1 << 0) 69#define IOPTE_LARGE (1 << 0)
68 70
@@ -70,12 +72,12 @@
70#define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1)) 72#define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1))
71#define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da)) 73#define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da))
72 74
73#define iopte_paddr(iopgd) (*iopgd & ~((1 << 10) - 1)) 75#define iopgd_page_paddr(iopgd) (*iopgd & ~((1 << 10) - 1))
74#define iopte_vaddr(iopgd) ((u32 *)phys_to_virt(iopte_paddr(iopgd))) 76#define iopgd_page_vaddr(iopgd) ((u32 *)phys_to_virt(iopgd_page_paddr(iopgd)))
75 77
76/* to find an entry in the second-level page table. */ 78/* to find an entry in the second-level page table. */
77#define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1)) 79#define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
78#define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da)) 80#define iopte_offset(iopgd, da) (iopgd_page_vaddr(iopgd) + iopte_index(da))
79 81
80static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, 82static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
81 u32 flags) 83 u32 flags)
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 08a2df76628..d2fafb892f7 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -21,19 +21,26 @@
21 * 21 *
22 */ 22 */
23 23
24#include <linux/module.h>
25#include <linux/interrupt.h> 24#include <linux/interrupt.h>
26#include <linux/device.h> 25#include <linux/spinlock.h>
26#include <linux/mutex.h>
27#include <linux/delay.h> 27#include <linux/delay.h>
28#include <linux/slab.h> 28#include <linux/slab.h>
29#include <linux/kfifo.h>
30#include <linux/err.h>
29 31
30#include <plat/mailbox.h> 32#include <plat/mailbox.h>
31 33
32static struct workqueue_struct *mboxd; 34static struct workqueue_struct *mboxd;
33static struct omap_mbox *mboxes; 35static struct omap_mbox **mboxes;
34static DEFINE_RWLOCK(mboxes_lock); 36static bool rq_full;
35 37
36static int mbox_configured; 38static int mbox_configured;
39static DEFINE_MUTEX(mbox_configured_lock);
40
41static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
42module_param(mbox_kfifo_size, uint, S_IRUGO);
43MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
37 44
38/* Mailbox FIFO handle functions */ 45/* Mailbox FIFO handle functions */
39static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) 46static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
@@ -67,7 +74,7 @@ static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
67/* 74/*
68 * message sender 75 * message sender
69 */ 76 */
70static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg) 77static int __mbox_poll_for_space(struct omap_mbox *mbox)
71{ 78{
72 int ret = 0, i = 1000; 79 int ret = 0, i = 1000;
73 80
@@ -78,49 +85,50 @@ static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
78 return -1; 85 return -1;
79 udelay(1); 86 udelay(1);
80 } 87 }
81 mbox_fifo_write(mbox, msg);
82 return ret; 88 return ret;
83} 89}
84 90
85
86int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg) 91int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
87{ 92{
93 struct omap_mbox_queue *mq = mbox->txq;
94 int ret = 0, len;
88 95
89 struct request *rq; 96 spin_lock(&mq->lock);
90 struct request_queue *q = mbox->txq->queue;
91 97
92 rq = blk_get_request(q, WRITE, GFP_ATOMIC); 98 if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
93 if (unlikely(!rq)) 99 ret = -ENOMEM;
94 return -ENOMEM; 100 goto out;
101 }
102
103 len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
104 WARN_ON(len != sizeof(msg));
95 105
96 blk_insert_request(q, rq, 0, (void *) msg);
97 tasklet_schedule(&mbox->txq->tasklet); 106 tasklet_schedule(&mbox->txq->tasklet);
98 107
99 return 0; 108out:
109 spin_unlock(&mq->lock);
110 return ret;
100} 111}
101EXPORT_SYMBOL(omap_mbox_msg_send); 112EXPORT_SYMBOL(omap_mbox_msg_send);
102 113
103static void mbox_tx_tasklet(unsigned long tx_data) 114static void mbox_tx_tasklet(unsigned long tx_data)
104{ 115{
105 int ret;
106 struct request *rq;
107 struct omap_mbox *mbox = (struct omap_mbox *)tx_data; 116 struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
108 struct request_queue *q = mbox->txq->queue; 117 struct omap_mbox_queue *mq = mbox->txq;
109 118 mbox_msg_t msg;
110 while (1) { 119 int ret;
111
112 rq = blk_fetch_request(q);
113
114 if (!rq)
115 break;
116 120
117 ret = __mbox_msg_send(mbox, (mbox_msg_t)rq->special); 121 while (kfifo_len(&mq->fifo)) {
118 if (ret) { 122 if (__mbox_poll_for_space(mbox)) {
119 omap_mbox_enable_irq(mbox, IRQ_TX); 123 omap_mbox_enable_irq(mbox, IRQ_TX);
120 blk_requeue_request(q, rq); 124 break;
121 return;
122 } 125 }
123 blk_end_request_all(rq, 0); 126
127 ret = kfifo_out(&mq->fifo, (unsigned char *)&msg,
128 sizeof(msg));
129 WARN_ON(ret != sizeof(msg));
130
131 mbox_fifo_write(mbox, msg);
124 } 132 }
125} 133}
126 134
@@ -131,36 +139,21 @@ static void mbox_rx_work(struct work_struct *work)
131{ 139{
132 struct omap_mbox_queue *mq = 140 struct omap_mbox_queue *mq =
133 container_of(work, struct omap_mbox_queue, work); 141 container_of(work, struct omap_mbox_queue, work);
134 struct omap_mbox *mbox = mq->queue->queuedata;
135 struct request_queue *q = mbox->rxq->queue;
136 struct request *rq;
137 mbox_msg_t msg; 142 mbox_msg_t msg;
138 unsigned long flags; 143 int len;
139 144
140 while (1) { 145 while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
141 spin_lock_irqsave(q->queue_lock, flags); 146 len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
142 rq = blk_fetch_request(q); 147 WARN_ON(len != sizeof(msg));
143 spin_unlock_irqrestore(q->queue_lock, flags);
144 if (!rq)
145 break;
146 148
147 msg = (mbox_msg_t)rq->special; 149 if (mq->callback)
148 blk_end_request_all(rq, 0); 150 mq->callback((void *)msg);
149 mbox->rxq->callback((void *)msg);
150 } 151 }
151} 152}
152 153
153/* 154/*
154 * Mailbox interrupt handler 155 * Mailbox interrupt handler
155 */ 156 */
156static void mbox_txq_fn(struct request_queue *q)
157{
158}
159
160static void mbox_rxq_fn(struct request_queue *q)
161{
162}
163
164static void __mbox_tx_interrupt(struct omap_mbox *mbox) 157static void __mbox_tx_interrupt(struct omap_mbox *mbox)
165{ 158{
166 omap_mbox_disable_irq(mbox, IRQ_TX); 159 omap_mbox_disable_irq(mbox, IRQ_TX);
@@ -170,19 +163,22 @@ static void __mbox_tx_interrupt(struct omap_mbox *mbox)
170 163
171static void __mbox_rx_interrupt(struct omap_mbox *mbox) 164static void __mbox_rx_interrupt(struct omap_mbox *mbox)
172{ 165{
173 struct request *rq; 166 struct omap_mbox_queue *mq = mbox->rxq;
174 mbox_msg_t msg; 167 mbox_msg_t msg;
175 struct request_queue *q = mbox->rxq->queue; 168 int len;
176 169
177 while (!mbox_fifo_empty(mbox)) { 170 while (!mbox_fifo_empty(mbox)) {
178 rq = blk_get_request(q, WRITE, GFP_ATOMIC); 171 if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
179 if (unlikely(!rq)) 172 omap_mbox_disable_irq(mbox, IRQ_RX);
173 rq_full = true;
180 goto nomem; 174 goto nomem;
175 }
181 176
182 msg = mbox_fifo_read(mbox); 177 msg = mbox_fifo_read(mbox);
183 178
179 len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
180 WARN_ON(len != sizeof(msg));
184 181
185 blk_insert_request(q, rq, 0, (void *)msg);
186 if (mbox->ops->type == OMAP_MBOX_TYPE1) 182 if (mbox->ops->type == OMAP_MBOX_TYPE1)
187 break; 183 break;
188 } 184 }
@@ -207,11 +203,9 @@ static irqreturn_t mbox_interrupt(int irq, void *p)
207} 203}
208 204
209static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, 205static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
210 request_fn_proc *proc,
211 void (*work) (struct work_struct *), 206 void (*work) (struct work_struct *),
212 void (*tasklet)(unsigned long)) 207 void (*tasklet)(unsigned long))
213{ 208{
214 struct request_queue *q;
215 struct omap_mbox_queue *mq; 209 struct omap_mbox_queue *mq;
216 210
217 mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL); 211 mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
@@ -220,11 +214,8 @@ static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
220 214
221 spin_lock_init(&mq->lock); 215 spin_lock_init(&mq->lock);
222 216
223 q = blk_init_queue(proc, &mq->lock); 217 if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
224 if (!q)
225 goto error; 218 goto error;
226 q->queuedata = mbox;
227 mq->queue = q;
228 219
229 if (work) 220 if (work)
230 INIT_WORK(&mq->work, work); 221 INIT_WORK(&mq->work, work);
@@ -239,7 +230,7 @@ error:
239 230
240static void mbox_queue_free(struct omap_mbox_queue *q) 231static void mbox_queue_free(struct omap_mbox_queue *q)
241{ 232{
242 blk_cleanup_queue(q->queue); 233 kfifo_free(&q->fifo);
243 kfree(q); 234 kfree(q);
244} 235}
245 236
@@ -248,35 +239,35 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
248 int ret = 0; 239 int ret = 0;
249 struct omap_mbox_queue *mq; 240 struct omap_mbox_queue *mq;
250 241
251 if (likely(mbox->ops->startup)) { 242 if (mbox->ops->startup) {
252 write_lock(&mboxes_lock); 243 mutex_lock(&mbox_configured_lock);
253 if (!mbox_configured) 244 if (!mbox_configured)
254 ret = mbox->ops->startup(mbox); 245 ret = mbox->ops->startup(mbox);
255 246
256 if (unlikely(ret)) { 247 if (ret) {
257 write_unlock(&mboxes_lock); 248 mutex_unlock(&mbox_configured_lock);
258 return ret; 249 return ret;
259 } 250 }
260 mbox_configured++; 251 mbox_configured++;
261 write_unlock(&mboxes_lock); 252 mutex_unlock(&mbox_configured_lock);
262 } 253 }
263 254
264 ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, 255 ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
265 mbox->name, mbox); 256 mbox->name, mbox);
266 if (unlikely(ret)) { 257 if (ret) {
267 printk(KERN_ERR 258 printk(KERN_ERR
268 "failed to register mailbox interrupt:%d\n", ret); 259 "failed to register mailbox interrupt:%d\n", ret);
269 goto fail_request_irq; 260 goto fail_request_irq;
270 } 261 }
271 262
272 mq = mbox_queue_alloc(mbox, mbox_txq_fn, NULL, mbox_tx_tasklet); 263 mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
273 if (!mq) { 264 if (!mq) {
274 ret = -ENOMEM; 265 ret = -ENOMEM;
275 goto fail_alloc_txq; 266 goto fail_alloc_txq;
276 } 267 }
277 mbox->txq = mq; 268 mbox->txq = mq;
278 269
279 mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work, NULL); 270 mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
280 if (!mq) { 271 if (!mq) {
281 ret = -ENOMEM; 272 ret = -ENOMEM;
282 goto fail_alloc_rxq; 273 goto fail_alloc_rxq;
@@ -290,7 +281,7 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
290 fail_alloc_txq: 281 fail_alloc_txq:
291 free_irq(mbox->irq, mbox); 282 free_irq(mbox->irq, mbox);
292 fail_request_irq: 283 fail_request_irq:
293 if (unlikely(mbox->ops->shutdown)) 284 if (mbox->ops->shutdown)
294 mbox->ops->shutdown(mbox); 285 mbox->ops->shutdown(mbox);
295 286
296 return ret; 287 return ret;
@@ -298,31 +289,20 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
298 289
299static void omap_mbox_fini(struct omap_mbox *mbox) 290static void omap_mbox_fini(struct omap_mbox *mbox)
300{ 291{
292 free_irq(mbox->irq, mbox);
293 tasklet_kill(&mbox->txq->tasklet);
294 flush_work(&mbox->rxq->work);
301 mbox_queue_free(mbox->txq); 295 mbox_queue_free(mbox->txq);
302 mbox_queue_free(mbox->rxq); 296 mbox_queue_free(mbox->rxq);
303 297
304 free_irq(mbox->irq, mbox); 298 if (mbox->ops->shutdown) {
305 299 mutex_lock(&mbox_configured_lock);
306 if (unlikely(mbox->ops->shutdown)) {
307 write_lock(&mboxes_lock);
308 if (mbox_configured > 0) 300 if (mbox_configured > 0)
309 mbox_configured--; 301 mbox_configured--;
310 if (!mbox_configured) 302 if (!mbox_configured)
311 mbox->ops->shutdown(mbox); 303 mbox->ops->shutdown(mbox);
312 write_unlock(&mboxes_lock); 304 mutex_unlock(&mbox_configured_lock);
313 }
314}
315
316static struct omap_mbox **find_mboxes(const char *name)
317{
318 struct omap_mbox **p;
319
320 for (p = &mboxes; *p; p = &(*p)->next) {
321 if (strcmp((*p)->name, name) == 0)
322 break;
323 } 305 }
324
325 return p;
326} 306}
327 307
328struct omap_mbox *omap_mbox_get(const char *name) 308struct omap_mbox *omap_mbox_get(const char *name)
@@ -330,14 +310,15 @@ struct omap_mbox *omap_mbox_get(const char *name)
330 struct omap_mbox *mbox; 310 struct omap_mbox *mbox;
331 int ret; 311 int ret;
332 312
333 read_lock(&mboxes_lock); 313 if (!mboxes)
334 mbox = *(find_mboxes(name)); 314 return ERR_PTR(-EINVAL);
335 if (mbox == NULL) {
336 read_unlock(&mboxes_lock);
337 return ERR_PTR(-ENOENT);
338 }
339 315
340 read_unlock(&mboxes_lock); 316 for (mbox = *mboxes; mbox; mbox++)
317 if (!strcmp(mbox->name, name))
318 break;
319
320 if (!mbox)
321 return ERR_PTR(-ENOENT);
341 322
342 ret = omap_mbox_startup(mbox); 323 ret = omap_mbox_startup(mbox);
343 if (ret) 324 if (ret)
@@ -353,70 +334,77 @@ void omap_mbox_put(struct omap_mbox *mbox)
353} 334}
354EXPORT_SYMBOL(omap_mbox_put); 335EXPORT_SYMBOL(omap_mbox_put);
355 336
356int omap_mbox_register(struct device *parent, struct omap_mbox *mbox) 337static struct class omap_mbox_class = { .name = "mbox", };
338
339int omap_mbox_register(struct device *parent, struct omap_mbox **list)
357{ 340{
358 int ret = 0; 341 int ret;
359 struct omap_mbox **tmp; 342 int i;
360 343
361 if (!mbox) 344 mboxes = list;
345 if (!mboxes)
362 return -EINVAL; 346 return -EINVAL;
363 if (mbox->next)
364 return -EBUSY;
365
366 write_lock(&mboxes_lock);
367 tmp = find_mboxes(mbox->name);
368 if (*tmp) {
369 ret = -EBUSY;
370 write_unlock(&mboxes_lock);
371 goto err_find;
372 }
373 *tmp = mbox;
374 write_unlock(&mboxes_lock);
375 347
348 for (i = 0; mboxes[i]; i++) {
349 struct omap_mbox *mbox = mboxes[i];
350 mbox->dev = device_create(&omap_mbox_class,
351 parent, 0, mbox, "%s", mbox->name);
352 if (IS_ERR(mbox->dev)) {
353 ret = PTR_ERR(mbox->dev);
354 goto err_out;
355 }
356 }
376 return 0; 357 return 0;
377 358
378err_find: 359err_out:
360 while (i--)
361 device_unregister(mboxes[i]->dev);
379 return ret; 362 return ret;
380} 363}
381EXPORT_SYMBOL(omap_mbox_register); 364EXPORT_SYMBOL(omap_mbox_register);
382 365
383int omap_mbox_unregister(struct omap_mbox *mbox) 366int omap_mbox_unregister(void)
384{ 367{
385 struct omap_mbox **tmp; 368 int i;
386 369
387 write_lock(&mboxes_lock); 370 if (!mboxes)
388 tmp = &mboxes; 371 return -EINVAL;
389 while (*tmp) {
390 if (mbox == *tmp) {
391 *tmp = mbox->next;
392 mbox->next = NULL;
393 write_unlock(&mboxes_lock);
394 return 0;
395 }
396 tmp = &(*tmp)->next;
397 }
398 write_unlock(&mboxes_lock);
399 372
400 return -EINVAL; 373 for (i = 0; mboxes[i]; i++)
374 device_unregister(mboxes[i]->dev);
375 mboxes = NULL;
376 return 0;
401} 377}
402EXPORT_SYMBOL(omap_mbox_unregister); 378EXPORT_SYMBOL(omap_mbox_unregister);
403 379
404static int __init omap_mbox_init(void) 380static int __init omap_mbox_init(void)
405{ 381{
382 int err;
383
384 err = class_register(&omap_mbox_class);
385 if (err)
386 return err;
387
406 mboxd = create_workqueue("mboxd"); 388 mboxd = create_workqueue("mboxd");
407 if (!mboxd) 389 if (!mboxd)
408 return -ENOMEM; 390 return -ENOMEM;
409 391
392 /* kfifo size sanity check: alignment and minimal size */
393 mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
394 mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(mbox_msg_t));
395
410 return 0; 396 return 0;
411} 397}
412module_init(omap_mbox_init); 398subsys_initcall(omap_mbox_init);
413 399
414static void __exit omap_mbox_exit(void) 400static void __exit omap_mbox_exit(void)
415{ 401{
416 destroy_workqueue(mboxd); 402 destroy_workqueue(mboxd);
403 class_unregister(&omap_mbox_class);
417} 404}
418module_exit(omap_mbox_exit); 405module_exit(omap_mbox_exit);
419 406
420MODULE_LICENSE("GPL v2"); 407MODULE_LICENSE("GPL v2");
421MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); 408MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
422MODULE_AUTHOR("Toshihiro Kobayashi and Hiroshi DOYU"); 409MODULE_AUTHOR("Toshihiro Kobayashi");
410MODULE_AUTHOR("Hiroshi DOYU");
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 06703635ace..0d4aa0d5876 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -54,7 +54,7 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
54{ 54{
55 struct pin_config *reg; 55 struct pin_config *reg;
56 56
57 if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 57 if (!cpu_class_is_omap1()) {
58 printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n", 58 printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
59 index); 59 index);
60 WARN_ON(1); 60 WARN_ON(1);
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index 186bca82cfa..e129ce80c53 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -34,11 +34,11 @@ struct omap_opp *l3_opps;
34 * Device-driver-originated constraints (via board-*.c files) 34 * Device-driver-originated constraints (via board-*.c files)
35 */ 35 */
36 36
37void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) 37int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
38{ 38{
39 if (!dev || t < -1) { 39 if (!dev || t < -1) {
40 WARN_ON(1); 40 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
41 return; 41 return -EINVAL;
42 }; 42 };
43 43
44 if (t == -1) 44 if (t == -1)
@@ -58,14 +58,16 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
58 * 58 *
59 * TI CDP code can call constraint_set here. 59 * TI CDP code can call constraint_set here.
60 */ 60 */
61
62 return 0;
61} 63}
62 64
63void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) 65int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
64{ 66{
65 if (!dev || (agent_id != OCP_INITIATOR_AGENT && 67 if (!dev || (agent_id != OCP_INITIATOR_AGENT &&
66 agent_id != OCP_TARGET_AGENT)) { 68 agent_id != OCP_TARGET_AGENT)) {
67 WARN_ON(1); 69 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
68 return; 70 return -EINVAL;
69 }; 71 };
70 72
71 if (r == 0) 73 if (r == 0)
@@ -83,13 +85,16 @@ void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
83 * 85 *
84 * TI CDP code can call constraint_set here on the VDD2 OPP. 86 * TI CDP code can call constraint_set here on the VDD2 OPP.
85 */ 87 */
88
89 return 0;
86} 90}
87 91
88void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t) 92int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
93 long t)
89{ 94{
90 if (!dev || t < -1) { 95 if (!req_dev || !dev || t < -1) {
91 WARN_ON(1); 96 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
92 return; 97 return -EINVAL;
93 }; 98 };
94 99
95 if (t == -1) 100 if (t == -1)
@@ -111,13 +116,15 @@ void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t)
111 * 116 *
112 * TI CDP code can call constraint_set here. 117 * TI CDP code can call constraint_set here.
113 */ 118 */
119
120 return 0;
114} 121}
115 122
116void omap_pm_set_max_sdma_lat(struct device *dev, long t) 123int omap_pm_set_max_sdma_lat(struct device *dev, long t)
117{ 124{
118 if (!dev || t < -1) { 125 if (!dev || t < -1) {
119 WARN_ON(1); 126 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
120 return; 127 return -EINVAL;
121 }; 128 };
122 129
123 if (t == -1) 130 if (t == -1)
@@ -139,8 +146,36 @@ void omap_pm_set_max_sdma_lat(struct device *dev, long t)
139 * TI CDP code can call constraint_set here. 146 * TI CDP code can call constraint_set here.
140 */ 147 */
141 148
149 return 0;
142} 150}
143 151
152int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
153{
154 if (!dev || !c || r < 0) {
155 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
156 return -EINVAL;
157 }
158
159 if (r == 0)
160 pr_debug("OMAP PM: remove min clk rate constraint: "
161 "dev %s\n", dev_name(dev));
162 else
163 pr_debug("OMAP PM: add min clk rate constraint: "
164 "dev %s, rate = %ld Hz\n", dev_name(dev), r);
165
166 /*
167 * Code in a real implementation should keep track of these
168 * constraints on the clock, and determine the highest minimum
169 * clock rate. It should iterate over each OPP and determine
170 * whether the OPP will result in a clock rate that would
171 * satisfy this constraint (and any other PM constraint in effect
172 * at that time). Once it finds the lowest-voltage OPP that
173 * meets those conditions, it should switch to it, or return
174 * an error if the code is not capable of doing so.
175 */
176
177 return 0;
178}
144 179
145/* 180/*
146 * DSP Bridge-specific constraints 181 * DSP Bridge-specific constraints
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index f899603051a..d2b160942cc 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_device implementation 2 * omap_device implementation
3 * 3 *
4 * Copyright (C) 2009 Nokia Corporation 4 * Copyright (C) 2009-2010 Nokia Corporation
5 * Paul Walmsley, Kevin Hilman 5 * Paul Walmsley, Kevin Hilman
6 * 6 *
7 * Developed in collaboration with (alphabetical order): Benoit 7 * Developed in collaboration with (alphabetical order): Benoit
@@ -90,8 +90,11 @@
90#define USE_WAKEUP_LAT 0 90#define USE_WAKEUP_LAT 0
91#define IGNORE_WAKEUP_LAT 1 91#define IGNORE_WAKEUP_LAT 1
92 92
93 93/*
94#define OMAP_DEVICE_MAGIC 0xf00dcafe 94 * OMAP_DEVICE_MAGIC: used to determine whether a struct omap_device
95 * obtained via container_of() is in fact a struct omap_device
96 */
97#define OMAP_DEVICE_MAGIC 0xf00dcafe
95 98
96/* Private functions */ 99/* Private functions */
97 100
@@ -359,7 +362,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
359 struct omap_device *od; 362 struct omap_device *od;
360 char *pdev_name2; 363 char *pdev_name2;
361 struct resource *res = NULL; 364 struct resource *res = NULL;
362 int res_count; 365 int i, res_count;
363 struct omap_hwmod **hwmods; 366 struct omap_hwmod **hwmods;
364 367
365 if (!ohs || oh_cnt == 0 || !pdev_name) 368 if (!ohs || oh_cnt == 0 || !pdev_name)
@@ -404,7 +407,9 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
404 od->pdev.num_resources = res_count; 407 od->pdev.num_resources = res_count;
405 od->pdev.resource = res; 408 od->pdev.resource = res;
406 409
407 platform_device_add_data(&od->pdev, pdata, pdata_len); 410 ret = platform_device_add_data(&od->pdev, pdata, pdata_len);
411 if (ret)
412 goto odbs_exit4;
408 413
409 od->pm_lats = pm_lats; 414 od->pm_lats = pm_lats;
410 od->pm_lats_cnt = pm_lats_cnt; 415 od->pm_lats_cnt = pm_lats_cnt;
@@ -416,6 +421,9 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
416 else 421 else
417 ret = omap_device_register(od); 422 ret = omap_device_register(od);
418 423
424 for (i = 0; i < oh_cnt; i++)
425 hwmods[i]->od = od;
426
419 if (ret) 427 if (ret)
420 goto odbs_exit4; 428 goto odbs_exit4;
421 429
@@ -652,6 +660,25 @@ struct powerdomain *omap_device_get_pwrdm(struct omap_device *od)
652 return omap_hwmod_get_pwrdm(od->hwmods[0]); 660 return omap_hwmod_get_pwrdm(od->hwmods[0]);
653} 661}
654 662
663/**
664 * omap_device_get_mpu_rt_va - return the MPU's virtual addr for the hwmod base
665 * @od: struct omap_device *
666 *
667 * Return the MPU's virtual address for the base of the hwmod, from
668 * the ioremap() that the hwmod code does. Only valid if there is one
669 * hwmod associated with this device. Returns NULL if there are zero
670 * or more than one hwmods associated with this omap_device;
671 * otherwise, passes along the return value from
672 * omap_hwmod_get_mpu_rt_va().
673 */
674void __iomem *omap_device_get_rt_va(struct omap_device *od)
675{
676 if (od->hwmods_cnt != 1)
677 return NULL;
678
679 return omap_hwmod_get_mpu_rt_va(od->hwmods[0]);
680}
681
655/* 682/*
656 * Public functions intended for use in omap_device_pm_latency 683 * Public functions intended for use in omap_device_pm_latency
657 * .activate_func and .deactivate_func function pointers 684 * .activate_func and .deactivate_func function pointers
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index d3bf17cd36f..f3570884883 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -22,524 +22,13 @@
22 22
23#include <linux/module.h> 23#include <linux/module.h>
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/types.h>
26#include <linux/errno.h>
27#include <linux/init.h> 25#include <linux/init.h>
28#include <linux/platform_device.h> 26#include <linux/platform_device.h>
29#include <linux/usb/otg.h>
30#include <linux/io.h> 27#include <linux/io.h>
31 28
32#include <asm/irq.h>
33#include <asm/system.h>
34#include <mach/hardware.h>
35
36#include <plat/control.h>
37#include <plat/mux.h>
38#include <plat/usb.h> 29#include <plat/usb.h>
39#include <plat/board.h> 30#include <plat/board.h>
40 31
41#ifdef CONFIG_ARCH_OMAP1
42
43#define INT_USB_IRQ_GEN IH2_BASE + 20
44#define INT_USB_IRQ_NISO IH2_BASE + 30
45#define INT_USB_IRQ_ISO IH2_BASE + 29
46#define INT_USB_IRQ_HGEN INT_USB_HHC_1
47#define INT_USB_IRQ_OTG IH2_BASE + 8
48
49#else
50
51#define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN
52#define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO
53#define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO
54#define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN
55#define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG
56
57#endif
58
59
60/* These routines should handle the standard chip-specific modes
61 * for usb0/1/2 ports, covering basic mux and transceiver setup.
62 *
63 * Some board-*.c files will need to set up additional mux options,
64 * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup.
65 */
66
67/* TESTED ON:
68 * - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables
69 * - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables
70 * - 5912 OSK UDC, with *nonstandard* A-to-A cable
71 * - 1510 Innovator UDC with bundled usb0 cable
72 * - 1510 Innovator OHCI with bundled usb1/usb2 cable
73 * - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS
74 * - 1710 custom development board using alternate pin group
75 * - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables
76 */
77
78/*-------------------------------------------------------------------------*/
79
80#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
81
82static void omap2_usb_devconf_clear(u8 port, u32 mask)
83{
84 u32 r;
85
86 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
87 r &= ~USBTXWRMODEI(port, mask);
88 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
89}
90
91static void omap2_usb_devconf_set(u8 port, u32 mask)
92{
93 u32 r;
94
95 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
96 r |= USBTXWRMODEI(port, mask);
97 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
98}
99
100static void omap2_usb2_disable_5pinbitll(void)
101{
102 u32 r;
103
104 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
105 r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
106 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
107}
108
109static void omap2_usb2_enable_5pinunitll(void)
110{
111 u32 r;
112
113 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
114 r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
115 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
116}
117
118static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
119{
120 u32 syscon1 = 0;
121
122 if (cpu_is_omap24xx())
123 omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
124
125 if (nwires == 0) {
126 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
127 u32 l;
128
129 /* pulldown D+/D- */
130 l = omap_readl(USB_TRANSCEIVER_CTRL);
131 l &= ~(3 << 1);
132 omap_writel(l, USB_TRANSCEIVER_CTRL);
133 }
134 return 0;
135 }
136
137 if (is_device) {
138 if (cpu_is_omap24xx())
139 omap_cfg_reg(J20_24XX_USB0_PUEN);
140 else if (cpu_is_omap7xx()) {
141 omap_cfg_reg(AA17_7XX_USB_DM);
142 omap_cfg_reg(W16_7XX_USB_PU_EN);
143 omap_cfg_reg(W17_7XX_USB_VBUSI);
144 omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
145 omap_cfg_reg(W19_7XX_USB_DCRST);
146 } else
147 omap_cfg_reg(W4_USB_PUEN);
148 }
149
150 /* internal transceiver (unavailable on 17xx, 24xx) */
151 if (!cpu_class_is_omap2() && nwires == 2) {
152 u32 l;
153
154 // omap_cfg_reg(P9_USB_DP);
155 // omap_cfg_reg(R8_USB_DM);
156
157 if (cpu_is_omap15xx()) {
158 /* This works on 1510-Innovator */
159 return 0;
160 }
161
162 /* NOTES:
163 * - peripheral should configure VBUS detection!
164 * - only peripherals may use the internal D+/D- pulldowns
165 * - OTG support on this port not yet written
166 */
167
168 /* Don't do this for omap7xx -- it causes USB to not work correctly */
169 if (!cpu_is_omap7xx()) {
170 l = omap_readl(USB_TRANSCEIVER_CTRL);
171 l &= ~(7 << 4);
172 if (!is_device)
173 l |= (3 << 1);
174 omap_writel(l, USB_TRANSCEIVER_CTRL);
175 }
176
177 return 3 << 16;
178 }
179
180 /* alternate pin config, external transceiver */
181 if (cpu_is_omap15xx()) {
182 printk(KERN_ERR "no usb0 alt pin config on 15xx\n");
183 return 0;
184 }
185
186 if (cpu_is_omap24xx()) {
187 omap_cfg_reg(K18_24XX_USB0_DAT);
188 omap_cfg_reg(K19_24XX_USB0_TXEN);
189 omap_cfg_reg(J14_24XX_USB0_SE0);
190 if (nwires != 3)
191 omap_cfg_reg(J18_24XX_USB0_RCV);
192 } else {
193 omap_cfg_reg(V6_USB0_TXD);
194 omap_cfg_reg(W9_USB0_TXEN);
195 omap_cfg_reg(W5_USB0_SE0);
196 if (nwires != 3)
197 omap_cfg_reg(Y5_USB0_RCV);
198 }
199
200 /* NOTE: SPEED and SUSP aren't configured here. OTG hosts
201 * may be able to use I2C requests to set those bits along
202 * with VBUS switching and overcurrent detection.
203 */
204
205 if (cpu_class_is_omap1() && nwires != 6) {
206 u32 l;
207
208 l = omap_readl(USB_TRANSCEIVER_CTRL);
209 l &= ~CONF_USB2_UNI_R;
210 omap_writel(l, USB_TRANSCEIVER_CTRL);
211 }
212
213 switch (nwires) {
214 case 3:
215 syscon1 = 2;
216 if (cpu_is_omap24xx())
217 omap2_usb_devconf_set(0, USB_BIDIR);
218 break;
219 case 4:
220 syscon1 = 1;
221 if (cpu_is_omap24xx())
222 omap2_usb_devconf_set(0, USB_BIDIR);
223 break;
224 case 6:
225 syscon1 = 3;
226 if (cpu_is_omap24xx()) {
227 omap_cfg_reg(J19_24XX_USB0_VP);
228 omap_cfg_reg(K20_24XX_USB0_VM);
229 omap2_usb_devconf_set(0, USB_UNIDIR);
230 } else {
231 u32 l;
232
233 omap_cfg_reg(AA9_USB0_VP);
234 omap_cfg_reg(R9_USB0_VM);
235 l = omap_readl(USB_TRANSCEIVER_CTRL);
236 l |= CONF_USB2_UNI_R;
237 omap_writel(l, USB_TRANSCEIVER_CTRL);
238 }
239 break;
240 default:
241 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
242 0, nwires);
243 }
244 return syscon1 << 16;
245}
246
247static u32 __init omap_usb1_init(unsigned nwires)
248{
249 u32 syscon1 = 0;
250
251 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
252 u32 l;
253
254 l = omap_readl(USB_TRANSCEIVER_CTRL);
255 l &= ~CONF_USB1_UNI_R;
256 omap_writel(l, USB_TRANSCEIVER_CTRL);
257 }
258 if (cpu_is_omap24xx())
259 omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
260
261 if (nwires == 0)
262 return 0;
263
264 /* external transceiver */
265 if (cpu_class_is_omap1()) {
266 omap_cfg_reg(USB1_TXD);
267 omap_cfg_reg(USB1_TXEN);
268 if (nwires != 3)
269 omap_cfg_reg(USB1_RCV);
270 }
271
272 if (cpu_is_omap15xx()) {
273 omap_cfg_reg(USB1_SEO);
274 omap_cfg_reg(USB1_SPEED);
275 // SUSP
276 } else if (cpu_is_omap1610() || cpu_is_omap5912()) {
277 omap_cfg_reg(W13_1610_USB1_SE0);
278 omap_cfg_reg(R13_1610_USB1_SPEED);
279 // SUSP
280 } else if (cpu_is_omap1710()) {
281 omap_cfg_reg(R13_1710_USB1_SE0);
282 // SUSP
283 } else if (cpu_is_omap24xx()) {
284 /* NOTE: board-specific code must set up pin muxing for usb1,
285 * since each signal could come out on either of two balls.
286 */
287 } else {
288 pr_debug("usb%d cpu unrecognized\n", 1);
289 return 0;
290 }
291
292 switch (nwires) {
293 case 2:
294 if (!cpu_is_omap24xx())
295 goto bad;
296 /* NOTE: board-specific code must override this setting if
297 * this TLL link is not using DP/DM
298 */
299 syscon1 = 1;
300 omap2_usb_devconf_set(1, USB_BIDIR_TLL);
301 break;
302 case 3:
303 syscon1 = 2;
304 if (cpu_is_omap24xx())
305 omap2_usb_devconf_set(1, USB_BIDIR);
306 break;
307 case 4:
308 syscon1 = 1;
309 if (cpu_is_omap24xx())
310 omap2_usb_devconf_set(1, USB_BIDIR);
311 break;
312 case 6:
313 if (cpu_is_omap24xx())
314 goto bad;
315 syscon1 = 3;
316 omap_cfg_reg(USB1_VP);
317 omap_cfg_reg(USB1_VM);
318 if (!cpu_is_omap15xx()) {
319 u32 l;
320
321 l = omap_readl(USB_TRANSCEIVER_CTRL);
322 l |= CONF_USB1_UNI_R;
323 omap_writel(l, USB_TRANSCEIVER_CTRL);
324 }
325 break;
326 default:
327bad:
328 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
329 1, nwires);
330 }
331 return syscon1 << 20;
332}
333
334static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
335{
336 u32 syscon1 = 0;
337
338 if (cpu_is_omap24xx()) {
339 omap2_usb2_disable_5pinbitll();
340 alt_pingroup = 0;
341 }
342
343 /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
344 if (alt_pingroup || nwires == 0)
345 return 0;
346
347 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
348 u32 l;
349
350 l = omap_readl(USB_TRANSCEIVER_CTRL);
351 l &= ~CONF_USB2_UNI_R;
352 omap_writel(l, USB_TRANSCEIVER_CTRL);
353 }
354
355 /* external transceiver */
356 if (cpu_is_omap15xx()) {
357 omap_cfg_reg(USB2_TXD);
358 omap_cfg_reg(USB2_TXEN);
359 omap_cfg_reg(USB2_SEO);
360 if (nwires != 3)
361 omap_cfg_reg(USB2_RCV);
362 /* there is no USB2_SPEED */
363 } else if (cpu_is_omap16xx()) {
364 omap_cfg_reg(V6_USB2_TXD);
365 omap_cfg_reg(W9_USB2_TXEN);
366 omap_cfg_reg(W5_USB2_SE0);
367 if (nwires != 3)
368 omap_cfg_reg(Y5_USB2_RCV);
369 // FIXME omap_cfg_reg(USB2_SPEED);
370 } else if (cpu_is_omap24xx()) {
371 omap_cfg_reg(Y11_24XX_USB2_DAT);
372 omap_cfg_reg(AA10_24XX_USB2_SE0);
373 if (nwires > 2)
374 omap_cfg_reg(AA12_24XX_USB2_TXEN);
375 if (nwires > 3)
376 omap_cfg_reg(AA6_24XX_USB2_RCV);
377 } else {
378 pr_debug("usb%d cpu unrecognized\n", 1);
379 return 0;
380 }
381 // if (cpu_class_is_omap1()) omap_cfg_reg(USB2_SUSP);
382
383 switch (nwires) {
384 case 2:
385 if (!cpu_is_omap24xx())
386 goto bad;
387 /* NOTE: board-specific code must override this setting if
388 * this TLL link is not using DP/DM
389 */
390 syscon1 = 1;
391 omap2_usb_devconf_set(2, USB_BIDIR_TLL);
392 break;
393 case 3:
394 syscon1 = 2;
395 if (cpu_is_omap24xx())
396 omap2_usb_devconf_set(2, USB_BIDIR);
397 break;
398 case 4:
399 syscon1 = 1;
400 if (cpu_is_omap24xx())
401 omap2_usb_devconf_set(2, USB_BIDIR);
402 break;
403 case 5:
404 if (!cpu_is_omap24xx())
405 goto bad;
406 omap_cfg_reg(AA4_24XX_USB2_TLLSE0);
407 /* NOTE: board-specific code must override this setting if
408 * this TLL link is not using DP/DM. Something must also
409 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
410 */
411 syscon1 = 3;
412 omap2_usb2_enable_5pinunitll();
413 break;
414 case 6:
415 if (cpu_is_omap24xx())
416 goto bad;
417 syscon1 = 3;
418 if (cpu_is_omap15xx()) {
419 omap_cfg_reg(USB2_VP);
420 omap_cfg_reg(USB2_VM);
421 } else {
422 u32 l;
423
424 omap_cfg_reg(AA9_USB2_VP);
425 omap_cfg_reg(R9_USB2_VM);
426 l = omap_readl(USB_TRANSCEIVER_CTRL);
427 l |= CONF_USB2_UNI_R;
428 omap_writel(l, USB_TRANSCEIVER_CTRL);
429 }
430 break;
431 default:
432bad:
433 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
434 2, nwires);
435 }
436 return syscon1 << 24;
437}
438
439#endif
440
441/*-------------------------------------------------------------------------*/
442
443#ifdef CONFIG_USB_GADGET_OMAP
444
445static struct resource udc_resources[] = {
446 /* order is significant! */
447 { /* registers */
448 .start = UDC_BASE,
449 .end = UDC_BASE + 0xff,
450 .flags = IORESOURCE_MEM,
451 }, { /* general IRQ */
452 .start = INT_USB_IRQ_GEN,
453 .flags = IORESOURCE_IRQ,
454 }, { /* PIO IRQ */
455 .start = INT_USB_IRQ_NISO,
456 .flags = IORESOURCE_IRQ,
457 }, { /* SOF IRQ */
458 .start = INT_USB_IRQ_ISO,
459 .flags = IORESOURCE_IRQ,
460 },
461};
462
463static u64 udc_dmamask = ~(u32)0;
464
465static struct platform_device udc_device = {
466 .name = "omap_udc",
467 .id = -1,
468 .dev = {
469 .dma_mask = &udc_dmamask,
470 .coherent_dma_mask = 0xffffffff,
471 },
472 .num_resources = ARRAY_SIZE(udc_resources),
473 .resource = udc_resources,
474};
475
476#endif
477
478#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
479
480/* The dmamask must be set for OHCI to work */
481static u64 ohci_dmamask = ~(u32)0;
482
483static struct resource ohci_resources[] = {
484 {
485 .start = OMAP_OHCI_BASE,
486 .end = OMAP_OHCI_BASE + 0xff,
487 .flags = IORESOURCE_MEM,
488 },
489 {
490 .start = INT_USB_IRQ_HGEN,
491 .flags = IORESOURCE_IRQ,
492 },
493};
494
495static struct platform_device ohci_device = {
496 .name = "ohci",
497 .id = -1,
498 .dev = {
499 .dma_mask = &ohci_dmamask,
500 .coherent_dma_mask = 0xffffffff,
501 },
502 .num_resources = ARRAY_SIZE(ohci_resources),
503 .resource = ohci_resources,
504};
505
506#endif
507
508#if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
509
510static struct resource otg_resources[] = {
511 /* order is significant! */
512 {
513 .start = OTG_BASE,
514 .end = OTG_BASE + 0xff,
515 .flags = IORESOURCE_MEM,
516 }, {
517 .start = INT_USB_IRQ_OTG,
518 .flags = IORESOURCE_IRQ,
519 },
520};
521
522static struct platform_device otg_device = {
523 .name = "omap_otg",
524 .id = -1,
525 .num_resources = ARRAY_SIZE(otg_resources),
526 .resource = otg_resources,
527};
528
529#endif
530
531/*-------------------------------------------------------------------------*/
532
533// FIXME correct answer depends on hmc_mode,
534// as does (on omap1) any nonzero value for config->otg port number
535#ifdef CONFIG_USB_GADGET_OMAP
536#define is_usb0_device(config) 1
537#else
538#define is_usb0_device(config) 0
539#endif
540
541/*-------------------------------------------------------------------------*/
542
543#ifdef CONFIG_ARCH_OMAP_OTG 32#ifdef CONFIG_ARCH_OMAP_OTG
544 33
545void __init 34void __init
@@ -560,9 +49,9 @@ omap_otg_init(struct omap_usb_config *config)
560 /* pin muxing and transceiver pinouts */ 49 /* pin muxing and transceiver pinouts */
561 if (config->pins[0] > 2) /* alt pingroup 2 */ 50 if (config->pins[0] > 2) /* alt pingroup 2 */
562 alt_pingroup = 1; 51 alt_pingroup = 1;
563 syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config)); 52 syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
564 syscon |= omap_usb1_init(config->pins[1]); 53 syscon |= config->usb1_init(config->pins[1]);
565 syscon |= omap_usb2_init(config->pins[2], alt_pingroup); 54 syscon |= config->usb2_init(config->pins[2], alt_pingroup);
566 pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); 55 pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
567 omap_writel(syscon, OTG_SYSCON_1); 56 omap_writel(syscon, OTG_SYSCON_1);
568 57
@@ -610,15 +99,11 @@ omap_otg_init(struct omap_usb_config *config)
610 99
611#ifdef CONFIG_USB_GADGET_OMAP 100#ifdef CONFIG_USB_GADGET_OMAP
612 if (config->otg || config->register_dev) { 101 if (config->otg || config->register_dev) {
102 struct platform_device *udc_device = config->udc_device;
103
613 syscon &= ~DEV_IDLE_EN; 104 syscon &= ~DEV_IDLE_EN;
614 udc_device.dev.platform_data = config; 105 udc_device->dev.platform_data = config;
615 /* IRQ numbers for omap7xx */ 106 status = platform_device_register(udc_device);
616 if(cpu_is_omap7xx()) {
617 udc_resources[1].start = INT_7XX_USB_GENI;
618 udc_resources[2].start = INT_7XX_USB_NON_ISO;
619 udc_resources[3].start = INT_7XX_USB_ISO;
620 }
621 status = platform_device_register(&udc_device);
622 if (status) 107 if (status)
623 pr_debug("can't register UDC device, %d\n", status); 108 pr_debug("can't register UDC device, %d\n", status);
624 } 109 }
@@ -626,11 +111,11 @@ omap_otg_init(struct omap_usb_config *config)
626 111
627#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 112#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
628 if (config->otg || config->register_host) { 113 if (config->otg || config->register_host) {
114 struct platform_device *ohci_device = config->ohci_device;
115
629 syscon &= ~HST_IDLE_EN; 116 syscon &= ~HST_IDLE_EN;
630 ohci_device.dev.platform_data = config; 117 ohci_device->dev.platform_data = config;
631 if (cpu_is_omap7xx()) 118 status = platform_device_register(ohci_device);
632 ohci_resources[1].start = INT_7XX_USB_HHC_1;
633 status = platform_device_register(&ohci_device);
634 if (status) 119 if (status)
635 pr_debug("can't register OHCI device, %d\n", status); 120 pr_debug("can't register OHCI device, %d\n", status);
636 } 121 }
@@ -638,11 +123,11 @@ omap_otg_init(struct omap_usb_config *config)
638 123
639#ifdef CONFIG_USB_OTG 124#ifdef CONFIG_USB_OTG
640 if (config->otg) { 125 if (config->otg) {
126 struct platform_device *otg_device = config->otg_device;
127
641 syscon &= ~OTG_IDLE_EN; 128 syscon &= ~OTG_IDLE_EN;
642 otg_device.dev.platform_data = config; 129 otg_device->dev.platform_data = config;
643 if (cpu_is_omap7xx()) 130 status = platform_device_register(otg_device);
644 otg_resources[1].start = INT_7XX_USB_OTG;
645 status = platform_device_register(&otg_device);
646 if (status) 131 if (status)
647 pr_debug("can't register OTG device, %d\n", status); 132 pr_debug("can't register OTG device, %d\n", status);
648 } 133 }
@@ -654,102 +139,5 @@ omap_otg_init(struct omap_usb_config *config)
654} 139}
655 140
656#else 141#else
657static inline void omap_otg_init(struct omap_usb_config *config) {} 142void omap_otg_init(struct omap_usb_config *config) {}
658#endif
659
660/*-------------------------------------------------------------------------*/
661
662#ifdef CONFIG_ARCH_OMAP15XX
663
664/* ULPD_DPLL_CTRL */
665#define DPLL_IOB (1 << 13)
666#define DPLL_PLL_ENABLE (1 << 4)
667#define DPLL_LOCK (1 << 0)
668
669/* ULPD_APLL_CTRL */
670#define APLL_NDPLL_SWITCH (1 << 0)
671
672
673static void __init omap_1510_usb_init(struct omap_usb_config *config)
674{
675 unsigned int val;
676 u16 w;
677
678 omap_usb0_init(config->pins[0], is_usb0_device(config));
679 omap_usb1_init(config->pins[1]);
680 omap_usb2_init(config->pins[2], 0);
681
682 val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
683 val |= (config->hmc_mode << 1);
684 omap_writel(val, MOD_CONF_CTRL_0);
685
686 printk("USB: hmc %d", config->hmc_mode);
687 if (config->pins[0])
688 printk(", usb0 %d wires%s", config->pins[0],
689 is_usb0_device(config) ? " (dev)" : "");
690 if (config->pins[1])
691 printk(", usb1 %d wires", config->pins[1]);
692 if (config->pins[2])
693 printk(", usb2 %d wires", config->pins[2]);
694 printk("\n");
695
696 /* use DPLL for 48 MHz function clock */
697 pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
698 omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
699
700 w = omap_readw(ULPD_APLL_CTRL);
701 w &= ~APLL_NDPLL_SWITCH;
702 omap_writew(w, ULPD_APLL_CTRL);
703
704 w = omap_readw(ULPD_DPLL_CTRL);
705 w |= DPLL_IOB | DPLL_PLL_ENABLE;
706 omap_writew(w, ULPD_DPLL_CTRL);
707
708 w = omap_readw(ULPD_SOFT_REQ);
709 w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
710 omap_writew(w, ULPD_SOFT_REQ);
711
712 while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
713 cpu_relax();
714
715#ifdef CONFIG_USB_GADGET_OMAP
716 if (config->register_dev) {
717 int status;
718
719 udc_device.dev.platform_data = config;
720 status = platform_device_register(&udc_device);
721 if (status)
722 pr_debug("can't register UDC device, %d\n", status);
723 /* udc driver gates 48MHz by D+ pullup */
724 }
725#endif
726
727#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
728 if (config->register_host) {
729 int status;
730
731 ohci_device.dev.platform_data = config;
732 status = platform_device_register(&ohci_device);
733 if (status)
734 pr_debug("can't register OHCI device, %d\n", status);
735 /* hcd explicitly gates 48MHz */
736 }
737#endif
738}
739
740#else
741static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
742#endif 143#endif
743
744/*-------------------------------------------------------------------------*/
745
746void __init omap_usb_init(struct omap_usb_config *pdata)
747{
748 if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx())
749 omap_otg_init(pdata);
750 else if (cpu_is_omap15xx())
751 omap_1510_usb_init(pdata);
752 else
753 printk(KERN_ERR "USB: No init for your chip yet\n");
754}
755