Patched in Tegra support.

5 files changed, 719 insertions, 207 deletions

diff --git a/arch/arm/plat-omap/include/plat/counter-32k.h b/arch/arm/plat-omap/include/plat/counter-32k.h
deleted file mode 100644
index da000d482ff..00000000000
--- a/arch/arm/plat-omap/include/plat/counter-32k.h
+++ /dev/null
@@ -1 +0,0 @@
-int omap_init_clocksource_32k(void __iomem *vbase);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index c9a66bf36c9..67b3d75884c 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -1,4 +1,6 @@
 /*
+ * arch/arm/plat-omap/include/mach/cpu.h
+ *
  * OMAP cpu type detection
  *
  * Copyright (C) 2004, 2008 Nokia Corporation
@@ -7,7 +9,7 @@
  *
  * Written by Tony Lindgren <tony.lindgren@nokia.com>
  *
- * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,8 +30,497 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
 
-#ifdef CONFIG_ARCH_OMAP1
-#include <mach/soc.h>
+#include <linux/bitops.h>
+#include <plat/multi.h>
+
+/*
+ * Omap device type i.e. EMU/HS/TST/GP/BAD
+ */
+#define OMAP2_DEVICE_TYPE_TEST          0
+#define OMAP2_DEVICE_TYPE_EMU           1
+#define OMAP2_DEVICE_TYPE_SEC           2
+#define OMAP2_DEVICE_TYPE_GP            3
+#define OMAP2_DEVICE_TYPE_BAD           4
+
+int omap_type(void);
+
+struct omap_chip_id {
+        u16 oc;
+        u8 type;
+};
+
+#define OMAP_CHIP_INIT(x)       { .oc = x }
+
+/*
+ * omap_rev bits:
+ * CPU id bits  (0730, 1510, 1710, 2422...)     [31:16]
+ * CPU revision (See _REV_ defined in cpu.h)    [15:08]
+ * CPU class bits (15xx, 16xx, 24xx, 34xx...)   [07:00]
+ */
+unsigned int omap_rev(void);
+
+/*
+ * Define CPU revision bits
+ *
+ * Verbose meaning of the revision bits may be different for a silicon
+ * family. This difference can be handled separately.
+ */
+#define OMAP_REVBITS_00         0x00
+#define OMAP_REVBITS_01         0x01
+#define OMAP_REVBITS_02         0x02
+#define OMAP_REVBITS_03         0x03
+#define OMAP_REVBITS_04         0x04
+#define OMAP_REVBITS_05         0x05
+
+/*
+ * Get the CPU revision for OMAP devices
+ */
+#define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
+
+/*
+ * Macros to group OMAP into cpu classes.
+ * These can be used in most places.
+ * cpu_is_omap7xx():    True for OMAP730, OMAP850
+ * cpu_is_omap15xx():   True for OMAP1510, OMAP5910 and OMAP310
+ * cpu_is_omap16xx():   True for OMAP1610, OMAP5912 and OMAP1710
+ * cpu_is_omap24xx():   True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
+ * cpu_is_omap242x():   True for OMAP2420, OMAP2422, OMAP2423
+ * cpu_is_omap243x():   True for OMAP2430
+ * cpu_is_omap343x():   True for OMAP3430
+ * cpu_is_omap443x():   True for OMAP4430
+ * cpu_is_omap446x():   True for OMAP4460
+ */
+#define GET_OMAP_CLASS  (omap_rev() & 0xff)
+
+#define IS_OMAP_CLASS(class, id)                        \
+static inline int is_omap ##class (void)                \
+{                                                       \
+        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
+}
+
+#define GET_OMAP_SUBCLASS       ((omap_rev() >> 20) & 0x0fff)
+
+#define IS_OMAP_SUBCLASS(subclass, id)                  \
+static inline int is_omap ##subclass (void)             \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+
+#define IS_TI_SUBCLASS(subclass, id)                    \
+static inline int is_ti ##subclass (void)               \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+
+IS_OMAP_CLASS(7xx, 0x07)
+IS_OMAP_CLASS(15xx, 0x15)
+IS_OMAP_CLASS(16xx, 0x16)
+IS_OMAP_CLASS(24xx, 0x24)
+IS_OMAP_CLASS(34xx, 0x34)
+IS_OMAP_CLASS(44xx, 0x44)
+
+IS_OMAP_SUBCLASS(242x, 0x242)
+IS_OMAP_SUBCLASS(243x, 0x243)
+IS_OMAP_SUBCLASS(343x, 0x343)
+IS_OMAP_SUBCLASS(363x, 0x363)
+IS_OMAP_SUBCLASS(443x, 0x443)
+IS_OMAP_SUBCLASS(446x, 0x446)
+
+IS_TI_SUBCLASS(816x, 0x816)
+
+#define cpu_is_omap7xx()                0
+#define cpu_is_omap15xx()               0
+#define cpu_is_omap16xx()               0
+#define cpu_is_omap24xx()               0
+#define cpu_is_omap242x()               0
+#define cpu_is_omap243x()               0
+#define cpu_is_omap34xx()               0
+#define cpu_is_omap343x()               0
+#define cpu_is_ti816x()                 0
+#define cpu_is_omap44xx()               0
+#define cpu_is_omap443x()               0
+#define cpu_is_omap446x()               0
+
+#if defined(MULTI_OMAP1)
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              is_omap7xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP850)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              is_omap7xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP15XX)
+#  undef  cpu_is_omap15xx
+#  define cpu_is_omap15xx()             is_omap15xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  undef  cpu_is_omap16xx
+#  define cpu_is_omap16xx()             is_omap16xx()
+# endif
+#else
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              1
+# endif
+# if defined(CONFIG_ARCH_OMAP850)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              1
+# endif
+# if defined(CONFIG_ARCH_OMAP15XX)
+#  undef  cpu_is_omap15xx
+#  define cpu_is_omap15xx()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  undef  cpu_is_omap16xx
+#  define cpu_is_omap16xx()             1
+# endif
+#endif
+
+#if defined(MULTI_OMAP2)
+# if defined(CONFIG_ARCH_OMAP2)
+#  undef  cpu_is_omap24xx
+#  define cpu_is_omap24xx()             is_omap24xx()
+# endif
+# if defined (CONFIG_SOC_OMAP2420)
+#  undef  cpu_is_omap242x
+#  define cpu_is_omap242x()             is_omap242x()
+# endif
+# if defined (CONFIG_SOC_OMAP2430)
+#  undef  cpu_is_omap243x
+#  define cpu_is_omap243x()             is_omap243x()
+# endif
+# if defined(CONFIG_ARCH_OMAP3)
+#  undef  cpu_is_omap34xx
+#  undef  cpu_is_omap343x
+#  define cpu_is_omap34xx()             is_omap34xx()
+#  define cpu_is_omap343x()             is_omap343x()
+# endif
+#else
+# if defined(CONFIG_ARCH_OMAP2)
+#  undef  cpu_is_omap24xx
+#  define cpu_is_omap24xx()             1
+# endif
+# if defined(CONFIG_SOC_OMAP2420)
+#  undef  cpu_is_omap242x
+#  define cpu_is_omap242x()             1
+# endif
+# if defined(CONFIG_SOC_OMAP2430)
+#  undef  cpu_is_omap243x
+#  define cpu_is_omap243x()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP3)
+#  undef  cpu_is_omap34xx
+#  define cpu_is_omap34xx()             1
+# endif
+# if defined(CONFIG_SOC_OMAP3430)
+#  undef  cpu_is_omap343x
+#  define cpu_is_omap343x()             1
+# endif
+#endif
+
+/*
+ * Macros to detect individual cpu types.
+ * These are only rarely needed.
+ * cpu_is_omap330():    True for OMAP330
+ * cpu_is_omap730():    True for OMAP730
+ * cpu_is_omap850():    True for OMAP850
+ * cpu_is_omap1510():   True for OMAP1510
+ * cpu_is_omap1610():   True for OMAP1610
+ * cpu_is_omap1611():   True for OMAP1611
+ * cpu_is_omap5912():   True for OMAP5912
+ * cpu_is_omap1621():   True for OMAP1621
+ * cpu_is_omap1710():   True for OMAP1710
+ * cpu_is_omap2420():   True for OMAP2420
+ * cpu_is_omap2422():   True for OMAP2422
+ * cpu_is_omap2423():   True for OMAP2423
+ * cpu_is_omap2430():   True for OMAP2430
+ * cpu_is_omap3430():   True for OMAP3430
+ * cpu_is_omap4430():   True for OMAP4430
+ * cpu_is_omap3505():   True for OMAP3505
+ * cpu_is_omap3517():   True for OMAP3517
+ */
+#define GET_OMAP_TYPE   ((omap_rev() >> 16) & 0xffff)
+
+#define IS_OMAP_TYPE(type, id)                          \
+static inline int is_omap ##type (void)                 \
+{                                                       \
+        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
+}
+
+IS_OMAP_TYPE(310, 0x0310)
+IS_OMAP_TYPE(730, 0x0730)
+IS_OMAP_TYPE(850, 0x0850)
+IS_OMAP_TYPE(1510, 0x1510)
+IS_OMAP_TYPE(1610, 0x1610)
+IS_OMAP_TYPE(1611, 0x1611)
+IS_OMAP_TYPE(5912, 0x1611)
+IS_OMAP_TYPE(1621, 0x1621)
+IS_OMAP_TYPE(1710, 0x1710)
+IS_OMAP_TYPE(2420, 0x2420)
+IS_OMAP_TYPE(2422, 0x2422)
+IS_OMAP_TYPE(2423, 0x2423)
+IS_OMAP_TYPE(2430, 0x2430)
+IS_OMAP_TYPE(3430, 0x3430)
+IS_OMAP_TYPE(3505, 0x3505)
+IS_OMAP_TYPE(3517, 0x3517)
+
+#define cpu_is_omap310()                0
+#define cpu_is_omap730()                0
+#define cpu_is_omap850()                0
+#define cpu_is_omap1510()               0
+#define cpu_is_omap1610()               0
+#define cpu_is_omap5912()               0
+#define cpu_is_omap1611()               0
+#define cpu_is_omap1621()               0
+#define cpu_is_omap1710()               0
+#define cpu_is_omap2420()               0
+#define cpu_is_omap2422()               0
+#define cpu_is_omap2423()               0
+#define cpu_is_omap2430()               0
+#define cpu_is_omap3503()               0
+#define cpu_is_omap3515()               0
+#define cpu_is_omap3525()               0
+#define cpu_is_omap3530()               0
+#define cpu_is_omap3505()               0
+#define cpu_is_omap3517()               0
+#define cpu_is_omap3430()               0
+#define cpu_is_omap4430()               0
+#define cpu_is_omap3630()               0
+
+/*
+ * Whether we have MULTI_OMAP1 or not, we still need to distinguish
+ * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
+ */
+
+#if defined(CONFIG_ARCH_OMAP730)
+# undef  cpu_is_omap730
+# define cpu_is_omap730()               is_omap730()
+#endif
+
+#if defined(CONFIG_ARCH_OMAP850)
+# undef  cpu_is_omap850
+# define cpu_is_omap850()               is_omap850()
 #endif
 
+#if defined(CONFIG_ARCH_OMAP15XX)
+# undef  cpu_is_omap310
+# undef  cpu_is_omap1510
+# define cpu_is_omap310()               is_omap310()
+# define cpu_is_omap1510()              is_omap1510()
+#endif
+
+#if defined(CONFIG_ARCH_OMAP16XX)
+# undef  cpu_is_omap1610
+# undef  cpu_is_omap1611
+# undef  cpu_is_omap5912
+# undef  cpu_is_omap1621
+# undef  cpu_is_omap1710
+# define cpu_is_omap1610()              is_omap1610()
+# define cpu_is_omap1611()              is_omap1611()
+# define cpu_is_omap5912()              is_omap5912()
+# define cpu_is_omap1621()              is_omap1621()
+# define cpu_is_omap1710()              is_omap1710()
+#endif
+
+#if defined(CONFIG_ARCH_OMAP2)
+# undef  cpu_is_omap2420
+# undef  cpu_is_omap2422
+# undef  cpu_is_omap2423
+# undef  cpu_is_omap2430
+# define cpu_is_omap2420()              is_omap2420()
+# define cpu_is_omap2422()              is_omap2422()
+# define cpu_is_omap2423()              is_omap2423()
+# define cpu_is_omap2430()              is_omap2430()
+#endif
+
+#if defined(CONFIG_ARCH_OMAP3)
+# undef cpu_is_omap3430
+# undef cpu_is_omap3503
+# undef cpu_is_omap3515
+# undef cpu_is_omap3525
+# undef cpu_is_omap3530
+# undef cpu_is_omap3505
+# undef cpu_is_omap3517
+# undef cpu_is_ti816x
+# define cpu_is_omap3430()              is_omap3430()
+# define cpu_is_omap3503()              (cpu_is_omap3430() &&           \
+                                                (!omap3_has_iva()) &&   \
+                                                (!omap3_has_sgx()))
+# define cpu_is_omap3515()              (cpu_is_omap3430() &&           \
+                                                (!omap3_has_iva()) &&   \
+                                                (omap3_has_sgx()))
+# define cpu_is_omap3525()              (cpu_is_omap3430() &&           \
+                                                (!omap3_has_sgx()) &&   \
+                                                (omap3_has_iva()))
+# define cpu_is_omap3530()              (cpu_is_omap3430())
+# define cpu_is_omap3505()              is_omap3505()
+# define cpu_is_omap3517()              is_omap3517()
+# undef cpu_is_omap3630
+# define cpu_is_omap3630()              is_omap363x()
+# define cpu_is_ti816x()                is_ti816x()
+#endif
+
+# if defined(CONFIG_ARCH_OMAP4)
+# undef cpu_is_omap44xx
+# undef cpu_is_omap443x
+# undef cpu_is_omap446x
+# define cpu_is_omap44xx()              is_omap44xx()
+# define cpu_is_omap443x()              is_omap443x()
+# define cpu_is_omap446x()              is_omap446x()
+# endif
+
+/* Macros to detect if we have OMAP1 or OMAP2 */
+#define cpu_class_is_omap1()    (cpu_is_omap7xx() || cpu_is_omap15xx() || \
+                                cpu_is_omap16xx())
+#define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx() || \
+                                cpu_is_omap44xx())
+
+/* Various silicon revisions for omap2 */
+#define OMAP242X_CLASS          0x24200024
+#define OMAP2420_REV_ES1_0      OMAP242X_CLASS
+#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8))
+
+#define OMAP243X_CLASS          0x24300024
+#define OMAP2430_REV_ES1_0      OMAP243X_CLASS
+
+#define OMAP343X_CLASS          0x34300034
+#define OMAP3430_REV_ES1_0      OMAP343X_CLASS
+#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8))
+#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8))
+#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8))
+#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8))
+
+#define OMAP363X_CLASS          0x36300034
+#define OMAP3630_REV_ES1_0      OMAP363X_CLASS
+#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
+
+#define OMAP35XX_CLASS          0x35000034
+#define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
+#define OMAP3515_REV(v)         (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
+#define OMAP3525_REV(v)         (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
+#define OMAP3530_REV(v)         (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
+#define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
+#define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
+
+#define TI816X_CLASS            0x81600034
+#define TI8168_REV_ES1_0        TI816X_CLASS
+#define TI8168_REV_ES1_1        (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
+
+#define OMAP443X_CLASS          0x44300044
+#define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
+#define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
+#define OMAP4430_REV_ES2_1      (OMAP443X_CLASS | (0x21 << 8))
+#define OMAP4430_REV_ES2_2      (OMAP443X_CLASS | (0x22 << 8))
+
+#define OMAP446X_CLASS          0x44600044
+#define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
+
+/*
+ * omap_chip bits
+ *
+ * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
+ * valid on all chips of that type.  CHIP_IS_OMAP3430ES{1,2} indicates
+ * something that is only valid on that particular ES revision.
+ *
+ * These bits may be ORed together to indicate structures that are
+ * available on multiple chip types.
+ *
+ * To test whether a particular structure matches the current OMAP chip type,
+ * use omap_chip_is().
+ *
+ */
+#define CHIP_IS_OMAP2420                (1 << 0)
+#define CHIP_IS_OMAP2430                (1 << 1)
+#define CHIP_IS_OMAP3430                (1 << 2)
+#define CHIP_IS_OMAP3430ES1             (1 << 3)
+#define CHIP_IS_OMAP3430ES2             (1 << 4)
+#define CHIP_IS_OMAP3430ES3_0           (1 << 5)
+#define CHIP_IS_OMAP3430ES3_1           (1 << 6)
+#define CHIP_IS_OMAP3630ES1             (1 << 7)
+#define CHIP_IS_OMAP4430ES1             (1 << 8)
+#define CHIP_IS_OMAP3630ES1_1           (1 << 9)
+#define CHIP_IS_OMAP3630ES1_2           (1 << 10)
+#define CHIP_IS_OMAP4430ES2             (1 << 11)
+#define CHIP_IS_OMAP4430ES2_1           (1 << 12)
+#define CHIP_IS_OMAP4430ES2_2           (1 << 13)
+#define CHIP_IS_TI816X                  (1 << 14)
+#define CHIP_IS_OMAP4460ES1_0           (1 << 15)
+
+#define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
+
+#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 |          \
+                                         CHIP_IS_OMAP4430ES2 |          \
+                                         CHIP_IS_OMAP4430ES2_1 |        \
+                                         CHIP_IS_OMAP4430ES2_2 |        \
+                                         CHIP_IS_OMAP4460ES1_0)
+
+/*
+ * "GE" here represents "greater than or equal to" in terms of ES
+ * levels.  So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
+ * chips at ES2 and beyond, but not, for example, any OMAP lines after
+ * OMAP3.
+ */
+#define CHIP_GE_OMAP3430ES2             (CHIP_IS_OMAP3430ES2 | \
+                                         CHIP_IS_OMAP3430ES3_0 | \
+                                         CHIP_GE_OMAP3430ES3_1)
+#define CHIP_GE_OMAP3430ES3_1           (CHIP_IS_OMAP3430ES3_1 | \
+                                         CHIP_IS_OMAP3630ES1 | \
+                                         CHIP_GE_OMAP3630ES1_1)
+#define CHIP_GE_OMAP3630ES1_1           (CHIP_IS_OMAP3630ES1_1 | \
+                                         CHIP_IS_OMAP3630ES1_2)
+
+int omap_chip_is(struct omap_chip_id oci);
+void omap2_check_revision(void);
+
+/*
+ * Runtime detection of OMAP3 features
+ */
+extern u32 omap_features;
+
+#define OMAP3_HAS_L2CACHE               BIT(0)
+#define OMAP3_HAS_IVA                   BIT(1)
+#define OMAP3_HAS_SGX                   BIT(2)
+#define OMAP3_HAS_NEON                  BIT(3)
+#define OMAP3_HAS_ISP                   BIT(4)
+#define OMAP3_HAS_192MHZ_CLK            BIT(5)
+#define OMAP3_HAS_IO_WAKEUP             BIT(6)
+#define OMAP3_HAS_SDRC                  BIT(7)
+#define OMAP4_HAS_MPU_1GHZ              BIT(8)
+#define OMAP4_HAS_MPU_1_2GHZ            BIT(9)
+#define OMAP4_HAS_MPU_1_5GHZ            BIT(10)
+
+
+#define OMAP3_HAS_FEATURE(feat,flag)                    \
+static inline unsigned int omap3_has_ ##feat(void)      \
+{                                                       \
+        return omap_features & OMAP3_HAS_ ##flag;       \
+}                                                       \
+
+OMAP3_HAS_FEATURE(l2cache, L2CACHE)
+OMAP3_HAS_FEATURE(sgx, SGX)
+OMAP3_HAS_FEATURE(iva, IVA)
+OMAP3_HAS_FEATURE(neon, NEON)
+OMAP3_HAS_FEATURE(isp, ISP)
+OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
+OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
+OMAP3_HAS_FEATURE(sdrc, SDRC)
+
+/*
+ * Runtime detection of OMAP4 features
+ */
+extern u32 omap_features;
+
+#define OMAP4_HAS_FEATURE(feat, flag)                   \
+static inline unsigned int omap4_has_ ##feat(void)      \
+{                                                       \
+        return omap_features & OMAP4_HAS_ ##flag;       \
+}                                                       \
+
+OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
+OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
+OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
+
 #endif
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index a3fbc48c332..eb5d16c60cd 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -1,5 +1,5 @@
 /*
- * arch/arm/plat-omap/include/plat/dmtimer.h
+ * arch/arm/plat-omap/include/mach/dmtimer.h
  *
  * OMAP Dual-Mode Timers
  *
@@ -32,9 +32,9 @@
  * 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/platform_device.h>
 
 #ifndef __ASM_ARCH_DMTIMER_H
 #define __ASM_ARCH_DMTIMER_H
@@ -54,81 +54,17 @@
 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
 
-/* posted mode types */
-#define OMAP_TIMER_NONPOSTED                    0x00
-#define OMAP_TIMER_POSTED                       0x01
-
-/* timer capabilities used in hwmod database */
-#define OMAP_TIMER_SECURE                               0x80000000
-#define OMAP_TIMER_ALWON                                0x40000000
-#define OMAP_TIMER_HAS_PWM                              0x20000000
-#define OMAP_TIMER_NEEDS_RESET                          0x10000000
-#define OMAP_TIMER_HAS_DSP_IRQ                          0x08000000
-
 /*
- * timer errata flags
- *
- * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
- * errata prevents us from using posted mode on these devices, unless the
- * timer counter register is never read. For more details please refer to
- * the OMAP3/4/5 errata documents.
+ * IP revision identifier so that Highlander IP
+ * in OMAP4 can be distinguished.
  */
-#define OMAP_TIMER_ERRATA_I103_I767                     0x80000000
-
-struct omap_timer_capability_dev_attr {
-        u32 timer_capability;
-};
-
-struct timer_regs {
-        u32 tidr;
-        u32 tier;
-        u32 twer;
-        u32 tclr;
-        u32 tcrr;
-        u32 tldr;
-        u32 ttrg;
-        u32 twps;
-        u32 tmar;
-        u32 tcar1;
-        u32 tsicr;
-        u32 tcar2;
-        u32 tpir;
-        u32 tnir;
-        u32 tcvr;
-        u32 tocr;
-        u32 towr;
-};
-
-struct omap_dm_timer {
-        int id;
-        int irq;
-        struct clk *fclk;
-
-        void __iomem    *io_base;
-        void __iomem    *irq_stat;      /* TISR/IRQSTATUS interrupt status */
-        void __iomem    *irq_ena;       /* irq enable */
-        void __iomem    *irq_dis;       /* irq disable, only on v2 ip */
-        void __iomem    *pend;          /* write pending */
-        void __iomem    *func_base;     /* function register base */
-
-        unsigned long rate;
-        unsigned reserved:1;
-        unsigned posted:1;
-        struct timer_regs context;
-        int (*get_context_loss_count)(struct device *);
-        int ctx_loss_count;
-        int revision;
-        u32 capability;
-        u32 errata;
-        struct platform_device *pdev;
-        struct list_head node;
-};
+#define OMAP_TIMER_IP_VERSION_1                        0x1
+struct omap_dm_timer;
+struct clk;
 
-int omap_dm_timer_reserve_systimer(int id);
 struct omap_dm_timer *omap_dm_timer_request(void);
 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
-struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
-int omap_dm_timer_free(struct omap_dm_timer *timer);
+void omap_dm_timer_free(struct omap_dm_timer *timer);
 void omap_dm_timer_enable(struct omap_dm_timer *timer);
 void omap_dm_timer_disable(struct omap_dm_timer *timer);
 
@@ -137,24 +73,23 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
 
-int omap_dm_timer_trigger(struct omap_dm_timer *timer);
-int omap_dm_timer_start(struct omap_dm_timer *timer);
-int omap_dm_timer_stop(struct omap_dm_timer *timer);
+void omap_dm_timer_trigger(struct omap_dm_timer *timer);
+void omap_dm_timer_start(struct omap_dm_timer *timer);
+void omap_dm_timer_stop(struct omap_dm_timer *timer);
 
 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
-int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
-int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
-int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
+void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
+void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
+void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
 
-int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
-int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask);
+void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
 
 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
-int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
+void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
-int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
+void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
 
 int omap_dm_timers_active(void);
 
@@ -163,30 +98,12 @@ int omap_dm_timers_active(void);
  * used by dmtimer.c and sys_timer related code.
  */
 
-/*
- * The interrupt registers are different between v1 and v2 ip.
- * These registers are offsets from timer->iobase.
- */
-#define OMAP_TIMER_ID_OFFSET            0x00
-#define OMAP_TIMER_OCP_CFG_OFFSET       0x10
-
-#define OMAP_TIMER_V1_SYS_STAT_OFFSET   0x14
-#define OMAP_TIMER_V1_STAT_OFFSET       0x18
-#define OMAP_TIMER_V1_INT_EN_OFFSET     0x1c
-
-#define OMAP_TIMER_V2_IRQSTATUS_RAW     0x24
-#define OMAP_TIMER_V2_IRQSTATUS         0x28
-#define OMAP_TIMER_V2_IRQENABLE_SET     0x2c
-#define OMAP_TIMER_V2_IRQENABLE_CLR     0x30
-
-/*
- * The functional registers have a different base on v1 and v2 ip.
- * These registers are offsets from timer->func_base. The func_base
- * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
- *
- */
-#define OMAP_TIMER_V2_FUNC_OFFSET               0x14
-
+/* register offsets */
+#define _OMAP_TIMER_ID_OFFSET           0x00
+#define _OMAP_TIMER_OCP_CFG_OFFSET      0x10
+#define _OMAP_TIMER_SYS_STAT_OFFSET     0x14
+#define _OMAP_TIMER_STAT_OFFSET         0x18
+#define _OMAP_TIMER_INT_EN_OFFSET       0x1c
 #define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
 #define _OMAP_TIMER_CTRL_OFFSET         0x24
 #define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
@@ -230,6 +147,21 @@ int omap_dm_timers_active(void);
 /* register offsets with the write pending bit encoded */
 #define WPSHIFT                                 16
 
+#define OMAP_TIMER_ID_REG                       (_OMAP_TIMER_ID_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_OCP_CFG_REG                  (_OMAP_TIMER_OCP_CFG_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_SYS_STAT_REG                 (_OMAP_TIMER_SYS_STAT_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_STAT_REG                     (_OMAP_TIMER_STAT_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_INT_EN_REG                   (_OMAP_TIMER_INT_EN_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
 #define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
                                                         | (WP_NONE << WPSHIFT))
 
@@ -275,103 +207,97 @@ int omap_dm_timers_active(void);
 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
                 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
 
-static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
+struct omap_dm_timer {
+        unsigned long phys_base;
+        int irq;
+#ifdef CONFIG_ARCH_OMAP2PLUS
+        struct clk *iclk, *fclk;
+#endif
+        void __iomem *io_base;
+        unsigned long rate;
+        unsigned reserved:1;
+        unsigned enabled:1;
+        unsigned posted:1;
+};
+
+extern u32 sys_timer_reserved;
+void omap_dm_timer_prepare(struct omap_dm_timer *timer);
+
+static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
                                                 int posted)
 {
         if (posted)
-                while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
+                while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+                                & (reg >> WPSHIFT))
                         cpu_relax();
 
-        return __raw_readl(timer->func_base + (reg & 0xff));
+        return __raw_readl(base + (reg & 0xff));
 }
 
-static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
-                                        u32 reg, u32 val, int posted)
+static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val,
+                                                int posted)
 {
         if (posted)
-                while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
+                while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+                                & (reg >> WPSHIFT))
                         cpu_relax();
 
-        __raw_writel(val, timer->func_base + (reg & 0xff));
+        __raw_writel(val, base + (reg & 0xff));
 }
 
-static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
+/* Assumes the source clock has been set by caller */
+static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
+                                                int wakeup)
 {
-        u32 tidr;
-
-        /* Assume v1 ip if bits [31:16] are zero */
-        tidr = __raw_readl(timer->io_base);
-        if (!(tidr >> 16)) {
-                timer->revision = 1;
-                timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
-                timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
-                timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
-                timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
-                timer->func_base = timer->io_base;
-        } else {
-                timer->revision = 2;
-                timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
-                timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
-                timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
-                timer->pend = timer->io_base +
-                        _OMAP_TIMER_WRITE_PEND_OFFSET +
-                                OMAP_TIMER_V2_FUNC_OFFSET;
-                timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
-        }
-}
+        u32 l;
 
-/*
- * __omap_dm_timer_enable_posted - enables write posted mode
- * @timer:      pointer to timer instance handle
- *
- * Enables the write posted mode for the timer. When posted mode is enabled
- * writes to certain timer registers are immediately acknowledged by the
- * internal bus and hence prevents stalling the CPU waiting for the write to
- * complete. Enabling this feature can improve performance for writing to the
- * timer registers.
- */
-static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
-{
-        if (timer->posted)
-                return;
+        l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0);
+        l |= 0x02 << 3;  /* Set to smart-idle mode */
+        l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
+
+        if (autoidle)
+                l |= 0x1 << 0;
 
-        if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
-                return;
+        if (wakeup)
+                l |= 1 << 2;
 
-        __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
-                              OMAP_TIMER_CTRL_POSTED, 0);
-        timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
-        timer->posted = OMAP_TIMER_POSTED;
+        __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0);
+
+        /* Match hardware reset default of posted mode */
+        __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG,
+                                        OMAP_TIMER_CTRL_POSTED, 0);
 }
 
-/**
- * __omap_dm_timer_override_errata - override errata flags for a timer
- * @timer:      pointer to timer handle
- * @errata:     errata flags to be ignored
- *
- * For a given timer, override a timer errata by clearing the flags
- * specified by the errata argument. A specific erratum should only be
- * overridden for a timer if the timer is used in such a way the erratum
- * has no impact.
- */
-static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
-                                                   u32 errata)
+static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
+                                                struct clk *parent)
 {
-        timer->errata &= ~errata;
+        int ret;
+
+        clk_disable(timer_fck);
+        ret = clk_set_parent(timer_fck, parent);
+        clk_enable(timer_fck);
+
+        /*
+         * When the functional clock disappears, too quick writes seem
+         * to cause an abort. XXX Is this still necessary?
+         */
+        __delay(300000);
+
+        return ret;
 }
 
-static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
-                                        int posted, unsigned long rate)
+static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
+                                                unsigned long rate)
 {
         u32 l;
 
-        l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
+        l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
         if (l & OMAP_TIMER_CTRL_ST) {
                 l &= ~0x1;
-                __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
+                __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted);
 #ifdef CONFIG_ARCH_OMAP2PLUS
                 /* Readback to make sure write has completed */
-                __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
+                __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
                 /*
                  * Wait for functional clock period x 3.5 to make sure that
                  * timer is stopped
@@ -381,34 +307,34 @@ static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
         }
 
         /* Ack possibly pending interrupt */
-        __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
+        __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG,
+                                        OMAP_TIMER_INT_OVERFLOW, 0);
 }
 
-static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
-                                                u32 ctrl, unsigned int load,
-                                                int posted)
+static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl,
+                                                unsigned int load, int posted)
 {
-        __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
-        __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
+        __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted);
+        __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted);
 }
 
-static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
+static inline void __omap_dm_timer_int_enable(void __iomem *base,
                                                 unsigned int value)
 {
-        __raw_writel(value, timer->irq_ena);
-        __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
+        __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0);
+        __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
 }
 
-static inline unsigned int
-__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
+static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base,
+                                                        int posted)
 {
-        return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
+        return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted);
 }
 
-static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
+static inline void __omap_dm_timer_write_status(void __iomem *base,
                                                 unsigned int value)
 {
-        __raw_writel(value, timer->irq_stat);
+        __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0);
 }
 
 #endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 7a9028cb5a7..7c22b9e10dc 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -18,15 +18,11 @@
  * 02110-1301 USA
  *
  */
+#ifndef __ASM__ARCH_OMAP_I2C_H
+#define __ASM__ARCH_OMAP_I2C_H
 
-#ifndef __PLAT_OMAP_I2C_H
-#define __PLAT_OMAP_I2C_H
-
-struct i2c_board_info;
-struct omap_i2c_bus_platform_data;
-
-int omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
-                        int bus_id);
+#include <linux/i2c.h>
+#include <linux/i2c-omap.h>
 
 #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
 extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
@@ -41,7 +37,23 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 }
 #endif
 
+/**
+ * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
+ * @fifo_depth: total controller FIFO size (in bytes)
+ * @flags: differences in hardware support capability
+ *
+ * @fifo_depth represents what exists on the hardware, not what is
+ * actually configured at runtime by the device driver.
+ */
+struct omap_i2c_dev_attr {
+        u8      fifo_depth;
+        u32     flags;
+};
+
+void __init omap1_i2c_mux_pins(int bus_id);
+void __init omap2_i2c_mux_pins(int bus_id);
+
 struct omap_hwmod;
 int omap_i2c_reset(struct omap_hwmod *oh);
 
-#endif /* __PLAT_OMAP_I2C_H */
+#endif /* __ASM__ARCH_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index ba4525059a9..f500fc34d06 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -1,8 +1,18 @@
-int omap_sram_init(void);
+/*
+ * arch/arm/plat-omap/include/mach/sram.h
+ *
+ * Interface for functions that need to be run in internal SRAM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
 
-void omap_map_sram(unsigned long start, unsigned long size,
-                        unsigned long skip, int cached);
-void omap_sram_reset(void);
+#ifndef __ARCH_ARM_OMAP_SRAM_H
+#define __ARCH_ARM_OMAP_SRAM_H
+
+#ifndef __ASSEMBLY__
+#include <asm/fncpy.h>
 
 extern void *omap_sram_push_address(unsigned long size);
 
@@ -14,3 +24,77 @@ extern void *omap_sram_push_address(unsigned long size);
                 _res = fncpy(_sram_address, &(funcp), size);    \
         _res;                                                   \
 })
+
+extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
+
+extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                u32 base_cs, u32 force_unlock);
+extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                      u32 mem_type);
+extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
+
+extern u32 omap3_configure_core_dpll(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+extern void omap3_sram_restore_context(void);
+
+/* Do not use these */
+extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap1_sram_reprogram_clock_sz;
+
+extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap24xx_sram_reprogram_clock_sz;
+
+extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap242x_sram_ddr_init_sz;
+
+extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap242x_sram_set_prcm_sz;
+
+extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap242x_sram_reprogram_sdrc_sz;
+
+
+extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap243x_sram_ddr_init_sz;
+
+extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap243x_sram_set_prcm_sz;
+
+extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap243x_sram_reprogram_sdrc_sz;
+
+extern u32 omap3_sram_configure_core_dpll(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+extern unsigned long omap3_sram_configure_core_dpll_sz;
+
+#ifdef CONFIG_PM
+extern void omap_push_sram_idle(void);
+#else
+static inline void omap_push_sram_idle(void) {}
+#endif /* CONFIG_PM */
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * OMAP2+: define the SRAM PA addresses.
+ * Used by the SRAM management code and the idle sleep code.
+ */
+#define OMAP2_SRAM_PA           0x40200000
+#define OMAP3_SRAM_PA           0x40200000
+#define OMAP4_SRAM_PA           0x40300000
+
+#endif